diff --git a/cores/zxgate/zx/zx01/user_io.v b/cores/zxgate/zx/zx01/user_io.v
index 64a5aaf..18ec685 100644
--- a/cores/zxgate/zx/zx01/user_io.v
+++ b/cores/zxgate/zx/zx01/user_io.v
@@ -20,7 +20,11 @@
 // along with this program.  If not, see <http://www.gnu.org/licenses/>.
 //
 
-module user_io(
+// parameter STRLEN and the actual length of conf_str have to match
+
+module user_io #(parameter STRLEN=0) (
+	input [(8*STRLEN)-1:0] conf_str,
+
 	input      		SPI_CLK,
 	input      		SPI_SS_IO,
 	output     		reg SPI_MISO,
@@ -32,7 +36,7 @@ module user_io(
 	output [1:0] 	SWITCHES,
 
 	output reg [7:0]   status,
-	
+		
 	input 	  		clk,
 	output	 		ps2_clk,
 	output reg 		ps2_data
@@ -41,7 +45,7 @@ module user_io(
 // config string, it is assumed that any core returning a string here
 // also supports the OSD
 //                   0123456789abcdef 
-wire [127:0] name = "ZX01;P;         ";
+//wire [127:0] name = "ZX01;P;         ";
 
 reg [6:0]         sbuf;
 reg [7:0]         cmd;
@@ -72,8 +76,8 @@ always@(negedge SPI_CLK or posedge SPI_SS_IO) begin
 			// reading config string
 		   if(cmd == 8'h14) begin
 				// returning a byte from string
-				if(byte_cnt < 6'd17)
-					SPI_MISO <= name[{~(byte_cnt-6'd1),~bit_cnt}];
+				if(byte_cnt < STRLEN + 1)
+					SPI_MISO <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
 				else
 					SPI_MISO <= 1'b0;
 			end
diff --git a/cores/zxgate/zx/zx01/zx01.vhd b/cores/zxgate/zx/zx01/zx01.vhd
index a9c11c9..40573e2 100644
--- a/cores/zxgate/zx/zx01/zx01.vhd
+++ b/cores/zxgate/zx/zx01/zx01.vhd
@@ -22,6 +22,7 @@ entity zx01 is
         kbd_data: in    std_ulogic;
         v_inv:    in    std_ulogic;
         usa_uk:   in   	std_ulogic;
+        mem16k:   in   	std_ulogic;
         video:    out   std_ulogic;
         tape_in:  in    std_ulogic;
         tape_out: out   std_ulogic;
@@ -125,6 +126,7 @@ architecture rtl of zx01 is
   signal a_mem_h:   std_ulogic_vector(14 downto 13);
   signal a_mem_l:   std_ulogic_vector(8 downto 0);
   signal a_mem:     std_logic_vector(14 downto 0);
+  signal a_ram:     std_logic_vector(13 downto 0);
   signal d_ram:     std_logic_vector(7 downto 0);
   signal d_rom:     std_logic_vector(7 downto 0);
   signal n_romcs:   std_ulogic;
@@ -217,14 +219,16 @@ begin
               DO => d_cpu_i);
 
   c_SSRAM: SSRAM
-    generic map (AddrWidth => 14)  -- 11
+    generic map (AddrWidth => 14)
     port map (Clk => i_phi,
               CE_n => n_ramcs,
               WE_n => n_wr,
-              A => a_mem(13 downto 0),  -- 10..0
+              A => a_ram,
               DIn => d_cpu_i,
               DOut => d_ram);
 
+  a_ram <= a_mem(13 downto 0) when mem16k = '1' else "0000" & a_mem(9 downto 0);
+				  
   c_ROM81: ROM81
     port map (clock => i_phi,
               address => a_mem(12 downto 0),
diff --git a/cores/zxgate/zx/zx01/zx01_mist.v b/cores/zxgate/zx/zx01/zx01_mist.v
index fe6069b..da9561c 100644
--- a/cores/zxgate/zx/zx01/zx01_mist.v
+++ b/cores/zxgate/zx/zx01/zx01_mist.v
@@ -63,8 +63,14 @@ assign SDRAM_nCS = 1'b1;   // disable ram
 
 // reset geenration
 reg [7:0] reset_cnt;
+reg mem16kD, mem16kD2;
 always @(posedge clk) begin
-	if(!pll_locked || status[0])
+	mem16kD <= mem16k;
+	mem16kD2 <= mem16kD;
+
+	// reset on board setup, when io controller signals reset
+	// or when memory size changes
+	if(!pll_locked || reset_in || (mem16kD != mem16kD2))
 		reset_cnt <= 8'h0;
 	else if(reset_cnt != 8'd255)
 		reset_cnt <= reset_cnt + 8'd1;
@@ -102,9 +108,20 @@ always @(posedge clk)
 wire ps2_clk;
 wire ps2_data;
 
+// the configuration string is returned to the io controller to allow
+// it to control the menu on the OSD 
+parameter CONF_STR = {
+	"ZX01;P;",
+	"O1,Video standard,PAL,NTSC;",
+	"O2,Memory size,16k,1k;"
+};
+parameter CONF_STR_LEN = 7+27+22;
+
 wire [7:0] status;
 
-user_io user_io(
+user_io #(.STRLEN(CONF_STR_LEN)) user_io(
+	.conf_str		( CONF_STR     ),
+
 	// the spi interface
    .SPI_CLK     	(SPI_SCK			),
    .SPI_SS_IO   	(CONF_DATA0		),
@@ -127,6 +144,10 @@ user_io user_io(
 	.ps2_clk       (ps2_clk  		)
 );
 
+wire reset_in = status[0];
+wire ntsc = status[1];
+wire mem16k = !status[2];   // bit 2 of status register is 0 when 16k is enabled
+
 // ----------------------- Quick'n dirty scan doubler ---------------------------
 // This reveals a problem of the zx01: The video timing isn't perfect,
 // the hsync jumps in line 1 and in line 32 relative to the end of
@@ -275,8 +296,9 @@ zx01 zx01 (
 	.clock		(clk       		),
    .kbd_clk		(ps2_clk      	),
 	.kbd_data	(ps2_data		),
-	.v_inv    	(switches[1]	),
-	.usa_uk		(1'b0				),
+	.v_inv    	(1'b0				),
+	.usa_uk		(ntsc				),
+	.mem16k		(mem16k			),
 	.video    	(video			),
 	.tape_in		(tape_data		),
 	.tape_out	(csync      	),