From 2a64f9de5f1dffc8f9d13ae370f95ef2e2e749e4 Mon Sep 17 00:00:00 2001 From: phoboz Date: Fri, 23 Dec 2016 00:03:07 +0100 Subject: [PATCH 01/13] Starting to implement 15 kHz mode for SEGA Master System core --- cores/sms/sms_mist.qsf | 294 +----------------------------------- cores/sms/src/scandoubler.v | 147 ++++++++++++++++++ cores/sms/src/sms_mist.vhd | 108 ++++++++++--- cores/sms/src/tv_video.vhd | 120 +++++++++++++++ 4 files changed, 359 insertions(+), 310 deletions(-) create mode 100644 cores/sms/src/scandoubler.v create mode 100644 cores/sms/src/tv_video.vhd diff --git a/cores/sms/sms_mist.qsf b/cores/sms/sms_mist.qsf index c1c2737..a3ac008 100644 --- a/cores/sms/sms_mist.qsf +++ b/cores/sms/sms_mist.qsf @@ -314,6 +314,12 @@ set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top +set_global_assignment -name ENABLE_SIGNALTAP ON +set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name VERILOG_FILE src/scandoubler.v +set_global_assignment -name VHDL_FILE src/tv_video.vhd set_global_assignment -name VERILOG_FILE src/data_io.v set_global_assignment -name VERILOG_FILE src/osd.v set_global_assignment -name VERILOG_FILE src/user_io.v @@ -342,290 +348,4 @@ set_global_assignment -name VHDL_FILE t80/T80_MCode.vhd set_global_assignment -name VHDL_FILE t80/T80_ALU.vhd set_global_assignment -name VHDL_FILE t80/T80.vhd set_global_assignment -name QIP_FILE pll.qip -set_global_assignment -name ENABLE_SIGNALTAP ON -set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp -set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "pll:clock_inst|altpll:altpll_component|clk[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to SDRAM_A[0] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to SDRAM_A[10] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to SDRAM_A[11] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to SDRAM_A[12] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to SDRAM_A[1] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to SDRAM_A[2] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to SDRAM_A[3] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to SDRAM_A[4] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to SDRAM_A[5] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to SDRAM_A[6] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to SDRAM_A[7] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to SDRAM_A[8] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to SDRAM_A[9] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to SDRAM_BA[0] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to SDRAM_BA[1] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to SDRAM_DQMH -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to SDRAM_DQML -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to SDRAM_nCAS -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to SDRAM_nCS -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to SDRAM_nRAS -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to SDRAM_nWE -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to clk_cpu -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "pll:clock_inst|locked" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "sdram:sdram_inst|addr[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "sdram:sdram_inst|addr[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "sdram:sdram_inst|addr[11]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "sdram:sdram_inst|addr[12]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "sdram:sdram_inst|addr[13]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "sdram:sdram_inst|addr[14]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "sdram:sdram_inst|addr[15]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "sdram:sdram_inst|addr[16]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "sdram:sdram_inst|addr[17]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "sdram:sdram_inst|addr[18]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "sdram:sdram_inst|addr[19]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "sdram:sdram_inst|addr[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "sdram:sdram_inst|addr[20]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "sdram:sdram_inst|addr[21]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "sdram:sdram_inst|addr[22]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "sdram:sdram_inst|addr[23]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "sdram:sdram_inst|addr[24]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "sdram:sdram_inst|addr[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "sdram:sdram_inst|addr[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "sdram:sdram_inst|addr[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "sdram:sdram_inst|addr[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "sdram:sdram_inst|addr[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "sdram:sdram_inst|addr[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "sdram:sdram_inst|addr[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "sdram:sdram_inst|addr[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "sdram:sdram_inst|din[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "sdram:sdram_inst|din[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "sdram:sdram_inst|din[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "sdram:sdram_inst|din[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "sdram:sdram_inst|din[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "sdram:sdram_inst|din[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "sdram:sdram_inst|din[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "sdram:sdram_inst|din[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "sdram:sdram_inst|dout[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "sdram:sdram_inst|dout[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "sdram:sdram_inst|dout[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "sdram:sdram_inst|dout[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "sdram:sdram_inst|dout[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "sdram:sdram_inst|dout[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "sdram:sdram_inst|dout[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "sdram:sdram_inst|dout[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "sdram:sdram_inst|oe" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "sdram:sdram_inst|q[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "sdram:sdram_inst|q[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "sdram:sdram_inst|q[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "sdram:sdram_inst|reset[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "sdram:sdram_inst|reset[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "sdram:sdram_inst|reset[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "sdram:sdram_inst|reset[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "sdram:sdram_inst|reset[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "system:system_inst|T80se:z80_inst|A[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "system:system_inst|T80se:z80_inst|A[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "system:system_inst|T80se:z80_inst|A[11]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to "system:system_inst|T80se:z80_inst|A[12]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to "system:system_inst|T80se:z80_inst|A[13]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to "system:system_inst|T80se:z80_inst|A[14]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to "system:system_inst|T80se:z80_inst|A[15]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to "system:system_inst|T80se:z80_inst|A[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to "system:system_inst|T80se:z80_inst|A[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to "system:system_inst|T80se:z80_inst|A[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to "system:system_inst|T80se:z80_inst|A[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to "system:system_inst|T80se:z80_inst|A[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to "system:system_inst|T80se:z80_inst|A[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "system:system_inst|T80se:z80_inst|A[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "system:system_inst|T80se:z80_inst|A[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "system:system_inst|T80se:z80_inst|A[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "system:system_inst|T80se:z80_inst|CLKEN" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "system:system_inst|T80se:z80_inst|CLK_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "system:system_inst|T80se:z80_inst|DI[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[92] -to "system:system_inst|T80se:z80_inst|DI[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "system:system_inst|T80se:z80_inst|DI[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "system:system_inst|T80se:z80_inst|DI[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "system:system_inst|T80se:z80_inst|DI[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "system:system_inst|T80se:z80_inst|DI[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "system:system_inst|T80se:z80_inst|DI[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "system:system_inst|T80se:z80_inst|DI[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "system:system_inst|T80se:z80_inst|DO[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to "system:system_inst|T80se:z80_inst|DO[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to "system:system_inst|T80se:z80_inst|DO[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to "system:system_inst|T80se:z80_inst|DO[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to "system:system_inst|T80se:z80_inst|DO[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to "system:system_inst|T80se:z80_inst|DO[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to "system:system_inst|T80se:z80_inst|DO[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to "system:system_inst|T80se:z80_inst|DO[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to "system:system_inst|T80se:z80_inst|IORQ_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to "system:system_inst|T80se:z80_inst|MREQ_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to "system:system_inst|T80se:z80_inst|RD_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[110] -to "system:system_inst|T80se:z80_inst|RESET_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[111] -to "system:system_inst|T80se:z80_inst|WR_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[112] -to "system:system_inst|bootloader" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[113] -to "system:system_inst|ctl_WR_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[114] -to "system:system_inst|io_RD_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[115] -to "system:system_inst|io_WR_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[116] -to "system:system_inst|psg_WR_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[117] -to "system:system_inst|ram_WR_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[118] -to "system:system_inst|reset" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[119] -to "system:system_inst|sprom:boot_rom_inst|q[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[120] -to "system:system_inst|sprom:boot_rom_inst|q[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[121] -to "system:system_inst|sprom:boot_rom_inst|q[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[122] -to "system:system_inst|sprom:boot_rom_inst|q[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[123] -to "system:system_inst|sprom:boot_rom_inst|q[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[124] -to "system:system_inst|sprom:boot_rom_inst|q[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[125] -to "system:system_inst|sprom:boot_rom_inst|q[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[126] -to "system:system_inst|sprom:boot_rom_inst|q[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[127] -to "system:system_inst|vdp_RD_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[128] -to "system:system_inst|vdp_WR_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to SDRAM_A[0] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to SDRAM_A[10] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to SDRAM_A[11] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to SDRAM_A[12] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to SDRAM_A[1] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to SDRAM_A[2] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to SDRAM_A[3] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to SDRAM_A[4] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to SDRAM_A[5] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to SDRAM_A[6] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to SDRAM_A[7] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to SDRAM_A[8] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to SDRAM_A[9] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to SDRAM_BA[0] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to SDRAM_BA[1] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to SDRAM_DQMH -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to SDRAM_DQML -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to SDRAM_nCAS -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to SDRAM_nCS -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to SDRAM_nRAS -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to SDRAM_nWE -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to clk_cpu -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "pll:clock_inst|locked" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "sdram:sdram_inst|addr[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "sdram:sdram_inst|addr[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "sdram:sdram_inst|addr[11]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "sdram:sdram_inst|addr[12]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "sdram:sdram_inst|addr[13]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "sdram:sdram_inst|addr[14]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "sdram:sdram_inst|addr[15]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "sdram:sdram_inst|addr[16]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "sdram:sdram_inst|addr[17]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "sdram:sdram_inst|addr[18]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "sdram:sdram_inst|addr[19]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "sdram:sdram_inst|addr[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "sdram:sdram_inst|addr[20]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "sdram:sdram_inst|addr[21]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "sdram:sdram_inst|addr[22]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "sdram:sdram_inst|addr[23]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "sdram:sdram_inst|addr[24]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "sdram:sdram_inst|addr[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "sdram:sdram_inst|addr[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "sdram:sdram_inst|addr[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "sdram:sdram_inst|addr[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "sdram:sdram_inst|addr[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "sdram:sdram_inst|addr[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "sdram:sdram_inst|addr[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "sdram:sdram_inst|addr[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "sdram:sdram_inst|din[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "sdram:sdram_inst|din[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "sdram:sdram_inst|din[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "sdram:sdram_inst|din[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "sdram:sdram_inst|din[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "sdram:sdram_inst|din[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "sdram:sdram_inst|din[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "sdram:sdram_inst|din[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "sdram:sdram_inst|dout[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "sdram:sdram_inst|dout[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "sdram:sdram_inst|dout[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "sdram:sdram_inst|dout[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "sdram:sdram_inst|dout[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "sdram:sdram_inst|dout[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "sdram:sdram_inst|dout[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "sdram:sdram_inst|dout[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "sdram:sdram_inst|oe" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "sdram:sdram_inst|q[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "sdram:sdram_inst|q[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "sdram:sdram_inst|q[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "sdram:sdram_inst|reset[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "sdram:sdram_inst|reset[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "sdram:sdram_inst|reset[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "sdram:sdram_inst|reset[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "sdram:sdram_inst|reset[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "system:system_inst|T80se:z80_inst|A[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "system:system_inst|T80se:z80_inst|A[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "system:system_inst|T80se:z80_inst|A[11]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "system:system_inst|T80se:z80_inst|A[12]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "system:system_inst|T80se:z80_inst|A[13]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "system:system_inst|T80se:z80_inst|A[14]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "system:system_inst|T80se:z80_inst|A[15]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "system:system_inst|T80se:z80_inst|A[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "system:system_inst|T80se:z80_inst|A[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "system:system_inst|T80se:z80_inst|A[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "system:system_inst|T80se:z80_inst|A[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "system:system_inst|T80se:z80_inst|A[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "system:system_inst|T80se:z80_inst|A[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "system:system_inst|T80se:z80_inst|A[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "system:system_inst|T80se:z80_inst|A[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "system:system_inst|T80se:z80_inst|A[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "system:system_inst|T80se:z80_inst|CLKEN" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "system:system_inst|T80se:z80_inst|CLK_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "system:system_inst|T80se:z80_inst|DI[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "system:system_inst|T80se:z80_inst|DI[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "system:system_inst|T80se:z80_inst|DI[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "system:system_inst|T80se:z80_inst|DI[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "system:system_inst|T80se:z80_inst|DI[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "system:system_inst|T80se:z80_inst|DI[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "system:system_inst|T80se:z80_inst|DI[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "system:system_inst|T80se:z80_inst|DI[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "system:system_inst|T80se:z80_inst|DO[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "system:system_inst|T80se:z80_inst|DO[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "system:system_inst|T80se:z80_inst|DO[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "system:system_inst|T80se:z80_inst|DO[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to "system:system_inst|T80se:z80_inst|DO[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to "system:system_inst|T80se:z80_inst|DO[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to "system:system_inst|T80se:z80_inst|DO[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to "system:system_inst|T80se:z80_inst|DO[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to "system:system_inst|T80se:z80_inst|IORQ_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to "system:system_inst|T80se:z80_inst|MREQ_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to "system:system_inst|T80se:z80_inst|RD_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[110] -to "system:system_inst|T80se:z80_inst|RESET_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[111] -to "system:system_inst|T80se:z80_inst|WR_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[112] -to "system:system_inst|bootloader" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[113] -to "system:system_inst|ctl_WR_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[114] -to "system:system_inst|io_RD_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[115] -to "system:system_inst|io_WR_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[116] -to "system:system_inst|psg_WR_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[117] -to "system:system_inst|ram_WR_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[118] -to "system:system_inst|reset" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[119] -to "system:system_inst|sprom:boot_rom_inst|q[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[120] -to "system:system_inst|sprom:boot_rom_inst|q[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[121] -to "system:system_inst|sprom:boot_rom_inst|q[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[122] -to "system:system_inst|sprom:boot_rom_inst|q[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[123] -to "system:system_inst|sprom:boot_rom_inst|q[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[124] -to "system:system_inst|sprom:boot_rom_inst|q[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[125] -to "system:system_inst|sprom:boot_rom_inst|q[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[126] -to "system:system_inst|sprom:boot_rom_inst|q[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[127] -to "system:system_inst|vdp_RD_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[128] -to "system:system_inst|vdp_WR_n" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=129" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=129" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=410" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=512" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=63756" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=55445" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=512" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0 -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp \ No newline at end of file +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/cores/sms/src/scandoubler.v b/cores/sms/src/scandoubler.v new file mode 100644 index 0000000..6edcc8d --- /dev/null +++ b/cores/sms/src/scandoubler.v @@ -0,0 +1,147 @@ +// +// scandoubler.v +// +// Copyright (c) 2015 Till Harbaum +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . + +module scandoubler ( + // system interface + input clk_in, + input clk_out, + + input scanlines, + + // shifter video interface + input hs_in, + input vs_in, + input [5:0] r_in, + input [5:0] g_in, + input [5:0] b_in, + + // output interface + output reg [5:0] r_out, + output reg [5:0] g_out, + output reg [5:0] b_out, + output reg vs_out, + output reg hs_out +); + +// scan doubler output register +reg [17:0] sd_out; + +// --------------------- create output signals ----------------- +// latch everything once more to make it glitch free and apply scanline effect +reg scanline; + +always @(posedge clk_out) begin + vs_out <= vs_in; + hs_out <= hs_sd; + + // reset scanlines at every new screen + if(vs_out != vs_in) + scanline <= 1'b0; + + // toggle scanlines at begin of every hsync + if(hs_out && !hs_sd) + scanline <= !scanline; + + // if no scanlines or not a scanline + if(!scanlines || !scanline) begin + r_out <= { sd_out[17:12] }; + g_out <= { sd_out[11:6] }; + b_out <= { sd_out[5:0] }; + end else begin + r_out <= { 1'b0, sd_out[17:13] }; + g_out <= { 1'b0, sd_out[11:7] }; + b_out <= { 1'b0, sd_out[5:1] }; + end +end + + + +// ================================================================== +// ======================== the line buffers ======================== +// ================================================================== + +// 2 lines of 1024 pixels 3*6 bit RGB +reg [17:0] sd_buffer [2047:0]; + +// use alternating sd_buffers when storing/reading data +reg vsD; +reg line_toggle; +always @(negedge clk_in) begin + vsD <= vs_in; + + if(vsD != vs_in) + line_toggle <= 1'b0; + + // begin of incoming hsync + if(hsD && !hs_in) + line_toggle <= !line_toggle; +end + +always @(negedge clk_in) begin + sd_buffer[{line_toggle, hcnt}] <= { r_in, g_in, b_in }; +end + +// ================================================================== +// =================== horizontal timing analysis =================== +// ================================================================== + +// total hsync time (in 16MHz cycles), hs_total reaches 1024 +reg [9:0] hs_max; +reg [9:0] hs_rise; +reg [9:0] hcnt; +reg hsD; + +always @(negedge clk_in) begin + hsD <= hs_in; + + // falling edge of hsync indicates start of line + if(hsD && !hs_in) begin + hs_max <= hcnt; + hcnt <= 10'd0; + end else + hcnt <= hcnt + 10'd1; + + // save position of rising edge + if(!hsD && hs_in) + hs_rise <= hcnt; +end + +// ================================================================== +// ==================== output timing generation ==================== +// ================================================================== + +reg [9:0] sd_hcnt; +reg hs_sd; + +// timing generation runs 32 MHz (twice the input signal analysis speed) +always @(posedge clk_out) begin + + // output counter synchronous to input and at twice the rate + sd_hcnt <= sd_hcnt + 10'd1; + if(hsD && !hs_in) sd_hcnt <= hs_max; + if(sd_hcnt == hs_max) sd_hcnt <= 10'd0; + + // replicate horizontal sync at twice the speed + if(sd_hcnt == hs_max) hs_sd <= 1'b0; + if(sd_hcnt == hs_rise) hs_sd <= 1'b1; + + // read data from line sd_buffer + sd_out <= sd_buffer[{~line_toggle, sd_hcnt}]; +end + +endmodule diff --git a/cores/sms/src/sms_mist.vhd b/cores/sms/src/sms_mist.vhd index 73feb4b..25d4061 100644 --- a/cores/sms/src/sms_mist.vhd +++ b/cores/sms/src/sms_mist.vhd @@ -46,7 +46,28 @@ entity sms_mist is end sms_mist; architecture Behavioral of sms_mist is - + + component scandoubler is + port ( + clk_in: in std_logic; + clk_out: in std_logic; + + scanlines: in std_logic; + + hs_in: in std_logic; + vs_in: in std_logic; + r_in: in std_logic_vector(5 downto 0); + g_in: in std_logic_vector(5 downto 0); + b_in: in std_logic_vector(5 downto 0); + + r_out: out std_logic_vector(5 downto 0); + g_out: out std_logic_vector(5 downto 0); + b_out: out std_logic_vector(5 downto 0); + hs_out: out std_logic; + vs_out: out std_logic + ); + end component; + component vga_video is port ( clk16: in std_logic; @@ -60,7 +81,20 @@ architecture Behavioral of sms_mist is green: out std_logic_vector(1 downto 0); blue: out std_logic_vector(1 downto 0)); end component; - + + component tv_video is + port ( + clk8: in std_logic; + x: out unsigned(8 downto 0); + y: out unsigned(7 downto 0); + color: in std_logic_vector(5 downto 0); + hsync: out std_logic; + vsync: out std_logic; + red: out std_logic_vector(1 downto 0); + green: out std_logic_vector(1 downto 0); + blue: out std_logic_vector(1 downto 0)); + end component; + component sdram is port( sd_data : inout std_logic_vector(15 downto 0); sd_addr : out std_logic_vector(12 downto 0); @@ -172,6 +206,8 @@ architecture Behavioral of sms_mist is signal b : std_logic_vector(1 downto 0); signal vs: std_logic; signal hs: std_logic; + signal hs_out: std_logic; + signal vs_out: std_logic; signal ioctl_wr : std_logic; signal ioctl_addr : std_logic_vector(24 downto 0); @@ -211,10 +247,10 @@ begin end if; end process; - video_inst: vga_video + video_inst: tv_video port map ( - clk16 => clk16, - pal => status(1), + clk8 => clk_cpu, + --pal => status(1), x => x, y => y, color => color, @@ -226,23 +262,49 @@ begin blue => b ); - osd_inst : osd - port map ( - pclk => clk16, - sdi => SPI_DI, - sck => SPI_SCK, - ss => SPI_SS3, - red_in => r & r & r, - green_in => g & g & g, - blue_in => b & b & b, - hs_in => hs, - vs_in => vs, - red_out => VGA_R, - green_out => VGA_G, - blue_out => VGA_B, - hs_out => VGA_HS, - vs_out => VGA_VS - ); + --scandouble_inst: scandoubler + --port map( + -- clk_in => clk_cpu, + -- clk_out => clk16, + -- scanlines => '0', + -- hs_in => hs, + -- vs_in => vs, + -- r_in => r & r & r, + -- g_in => g & g & g, + -- b_in => b & b & b, + -- r_out => red_vga, + -- g_out => green_vga, + -- b_out => blue_vga, + -- hs_out => hs_vga, + -- vs_out => vs_vga + --); + + VGA_R <= r & r & r; + VGA_G <= g & g & g; + VGA_B <= b & b & b; + VGA_HS <= hs xor vs; + VGA_VS <= '1'; + + --osd_inst : osd + -- port map ( + -- pclk => clk_cpu, + -- sdi => SPI_DI, + -- sck => SPI_SCK, + -- ss => SPI_SS3, + -- red_in => r & r & r, + -- green_in => g & g & g, + -- blue_in => b & b & b, + -- hs_in => hs, + -- vs_in => vs, + -- red_out => VGA_R, + -- green_out => VGA_G, + -- blue_out => VGA_B, + -- hs_out => hs_out, + -- vs_out => vs_out + -- ); + + --VGA_HS <= hs_out xor vs_out; + --VGA_VS <= '1'; -- sdram interface SDRAM_CKE <= '1'; @@ -322,7 +384,7 @@ begin system_inst: work.system port map ( clk_cpu => clk_cpu, - clk_vdp => clk16, + clk_vdp => clk_cpu, -- ram interface used for cartridge emulation ram_oe_n => ram_oe_n, diff --git a/cores/sms/src/tv_video.vhd b/cores/sms/src/tv_video.vhd new file mode 100644 index 0000000..10cd5d5 --- /dev/null +++ b/cores/sms/src/tv_video.vhd @@ -0,0 +1,120 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity tv_video is + Port ( + clk8: in STD_LOGIC; + x: out unsigned(8 downto 0); + y: out unsigned(7 downto 0); + color: in std_logic_vector(5 downto 0); + hsync: out std_logic; + vsync: out std_logic; + red: out std_logic_vector(1 downto 0); + green: out std_logic_vector(1 downto 0); + blue: out std_logic_vector(1 downto 0)); +end tv_video; + +architecture Behavioral of tv_video is + + signal hcount: unsigned(8 downto 0) := (others => '0'); + signal vcount: unsigned(8 downto 0) := (others => '0'); + signal y9: unsigned(8 downto 0); + + signal in_vbl: std_logic; + signal screen_sync: std_logic; + signal vbl_sync: std_logic; + + signal line_visible: std_logic; + signal line_even: std_logic; + signal hblank: std_logic; + signal vblank: std_logic; + signal visible: boolean; + +begin + + process (clk8) + begin + if rising_edge(clk8) then + if hcount=507 then + hcount <= (others => '0'); + if vcount=261 then + vcount <= (others=>'0'); + else + vcount <= vcount + 1; + end if; + else + hcount <= hcount + 1; + end if; + end if; + end process; + + process (hcount) + begin + if hcount<38 then + screen_sync <= '0'; + else + screen_sync <= '1'; + end if; + end process; + + in_vbl <= '1' when vcount<9 else '0'; + + x <= hcount-166; + y9 <= vcount-40; + y <= y9(7 downto 0); + vblank <= '1' when hcount=0 and vcount=0 else '0'; + hblank <= '1' when hcount=0 else '0'; + line_visible <= not in_vbl; + line_even <= not vcount(0); + + process (vcount,hcount) + begin + if vcount<3 or (vcount>=6 and vcount<9) then + -- _^^^^^_^^^^^ : low pulse = 2.35us + if hcount<19 or (hcount>=254 and hcount<254+19) then + vbl_sync <= '0'; + else + vbl_sync <= '1'; + end if; + else + -- ____^^ : high pulse = 4.7us + if hcount<(254-38) or (hcount>=254 and hcount<508-38) then + vbl_sync <= '0'; + else + vbl_sync <= '1'; + end if; + end if; + end process; + + --process (in_vbl,screen_sync,vbl_sync) + --begin + -- if in_vbl='1' then + -- hsync <= vbl_sync; + -- else + -- hsync <= screen_sync; + -- end if; + --end process; + + hsync <= screen_sync; + vsync <= vbl_sync; + + visible <= (line_visible = '1' and vcount>=40 and vcount<467); + + process (clk8) + begin + if rising_edge(clk8) then + if visible then + red <= color(1 downto 0); + green <= color(3 downto 2); + blue <= color(5 downto 4); + else + red <= (others=>'0'); + green <= (others=>'0'); + blue <= (others=>'0'); + end if; + end if; + end process; + +end Behavioral; + From 5162b3dd0db7f23e7adc0655cbaeda7c5f3621a5 Mon Sep 17 00:00:00 2001 From: phoboz Date: Fri, 23 Dec 2016 22:41:08 +0100 Subject: [PATCH 02/13] Split composite sync correctly --- cores/sms/src/sms_mist.vhd | 4 ++-- cores/sms/src/tv_video.vhd | 7 ++++--- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/cores/sms/src/sms_mist.vhd b/cores/sms/src/sms_mist.vhd index 25d4061..5c66a9b 100644 --- a/cores/sms/src/sms_mist.vhd +++ b/cores/sms/src/sms_mist.vhd @@ -282,7 +282,7 @@ begin VGA_R <= r & r & r; VGA_G <= g & g & g; VGA_B <= b & b & b; - VGA_HS <= hs xor vs; + VGA_HS <= not (hs xor vs); VGA_VS <= '1'; --osd_inst : osd @@ -303,7 +303,7 @@ begin -- vs_out => vs_out -- ); - --VGA_HS <= hs_out xor vs_out; + --VGA_HS <= not (hs_out xor vs_out); --VGA_VS <= '1'; -- sdram interface diff --git a/cores/sms/src/tv_video.vhd b/cores/sms/src/tv_video.vhd index 10cd5d5..5a96b71 100644 --- a/cores/sms/src/tv_video.vhd +++ b/cores/sms/src/tv_video.vhd @@ -95,9 +95,10 @@ begin -- hsync <= screen_sync; -- end if; --end process; - - hsync <= screen_sync; - vsync <= vbl_sync; + --vsync <= '1'; + + hsync <= not screen_sync when in_vbl='0' else '0'; + vsync <= not vbl_sync when in_vbl='1' else '0'; visible <= (line_visible = '1' and vcount>=40 and vcount<467); From d0df98f6bc8abc64abca1ef9d0ccc4756c17d7e1 Mon Sep 17 00:00:00 2001 From: phoboz Date: Fri, 23 Dec 2016 22:55:07 +0100 Subject: [PATCH 03/13] Enabled osd --- cores/sms/src/sms_mist.vhd | 48 +++++++++++++++++++------------------- cores/sms/src/tv_video.vhd | 2 +- 2 files changed, 25 insertions(+), 25 deletions(-) diff --git a/cores/sms/src/sms_mist.vhd b/cores/sms/src/sms_mist.vhd index 5c66a9b..aa0e35e 100644 --- a/cores/sms/src/sms_mist.vhd +++ b/cores/sms/src/sms_mist.vhd @@ -279,32 +279,32 @@ begin -- vs_out => vs_vga --); - VGA_R <= r & r & r; - VGA_G <= g & g & g; - VGA_B <= b & b & b; - VGA_HS <= not (hs xor vs); - VGA_VS <= '1'; + --VGA_R <= r & r & r; + --VGA_G <= g & g & g; + --VGA_B <= b & b & b; + --VGA_HS <= not (hs xor vs); + --VGA_VS <= '1'; - --osd_inst : osd - -- port map ( - -- pclk => clk_cpu, - -- sdi => SPI_DI, - -- sck => SPI_SCK, - -- ss => SPI_SS3, - -- red_in => r & r & r, - -- green_in => g & g & g, - -- blue_in => b & b & b, - -- hs_in => hs, - -- vs_in => vs, - -- red_out => VGA_R, - -- green_out => VGA_G, - -- blue_out => VGA_B, - -- hs_out => hs_out, - -- vs_out => vs_out - -- ); + osd_inst : osd + port map ( + pclk => clk16, + sdi => SPI_DI, + sck => SPI_SCK, + ss => SPI_SS3, + red_in => r & r & r, + green_in => g & g & g, + blue_in => b & b & b, + hs_in => hs, + vs_in => vs, + red_out => VGA_R, + green_out => VGA_G, + blue_out => VGA_B, + hs_out => hs_out, + vs_out => vs_out + ); - --VGA_HS <= not (hs_out xor vs_out); - --VGA_VS <= '1'; + VGA_HS <= not (hs_out xor vs_out); + VGA_VS <= '1'; -- sdram interface SDRAM_CKE <= '1'; diff --git a/cores/sms/src/tv_video.vhd b/cores/sms/src/tv_video.vhd index 5a96b71..254036a 100644 --- a/cores/sms/src/tv_video.vhd +++ b/cores/sms/src/tv_video.vhd @@ -100,7 +100,7 @@ begin hsync <= not screen_sync when in_vbl='0' else '0'; vsync <= not vbl_sync when in_vbl='1' else '0'; - visible <= (line_visible = '1' and vcount>=40 and vcount<467); + visible <= (line_visible = '1' and vcount>=33 and vcount<453); process (clk8) begin From a8760a1c6d330b58eacd9e99fcaecff38a9b5fb4 Mon Sep 17 00:00:00 2001 From: phoboz Date: Sat, 24 Dec 2016 22:46:49 +0100 Subject: [PATCH 04/13] Added scandoubler --- cores/sms/src/sms_mist.vhd | 58 +++++++++++++++++--------------------- 1 file changed, 26 insertions(+), 32 deletions(-) diff --git a/cores/sms/src/sms_mist.vhd b/cores/sms/src/sms_mist.vhd index aa0e35e..7831524 100644 --- a/cores/sms/src/sms_mist.vhd +++ b/cores/sms/src/sms_mist.vhd @@ -206,6 +206,9 @@ architecture Behavioral of sms_mist is signal b : std_logic_vector(1 downto 0); signal vs: std_logic; signal hs: std_logic; + signal r_out : std_logic_vector(5 downto 0); + signal g_out : std_logic_vector(5 downto 0); + signal b_out : std_logic_vector(5 downto 0); signal hs_out: std_logic; signal vs_out: std_logic; @@ -262,28 +265,22 @@ begin blue => b ); - --scandouble_inst: scandoubler - --port map( - -- clk_in => clk_cpu, - -- clk_out => clk16, - -- scanlines => '0', - -- hs_in => hs, - -- vs_in => vs, - -- r_in => r & r & r, - -- g_in => g & g & g, - -- b_in => b & b & b, - -- r_out => red_vga, - -- g_out => green_vga, - -- b_out => blue_vga, - -- hs_out => hs_vga, - -- vs_out => vs_vga - --); - - --VGA_R <= r & r & r; - --VGA_G <= g & g & g; - --VGA_B <= b & b & b; - --VGA_HS <= not (hs xor vs); - --VGA_VS <= '1'; + scandouble_inst: scandoubler + port map( + clk_in => clk_cpu, + clk_out => clk16, + scanlines => '0', + hs_in => hs, + vs_in => vs, + r_in => r & r & r, + g_in => g & g & g, + b_in => b & b & b, + r_out => r_out, + g_out => g_out, + b_out => b_out, + hs_out => hs_out, + vs_out => vs_out + ); osd_inst : osd port map ( @@ -291,21 +288,18 @@ begin sdi => SPI_DI, sck => SPI_SCK, ss => SPI_SS3, - red_in => r & r & r, - green_in => g & g & g, - blue_in => b & b & b, - hs_in => hs, - vs_in => vs, + red_in => r_out, + green_in => g_out, + blue_in => b_out, + hs_in => hs_out, + vs_in => vs_out, red_out => VGA_R, green_out => VGA_G, blue_out => VGA_B, - hs_out => hs_out, - vs_out => vs_out + hs_out => VGA_HS, + vs_out => VGA_VS ); - VGA_HS <= not (hs_out xor vs_out); - VGA_VS <= '1'; - -- sdram interface SDRAM_CKE <= '1'; SDRAM_DQMH <= sdram_dqm(1); From 2c8126506616eca4c0905edba7e278882a7fd8d1 Mon Sep 17 00:00:00 2001 From: phoboz Date: Sat, 24 Dec 2016 23:43:48 +0100 Subject: [PATCH 05/13] Option between 15 kHz and 30 kHz video mode --- cores/sms/src/sms_mist.vhd | 78 +++++++++++++++++++++++++------------- 1 file changed, 52 insertions(+), 26 deletions(-) diff --git a/cores/sms/src/sms_mist.vhd b/cores/sms/src/sms_mist.vhd index 7831524..c2b8359 100644 --- a/cores/sms/src/sms_mist.vhd +++ b/cores/sms/src/sms_mist.vhd @@ -197,6 +197,7 @@ architecture Behavioral of sms_mist is signal joy1 : std_logic_vector(5 downto 0); signal joya : std_logic_vector(5 downto 0); signal joyb : std_logic_vector(5 downto 0); + signal scandoubler_disable : std_logic; signal status : std_logic_vector(7 downto 0); signal j1_tr : std_logic; signal j2_tr : std_logic; @@ -206,11 +207,23 @@ architecture Behavioral of sms_mist is signal b : std_logic_vector(1 downto 0); signal vs: std_logic; signal hs: std_logic; - signal r_out : std_logic_vector(5 downto 0); - signal g_out : std_logic_vector(5 downto 0); - signal b_out : std_logic_vector(5 downto 0); - signal hs_out: std_logic; - signal vs_out: std_logic; + + signal video_r: std_logic_vector(5 downto 0); + signal video_g: std_logic_vector(5 downto 0); + signal video_b: std_logic_vector(5 downto 0); + + signal sd_r : std_logic_vector(5 downto 0); + signal sd_g : std_logic_vector(5 downto 0); + signal sd_b : std_logic_vector(5 downto 0); + signal sd_hs: std_logic; + signal sd_vs: std_logic; + + signal osd_clk: std_logic; + signal osd_r : std_logic_vector(5 downto 0); + signal osd_g : std_logic_vector(5 downto 0); + signal osd_b : std_logic_vector(5 downto 0); + signal osd_hs : std_logic; + signal osd_vs : std_logic; signal ioctl_wr : std_logic; signal ioctl_addr : std_logic_vector(24 downto 0); @@ -249,7 +262,7 @@ begin clk_cpu <= not clk_cpu; end if; end process; - + video_inst: tv_video port map ( clk8 => clk_cpu, @@ -264,7 +277,11 @@ begin green => g, blue => b ); - + + video_r <= r & r & r; + video_g <= g & g & g; + video_b <= b & b & b; + scandouble_inst: scandoubler port map( clk_in => clk_cpu, @@ -272,32 +289,41 @@ begin scanlines => '0', hs_in => hs, vs_in => vs, - r_in => r & r & r, - g_in => g & g & g, - b_in => b & b & b, - r_out => r_out, - g_out => g_out, - b_out => b_out, - hs_out => hs_out, - vs_out => vs_out + r_in => video_r, + g_in => video_g, + b_in => video_b, + r_out => sd_r, + g_out => sd_g, + b_out => sd_b, + hs_out => sd_hs, + vs_out => sd_vs ); - - osd_inst : osd + + scandoubler_disable <= '1'; + VGA_HS <= not(hs xor vs) when scandoubler_disable = '1' else sd_hs; + VGA_VS <= '1' when scandoubler_disable = '1' else sd_vs; + + osd_clk <= clk_cpu when scandoubler_disable = '1' else clk16; + osd_hs <= hs when scandoubler_disable = '1' else sd_hs; + osd_vs <= vs when scandoubler_disable = '1' else sd_vs; + osd_r <= video_r when scandoubler_disable = '1' else sd_r; + osd_g <= video_g when scandoubler_disable = '1' else sd_g; + osd_b <= video_b when scandoubler_disable = '1' else sd_b; + + osd_inst : osd port map ( - pclk => clk16, + pclk => osd_clk, sdi => SPI_DI, sck => SPI_SCK, ss => SPI_SS3, - red_in => r_out, - green_in => g_out, - blue_in => b_out, - hs_in => hs_out, - vs_in => vs_out, + red_in => osd_r, + green_in => osd_g, + blue_in => osd_b, + hs_in => osd_hs, + vs_in => osd_vs, red_out => VGA_R, green_out => VGA_G, - blue_out => VGA_B, - hs_out => VGA_HS, - vs_out => VGA_VS + blue_out => VGA_B ); -- sdram interface From 9b0cf5004e57f5be480794b0bd3831fe45bf48af Mon Sep 17 00:00:00 2001 From: phoboz Date: Sun, 25 Dec 2016 21:40:53 +0100 Subject: [PATCH 06/13] Fixed video off outside visible area. --- cores/sms/src/tv_video.vhd | 20 +++----------------- 1 file changed, 3 insertions(+), 17 deletions(-) diff --git a/cores/sms/src/tv_video.vhd b/cores/sms/src/tv_video.vhd index 254036a..f96debf 100644 --- a/cores/sms/src/tv_video.vhd +++ b/cores/sms/src/tv_video.vhd @@ -4,7 +4,7 @@ use IEEE.NUMERIC_STD.ALL; entity tv_video is Port ( - clk8: in STD_LOGIC; + clk8: in std_logic; x: out unsigned(8 downto 0); y: out unsigned(7 downto 0); color: in std_logic_vector(5 downto 0); @@ -25,8 +25,6 @@ architecture Behavioral of tv_video is signal screen_sync: std_logic; signal vbl_sync: std_logic; - signal line_visible: std_logic; - signal line_even: std_logic; signal hblank: std_logic; signal vblank: std_logic; signal visible: boolean; @@ -65,8 +63,6 @@ begin y <= y9(7 downto 0); vblank <= '1' when hcount=0 and vcount=0 else '0'; hblank <= '1' when hcount=0 else '0'; - line_visible <= not in_vbl; - line_even <= not vcount(0); process (vcount,hcount) begin @@ -86,21 +82,11 @@ begin end if; end if; end process; - - --process (in_vbl,screen_sync,vbl_sync) - --begin - -- if in_vbl='1' then - -- hsync <= vbl_sync; - -- else - -- hsync <= screen_sync; - -- end if; - --end process; - --vsync <= '1'; - + hsync <= not screen_sync when in_vbl='0' else '0'; vsync <= not vbl_sync when in_vbl='1' else '0'; - visible <= (line_visible = '1' and vcount>=33 and vcount<453); + visible <= (hcount>=166 and hcount<422 and vcount>=40 and vcount<232); process (clk8) begin From fe36c5e212f89a6c86dba043cb33df0fca17b7ee Mon Sep 17 00:00:00 2001 From: phoboz Date: Sun, 25 Dec 2016 22:03:24 +0100 Subject: [PATCH 07/13] Added scandoubler_disable option --- cores/sms/src/sms_mist.vhd | 4 +++- cores/sms/src/user_io.v | 10 ++++++---- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/cores/sms/src/sms_mist.vhd b/cores/sms/src/sms_mist.vhd index c2b8359..1f5d121 100644 --- a/cores/sms/src/sms_mist.vhd +++ b/cores/sms/src/sms_mist.vhd @@ -143,6 +143,7 @@ architecture Behavioral of sms_mist is status: out std_logic_vector(7 downto 0); SWITCHES : out std_logic_vector(1 downto 0); BUTTONS : out std_logic_vector(1 downto 0); + scandoubler_disable : out std_logic; -- clk : in std_logic; ps2_clk : out std_logic; ps2_data : out std_logic @@ -299,7 +300,7 @@ begin vs_out => sd_vs ); - scandoubler_disable <= '1'; + --scandoubler_disable <= '1'; VGA_HS <= not(hs xor vs) when scandoubler_disable = '1' else sd_hs; VGA_VS <= '1' when scandoubler_disable = '1' else sd_vs; @@ -392,6 +393,7 @@ begin JOY1 => joy1, SWITCHES => switches, BUTTONS => buttons, + scandoubler_disable => scandoubler_disable, -- clk => open, ps2_clk => open, ps2_data => open diff --git a/cores/sms/src/user_io.v b/cores/sms/src/user_io.v index 3f534c9..5307ec3 100644 --- a/cores/sms/src/user_io.v +++ b/cores/sms/src/user_io.v @@ -34,8 +34,9 @@ module user_io #(parameter STRLEN=0) ( output [5:0] JOY1, output [1:0] BUTTONS, output [1:0] SWITCHES, - - output reg [7:0] status, + output scandoubler_disable, + + output reg [7:0] status, input clk, output ps2_clk, @@ -48,12 +49,13 @@ reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... reg [7:0] byte_cnt; // counts bytes reg [5:0] joystick0; reg [5:0] joystick1; -reg [3:0] but_sw; +reg [4:0] but_sw; assign JOY0 = joystick0; assign JOY1 = joystick1; assign BUTTONS = but_sw[1:0]; assign SWITCHES = but_sw[3:2]; +assign scandoubler_disable = but_sw[4]; // this variant of user_io is for 8 bit cores (type == a4) only wire [7:0] core_type = 8'ha4; @@ -164,7 +166,7 @@ always@(posedge SPI_CLK or posedge SPI_SS_IO) begin if(byte_cnt != 0) begin if(cmd == 8'h01) - but_sw <= { sbuf[2:0], SPI_MOSI }; + but_sw <= { sbuf[3:0], SPI_MOSI }; if(cmd == 8'h02) joystick0 <= { sbuf[4:0], SPI_MOSI }; From 6be111a3f11166f20f13485ef685c60b8020e52f Mon Sep 17 00:00:00 2001 From: phoboz Date: Sun, 25 Dec 2016 22:57:59 +0100 Subject: [PATCH 08/13] Added option scanlines: off, on --- cores/sms/src/sms_mist.vhd | 26 ++++++-------------------- 1 file changed, 6 insertions(+), 20 deletions(-) diff --git a/cores/sms/src/sms_mist.vhd b/cores/sms/src/sms_mist.vhd index 1f5d121..98fd1b8 100644 --- a/cores/sms/src/sms_mist.vhd +++ b/cores/sms/src/sms_mist.vhd @@ -67,20 +67,6 @@ architecture Behavioral of sms_mist is vs_out: out std_logic ); end component; - - component vga_video is - port ( - clk16: in std_logic; - pal: in std_logic; - x: out unsigned(8 downto 0); - y: out unsigned(7 downto 0); - color: in std_logic_vector(5 downto 0); - hsync: out std_logic; - vsync: out std_logic; - red: out std_logic_vector(1 downto 0); - green: out std_logic_vector(1 downto 0); - blue: out std_logic_vector(1 downto 0)); - end component; component tv_video is port ( @@ -115,7 +101,7 @@ architecture Behavioral of sms_mist is ); end component; - constant CONF_STR : string := "SMS;SMS;O1,Video,NTSC,PAL;O2,Joysticks,Normal,Swapped;T3,Pause;T4,Reset"; + constant CONF_STR : string := "SMS;SMS;O1,Video,NTSC,PAL;O2,Scanlines,Off,On;O3,Joysticks,Normal,Swapped;T4,Pause;T5,Reset"; function to_slv(s: string) return std_logic_vector is constant ss: string(1 to s'length) := s; @@ -287,7 +273,7 @@ begin port map( clk_in => clk_cpu, clk_out => clk16, - scanlines => '0', + scanlines => status(2), hs_in => hs, vs_in => vs, r_in => video_r, @@ -400,8 +386,8 @@ begin ); -- joysticks can be swapped - joya <= joy1 when status(2)='0' else joy0; - joyb <= joy0 when status(2)='0' else joy1; + joya <= joy1 when status(3)='0' else joy0; + joyb <= joy0 when status(3)='0' else joy1; system_inst: work.system port map ( @@ -426,8 +412,8 @@ begin j2_right => not joyb(0), j2_tl => not joyb(4), j2_tr => not joyb(5), - reset => not buttons(1) and not status(4) and not status(0) and pll_locked and reset_n, - pause => not status(3), + reset => not buttons(1) and not status(5) and not status(0) and pll_locked and reset_n, + pause => not status(4), -- video x => x, From 826c36bebd1cf64d3b4999c260081a5974096da1 Mon Sep 17 00:00:00 2001 From: phoboz Date: Mon, 26 Dec 2016 23:16:49 +0100 Subject: [PATCH 09/13] Added PAL video mode --- cores/sms/sms_mist.qsf | 3 +- .../sms/src/{tv_video.vhd => ntsc_video.vhd} | 16 ++- cores/sms/src/pal_video.vhd | 116 ++++++++++++++++++ cores/sms/src/sms_mist.vhd | 19 ++- 4 files changed, 141 insertions(+), 13 deletions(-) rename cores/sms/src/{tv_video.vhd => ntsc_video.vhd} (87%) create mode 100644 cores/sms/src/pal_video.vhd diff --git a/cores/sms/sms_mist.qsf b/cores/sms/sms_mist.qsf index a3ac008..c427e33 100644 --- a/cores/sms/sms_mist.qsf +++ b/cores/sms/sms_mist.qsf @@ -318,8 +318,9 @@ set_global_assignment -name ENABLE_SIGNALTAP ON set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name VHDL_FILE src/pal_video.vhd +set_global_assignment -name VHDL_FILE src/ntsc_video.vhd set_global_assignment -name VERILOG_FILE src/scandoubler.v -set_global_assignment -name VHDL_FILE src/tv_video.vhd set_global_assignment -name VERILOG_FILE src/data_io.v set_global_assignment -name VERILOG_FILE src/osd.v set_global_assignment -name VERILOG_FILE src/user_io.v diff --git a/cores/sms/src/tv_video.vhd b/cores/sms/src/ntsc_video.vhd similarity index 87% rename from cores/sms/src/tv_video.vhd rename to cores/sms/src/ntsc_video.vhd index f96debf..5de7ede 100644 --- a/cores/sms/src/tv_video.vhd +++ b/cores/sms/src/ntsc_video.vhd @@ -2,7 +2,7 @@ library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; -entity tv_video is +entity ntsc_video is Port ( clk8: in std_logic; x: out unsigned(8 downto 0); @@ -13,9 +13,9 @@ entity tv_video is red: out std_logic_vector(1 downto 0); green: out std_logic_vector(1 downto 0); blue: out std_logic_vector(1 downto 0)); -end tv_video; +end ntsc_video; -architecture Behavioral of tv_video is +architecture Behavioral of ntsc_video is signal hcount: unsigned(8 downto 0) := (others => '0'); signal vcount: unsigned(8 downto 0) := (others => '0'); @@ -24,9 +24,7 @@ architecture Behavioral of tv_video is signal in_vbl: std_logic; signal screen_sync: std_logic; signal vbl_sync: std_logic; - - signal hblank: std_logic; - signal vblank: std_logic; + signal visible: boolean; begin @@ -61,8 +59,8 @@ begin x <= hcount-166; y9 <= vcount-40; y <= y9(7 downto 0); - vblank <= '1' when hcount=0 and vcount=0 else '0'; - hblank <= '1' when hcount=0 else '0'; + --vblank <= '1' when hcount=0 and vcount=0 else '0'; + --hblank <= '1' when hcount=0 else '0'; process (vcount,hcount) begin @@ -86,7 +84,7 @@ begin hsync <= not screen_sync when in_vbl='0' else '0'; vsync <= not vbl_sync when in_vbl='1' else '0'; - visible <= (hcount>=166 and hcount<422 and vcount>=40 and vcount<232); + visible <= (hcount>=164 and hcount<420 and vcount>=60 and vcount<252); process (clk8) begin diff --git a/cores/sms/src/pal_video.vhd b/cores/sms/src/pal_video.vhd new file mode 100644 index 0000000..b9d662c --- /dev/null +++ b/cores/sms/src/pal_video.vhd @@ -0,0 +1,116 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity pal_video is + Port ( + clk8: in std_logic; + x: out unsigned(8 downto 0); + y: out unsigned(7 downto 0); + color: in std_logic_vector(5 downto 0); + hsync: out std_logic; + vsync: out std_logic; + red: out std_logic_vector(1 downto 0); + green: out std_logic_vector(1 downto 0); + blue: out std_logic_vector(1 downto 0)); +end pal_video; + +architecture Behavioral of pal_video is + + signal hcount: unsigned(8 downto 0) := (others => '0'); + signal vcount: unsigned(8 downto 0) := (others => '0'); + signal y9: unsigned(8 downto 0); + + signal in_vbl: std_logic; + signal screen_sync: std_logic; + signal vbl_sync: std_logic; + + signal visible: boolean; + +begin + + process (clk8) + begin + if rising_edge(clk8) then + if hcount=511 then + hcount <= (others => '0'); + if vcount=311 then + vcount <= (others=>'0'); + else + vcount <= vcount + 1; + end if; + else + hcount <= hcount + 1; + end if; + end if; + end process; + + process (hcount) + begin + if hcount<37 then + screen_sync <= '0'; + else + screen_sync <= '1'; + end if; + end process; + + process (vcount) + begin + if vcount>=5 and vcount<309 then + in_vbl <= '0'; + else + in_vbl <= '1'; + end if; + end process; + + x <= hcount-164; + y9 <= vcount-64 when vcount<256 else (others=>'1'); + y <= y9(7 downto 0); + --vblank <= '1' when hcount=0 and vcount=0 else '0'; + --hblank <= '1' when hcount=0 else '0'; + + process (vcount,hcount) + begin + if vcount<2 then + if hcount<240 or (hcount>=256 and hcount<496) then + vbl_sync <= '0'; + else + vbl_sync <= '1'; + end if; + elsif vcount=2 then + if hcount<240 or (hcount>=256 and hcount<272) then + vbl_sync <= '0'; + else + vbl_sync <= '1'; + end if; + else + if hcount<16 or (hcount>=256 and hcount<272) then + vbl_sync <= '0'; + else + vbl_sync <= '1'; + end if; + end if; + end process; + + hsync <= not screen_sync when in_vbl='0' else '0'; + vsync <= not vbl_sync when in_vbl='1' else '0'; + + visible <= (hcount>=166 and hcount<422 and vcount>=64 and vcount<256); + + process (clk8) + begin + if rising_edge(clk8) then + if visible then + red <= color(1 downto 0); + green <= color(3 downto 2); + blue <= color(5 downto 4); + else + red <= (others=>'0'); + green <= (others=>'0'); + blue <= (others=>'0'); + end if; + end if; + end process; + +end Behavioral; + diff --git a/cores/sms/src/sms_mist.vhd b/cores/sms/src/sms_mist.vhd index 98fd1b8..348ae56 100644 --- a/cores/sms/src/sms_mist.vhd +++ b/cores/sms/src/sms_mist.vhd @@ -68,7 +68,7 @@ architecture Behavioral of sms_mist is ); end component; - component tv_video is + component ntsc_video is port ( clk8: in std_logic; x: out unsigned(8 downto 0); @@ -80,7 +80,20 @@ architecture Behavioral of sms_mist is green: out std_logic_vector(1 downto 0); blue: out std_logic_vector(1 downto 0)); end component; - + + component pal_video is + port ( + clk8: in std_logic; + x: out unsigned(8 downto 0); + y: out unsigned(7 downto 0); + color: in std_logic_vector(5 downto 0); + hsync: out std_logic; + vsync: out std_logic; + red: out std_logic_vector(1 downto 0); + green: out std_logic_vector(1 downto 0); + blue: out std_logic_vector(1 downto 0)); + end component; + component sdram is port( sd_data : inout std_logic_vector(15 downto 0); sd_addr : out std_logic_vector(12 downto 0); @@ -250,7 +263,7 @@ begin end if; end process; - video_inst: tv_video + video_inst: pal_video port map ( clk8 => clk_cpu, --pal => status(1), From 17af51979027dfd97d41d54eac6b2e487dc1a85f Mon Sep 17 00:00:00 2001 From: phoboz Date: Mon, 26 Dec 2016 23:26:51 +0100 Subject: [PATCH 10/13] Fixed PAL mode for scandoubler --- cores/sms/src/pal_video.vhd | 11 ++--------- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/cores/sms/src/pal_video.vhd b/cores/sms/src/pal_video.vhd index b9d662c..ed33a82 100644 --- a/cores/sms/src/pal_video.vhd +++ b/cores/sms/src/pal_video.vhd @@ -54,17 +54,10 @@ begin end if; end process; - process (vcount) - begin - if vcount>=5 and vcount<309 then - in_vbl <= '0'; - else - in_vbl <= '1'; - end if; - end process; + in_vbl <= '1' when vcount<5 else '0'; x <= hcount-164; - y9 <= vcount-64 when vcount<256 else (others=>'1'); + y9 <= vcount-64; y <= y9(7 downto 0); --vblank <= '1' when hcount=0 and vcount=0 else '0'; --hblank <= '1' when hcount=0 else '0'; From 304653060c05cc16edf77bebfbf5b66b55f41439 Mon Sep 17 00:00:00 2001 From: phoboz Date: Tue, 27 Dec 2016 00:04:27 +0100 Subject: [PATCH 11/13] Restore option to select between PAL and NTSC --- cores/sms/sms_mist.qsf | 1 + cores/sms/src/ntsc_video.vhd | 2 +- cores/sms/src/sms_mist.vhd | 20 ++----- cores/sms/src/video.vhd | 103 +++++++++++++++++++++++++++++++++++ 4 files changed, 109 insertions(+), 17 deletions(-) create mode 100644 cores/sms/src/video.vhd diff --git a/cores/sms/sms_mist.qsf b/cores/sms/sms_mist.qsf index c427e33..fae0cba 100644 --- a/cores/sms/sms_mist.qsf +++ b/cores/sms/sms_mist.qsf @@ -318,6 +318,7 @@ set_global_assignment -name ENABLE_SIGNALTAP ON set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name VHDL_FILE src/video.vhd set_global_assignment -name VHDL_FILE src/pal_video.vhd set_global_assignment -name VHDL_FILE src/ntsc_video.vhd set_global_assignment -name VERILOG_FILE src/scandoubler.v diff --git a/cores/sms/src/ntsc_video.vhd b/cores/sms/src/ntsc_video.vhd index 5de7ede..9bdb6f6 100644 --- a/cores/sms/src/ntsc_video.vhd +++ b/cores/sms/src/ntsc_video.vhd @@ -84,7 +84,7 @@ begin hsync <= not screen_sync when in_vbl='0' else '0'; vsync <= not vbl_sync when in_vbl='1' else '0'; - visible <= (hcount>=164 and hcount<420 and vcount>=60 and vcount<252); + visible <= (hcount>=164 and hcount<420 and vcount>=40 and vcount<232); process (clk8) begin diff --git a/cores/sms/src/sms_mist.vhd b/cores/sms/src/sms_mist.vhd index 348ae56..49740b8 100644 --- a/cores/sms/src/sms_mist.vhd +++ b/cores/sms/src/sms_mist.vhd @@ -68,22 +68,10 @@ architecture Behavioral of sms_mist is ); end component; - component ntsc_video is - port ( - clk8: in std_logic; - x: out unsigned(8 downto 0); - y: out unsigned(7 downto 0); - color: in std_logic_vector(5 downto 0); - hsync: out std_logic; - vsync: out std_logic; - red: out std_logic_vector(1 downto 0); - green: out std_logic_vector(1 downto 0); - blue: out std_logic_vector(1 downto 0)); - end component; - - component pal_video is + component video is port ( clk8: in std_logic; + pal: in std_logic; x: out unsigned(8 downto 0); y: out unsigned(7 downto 0); color: in std_logic_vector(5 downto 0); @@ -263,10 +251,10 @@ begin end if; end process; - video_inst: pal_video + video_inst: video port map ( clk8 => clk_cpu, - --pal => status(1), + pal => status(1), x => x, y => y, color => color, diff --git a/cores/sms/src/video.vhd b/cores/sms/src/video.vhd new file mode 100644 index 0000000..152f8a4 --- /dev/null +++ b/cores/sms/src/video.vhd @@ -0,0 +1,103 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; +use IEEE.NUMERIC_STD.ALL; + +entity video is + Port ( + clk8: in std_logic; + pal: in std_logic; + x: out unsigned(8 downto 0); + y: out unsigned(7 downto 0); + color: in std_logic_vector(5 downto 0); + hsync: out std_logic; + vsync: out std_logic; + red: out std_logic_vector(1 downto 0); + green: out std_logic_vector(1 downto 0); + blue: out std_logic_vector(1 downto 0)); +end video; + +architecture Behavioral of video is + + component ntsc_video is + port ( + clk8: in std_logic; + x: out unsigned(8 downto 0); + y: out unsigned(7 downto 0); + color: in std_logic_vector(5 downto 0); + hsync: out std_logic; + vsync: out std_logic; + red: out std_logic_vector(1 downto 0); + green: out std_logic_vector(1 downto 0); + blue: out std_logic_vector(1 downto 0)); + end component; + + component pal_video is + port ( + clk8: in std_logic; + x: out unsigned(8 downto 0); + y: out unsigned(7 downto 0); + color: in std_logic_vector(5 downto 0); + hsync: out std_logic; + vsync: out std_logic; + red: out std_logic_vector(1 downto 0); + green: out std_logic_vector(1 downto 0); + blue: out std_logic_vector(1 downto 0)); + end component; + + signal ntsc_x: unsigned(8 downto 0); + signal ntsc_y: unsigned(7 downto 0); + signal ntsc_hsync: std_logic; + signal ntsc_vsync: std_logic; + signal ntsc_red: std_logic_vector(1 downto 0); + signal ntsc_green: std_logic_vector(1 downto 0); + signal ntsc_blue: std_logic_vector(1 downto 0); + + signal pal_x: unsigned(8 downto 0); + signal pal_y: unsigned(7 downto 0); + signal pal_hsync: std_logic; + signal pal_vsync: std_logic; + signal pal_red: std_logic_vector(1 downto 0); + signal pal_green: std_logic_vector(1 downto 0); + signal pal_blue: std_logic_vector(1 downto 0); + +begin + + x <= pal_x when pal='1' else ntsc_x; + y <= pal_y when pal='1' else ntsc_y; + + hsync <= pal_hsync when pal='1' else ntsc_hsync; + vsync <= pal_vsync when pal='1' else ntsc_vsync; + red <= pal_red when pal='1' else ntsc_red; + green <= pal_green when pal='1' else ntsc_green; + blue <= pal_blue when pal='1' else ntsc_blue; + + ntsc_inst: ntsc_video + port map ( + clk8 => clk8, + x => ntsc_x, + y => ntsc_y, + color => color, + + hsync => ntsc_hsync, + vsync => ntsc_vsync, + red => ntsc_red, + green => ntsc_green, + blue => ntsc_blue + ); + + pal_inst: pal_video + port map ( + clk8 => clk8, + x => pal_x, + y => pal_y, + color => color, + + hsync => pal_hsync, + vsync => pal_vsync, + red => pal_red, + green => pal_green, + blue => pal_blue + ); + +end Behavioral; + From 99fd0adc40751883c1cd7801e4dc305c9029bb70 Mon Sep 17 00:00:00 2001 From: phoboz Date: Tue, 27 Dec 2016 19:21:44 +0100 Subject: [PATCH 12/13] Fixed interferrance: only send clock pulses to active video generator --- cores/sms/src/video.vhd | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/cores/sms/src/video.vhd b/cores/sms/src/video.vhd index 152f8a4..370d23a 100644 --- a/cores/sms/src/video.vhd +++ b/cores/sms/src/video.vhd @@ -44,6 +44,7 @@ architecture Behavioral of video is blue: out std_logic_vector(1 downto 0)); end component; + signal ntsc_clk: std_logic; signal ntsc_x: unsigned(8 downto 0); signal ntsc_y: unsigned(7 downto 0); signal ntsc_hsync: std_logic; @@ -52,6 +53,7 @@ architecture Behavioral of video is signal ntsc_green: std_logic_vector(1 downto 0); signal ntsc_blue: std_logic_vector(1 downto 0); + signal pal_clk: std_logic; signal pal_x: unsigned(8 downto 0); signal pal_y: unsigned(7 downto 0); signal pal_hsync: std_logic; @@ -62,6 +64,9 @@ architecture Behavioral of video is begin + ntsc_clk <= '0' when pal='1' else clk8; + pal_clk <= clk8 when pal='1' else '0'; + x <= pal_x when pal='1' else ntsc_x; y <= pal_y when pal='1' else ntsc_y; @@ -73,7 +78,7 @@ begin ntsc_inst: ntsc_video port map ( - clk8 => clk8, + clk8 => ntsc_clk, x => ntsc_x, y => ntsc_y, color => color, @@ -87,7 +92,7 @@ begin pal_inst: pal_video port map ( - clk8 => clk8, + clk8 => pal_clk, x => pal_x, y => pal_y, color => color, From bd43e36e8ea573a571633a867d084030db8872fd Mon Sep 17 00:00:00 2001 From: phoboz Date: Wed, 28 Dec 2016 21:14:32 +0100 Subject: [PATCH 13/13] Fixed rolling OSD in 15 kHz mode, proper separation of vsync and hsync --- cores/sms/src/ntsc_video.vhd | 21 +++++++++++++-------- cores/sms/src/pal_video.vhd | 25 ++++++++++++++++--------- 2 files changed, 29 insertions(+), 17 deletions(-) diff --git a/cores/sms/src/ntsc_video.vhd b/cores/sms/src/ntsc_video.vhd index 9bdb6f6..51297eb 100644 --- a/cores/sms/src/ntsc_video.vhd +++ b/cores/sms/src/ntsc_video.vhd @@ -23,7 +23,8 @@ architecture Behavioral of ntsc_video is signal in_vbl: std_logic; signal screen_sync: std_logic; - signal vbl_sync: std_logic; + signal vbl_vsync: std_logic; + signal vbl_hsync: std_logic; signal visible: boolean; @@ -67,22 +68,26 @@ begin if vcount<3 or (vcount>=6 and vcount<9) then -- _^^^^^_^^^^^ : low pulse = 2.35us if hcount<19 or (hcount>=254 and hcount<254+19) then - vbl_sync <= '0'; + vbl_hsync <= '0'; + vbl_vsync <= '0'; else - vbl_sync <= '1'; + vbl_hsync <= '1'; + vbl_vsync <= '0'; end if; else -- ____^^ : high pulse = 4.7us if hcount<(254-38) or (hcount>=254 and hcount<508-38) then - vbl_sync <= '0'; + vbl_vsync <= '0'; + vbl_hsync <= '0'; else - vbl_sync <= '1'; + vbl_vsync <= '1'; + vbl_hsync <= '0'; end if; end if; end process; - - hsync <= not screen_sync when in_vbl='0' else '0'; - vsync <= not vbl_sync when in_vbl='1' else '0'; + + hsync <= not screen_sync when in_vbl='0' else vbl_hsync; + vsync <= not vbl_vsync when in_vbl='1' else '0'; visible <= (hcount>=164 and hcount<420 and vcount>=40 and vcount<232); diff --git a/cores/sms/src/pal_video.vhd b/cores/sms/src/pal_video.vhd index ed33a82..1fe7c1c 100644 --- a/cores/sms/src/pal_video.vhd +++ b/cores/sms/src/pal_video.vhd @@ -23,7 +23,8 @@ architecture Behavioral of pal_video is signal in_vbl: std_logic; signal screen_sync: std_logic; - signal vbl_sync: std_logic; + signal vbl_hsync: std_logic; + signal vbl_vsync: std_logic; signal visible: boolean; @@ -66,27 +67,33 @@ begin begin if vcount<2 then if hcount<240 or (hcount>=256 and hcount<496) then - vbl_sync <= '0'; + vbl_vsync <= '0'; + vbl_hsync <= '0'; else - vbl_sync <= '1'; + vbl_vsync <= '1'; + vbl_hsync <= '0'; end if; elsif vcount=2 then if hcount<240 or (hcount>=256 and hcount<272) then - vbl_sync <= '0'; + vbl_hsync <= '0'; + vbl_vsync <= '0'; else - vbl_sync <= '1'; + vbl_hsync <= '1'; + vbl_vsync <= '0'; end if; else if hcount<16 or (hcount>=256 and hcount<272) then - vbl_sync <= '0'; + vbl_hsync <= '0'; + vbl_vsync <= '0'; else - vbl_sync <= '1'; + vbl_hsync <= '1'; + vbl_vsync <= '0'; end if; end if; end process; - hsync <= not screen_sync when in_vbl='0' else '0'; - vsync <= not vbl_sync when in_vbl='1' else '0'; + hsync <= not screen_sync when in_vbl='0' else vbl_hsync; + vsync <= not vbl_vsync when in_vbl='1' else '0'; visible <= (hcount>=166 and hcount<422 and vcount>=64 and vcount<256);