diff --git a/cores/c16/README.txt b/cores/c16/README.txt
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index 0000000..914251f
--- /dev/null
+++ b/cores/c16/README.txt
@@ -0,0 +1,117 @@
+FPGATED v1.0
+Copyright 2013-2016 Istvan Hegedus
+MiST port by Till Harbaum
+
+FPGATED is a cycle exact FPGA core for the MOS 7360/8360 TED chip written in verilog language.
+MOS 7360/8360 is complex chip providing graphic, sound, bus and memory control for the Commodore 264
+series 8 bit computers, namely the Commodore Plus4, Commodore 16 and Commodore 116.
+
+In addition to the TED core modul FPGATED contains a simple C16 implementation using TED core and Gadget Factory's 
+Papilio One 500k platform with a customized IO wing called Papilio TEDWing. The 6502 CPU core of C16 is created by 
+Peter Wendrich in vhdl and is taken from the FPGA64 project with the permission of the author.
+
+For more technical details and building Papilio TEDWing module visit https://hackaday.io/project/11460-fpgated
+
+Files
+
+basic_rom.v		C16/Plus4 Basic rom module
+c16.v			This is the TOP module of FPGATED implementing a C16 computer
+c16_testbench.v		C16 testbench for simulation
+c16_keymatrix.v		C16/Plus4 keyboard matrix emulation module
+colors_to_rgb.v		TED color code conversion module to 12bit RGB values
+cpu65xx_e.vhd		6502 core vhdl header
+cpu65xx_fast.vhd	6502 core vhdl code
+dram.v			DRAM module for internal FPGA SRAM memory implementation
+kernal_rom.v		C16/Plus4 Kernal rom module
+mos6529.v		MOS 6529 IO chip emulation module
+mos8501.v		MOS 8501 CPU shell for 6502 core
+palclockgen.v		Xilinx DCM module for PAL system clock signal
+ps2receiver.v		PS2 keyboard receiver module
+ram.v			Simulated RAM for testbench
+ted.v			MOS 7360/8360 FPGA core
+
+basic.hex		C16/Plus4 BASIC rom hexadecimal dump
+Diag264_NTSC.hex	Diag264 NTSC kernal hexadecimal dump
+Diag264_PAL.hex		Diag264 PAL kernal hexadecimal dump
+kernal_NTSC.hex		C16/Plus4 NTSC Kernal rom hexadecimal dump
+kernal_PAL.hex		C16/PLus4 PAL Kernal rom hexadecimal dump
+
+TEDwing.ucf		Xilinx ucf file for Papilio TEDwing
+bin2hex.pl		Perl script for creating hex dump of binary rom image files
+  
+c16_PAL.bit		A compiled PAL FPGATED core for Papilio platform using FPGATED wing
+
+
+Installation instructions are for Xilinx FPGA platforms but the source files with the exception of palclockgen.v
+and Xilinx ucf files can be used for other vendor's FPGAs. 
+Some modules are using Xilinx specific (* RAM_STYLE="BLOCK" *) directive for forcing the synthesis tool to 
+use FPGA internal block ram for certain arrays. In case of other vendor's FPGAs see vendor specific documentation
+for generating block ram.
+
+Building FPGATED on the Papilio Platform requires a suitable wing. One can use the Arcade megawing but it lacks
+external memory and IEC bus for peripherial connections. Thus I recommend to build TEDwing designed by me. Look for
+eagle PCB and schematic files in FPGATED source package.
+Although FPGATED can be synthetised to a Papilio One board using Spartan3E chip, I recommend to go for Papilio Pro
+platform which has external 8Mbyte SDRAM and a Spartan 6 LX9 FPGA which has more internal sram. In both cases there
+are plenty of free resources on the FPGA for FPGATED (if you use external 64k ram).
+
+Installation instructions:
+
+1. Create a new project in Xilinx ISE Webpack and choose the proper FPGA family for the implementation.
+2. Choose to use HDL verilog and vhdl for the design.
+3. Add all *.v files to the project
+4. Using ISE DCM wizard create a clock generator for FPGATED. 
+   Use CLKFX output of DCM and specify 28.37515MHz PAL or 28.63636MHz for NTSC system
+   This will be the main FPGA clock connected to the clk signal of all modules
+   Modify C16.v to use proper DCM instantiation (out of scope of this document)
+5. Open kernal_rom.v and uncomment the proper Kernal file (Kernal_NTSC.hex or Kernal_PAL.hex) to use.
+   You can even use a custom rom or JiffyDos if you own it (JiffyDos is working fine, I have tested).
+   Diag264 roms are included for testing purposes.
+6. If you don't use TEDwing modify or replace TEDwing.ucf file for proper pinout setup
+7. Video output of FPGATED is a PAL/NTSC RGBS signal so you will need a VGA->scart custom cable to
+   hook it up to a monitor or television. The cable is identical to minimig scart cables (see internet for wiring diagram)
+
+Enjoy FPGATED.
+
+See https://hackaday.io/project/11460-fpgated for detailed installation instructions.
+
+TED module signals:
+
+ input wire clk			main FPGA clock must be 4*dot clk so 28.375152MHz for PAL and 28.63636 for NTSC 
+ input wire [15:0] addr_in	16 bits address bus in
+ output wire [15:0] addr_out	16 bits address bus out
+ input wire [7:0] data_in	8 bits data bus in
+ output wire [7:0] data_out	8 bits data bus out
+ input wire rw			RW signal to TED, low during write, high during read (real TED pulls it high during reads)
+ output wire cpuclk		this is a CPU clock out for external real CPU
+ output wire [6:0] color	7 bits color code using TED's color palette values
+ output wire csync		composite sync signal for PAL/NTSC displays
+ output wire irq		active low IRQ signal to CPU
+ output wire ba			BA (or with other name RDY) signal to 8501 CPU 
+ output reg mux			MUX signal, identical to original
+ output reg ras			RAS signal, identical to original
+ output reg cas			CAS signal, identical to original
+ output reg cs0			CS0 signal, identical to original
+ output reg cs1			CS1 signal, identical to original
+ output reg aec			AEC signal, identical to original
+ output wire snd		Sound output. PWM modulated sound, needs a low pass filter outside the FPGA
+ input wire [7:0] k		Keyport in, same as in original TED
+ output wire cpuenable		a short enable signal used for synchronous FPGA 6502 CPU clocking
+
+
+Still to do:
+
+FPGATED is not ready yet. I just released it in this state because I did not want to keep it in a secret longer before someone else
+creates it. I have plans to continue.
+
+- write a plus4 shell using Papilio Pro platform
+- Jostick emulation on keyboard (as TEDwing doesn't have joystick ports) 
+- scandoubler for VGA displays
+- fix internal video shift mechanism for proper FLI emulation
+- Chorma/Luma signal generation
+- Try it in a real C16 or Plus4!
+
+Contact: hegedusis@t-online.hu
+
+Special Thanks to Levente Harsfalvi for the technical information on TED sound generators and for some other important hints!
+Thanks to Laszlo Jozsef for the color conversion table and the Spartan6 board that I have never had time to build...
diff --git a/cores/c16/basic.hex b/cores/c16/basic.hex
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index 0000000..9711fc1
--- /dev/null
+++ b/cores/c16/basic.hex
@@ -0,0 +1,16384 @@
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diff --git a/cores/c16/basic_rom.v b/cores/c16/basic_rom.v
new file mode 100644
index 0000000..321597e
--- /dev/null
+++ b/cores/c16/basic_rom.v
@@ -0,0 +1,63 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+//  Copyright 2013-2016 Istvan Hegedus
+//
+//  FPGATED is free software: you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation, either version 3 of the License, or
+//  (at your option) any later version.
+//
+//  FPGATED is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program.  If not, see <http://www.gnu.org/licenses/>. 
+//
+// Create Date:    22:20:09 12/09/2014 
+// Module Name:    basic_rom.v 
+// Project Name: 	 FPGATED
+// Target Devices: Xilinx Spartan 3E
+//
+// Description: 
+//		Basic ROM synthetised to FPGA's internal SRAM. Xilinx ISE requires 
+//		ROM_STYLE="BLOCK" parameter next to kernal array. For other vendor's
+//		device syntax refer to the FPGA vendor's documentation.
+// 
+//
+// Dependencies: 
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module basic_rom(
+    input wire clk,
+    input wire [13:0] address_in,
+    output wire [7:0] data_out,
+    input wire cs
+    );
+
+(* ROM_STYLE="BLOCK" *)
+reg [7:0] basic [0:16383];
+reg [7:0] data;
+reg cs_prev=1'b1;
+wire enable;
+
+always@(posedge clk)
+	if(enable)
+		data<=basic[address_in];
+
+always@(posedge clk)
+	cs_prev<=cs;
+
+assign enable=~cs&cs_prev;		// cs falling edge detection
+assign data_out=(~cs)?data:8'hff;
+
+initial begin
+$readmemh("basic.hex",basic);
+end
+
+endmodule
diff --git a/cores/c16/c16.v b/cores/c16/c16.v
new file mode 100644
index 0000000..193109a
--- /dev/null
+++ b/cores/c16/c16.v
@@ -0,0 +1,263 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+//  Copyright 2013-2016 Istvan Hegedus
+//
+//  FPGATED is free software: you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation, either version 3 of the License, or
+//  (at your option) any later version.
+//
+//  FPGATED is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program.  If not, see <http://www.gnu.org/licenses/>. 
+//
+// 
+// Create Date:    12:02:05 10/24/2014 
+// Design Name: 	 Commodore 16 
+// Module Name:    C16.v
+// Project Name: 	 FPGATED
+//
+// Description: 	
+//	This module provides the top level framework for FPGATED. It implements a Commodore 16 computer without expansion port.
+// It is written for Papilio FPGATED wing 1.x but can be easily modified for any other platforms.
+//
+// Revision: 
+// Revision 0.01 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module C16(
+	input wire CLK28,
+	input wire RESET,
+	input wire WAIT,
+	
+	output wire HSYNC,
+	output wire VSYNC,
+	output wire CSYNC,
+	output wire [3:0] RED,
+	output wire [3:0] GREEN,
+	output wire [3:0] BLUE,
+	
+	output wire RAS,
+	output wire CAS,
+	output wire RW,
+	output wire [7:0] A,
+	input wire [7:0] DIN,
+	output wire [7:0] DOUT,
+	
+	input [4:0] JOY0,
+	input [4:0] JOY1,
+	
+	input PS2DAT,
+	input PS2CLK,
+	
+	output IEC_DATAOUT,
+	input IEC_DATAIN,
+	output IEC_CLKOUT,
+	input IEC_CLKIN,
+	output IEC_ATNOUT,
+	//input IEC_ATNIN,
+	output IEC_RESET,
+	
+	output AUDIO_L,
+	output AUDIO_R,
+	
+	input [13:0] kernal_dl_addr,
+	input [7:0] kernal_dl_data,
+	input kernal_dl_write,
+
+	output PAL,
+	
+	output RS232_TX,
+	output RGBS
+    );
+
+wire [15:0] c16_addr;
+wire [15:0] ted_addr;
+wire [15:0] cpu_addr;
+wire [7:0] c16_data,ted_data,ram_data,cpu_data,basic_data,kernal_data,port_in,port_out,keyport_data;
+wire [7:0] keyboard_row,kbus,kbus_kbd;
+wire [7:0] keyscancode;
+wire keyreceived;
+wire [6:0] c16_color;
+wire mux,cpuenable;
+wire aec,rdy;
+wire keyboardio;
+wire sound;
+reg [7:0] c16_datalatch=8'b0;
+reg sreset=1'b0;
+reg [23:0] resetcounter=24'b0;
+reg [15:0] c16_addrlatch=16'b0;
+wire irq1;
+wire keyreset;
+
+// wire joysticks 
+wire [4:0] joy0_sel = (!c16_data[2])?{!JOY0[4],!JOY0[0],!JOY0[1],!JOY0[2],!JOY0[3]}:5'h1f;
+wire [4:0] joy1_sel = (!c16_data[1])?{!JOY1[4],!JOY1[0],!JOY1[1],!JOY1[2],!JOY1[3]}:5'h1f;
+assign kbus[3:0] = kbus_kbd[3:0] & joy0_sel[3:0] & joy1_sel[3:0];
+assign kbus[5:4] = kbus_kbd[5:4]; // no joystick line connected here
+assign kbus[6] = kbus_kbd[6] & joy0_sel[4];
+assign kbus[7] = kbus_kbd[7] & joy1_sel[4];
+
+// 8501 CPU
+	mos8501 cpu (
+		.clk(CLK28), 
+		.reset(sreset), 
+		.enable(cpuenable && !WAIT),  
+		.irq_n(irq_n), 
+		.data_in(c16_data), 
+		.data_out(cpu_data), 
+		.address(cpu_addr),
+		.gate_in(mux),
+		.rw(RW),								// rw=high read, rw=low write
+		.port_in(port_in),
+		.port_out(port_out),
+		.rdy(rdy),
+		.aec(aec)
+	);
+
+// TED 8360 instance	
+
+ted mos8360(
+	.clk(CLK28),
+	.addr_in(c16_addr),
+	.addr_out(ted_addr),
+	.data_in(c16_data),
+	.data_out(ted_data),
+	.rw(RW),
+	.cpuclk(cpuclk),
+	.color(c16_color),
+	.csync(CSYNC),
+	.hsync(HSYNC),
+	.vsync(VSYNC),
+	.irq(irq_n),
+	.ba(rdy),
+	.mux(mux),
+	.ras(RAS),
+	.cas(CAS),
+	.cs0(cs0),
+	.cs1(cs1),
+	.aec(aec),
+	.k(kbus),
+	.snd(sound),
+	.pal(PAL),
+	.cpuenable(cpuenable)
+	);
+	
+// Kernal rom
+
+	kernal_rom kernal(
+		.clk(CLK28),
+		.address_in(sreset?kernal_dl_addr:c16_addr[13:0]),
+		.data_out(kernal_data),
+		.data_in(kernal_dl_data),
+		.wr(kernal_dl_write),
+		.cs(cs1)
+		);
+
+// Basic rom
+
+	basic_rom basic(
+		.clk(CLK28),
+		.address_in(c16_addr[13:0]),
+		.data_out(basic_data),
+		.cs(cs0)
+		);
+
+// Color decoder to 12bit RGB	
+ 
+colors_to_rgb colordecode (
+	.clk(CLK28),
+	.color(c16_color),
+	.red(RED),
+	.green(GREEN),
+	.blue(BLUE)
+	);
+
+// keyboard part
+
+ps2receiver ps2rcv(
+    .clk(CLK28),
+    .ps2_clk(PS2CLK),
+    .ps2_data(PS2DAT),
+    .rx_done(keyreceived),
+    .ps2scancode(keyscancode)
+    );
+
+c16_keymatrix keyboard(
+	 .clk(CLK28),
+    .scancode(keyscancode),
+    .receiveflag(keyreceived),
+	 .row(keyboard_row),
+    .kbus(kbus_kbd),
+	 .keyreset(keyreset)
+    );
+
+mos6529 keyport(
+	 .clk(CLK28),
+    .data_in(c16_data),
+    .data_out(keyport_data),
+    .port_in(keyboard_row),	// keyport 6529 in C16 is unidirectional however if we read it the last written data is read back so we feed back its output.
+    .port_out(keyboard_row),
+    .rw(RW),
+    .cs(keyboardio)
+    );
+	 
+assign AUDIO_R=sound;
+assign AUDIO_L=sound;
+assign RGBS=1'bz;				// VGA/RGBS jumper is not implemented in current version
+assign RS232_TX=1'bz;		// RS232 is not implemented in current version
+
+assign keyboardio=(c16_addr[15:4]==12'hfd3)?1'b1:1'b0;		// as we don't have PLA, keyport is identified here
+
+// C16 additional motherboard functions
+
+
+always @(posedge CLK28)		// reset tries to emulate the length of a real reset
+	begin
+	if(RESET|keyreset) begin		// reset can be triggered by reset button or CTRL+ALT+DEL from keyboard
+		resetcounter<=0;
+		sreset<=1;
+	end else begin
+		if(resetcounter==24'd16777215)
+			sreset<=0;
+		else begin
+			resetcounter<=resetcounter+1;
+			sreset<=1;
+			end
+		end
+	end	
+	
+// assign VSYNC=1'b1; // set scart mode to RGB for TV
+
+assign c16_addr=(~mux)?c16_addrlatch:cpu_addr&ted_addr;																	// C16 address bus
+assign c16_data=(mux)?c16_datalatch:cpu_data&ted_data&ram_data&kernal_data&basic_data&keyport_data;		// C16 data bus
+
+always @(posedge CLK28)							// addres and data bus latching emulates dynamic memory behaviour of these buses 
+	begin
+	c16_datalatch<=c16_data;
+	c16_addrlatch<=c16_addr;
+	end
+
+// external 4464 DRAM signal connections on Papilio FPGATED wing
+
+assign A=(~mux)?c16_addr[15:8]:c16_addr[7:0];	//  DRAM address multiplexer for TMS4464 address lines
+assign DOUT=c16_data;					// only drive external TMS4464 data lines when there is a write cycle
+
+assign ram_data=(RW & ~CAS)?DIN:8'hff;				// internal ram_data should be 0xff when external RAM's data line is in high impedance state
+
+// connect IEC bus
+
+assign IEC_DATAOUT=port_out[0];
+assign port_in[7]=IEC_DATAIN;
+assign IEC_CLKOUT=port_out[1];
+assign port_in[6]=IEC_CLKIN;
+assign IEC_ATNOUT=port_out[2];
+//assign ATN=IEC_ATNIN;
+assign IEC_RESET=sreset;
+
+endmodule
diff --git a/cores/c16/c16_keymatrix.v b/cores/c16/c16_keymatrix.v
new file mode 100644
index 0000000..e8837e7
--- /dev/null
+++ b/cores/c16/c16_keymatrix.v
@@ -0,0 +1,174 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+//  Copyright 2013-2016 Istvan Hegedus
+//
+//  FPGATED is free software: you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation, either version 3 of the License, or
+//  (at your option) any later version.
+//
+//  FPGATED is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program.  If not, see <http://www.gnu.org/licenses/>. 
+//
+// Create Date:    19:38:44 12/16/2015 
+// Module Name:    c16_keymatrix.v
+// Project Name: 	 FPGATED
+//
+// Description: 	C16/Plus4 keyboard matrix emulation for PS2 keyboards.
+//
+// Revisions:
+// 1.0	first release
+//
+//////////////////////////////////////////////////////////////////////////////////
+module c16_keymatrix(
+	 input clk,
+    input [7:0] scancode,
+    input receiveflag,
+	 input [7:0] row,
+    output [7:0] kbus,
+	 output keyreset
+    );
+
+reg releaseflag=0;
+reg extendedflag=0;
+reg [7:0] colsel=0;
+reg key_A=0,key_B=0,key_C=0,key_D=0,key_E=0,key_F=0,key_G=0,key_H=0,key_I=0,key_J=0,key_K=0,key_L=0,key_M=0,key_N=0,key_O=0,key_P=0,key_Q=0,key_R=0,key_S=0,key_T=0,key_U=0,key_V=0,key_W=0,key_X=0,key_Y=0,key_Z=0;
+reg key_1=0,key_2=0,key_3=0,key_4=0,key_5=0,key_6=0,key_7=0,key_8=0,key_9=0,key_0=0,key_del=0,key_return=0,key_help=0,key_F1=0,key_F2=0,key_F3=0,key_AT=0,key_shift=0,key_comma=0,key_dot=0;
+reg key_minus=0,key_colon=0,key_star=0,key_semicolon=0,key_esc=0,key_equal=0,key_plus=0,key_slash=0,key_control=0,key_space=0,key_runstop=0;
+reg key_pound=0,key_down=0,key_up=0,key_left=0,key_right=0,key_home=0,key_commodore=0,key_alt=0;
+wire [7:0] rowsel;
+
+assign rowsel=~row;
+assign keyreset=key_control&key_alt&key_del;
+
+always @(posedge clk)
+	begin
+	if(receiveflag)
+		begin
+		if(scancode==8'hF0)
+			releaseflag<=1;
+		else if (scancode==8'hE0)
+			extendedflag<=1;
+		else 
+			begin
+			releaseflag<=0;
+			if (~extendedflag)					// base code keys
+				begin
+				case(scancode)
+					8'h1C:			key_A<=~releaseflag;
+					8'h32:			key_B<=~releaseflag;
+					8'h21:			key_C<=~releaseflag;
+					8'h23:			key_D<=~releaseflag;
+					8'h24:			key_E<=~releaseflag;
+					8'h2B:			key_F<=~releaseflag;
+					8'h34:			key_G<=~releaseflag;
+					8'h33:			key_H<=~releaseflag;
+					8'h43:			key_I<=~releaseflag;
+					8'h3B:			key_J<=~releaseflag;
+					8'h42:			key_K<=~releaseflag;
+					8'h4B:			key_L<=~releaseflag;
+					8'h3A:			key_M<=~releaseflag;
+					8'h31:			key_N<=~releaseflag;
+					8'h44:			key_O<=~releaseflag;
+					8'h4D:			key_P<=~releaseflag;
+					8'h15:			key_Q<=~releaseflag;
+					8'h2D:			key_R<=~releaseflag;
+					8'h1B:			key_S<=~releaseflag;
+					8'h2C:			key_T<=~releaseflag;
+					8'h3C:			key_U<=~releaseflag;
+					8'h2A:			key_V<=~releaseflag;
+					8'h1D:			key_W<=~releaseflag;
+					8'h22:			key_X<=~releaseflag;
+					8'h35:			key_Y<=~releaseflag;
+					8'h1A:			key_Z<=~releaseflag;
+					8'h69,
+					8'h16:			key_1<=~releaseflag;
+					8'h72,
+					8'h1E:			key_2<=~releaseflag;
+					8'h7A,
+					8'h26:			key_3<=~releaseflag;
+					8'h6B,
+					8'h25:			key_4<=~releaseflag;
+					8'h73,
+					8'h2E:			key_5<=~releaseflag;
+					8'h74,
+					8'h36:			key_6<=~releaseflag;
+					8'h6C,
+					8'h3D:			key_7<=~releaseflag;
+					8'h75,
+					8'h3E:			key_8<=~releaseflag;
+					8'h7D,
+					8'h46:			key_9<=~releaseflag;
+					8'h70,
+					8'h45:			key_0<=~releaseflag;
+					8'h66:			key_del<=~releaseflag;
+					8'h5A:			key_return<=~releaseflag;
+					8'h0C:			key_help<=~releaseflag;
+					8'h05:			key_F1<=~releaseflag;
+					8'h06:			key_F2<=~releaseflag;
+					8'h04:			key_F3<=~releaseflag;
+					8'h54:			key_AT<=~releaseflag;
+					8'h12,
+					8'h59:			key_shift<=~releaseflag;
+					8'h41:			key_comma<=~releaseflag;
+					8'h49:			key_dot<=~releaseflag;
+					8'h7B,
+					8'h4E:			key_minus<=~releaseflag;
+					8'h4C:			key_colon<=~releaseflag;
+					8'h7C,
+					8'h5B:			key_star<=~releaseflag;
+					8'h52:			key_semicolon<=~releaseflag;
+					8'h76:			key_esc<=~releaseflag;
+					8'h5D:			key_equal<=~releaseflag;
+					8'h79,
+					8'h55:			key_plus<=~releaseflag;
+					8'h4A:			key_slash<=~releaseflag;
+					8'h14:			key_control<=~releaseflag;
+					8'h29:			key_space<=~releaseflag;
+					8'h0D:			key_runstop<=~releaseflag;
+					8'h11:			key_alt<=~releaseflag;
+					default:;
+				endcase
+				end
+			else begin									// extended code keys
+				extendedflag<=0;
+				case(scancode)
+					8'h2F:			key_pound<=~releaseflag;
+					8'h72:			key_down<=~releaseflag;
+					8'h75:			key_up<=~releaseflag;
+					8'h6B:			key_left<=~releaseflag;
+					8'h74:			key_right<=~releaseflag;
+					8'h6C:			key_home<=~releaseflag;
+					8'h14:			key_control<=~releaseflag;
+					8'h1F:			key_commodore<=~releaseflag;
+					8'h4A:			key_slash<=~releaseflag;
+					8'h5A:			key_return<=~releaseflag;
+					8'h71:			key_del<=~releaseflag;
+					8'h11:			key_alt<=~releaseflag;
+					default:;
+				endcase
+				end
+			end
+		end
+	end
+
+always @(posedge clk)
+	begin
+	colsel[0]<=(key_del & rowsel[0]) | (key_3 & rowsel[1]) | (key_5 & rowsel[2]) | (key_7 & rowsel[3]) | (key_9 & rowsel[4]) | (key_down & rowsel[5]) | (key_left & rowsel[6]) | (key_1 & rowsel[7]);
+	colsel[1]<=(key_return & rowsel[0]) | (key_W & rowsel[1]) | (key_R & rowsel[2]) | (key_Y & rowsel[3]) | (key_I & rowsel[4]) | (key_P & rowsel[5]) | (key_star & rowsel[6]) | (key_home & rowsel[7]);
+	colsel[2]<=(key_pound & rowsel[0]) | (key_A & rowsel[1]) | (key_D & rowsel[2]) | (key_G & rowsel[3]) | (key_J & rowsel[4]) | (key_L & rowsel[5]) | (key_semicolon & rowsel[6]) | (key_control & rowsel[7]);
+	colsel[3]<=(key_help & rowsel[0]) | (key_4 & rowsel[1]) | (key_6 & rowsel[2]) | (key_8 & rowsel[3]) | (key_0 & rowsel[4]) | (key_up & rowsel[5]) | (key_right & rowsel[6]) | (key_2 & rowsel[7]);
+	colsel[4]<=(key_F1 & rowsel[0]) | (key_Z & rowsel[1]) | (key_C & rowsel[2]) | (key_B & rowsel[3]) | (key_M & rowsel[4]) | (key_dot & rowsel[5]) | (key_esc & rowsel[6]) | (key_space & rowsel[7]);
+	colsel[5]<=(key_F2 & rowsel[0]) | (key_S & rowsel[1]) | (key_F & rowsel[2]) | (key_H & rowsel[3]) | (key_K & rowsel[4]) | (key_colon & rowsel[5]) | (key_equal & rowsel[6]) | (key_commodore & rowsel[7]);
+	colsel[6]<=(key_F3 & rowsel[0]) | (key_E & rowsel[1]) | (key_T & rowsel[2]) | (key_U & rowsel[3]) | (key_O & rowsel[4]) | (key_minus & rowsel[5]) | (key_plus & rowsel[6]) | (key_Q & rowsel[7]);
+	colsel[7]<=(key_AT & rowsel[0]) | (key_shift & rowsel[1]) | (key_X & rowsel[2]) | (key_V & rowsel[3]) | (key_N & rowsel[4]) | (key_comma & rowsel[5]) | (key_slash & rowsel[6]) | (key_runstop & rowsel[7]);
+	end
+
+assign kbus=~colsel;
+
+endmodule
diff --git a/cores/c16/c16_mist.qpf b/cores/c16/c16_mist.qpf
new file mode 100644
index 0000000..b724044
--- /dev/null
+++ b/cores/c16/c16_mist.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Web Edition
+# Date created = 09:30:37  July 09, 2015
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "13.1"
+DATE = "09:30:37  July 09, 2015"
+
+# Revisions
+
+PROJECT_REVISION = "c16_mist"
diff --git a/cores/c16/c16_mist.qsf b/cores/c16/c16_mist.qsf
new file mode 100644
index 0000000..a6389c0
--- /dev/null
+++ b/cores/c16/c16_mist.qsf
@@ -0,0 +1,343 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II 64-Bit
+# Version 13.1.4 Build 182 03/12/2014 SJ Full Version
+# Date created = 01:27:30  May 03, 2016
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		C64_MiST_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+
+# Project-Wide Assignments
+# ========================
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:40:24  MAY 17, 2014"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
+set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
+set_global_assignment -name SMART_RECOMPILE ON
+set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON
+
+# Pin & Location Assignments
+# ==========================
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_54 -to CLOCK_27
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_13 -to CONF_DATA0
+set_location_assignment PIN_49 -to SDRAM_A[0]
+set_location_assignment PIN_44 -to SDRAM_A[1]
+set_location_assignment PIN_42 -to SDRAM_A[2]
+set_location_assignment PIN_39 -to SDRAM_A[3]
+set_location_assignment PIN_4 -to SDRAM_A[4]
+set_location_assignment PIN_6 -to SDRAM_A[5]
+set_location_assignment PIN_8 -to SDRAM_A[6]
+set_location_assignment PIN_10 -to SDRAM_A[7]
+set_location_assignment PIN_11 -to SDRAM_A[8]
+set_location_assignment PIN_28 -to SDRAM_A[9]
+set_location_assignment PIN_50 -to SDRAM_A[10]
+set_location_assignment PIN_30 -to SDRAM_A[11]
+set_location_assignment PIN_32 -to SDRAM_A[12]
+set_location_assignment PIN_83 -to SDRAM_DQ[0]
+set_location_assignment PIN_79 -to SDRAM_DQ[1]
+set_location_assignment PIN_77 -to SDRAM_DQ[2]
+set_location_assignment PIN_76 -to SDRAM_DQ[3]
+set_location_assignment PIN_72 -to SDRAM_DQ[4]
+set_location_assignment PIN_71 -to SDRAM_DQ[5]
+set_location_assignment PIN_69 -to SDRAM_DQ[6]
+set_location_assignment PIN_68 -to SDRAM_DQ[7]
+set_location_assignment PIN_86 -to SDRAM_DQ[8]
+set_location_assignment PIN_87 -to SDRAM_DQ[9]
+set_location_assignment PIN_98 -to SDRAM_DQ[10]
+set_location_assignment PIN_99 -to SDRAM_DQ[11]
+set_location_assignment PIN_100 -to SDRAM_DQ[12]
+set_location_assignment PIN_101 -to SDRAM_DQ[13]
+set_location_assignment PIN_103 -to SDRAM_DQ[14]
+set_location_assignment PIN_104 -to SDRAM_DQ[15]
+set_location_assignment PIN_58 -to SDRAM_BA[0]
+set_location_assignment PIN_51 -to SDRAM_BA[1]
+set_location_assignment PIN_85 -to SDRAM_DQMH
+set_location_assignment PIN_67 -to SDRAM_DQML
+set_location_assignment PIN_60 -to SDRAM_nRAS
+set_location_assignment PIN_64 -to SDRAM_nCAS
+set_location_assignment PIN_66 -to SDRAM_nWE
+set_location_assignment PIN_59 -to SDRAM_nCS
+set_location_assignment PIN_33 -to SDRAM_CKE
+set_location_assignment PIN_43 -to SDRAM_CLK
+set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component"
+
+# Classic Timing Assignments
+# ==========================
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+
+# Analysis & Synthesis Assignments
+# ================================
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name TOP_LEVEL_ENTITY c16_mist
+set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
+set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
+set_global_assignment -name SAVE_DISK_SPACE OFF
+
+# Fitter Assignments
+# ==================
+set_global_assignment -name FITTER_EARLY_TIMING_ESTIMATE_MODE OPTIMISTIC
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
+set_global_assignment -name FITTER_EFFORT "AUTO FIT"
+
+# Assembler Assignments
+# =====================
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+
+# SignalTap II Assignments
+# ========================
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
+
+# Power Estimation Assignments
+# ============================
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+
+# Advanced I/O Timing Assignments
+# ===============================
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+
+# ------------------------
+# start ENTITY(C64_MiST)
+
+# Pin & Location Assignments
+# ==========================
+
+# Fitter Assignments
+# ==================
+
+# start DESIGN_PARTITION(Top)
+# ---------------------------
+
+# Incremental Compilation Assignments
+# ===================================
+
+# end DESIGN_PARTITION(Top)
+# -------------------------
+
+# end ENTITY(C64_MiST)
+# ----------------------
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[2]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[3]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[4]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[5]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[6]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[7]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[8]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[9]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[10]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[11]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[12]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[13]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[14]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[15]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[2]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[3]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[4]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[5]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[6]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[7]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[8]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[9]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[10]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[11]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[12]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1]
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE
+set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[0]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[1]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[2]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[3]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[4]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[5]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[6]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[7]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[8]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[9]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[10]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[11]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[6]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[7]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[8]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[9]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[10]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[11]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[12]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[6]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[7]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[8]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[9]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[10]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[11]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[12]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[13]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[14]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[15]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQML
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQMH
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nRAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCAS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nWE
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CKE
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_R[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_G[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[5]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[4]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[3]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[2]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[1]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_B[0]
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_HS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to VGA_VS
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to LED
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_L
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to AUDIO_R
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO
+set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CONF_DATA0
+set_global_assignment -name QIP_FILE pll_ntsc.qip
+set_global_assignment -name QIP_FILE pll_pal.qip
+set_global_assignment -name VERILOG_FILE data_io.v
+set_global_assignment -name VERILOG_FILE sdram.v
+set_global_assignment -name VERILOG_FILE osd.v
+set_global_assignment -name VERILOG_FILE scandoubler.v
+set_global_assignment -name VHDL_FILE cpu65xx_fast.vhd
+set_global_assignment -name VHDL_FILE cpu65xx_e.vhd
+set_global_assignment -name VERILOG_FILE user_io.v
+set_global_assignment -name VERILOG_FILE ted.v
+set_global_assignment -name VERILOG_FILE mos8501.v
+set_global_assignment -name VERILOG_FILE mos6529.v
+set_global_assignment -name VERILOG_FILE kernal_rom.v
+set_global_assignment -name VERILOG_FILE colors_to_rgb.v
+set_global_assignment -name VERILOG_FILE c16_mist.v
+set_global_assignment -name VERILOG_FILE c16_keymatrix.v
+set_global_assignment -name VERILOG_FILE c16.v
+set_global_assignment -name VERILOG_FILE basic_rom.v
+set_global_assignment -name SIGNALTAP_FILE stp1.stp
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/cores/c16/c16_mist.v b/cores/c16/c16_mist.v
new file mode 100644
index 0000000..a62690a
--- /dev/null
+++ b/cores/c16/c16_mist.v
@@ -0,0 +1,601 @@
+//
+// c16_mist.v - C16 for the MiST
+//
+// https://github.com/mist-devel
+// 
+// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
+// 
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or 
+// (at your option) any later version. 
+// 
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of 
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License 
+// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
+//
+
+module c16_mist (
+   input  	 CLOCK_27,
+
+	// LED outputs
+   output 	 LED, // LED Yellow
+	
+   // SDRAM interface
+   inout [15:0]  SDRAM_DQ, // SDRAM Data bus 16 Bits
+   output [12:0] SDRAM_A, // SDRAM Address bus 13 Bits
+   output 	 SDRAM_DQML, // SDRAM Low-byte Data Mask
+   output 	 SDRAM_DQMH, // SDRAM High-byte Data Mask
+   output 	 SDRAM_nWE, // SDRAM Write Enable
+   output 	 SDRAM_nCAS, // SDRAM Column Address Strobe
+   output 	 SDRAM_nRAS, // SDRAM Row Address Strobe
+   output 	 SDRAM_nCS, // SDRAM Chip Select
+   output [1:0]  SDRAM_BA, // SDRAM Bank Address
+   output 	 SDRAM_CLK, // SDRAM Clock
+   output 	 SDRAM_CKE, // SDRAM Clock Enable
+  
+   // SPI interface to arm io controller
+   output 	 SPI_DO,
+   input 	 SPI_DI,
+   input 	 SPI_SCK,
+   input 	 SPI_SS2,
+   input 	 SPI_SS3,
+   input 	 SPI_SS4,
+   input 	 CONF_DATA0, 
+
+   output 	 AUDIO_L, // sigma-delta DAC output left
+   output 	 AUDIO_R, // sigma-delta DAC output right
+
+   output 	 VGA_HS,
+   output 	 VGA_VS,
+   output [5:0]  VGA_R,
+   output [5:0]  VGA_G,
+   output [5:0]  VGA_B
+);
+
+// -------------------------------------------------------------------------
+// ------------------------------ user_io ----------------------------------
+// -------------------------------------------------------------------------
+
+// user_io implements a connection to the io controller and receives various
+// kind of user input from there (keyboard, buttons, mouse). It is also used
+// by the fake SD card to exchange data with the real sd card connected to the
+// io controller
+
+// the configuration string is returned to the io controller to allow
+// it to control the menu on the OSD 
+parameter CONF_STR = {
+        "C16;PRG;",
+        "O2,Scanlines,Off,On;",
+        "O3,Joysticks,Normal,Swapped;",
+        "T4,Reset"
+};
+
+parameter CONF_STR_LEN = 8+20+28+8;
+
+// the status register is controlled by the on screen display (OSD)
+wire [7:0] status;
+wire tv15khz;
+wire scanlines = status[2];
+wire joystick_swap = status[3];
+wire osd_reset = status[4];
+wire [1:0] buttons;
+
+wire [7:0] js0, js1;
+wire [7:0] jsA = joystick_swap?js1:js0;
+wire [7:0] jsB = joystick_swap?js0:js1;
+
+wire ps2_kbd_clk, ps2_kbd_data;
+wire ps2_mouse_clk, ps2_mouse_data;
+
+// generate ps2_clock
+wire ps2_clock = ps2_clk_div[10];  // ~12khz
+reg [10:0] ps2_clk_div;
+always @(posedge clk28)
+	ps2_clk_div <= ps2_clk_div + 7'd1;
+
+// -------------------------------------------------------------------------
+// ---------------- interface to the external sdram ------------------------
+// -------------------------------------------------------------------------
+
+// SDRAM control signals
+assign SDRAM_CKE = 1'b1;
+
+// ram access signals from c16
+wire [15:0] c16_sdram_addr = { c16_a_hi, c16_a_low };
+wire [7:0] c16_sdram_data = c16_dout;
+wire c16_sdram_wr = !c16_cas && !c16_rw;
+wire c16_sdram_oe = !c16_cas &&  c16_rw;
+
+// ram access signals from io controller
+// ioctl_sdram_write
+// ioctl_sdram_addr
+// ioctl_sdram_data
+
+// multiplex c16 and ioctl signals
+wire [15:0] mux_sdram_addr = c16_wait?ioctl_sdram_addr:c16_sdram_addr;
+wire [7:0] mux_sdram_data = c16_wait?ioctl_sdram_data:c16_sdram_data;
+wire mux_sdram_wr = c16_wait?ioctl_sdram_write:c16_sdram_wr;
+wire mux_sdram_oe = c16_wait?1'b0:c16_sdram_oe;
+  
+wire [15:0] sdram_din = { mux_sdram_data, mux_sdram_data };
+wire [24:0] sdram_addr = { 10'h00, mux_sdram_addr[15:1] };   // 64k mapping
+// wire [24:0] sdram_addr = { 12'h00, mux_sdram_addr[13:1] };   // 16k mapping
+wire sdram_wr = mux_sdram_wr;
+wire sdram_oe = mux_sdram_oe;
+wire [1:0] sdram_ds = { mux_sdram_addr[0], !mux_sdram_addr[0] }; 
+
+// only c16 reads from sdram
+wire [15:0] sdram_dout;
+wire [7:0] c16_din = zp_overwrite?zp_ovl_dout:
+	(c16_a_low[0]?sdram_dout[15:8]:sdram_dout[7:0]);
+
+assign SDRAM_CLK = ~clk28;
+
+// synchronize sdram state machine with the ras/cas phases of the c16
+reg last_ras;
+reg [3:0] clkdiv;
+wire clkref = clkdiv[3];
+always @(posedge clk28) begin	
+	if(!c16_ras && last_ras) begin
+		clkdiv <= 4'd0;
+		last_ras <= c16_ras;
+	end else
+		clkdiv <= clkdiv + 4'd1;
+end	
+
+// latch/demultiplex dram address
+reg [7:0] c16_a_low;
+always @(negedge c16_ras)
+	c16_a_low <= c16_a;
+
+reg [7:0] c16_a_hi;
+always @(negedge c16_cas)
+	c16_a_hi <= c16_a;
+
+sdram sdram (
+   // interface to the MT48LC16M16 chip
+   .sd_data        ( SDRAM_DQ                  ),
+   .sd_addr        ( SDRAM_A                   ),
+   .sd_dqm         ( {SDRAM_DQMH, SDRAM_DQML}  ),
+   .sd_cs          ( SDRAM_nCS                 ),
+   .sd_ba          ( SDRAM_BA                  ),
+   .sd_we          ( SDRAM_nWE                 ),
+   .sd_ras         ( SDRAM_nRAS                ),
+   .sd_cas         ( SDRAM_nCAS                ),
+
+   // system interface
+   .clk            ( clk28                     ),
+   .clkref         ( clkref                    ),
+   .init           ( !pll_locked               ),
+
+   // cpu interface
+   .din            ( sdram_din                 ),
+   .addr           ( sdram_addr                ),
+   .we             ( sdram_wr                  ),
+   .oe             ( sdram_oe                  ),
+   .ds             ( sdram_ds                  ),
+   .dout           ( sdram_dout                )
+);
+
+
+// ---------------------------------------------------------------------------------
+// -------------------------------------- reset ------------------------------------
+// ---------------------------------------------------------------------------------
+
+reg [31:0] reset_cnt;
+wire reset = (reset_cnt != 0);
+always @(posedge clk28) begin
+	// long reset on startup and when io controller reboots
+   if(status[0] || !pll_locked)
+		reset_cnt <= 32'd28000000;
+	// short reset on reset button, reset osd or when io controller is
+	// done downloading
+	else if(buttons[1] || osd_reset || rom_download)
+      reset_cnt <= 32'd65536;
+   else if(reset_cnt != 0)
+      reset_cnt <= reset_cnt - 32'd1;
+end
+
+// include user_io module for arm controller communication
+user_io #(.STRLEN(CONF_STR_LEN)) user_io ( 
+      .conf_str       ( CONF_STR       ),
+
+      .SPI_CLK        ( SPI_SCK        ),
+      .SPI_SS_IO      ( CONF_DATA0     ),
+      .SPI_MISO       ( SPI_DO         ),
+      .SPI_MOSI       ( SPI_DI         ),
+
+		.scandoubler_disable ( tv15khz   ),
+		.buttons        ( buttons        ),
+
+		.joystick_0     ( js0            ),
+		.joystick_1     ( js1            ),
+		
+      // ps2 interface
+      .ps2_clk        ( ps2_clock      ),
+      .ps2_kbd_clk    ( ps2_kbd_clk    ),
+      .ps2_kbd_data   ( ps2_kbd_data   ),
+      .ps2_mouse_clk  ( ps2_mouse_clk  ),
+      .ps2_mouse_data ( ps2_mouse_data ),
+
+      .status         ( status         )
+);
+
+
+// ---------------------------------------------------------------------------------
+// ------------------------------ prg memory injection -----------------------------
+// ---------------------------------------------------------------------------------
+
+wire ioctl_wr;
+wire [15:0] ioctl_addr;
+wire [7:0] ioctl_data;
+wire [4:0] ioctl_index;
+wire ioctl_downloading;
+
+wire rom_download = ioctl_downloading && (ioctl_index == 5'd0);
+wire prg_download = ioctl_downloading && (ioctl_index == 5'd1);
+
+// halt cpu when it's done with the current cycle
+reg c16_wait;
+always @(posedge c16_ras) 
+	c16_wait <= prg_download;
+
+data_io data_io (
+      // SPI interface
+      .sck ( SPI_SCK ),
+      .ss  ( SPI_SS2 ),
+      .sdi ( SPI_DI  ),
+			
+      // ram interface
+		.downloading ( ioctl_downloading ),
+      .index ( ioctl_index ),
+      .clk   ( clk28 ),
+      .wr    ( ioctl_wr ),
+      .a     ( ioctl_addr ),
+      .d     ( ioctl_data )
+);
+
+// magic zero page shadow registers to allow the injector to set the
+// basic program end pointers automagically after injection
+reg [15:0] reg_2d;
+reg [15:0] reg_2f;
+reg [15:0] reg_31;
+reg [15:0] reg_ae;
+
+wire zp_2d_sel = c16_sdram_addr == 16'h002d;
+wire zp_2e_sel = c16_sdram_addr == 16'h002e;
+wire zp_2f_sel = c16_sdram_addr == 16'h002f;
+wire zp_30_sel = c16_sdram_addr == 16'h0030;
+wire zp_31_sel = c16_sdram_addr == 16'h0031;
+wire zp_32_sel = c16_sdram_addr == 16'h0032;
+wire zp_ae_sel = c16_sdram_addr == 16'h00ae;
+wire zp_af_sel = c16_sdram_addr == 16'h00af;
+
+wire zp_overwrite = 
+	zp_2d_sel || zp_2e_sel || zp_2f_sel || zp_30_sel ||
+	zp_31_sel || zp_32_sel || zp_ae_sel || zp_af_sel;
+
+reg zp_cas_delay, zp_sel;
+reg zp_dl_delay, zp_dl;
+
+always @(posedge clk28) begin
+	// write pulse one cycle after falling edge of cas to make sure address
+	// is stable
+	zp_cas_delay <= c16_cas;
+	zp_sel <= !c16_cas && zp_cas_delay;
+	zp_dl_delay <= prg_download;
+	zp_dl <= !prg_download && zp_dl_delay;
+
+	if(zp_dl) begin
+		// registers are automatically adjusted at the end of the
+		// download/injection
+		// the registers to be set have been taken from the vice emulator
+		reg_2d <= ioctl_sdram_addr + 16'd1;
+		reg_2f <= ioctl_sdram_addr + 16'd1;
+		reg_31 <= ioctl_sdram_addr + 16'd1;
+		reg_ae <= ioctl_sdram_addr + 16'd1;
+	end else	if(zp_sel && !c16_rw) begin
+		// cpu writes registers
+		if(zp_2d_sel) reg_2d[ 7:0] <= c16_dout;
+		if(zp_2e_sel) reg_2d[15:8] <= c16_dout;
+		if(zp_2f_sel) reg_2f[ 7:0] <= c16_dout;
+		if(zp_30_sel) reg_2f[15:8] <= c16_dout;
+		if(zp_31_sel) reg_31[ 7:0] <= c16_dout;
+		if(zp_32_sel) reg_31[15:8] <= c16_dout;
+		if(zp_ae_sel) reg_ae[ 7:0] <= c16_dout;
+		if(zp_af_sel) reg_ae[15:8] <= c16_dout;
+	end
+end
+	
+wire [7:0] zp_ovl_dout =
+	zp_2d_sel?reg_2d[7:0]:zp_2e_sel?reg_2d[15:8]:
+	zp_2f_sel?reg_2f[7:0]:zp_30_sel?reg_2f[15:8]:
+	zp_31_sel?reg_31[7:0]:zp_32_sel?reg_31[15:8]:
+	zp_ae_sel?reg_ae[7:0]:zp_af_sel?reg_ae[15:8]:
+	8'hff;
+	
+// the address taken from the first to bytes of a prg file tell
+// us where the file is to go in memory
+reg [15:0] ioctl_load_addr /* synthesis noprune */;
+reg 	   ioctl_ram_wr /* synthesis noprune */;
+reg 	ioctl_sdram_write /* synthesis noprune */;
+reg [15:0] ioctl_sdram_addr /* synthesis noprune */;
+reg [7:0] ioctl_sdram_data /* synthesis noprune */;
+  
+always @(negedge c16_ras) begin
+	ioctl_sdram_write <= ioctl_ram_wr;
+
+	if(ioctl_ram_wr) begin
+		ioctl_sdram_addr <= ioctl_load_addr + ioctl_addr - 16'd2;
+		ioctl_sdram_data <= ioctl_data;
+	end
+end
+		
+// address starts counting with 0
+always @(negedge clk28) begin
+	if(ioctl_sdram_write) 
+		ioctl_ram_wr <= 1'b0;
+
+   // data io has a byte for us
+   if(ioctl_wr) begin
+      if(ioctl_addr == 16'h0000)
+			ioctl_load_addr[7:0] <= ioctl_data;
+      else if (ioctl_addr == 16'h0001) 
+			ioctl_load_addr[15:8] <= ioctl_data;
+      else 
+			// io controller sent a new byte. Store it until it can be
+			// saved in RAM
+			ioctl_ram_wr <= 1'b1;
+   end
+end
+
+	
+// ---------------------------------------------------------------------------------
+// ------------------------------ the on screen display ----------------------------
+// ---------------------------------------------------------------------------------
+	
+// in 15khz mode feed the c16 video directly into the OSD,
+// bypassing the scan doubler
+wire [5:0] osd_r_in = tv15khz?{c16_r, 2'b00}:video_r;
+wire [5:0] osd_g_in = tv15khz?{c16_g, 2'b00}:video_g;
+wire [5:0] osd_b_in = tv15khz?{c16_b, 2'b00}:video_b;
+wire osd_hs_in = tv15khz?!c16_hs:video_hs;
+wire osd_vs_in = tv15khz?!c16_vs:video_vs;
+
+wire osd_clk = tv15khz?clk7:clk28;
+
+// include the on screen display
+osd #(11,0,5) osd (
+   .pclk       ( osd_clk     ),
+
+   // spi for OSD
+   .sdi        ( SPI_DI       ),
+   .sck        ( SPI_SCK      ),
+   .ss         ( SPI_SS3      ),
+
+   .red_in     ( osd_r_in     ),
+   .green_in   ( osd_g_in     ),
+   .blue_in    ( osd_b_in     ),
+   .hs_in      ( osd_hs_in    ),
+   .vs_in      ( osd_vs_in    ),
+
+   .red_out    ( VGA_R        ),
+   .green_out  ( VGA_G        ),
+   .blue_out   ( VGA_B        )
+);
+
+// in 15khz tv mode directly use the c16's composite sync. Otherwise the VGA
+// output is driven from the sync signals generated by the scan doubler. In
+// 15khz mode the VS signal is used as the RGB detect signal on the SCART 
+// connector and thus needs to be driven to 1
+assign VGA_HS = tv15khz?c16_cs:video_hs;
+assign VGA_VS = tv15khz?1'b1:video_vs;
+
+wire video_hs, video_vs;
+wire [5:0] video_r;
+wire [5:0] video_g;
+wire [5:0] video_b;
+
+scandoubler scandoubler (
+	// system interface
+	.clk_sys   ( clk28 ),
+
+   // scanlines (00-none 01-25% 10-50% 11-75%)
+   .scanlines ( scanlines?2'b10:2'b00 ),
+
+   // shifter video interface
+   .hs_in     ( !c16_hs ),
+	.vs_in     ( !c16_vs ),
+	.r_in      ( c16_r ),
+	.g_in      ( c16_g ),
+	.b_in      ( c16_b ),
+
+    // output interface
+	.hs_out    ( video_hs ),
+   .vs_out    ( video_vs ),
+   .r_out     ( video_r  ),
+   .g_out     ( video_g  ),
+   .b_out     ( video_b  )
+);
+
+// ---------------------------------------------------------------------------------
+// ------------------------------------ c16 core -----------------------------------
+// ---------------------------------------------------------------------------------
+
+// c16 generated video signals
+wire c16_hs, c16_vs, c16_cs;
+wire [3:0] c16_r;
+wire [3:0] c16_g;
+wire [3:0] c16_b;
+wire c16_pal;
+
+// c16 generated ram access signals
+wire c16_ras;
+wire c16_cas;
+wire c16_rw;
+wire [7:0] c16_a;
+wire [7:0] c16_dout;
+
+reg kernal_dl_wr;
+reg [7:0] kernal_dl_data;
+reg [13:0] kernal_dl_addr;
+
+wire ioctl_kernal_wr = rom_download && ioctl_wr;
+
+reg last_ioctl_wr;
+always @(negedge clk28) begin
+	last_ioctl_wr <= ioctl_kernal_wr;
+	if(ioctl_kernal_wr && !last_ioctl_wr) begin
+		kernal_dl_data <= ioctl_data;
+		kernal_dl_addr <= ioctl_addr[13:0];
+		kernal_dl_wr <= 1'b1;
+	end else
+		kernal_dl_wr <= 1'b0;
+end
+
+// include the c16 itself
+C16 c16 (
+	.CLK28   ( clk28 ),
+	.RESET   ( reset ),
+	.WAIT    ( c16_wait ),
+	.HSYNC   ( c16_hs ),
+	.VSYNC   ( c16_vs ),
+	.CSYNC   ( c16_cs ),
+	.RED     ( c16_r ),
+	.GREEN   ( c16_g ),
+	.BLUE    ( c16_b ),
+	
+	.RAS     ( c16_ras ),
+	.CAS     ( c16_cas ),
+	.RW      ( c16_rw ),
+	.A       ( c16_a ),
+	.DOUT    ( c16_dout ),
+	.DIN     ( c16_din ),
+
+	.JOY0    ( jsB[4:0] ),
+	.JOY1    ( jsA[4:0] ),
+	
+	.PS2DAT  ( ps2_kbd_data ),
+	.PS2CLK  ( ps2_kbd_clk  ),
+
+	.kernal_dl_addr  ( kernal_dl_addr ),
+	.kernal_dl_data  ( kernal_dl_data ),
+	.kernal_dl_write ( kernal_dl_wr),
+	
+/*	
+	.IEC_DATAOUT ( c16_iec_data_o ),
+	.IEC_DATAIN  ( c16_iec_data_i ),
+	.IEC_CLKOUT  ( c16_iec_clk_o ),
+	.IEC_CLKIN   ( c16_iec_clk_i ),
+	.IEC_ATNOUT  ( c16_iec_atn_o ),
+	// .IEC_ATNIN,
+	.IEC_RESET   ( ),
+*/
+	.IEC_DATAIN  ( 1'b1 ),
+	.IEC_CLKIN   ( 1'b1 ),
+	
+	.AUDIO_L     ( AUDIO_L ),
+	.AUDIO_R     ( AUDIO_R ),
+
+	.PAL         ( c16_pal ),
+	
+	.RS232_TX    (),
+	.RGBS        ()
+);
+
+
+// ---------------------------------------------------------------------------------
+// ------------------------------- clock generation --------------------------------
+// ---------------------------------------------------------------------------------
+
+// the FPGATED uses two different clocks for NTSC and PAL mode.
+// Switching the clocks may crash the system. We might need to force a reset it.
+wire clk28 = c16_pal?clk28_pal:clk28_ntsc;
+wire pll_locked = pll_pal_locked && pll_ntsc_locked;
+	
+// tv15hkz has quarter the pixel rate, so we need a 7mhz clock for the OSD
+reg clk7;
+always @(posedge clk14)
+	clk7 <= !clk7;
+
+reg clk14;
+always @(posedge clk28)
+	clk14 <= !clk14;
+
+// A PLL to derive the system clock from the MiSTs 27MHz
+wire pll_pal_locked, clk28_pal;
+pll_pal pll_pal (
+	 .inclk0( CLOCK_27        ),
+	 .c0(     clk28_pal       ),
+	 .locked( pll_pal_locked  )
+);
+
+wire pll_ntsc_locked, clk28_ntsc;
+pll_ntsc pll_ntsc (
+	 .inclk0( CLOCK_27         ),
+	 .c0(     clk28_ntsc       ),
+	 .locked( pll_ntsc_locked  )
+);
+
+
+
+/*
+// ---------------------------------------------------------------------------------
+// ----------------------------------- floppy 1541 ---------------------------------
+// ---------------------------------------------------------------------------------
+
+wire [7:0] led_disk;
+assign LED = !led_disk[6];
+
+wire c16_iec_atn_o;
+wire c16_iec_data_o;
+wire c16_iec_clk_o;
+
+wire c16_iec_atn_i  = !((!c16_iec_atn_o)  & (!c1541_iec_atn_o) );
+wire c16_iec_data_i = !((!c16_iec_data_o) & (!c1541_iec_data_o));
+wire c16_iec_clk_i  = !((!c16_iec_clk_o)  & (!c1541_iec_clk_o) );
+
+wire c1541_iec_atn_o;
+wire c1541_iec_data_o;
+wire c1541_iec_clk_o;
+
+wire c1541_iec_atn_i  = c16_iec_atn_i;
+wire c1541_iec_data_i = c16_iec_data_i;
+wire c1541_iec_clk_i  = c16_iec_clk_i;
+
+
+c1541_sd c1541_sd (
+	.clk32 ( clk32 ),
+	.clk18 ( clk28 ),           // MiST uses virtual SPI SD, so any clock can be used.
+	.reset ( reset ),
+
+	.c1541rom_addr ( 14'h0000 ),
+	.c1541rom_data ( 8'h00 ),
+	.c1541rom_wr ( 1'b0 ),
+	
+   .disk_change (), 
+   .disk_num ( 10'd0 ),        // not seletable by f8 or similar
+
+	.iec_atn_i  ( c1541_iec_atn_i  ),
+	.iec_data_i ( c1541_iec_data_i ),
+	.iec_clk_i  ( c1541_iec_clk_i  ),
+
+	.iec_atn_o  ( c1541_iec_atn_o  ),
+	.iec_data_o ( c1541_iec_data_o ),
+	.iec_clk_o  ( c1541_iec_clk_o  ),
+
+   .sd_dat ( 1'b1 ),
+   .sd_dat3 (),
+   .sd_cmd (),
+   .sd_clk (),
+
+   .led ( led_disk )
+);
+*/
+
+endmodule
diff --git a/cores/c16/colors_to_rgb.v b/cores/c16/colors_to_rgb.v
new file mode 100644
index 0000000..5c97822
--- /dev/null
+++ b/cores/c16/colors_to_rgb.v
@@ -0,0 +1,183 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+//  Copyright 2013-2016 Istvan Hegedus
+//
+//  FPGATED is free software: you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation, either version 3 of the License, or
+//  (at your option) any later version.
+//
+//  FPGATED is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program.  If not, see <http://www.gnu.org/licenses/>. 
+//
+// Create Date:    22:03:30 11/20/2014 
+// Design Name: 	 Commodore Plus/4 color value conversion to 12bit RGB values 
+// Module Name:    colors_to_rgb.v 
+// Project Name:   FPGATED
+// Target Devices: Xilinx Spartan 3E
+//
+// Description: 	
+// 	Converts TED's 7 bit color codes to 12 bit RGB values used by video DAC.
+//		12 bit DAC values from Jozsef Laszlo
+//
+// Revisions: 
+// Revision 0.1 - File Created 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module colors_to_rgb(
+	 input clk,
+    input [6:0] color,
+    output [3:0] red,
+    output [3:0] green,
+    output [3:0] blue
+    );
+reg [11:0] color_lut [127:0];
+reg [11:0] rgbcolor;
+
+initial
+	begin
+	color_lut[0]=12'b0000_0000_0000;
+	color_lut[1]=12'b0010_0010_0010;
+	color_lut[2]=12'b0101_0000_0000;
+	color_lut[3]=12'b0000_0011_0011;
+	color_lut[4]=12'b0100_0000_0101;
+	color_lut[5]=12'b0000_0100_0000;
+	color_lut[6]=12'b0001_0001_0111;
+	color_lut[7]=12'b0010_0010_0000;
+	color_lut[8]=12'b0100_0001_0000;
+	color_lut[9]=12'b0011_0010_0000;
+	color_lut[10]=12'b0001_0011_0000;
+	color_lut[11]=12'b0101_0000_0010;
+	color_lut[12]=12'b0000_0011_0001;
+	color_lut[13]=12'b0000_0010_0110;
+	color_lut[14]=12'b0001_0001_0111;
+	color_lut[15]=12'b0000_0011_0000;
+	color_lut[16]=12'b0000_0000_0000;
+	color_lut[17]=12'b0010_0010_0010;
+	color_lut[18]=12'b0110_0001_0001;
+	color_lut[19]=12'b0000_0100_0100;
+	color_lut[20]=12'b0101_0000_0110;
+	color_lut[21]=12'b0000_0100_0000;
+	color_lut[22]=12'b0010_0010_1000;
+	color_lut[23]=12'b0011_0011_0000;
+	color_lut[24]=12'b0101_0010_0000;
+	color_lut[25]=12'b0100_0010_0000;
+	color_lut[26]=12'b0010_0100_0000;
+	color_lut[27]=12'b0110_0001_0011;
+	color_lut[28]=12'b0000_0100_0010;
+	color_lut[29]=12'b0000_0011_0111;
+	color_lut[30]=12'b0010_0001_1000;
+	color_lut[31]=12'b0001_0100_0000;
+	color_lut[32]=12'b0000_0000_0000;
+	color_lut[33]=12'b0011_0011_0011;
+	color_lut[34]=12'b0110_0010_0010;
+	color_lut[35]=12'b0000_0101_0101;
+	color_lut[36]=12'b0110_0001_0111;
+	color_lut[37]=12'b0000_0101_0000;
+	color_lut[38]=12'b0010_0011_1001;
+	color_lut[39]=12'b0100_0100_0000;
+	color_lut[40]=12'b0110_0010_0000;
+	color_lut[41]=12'b0101_0011_0000;
+	color_lut[42]=12'b0010_0101_0000;
+	color_lut[43]=12'b0110_0001_0100;
+	color_lut[44]=12'b0000_0101_0011;
+	color_lut[45]=12'b0001_0011_1000;
+	color_lut[46]=12'b0011_0010_1001;
+	color_lut[47]=12'b0001_0101_0000;
+	color_lut[48]=12'b0000_0000_0000;
+	color_lut[49]=12'b0100_0100_0100;
+	color_lut[50]=12'b0111_0011_0011;
+	color_lut[51]=12'b0001_0110_0110;
+	color_lut[52]=12'b0111_0010_1000;
+	color_lut[53]=12'b0001_0110_0010;
+	color_lut[54]=12'b0100_0100_1010;
+	color_lut[55]=12'b0101_0101_0000;
+	color_lut[56]=12'b0111_0100_0001;
+	color_lut[57]=12'b0110_0100_0000;
+	color_lut[58]=12'b0011_0110_0000;
+	color_lut[59]=12'b0111_0011_0101;
+	color_lut[60]=12'b0001_0110_0100;
+	color_lut[61]=12'b0010_0100_1001;
+	color_lut[62]=12'b0100_0011_1010;
+	color_lut[63]=12'b0011_0110_0000;
+	color_lut[64]=12'b0000_0000_0000;
+	color_lut[65]=12'b0110_0110_0110;
+	color_lut[66]=12'b1010_0101_0101;
+	color_lut[67]=12'b0011_1000_1000;
+	color_lut[68]=12'b1001_0100_1010;
+	color_lut[69]=12'b0100_1000_0100;
+	color_lut[70]=12'b0110_0110_1100;
+	color_lut[71]=12'b0111_0111_0001;
+	color_lut[72]=12'b1001_0110_0011;
+	color_lut[73]=12'b1000_0110_0010;
+	color_lut[74]=12'b0110_1000_0001;
+	color_lut[75]=12'b1010_0101_0111;
+	color_lut[76]=12'b0011_1000_0110;
+	color_lut[77]=12'b0100_0111_1011;
+	color_lut[78]=12'b0110_0101_1100;
+	color_lut[79]=12'b0101_1000_0010;
+	color_lut[80]=12'b0000_0000_0000;
+	color_lut[81]=12'b1000_1000_1000;
+	color_lut[82]=12'b1011_0111_0111;
+	color_lut[83]=12'b0101_1001_1001;
+	color_lut[84]=12'b1011_0110_1011;
+	color_lut[85]=12'b0101_1010_0101;
+	color_lut[86]=12'b0111_0111_1110;
+	color_lut[87]=12'b1001_1001_0010;
+	color_lut[88]=12'b1011_0111_0101;
+	color_lut[89]=12'b1010_1000_0011;
+	color_lut[90]=12'b0111_1001_0010;
+	color_lut[91]=12'b1011_0110_1001;
+	color_lut[92]=12'b0101_1010_1000;
+	color_lut[93]=12'b0110_1000_1101;
+	color_lut[94]=12'b1000_0111_1110;
+	color_lut[95]=12'b0110_1010_0011;
+	color_lut[96]=12'b0000_0000_0000;
+	color_lut[97]=12'b1011_1011_1011;
+	color_lut[98]=12'b1110_1001_1001;
+	color_lut[99]=12'b1000_1100_1100;
+	color_lut[100]=12'b1101_1001_1110;
+	color_lut[101]=12'b1000_1101_1000;
+	color_lut[102]=12'b1010_1010_1111;
+	color_lut[103]=12'b1011_1011_0101;
+	color_lut[104]=12'b1101_1010_1000;
+	color_lut[105]=12'b1100_1011_0110;
+	color_lut[106]=12'b1010_1100_0101;
+	color_lut[107]=12'b1110_1001_1011;
+	color_lut[108]=12'b0111_1100_1010;
+	color_lut[109]=12'b1001_1011_1111;
+	color_lut[110]=12'b1010_1010_1111;
+	color_lut[111]=12'b1001_1100_0110;
+	color_lut[112]=12'b0000_0000_0000;
+	color_lut[113]=12'b1110_1110_1110;
+	color_lut[114]=12'b1111_1101_1101;
+	color_lut[115]=12'b1011_1111_1111;
+	color_lut[116]=12'b1111_1100_1111;
+	color_lut[117]=12'b1100_1111_1100;
+	color_lut[118]=12'b1110_1110_1111;
+	color_lut[119]=12'b1111_1111_1001;
+	color_lut[120]=12'b1111_1110_1011;
+	color_lut[121]=12'b1111_1110_1010;
+	color_lut[122]=12'b1110_1111_1001;
+	color_lut[123]=12'b1111_1101_1111;
+	color_lut[124]=12'b1011_1111_1110;
+	color_lut[125]=12'b1100_1110_1111;
+	color_lut[126]=12'b1110_1101_1111;
+	color_lut[127]=12'b1101_1111_1010;
+	end
+
+always @(posedge clk)
+	begin
+	rgbcolor<=color_lut[color];
+	end
+	
+assign red=rgbcolor[11:8];
+assign green=rgbcolor[7:4];
+assign blue=rgbcolor[3:0];
+
+endmodule
diff --git a/cores/c16/cpu65xx_e.vhd b/cores/c16/cpu65xx_e.vhd
new file mode 100644
index 0000000..d15f0d8
--- /dev/null
+++ b/cores/c16/cpu65xx_e.vhd
@@ -0,0 +1,48 @@
+-- -----------------------------------------------------------------------
+--
+--                                 FPGA 64
+--
+--     A fully functional commodore 64 implementation in a single FPGA
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+-- -----------------------------------------------------------------------
+--
+-- Interface to 6502/6510 core
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use ieee.std_logic_1164.ALL;
+use ieee.numeric_std.ALL;
+
+-- -----------------------------------------------------------------------
+
+entity cpu65xx is
+	generic (
+		pipelineOpcode : boolean;
+		pipelineAluMux : boolean;
+		pipelineAluOut : boolean
+	);
+	port (
+		clk : in std_logic;
+		enable : in std_logic;
+		reset : in std_logic;
+		nmi_n : in std_logic;
+		irq_n : in std_logic;
+		so_n : in std_logic := '1';
+
+		di : in unsigned(7 downto 0);
+		do : out unsigned(7 downto 0);
+		addr : out unsigned(15 downto 0);
+		we : out std_logic;
+		
+		debugOpcode : out unsigned(7 downto 0);
+		debugPc : out unsigned(15 downto 0);
+		debugA : out unsigned(7 downto 0);
+		debugX : out unsigned(7 downto 0);
+		debugY : out unsigned(7 downto 0);
+		debugS : out unsigned(7 downto 0)
+	);
+end cpu65xx;
diff --git a/cores/c16/cpu65xx_fast.vhd b/cores/c16/cpu65xx_fast.vhd
new file mode 100644
index 0000000..190a2c6
--- /dev/null
+++ b/cores/c16/cpu65xx_fast.vhd
@@ -0,0 +1,1565 @@
+-- -----------------------------------------------------------------------
+--
+--                                 FPGA 64
+--
+--     A fully functional commodore 64 implementation in a single FPGA
+--
+-- -----------------------------------------------------------------------
+-- Copyright 2005-2008 by Peter Wendrich (pwsoft@syntiac.com)
+-- http://www.syntiac.com/fpga64.html
+-- -----------------------------------------------------------------------
+--
+-- Table driven, cycle exact 6502/6510 core
+--
+-- -----------------------------------------------------------------------
+
+library IEEE;
+use ieee.std_logic_1164.ALL;
+use ieee.std_logic_unsigned.ALL;
+use ieee.numeric_std.ALL;
+
+-- -----------------------------------------------------------------------
+
+-- Store Zp    (3) => fetch, cycle2, cycleEnd
+-- Store Zp,x  (4) => fetch, cycle2, preWrite, cycleEnd
+-- Read  Zp,x  (4) => fetch, cycle2, cycleRead, cycleRead2
+-- Rmw   Zp,x  (6) => fetch, cycle2, cycleRead, cycleRead2, cycleRmw, cycleEnd
+-- Store Abs   (4) => fetch, cycle2, cycle3, cycleEnd
+-- Store Abs,x (5) => fetch, cycle2, cycle3, preWrite, cycleEnd
+-- Rts         (6) => fetch, cycle2, cycle3, cycleRead, cycleJump, cycleIncrEnd
+-- Rti         (6) => fetch, cycle2, stack1, stack2, stack3, cycleJump
+-- Jsr         (6) => fetch, cycle2, .. cycle5, cycle6, cycleJump
+-- Jmp abs     (-) => fetch, cycle2, .., cycleJump
+-- Jmp (ind)   (-) => fetch, cycle2, .., cycleJump
+-- Brk / irq   (6) => fetch, cycle2, stack2, stack3, stack4
+-- -----------------------------------------------------------------------
+
+architecture fast of cpu65xx is
+-- Statemachine
+	type cpuCycles is (
+		opcodeFetch,  -- New opcode is read and registers updated
+		cycle2,
+		cycle3,
+		cyclePreIndirect,
+		cycleIndirect,
+		cycleBranchTaken,
+		cycleBranchPage,
+		cyclePreRead,     -- Cycle before read while doing zeropage indexed addressing.
+		cycleRead,        -- Read cycle
+		cycleRead2,       -- Second read cycle after page-boundary crossing.
+		cycleRmw,         -- Calculate ALU output for read-modify-write instr.		
+		cyclePreWrite,    -- Cycle before write when doing indexed addressing.
+		cycleWrite,       -- Write cycle for zeropage or absolute addressing.
+		cycleStack1,
+		cycleStack2,
+		cycleStack3,
+		cycleStack4,
+		cycleJump,	      -- Last cycle of Jsr, Jmp. Next fetch address is target addr.
+		cycleEnd
+	);
+	signal theCpuCycle : cpuCycles;
+	signal nextCpuCycle : cpuCycles;
+	signal updateRegisters : boolean;
+	signal processIrq : std_logic;
+	signal nmiReg: std_logic;
+	signal nmiEdge: std_logic;
+	signal irqReg : std_logic; -- Delay IRQ input with one clock cycle.
+	signal soReg : std_logic; -- SO pin edge detection
+
+-- Opcode decoding
+	constant opcUpdateA    : integer := 0;
+	constant opcUpdateX    : integer := 1;
+	constant opcUpdateY    : integer := 2;
+	constant opcUpdateS    : integer := 3;
+	constant opcUpdateN    : integer := 4;
+	constant opcUpdateV    : integer := 5;
+	constant opcUpdateD    : integer := 6;
+	constant opcUpdateI    : integer := 7;
+	constant opcUpdateZ    : integer := 8;
+	constant opcUpdateC    : integer := 9;
+
+	constant opcSecondByte : integer := 10;
+	constant opcAbsolute   : integer := 11;
+	constant opcZeroPage   : integer := 12;
+	constant opcIndirect   : integer := 13;
+	constant opcStackAddr  : integer := 14; -- Push/Pop address
+	constant opcStackData  : integer := 15; -- Push/Pop status/data
+	constant opcJump       : integer := 16;
+	constant opcBranch     : integer := 17;
+	constant indexX        : integer := 18;
+	constant indexY        : integer := 19;
+	constant opcStackUp    : integer := 20;
+	constant opcWrite      : integer := 21;
+	constant opcRmw        : integer := 22;
+	constant opcIncrAfter  : integer := 23; -- Insert extra cycle to increment PC (RTS)
+	constant opcRti        : integer := 24;
+	constant opcIRQ        : integer := 25;
+
+	constant opcInA        : integer := 26;
+	constant opcInE        : integer := 27;
+	constant opcInX        : integer := 28;
+	constant opcInY        : integer := 29;
+	constant opcInS        : integer := 30;
+	constant opcInT        : integer := 31;
+	constant opcInH        : integer := 32;
+	constant opcInClear    : integer := 33;
+	constant aluMode1From  : integer := 34;
+	--
+	constant aluMode1To    : integer := 37;
+	constant aluMode2From  : integer := 38;
+	--
+	constant aluMode2To    : integer := 40;
+	--
+	constant opcInCmp      : integer := 41;
+	constant opcInCpx      : integer := 42;
+	constant opcInCpy      : integer := 43;
+	
+
+	subtype addrDef is unsigned(0 to 15);
+	--
+	--               is Interrupt  -----------------+
+	--          instruction is RTI ----------------+|
+	--    PC++ on last cycle (RTS) ---------------+||
+	--                      RMW    --------------+|||
+	--                     Write   -------------+||||
+	--               Pop/Stack up -------------+|||||
+	--                    Branch   ---------+  ||||||
+	--                      Jump ----------+|  ||||||
+	--            Push or Pop data -------+||  ||||||
+	--            Push or Pop addr ------+|||  ||||||
+	--                   Indirect  -----+||||  ||||||
+	--                    ZeroPage ----+|||||  ||||||
+	--                    Absolute ---+||||||  ||||||
+	--              PC++ on cycle2 --+|||||||  ||||||
+	--                               |AZI||JBXY|WM|||
+	constant immediate : addrDef := "1000000000000000";
+	constant implied   : addrDef := "0000000000000000";
+	-- Zero page
+	constant readZp    : addrDef := "1010000000000000";
+	constant writeZp   : addrDef := "1010000000010000";
+	constant rmwZp     : addrDef := "1010000000001000";
+	-- Zero page indexed
+	constant readZpX   : addrDef := "1010000010000000";
+	constant writeZpX  : addrDef := "1010000010010000";
+	constant rmwZpX    : addrDef := "1010000010001000";
+	constant readZpY   : addrDef := "1010000001000000";
+	constant writeZpY  : addrDef := "1010000001010000";
+	constant rmwZpY    : addrDef := "1010000001001000";
+	-- Zero page indirect
+	constant readIndX  : addrDef := "1001000010000000";
+	constant writeIndX : addrDef := "1001000010010000";
+	constant rmwIndX   : addrDef := "1001000010001000";
+	constant readIndY  : addrDef := "1001000001000000";
+	constant writeIndY : addrDef := "1001000001010000";
+	constant rmwIndY   : addrDef := "1001000001001000";
+	--                               |AZI||JBXY|WM||
+	-- Absolute
+	constant readAbs   : addrDef := "1100000000000000";	
+	constant writeAbs  : addrDef := "1100000000010000";	
+	constant rmwAbs    : addrDef := "1100000000001000";	
+	constant readAbsX  : addrDef := "1100000010000000";	
+	constant writeAbsX : addrDef := "1100000010010000";	
+	constant rmwAbsX   : addrDef := "1100000010001000";	
+	constant readAbsY  : addrDef := "1100000001000000";	
+	constant writeAbsY : addrDef := "1100000001010000";	
+	constant rmwAbsY   : addrDef := "1100000001001000";	
+	-- PHA PHP
+	constant push      : addrDef := "0000010000000000";
+	-- PLA PLP
+	constant pop       : addrDef := "0000010000100000";
+	-- Jumps
+	constant jsr       : addrDef := "1000101000000000";
+	constant jumpAbs   : addrDef := "1000001000000000";
+	constant jumpInd   : addrDef := "1100001000000000";
+	constant relative  : addrDef := "1000000100000000";
+	-- Specials
+	constant rts       : addrDef := "0000101000100100";
+	constant rti       : addrDef := "0000111000100010";
+	constant brk       : addrDef := "1000111000000001";
+--	constant        : unsigned(0 to 0) := "0";
+	constant xxxxxxxx  : addrDef := "----------0---00";
+	
+	-- A = accu
+	-- E = Accu | 0xEE (for ANE, LXA)
+	-- X = index X
+	-- Y = index Y
+	-- S = Stack pointer
+	-- H = indexH
+	-- 
+	--                                       AEXYSTHc
+	constant aluInA   : unsigned(0 to 7) := "10000000";
+	constant aluInE   : unsigned(0 to 7) := "01000000";
+	constant aluInEXT : unsigned(0 to 7) := "01100100";
+	constant aluInET  : unsigned(0 to 7) := "01000100";
+	constant aluInX   : unsigned(0 to 7) := "00100000";
+	constant aluInXH  : unsigned(0 to 7) := "00100010";
+	constant aluInY   : unsigned(0 to 7) := "00010000";
+	constant aluInYH  : unsigned(0 to 7) := "00010010";
+	constant aluInS   : unsigned(0 to 7) := "00001000";
+	constant aluInT   : unsigned(0 to 7) := "00000100";
+	constant aluInAX  : unsigned(0 to 7) := "10100000";
+	constant aluInAXH : unsigned(0 to 7) := "10100010";
+	constant aluInAT  : unsigned(0 to 7) := "10000100";
+	constant aluInXT  : unsigned(0 to 7) := "00100100";
+	constant aluInST  : unsigned(0 to 7) := "00001100";
+	constant aluInSet : unsigned(0 to 7) := "00000000";
+	constant aluInClr : unsigned(0 to 7) := "00000001";
+	constant aluInXXX : unsigned(0 to 7) := "--------";
+	
+	-- Most of the aluModes are just like the opcodes.
+	-- aluModeInp -> input is output. calculate N and Z
+	-- aluModeCmp -> Compare for CMP, CPX, CPY
+	-- aluModeFlg -> input to flags needed for PLP, RTI and CLC, SEC, CLV
+	-- aluModeInc -> for INC but also INX, INY
+	-- aluModeDec -> for DEC but also DEX, DEY
+
+	subtype aluMode1 is unsigned(0 to 3);
+	subtype aluMode2 is unsigned(0 to 2);
+	subtype aluMode is unsigned(0 to 9);
+
+	-- Logic/Shift ALU
+	constant aluModeInp : aluMode1 := "0000";
+	constant aluModeP   : aluMode1 := "0001";
+	constant aluModeInc : aluMode1 := "0010";
+	constant aluModeDec : aluMode1 := "0011";
+	constant aluModeFlg : aluMode1 := "0100";
+	constant aluModeBit : aluMode1 := "0101";
+	-- 0110
+	-- 0111
+	constant aluModeLsr : aluMode1 := "1000";
+	constant aluModeRor : aluMode1 := "1001";
+	constant aluModeAsl : aluMode1 := "1010";
+	constant aluModeRol : aluMode1 := "1011";
+	-- 1100
+	-- 1101
+	-- 1110
+	constant aluModeAnc : aluMode1 := "1111";
+
+	-- Arithmetic ALU
+	constant aluModePss : aluMode2 := "000";
+	constant aluModeCmp : aluMode2 := "001";
+	constant aluModeAdc : aluMode2 := "010";
+	constant aluModeSbc : aluMode2 := "011";
+	constant aluModeAnd : aluMode2 := "100";
+	constant aluModeOra : aluMode2 := "101";
+	constant aluModeEor : aluMode2 := "110";
+	constant aluModeArr : aluMode2 := "111";
+
+
+	constant aluInp  : aluMode := aluModeInp & aluModePss & "---";
+	constant aluP    : aluMode := aluModeP   & aluModePss & "---";
+	constant aluInc  : aluMode := aluModeInc & aluModePss & "---";
+	constant aluDec  : aluMode := aluModeDec & aluModePss & "---";
+	constant aluFlg  : aluMode := aluModeFlg & aluModePss & "---";
+	constant aluBit  : aluMode := aluModeBit & aluModeAnd & "---";
+	constant aluRor  : aluMode := aluModeRor & aluModePss & "---";
+	constant aluLsr  : aluMode := aluModeLsr & aluModePss & "---";
+	constant aluRol  : aluMode := aluModeRol & aluModePss & "---";
+	constant aluAsl  : aluMode := aluModeAsl & aluModePss & "---";
+
+	constant aluCmp  : aluMode := aluModeInp & aluModeCmp & "100";
+	constant aluCpx  : aluMode := aluModeInp & aluModeCmp & "010";
+	constant aluCpy  : aluMode := aluModeInp & aluModeCmp & "001";
+	constant aluAdc  : aluMode := aluModeInp & aluModeAdc & "---";
+	constant aluSbc  : aluMode := aluModeInp & aluModeSbc & "---";
+	constant aluAnd  : aluMode := aluModeInp & aluModeAnd & "---";
+	constant aluOra  : aluMode := aluModeInp & aluModeOra & "---";
+	constant aluEor  : aluMode := aluModeInp & aluModeEor & "---";
+	
+	constant aluSlo  : aluMode := aluModeAsl & aluModeOra & "---";
+	constant aluSre  : aluMode := aluModeLsr & aluModeEor & "---";
+	constant aluRra  : aluMode := aluModeRor & aluModeAdc & "---";
+	constant aluRla  : aluMode := aluModeRol & aluModeAnd & "---";
+	constant aluDcp  : aluMode := aluModeDec & aluModeCmp & "100";
+	constant aluIsc  : aluMode := aluModeInc & aluModeSbc & "---";
+	constant aluAnc  : aluMode := aluModeAnc & aluModeAnd & "---";
+	constant aluArr  : aluMode := aluModeRor & aluModeArr & "---";
+	constant aluSbx  : aluMode := aluModeInp & aluModeCmp & "110";
+	
+	constant aluXXX  : aluMode := (others => '-');
+
+
+	-- Stack operations. Push/Pop/None
+	constant stackInc : unsigned(0 to 0) := "0";
+	constant stackDec : unsigned(0 to 0) := "1";
+	constant stackXXX : unsigned(0 to 0) := "-";
+
+	subtype decodedBitsDef is unsigned(0 to 43);
+	type opcodeInfoTableDef is array(0 to 255) of decodedBitsDef;
+	constant opcodeInfoTable : opcodeInfoTableDef := (
+	-- +------- Update register A
+	-- |+------ Update register X
+	-- ||+----- Update register Y
+	-- |||+---- Update register S
+	-- ||||       +-- Update Flags
+	-- ||||       |   
+	-- ||||      _|__ 
+	-- ||||     /    \
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "000100" & brk       & aluInXXX & aluP,   -- 00 BRK
+	  "1000" & "100010" & readIndX  & aluInT   & aluOra, -- 01 ORA (zp,x)
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 02 *** JAM ***
+	  "1000" & "100011" & rmwIndX   & aluInT   & aluSlo, -- 03 iSLO (zp,x)
+	  "0000" & "000000" & readZp    & aluInXXX & aluXXX, -- 04 iNOP zp
+	  "1000" & "100010" & readZp    & aluInT   & aluOra, -- 05 ORA zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluAsl, -- 06 ASL zp
+	  "1000" & "100011" & rmwZp     & aluInT   & aluSlo, -- 07 iSLO zp
+	  "0000" & "000000" & push      & aluInXXX & aluP,   -- 08 PHP
+	  "1000" & "100010" & immediate & aluInT   & aluOra, -- 09 ORA imm
+	  "1000" & "100011" & implied   & aluInA   & aluAsl, -- 0A ASL accu
+	  "1000" & "100011" & immediate & aluInT   & aluAnc, -- 0B iANC imm
+	  "0000" & "000000" & readAbs   & aluInXXX & aluXXX, -- 0C iNOP abs
+	  "1000" & "100010" & readAbs   & aluInT   & aluOra, -- 0D ORA abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluAsl, -- 0E ASL abs
+	  "1000" & "100011" & rmwAbs    & aluInT   & aluSlo, -- 0F iSLO abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 10 BPL
+	  "1000" & "100010" & readIndY  & aluInT   & aluOra, -- 11 ORA (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 12 *** JAM ***
+	  "1000" & "100011" & rmwIndY   & aluInT   & aluSlo, -- 13 iSLO (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- 14 iNOP zp,x
+	  "1000" & "100010" & readZpX   & aluInT   & aluOra, -- 15 ORA zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluAsl, -- 16 ASL zp,x
+	  "1000" & "100011" & rmwZpX    & aluInT   & aluSlo, -- 17 iSLO zp,x
+	  "0000" & "000001" & implied   & aluInClr & aluFlg, -- 18 CLC
+	  "1000" & "100010" & readAbsY  & aluInT   & aluOra, -- 19 ORA abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 1A iNOP implied
+	  "1000" & "100011" & rmwAbsY   & aluInT   & aluSlo, -- 1B iSLO abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- 1C iNOP abs,x
+	  "1000" & "100010" & readAbsX  & aluInT   & aluOra, -- 1D ORA abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluAsl, -- 1E ASL abs,x
+	  "1000" & "100011" & rmwAbsX   & aluInT   & aluSlo, -- 1F iSLO abs,x
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "000000" & jsr       & aluInXXX & aluXXX, -- 20 JSR
+	  "1000" & "100010" & readIndX  & aluInT   & aluAnd, -- 21 AND (zp,x)
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 22 *** JAM ***
+	  "1000" & "100011" & rmwIndX   & aluInT   & aluRla, -- 23 iRLA (zp,x)
+	  "0000" & "110010" & readZp    & aluInT   & aluBit, -- 24 BIT zp
+	  "1000" & "100010" & readZp    & aluInT   & aluAnd, -- 25 AND zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluRol, -- 26 ROL zp
+	  "1000" & "100011" & rmwZp     & aluInT   & aluRla, -- 27 iRLA zp
+	  "0000" & "111111" & pop       & aluInT   & aluFlg, -- 28 PLP
+	  "1000" & "100010" & immediate & aluInT   & aluAnd, -- 29 AND imm
+	  "1000" & "100011" & implied   & aluInA   & aluRol, -- 2A ROL accu
+	  "1000" & "100011" & immediate & aluInT   & aluAnc, -- 2B iANC imm
+	  "0000" & "110010" & readAbs   & aluInT   & aluBit, -- 2C BIT abs
+	  "1000" & "100010" & readAbs   & aluInT   & aluAnd, -- 2D AND abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluRol, -- 2E ROL abs
+	  "1000" & "100011" & rmwAbs    & aluInT   & aluRla, -- 2F iRLA abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 30 BMI
+	  "1000" & "100010" & readIndY  & aluInT   & aluAnd, -- 31 AND (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 32 *** JAM ***
+	  "1000" & "100011" & rmwIndY   & aluInT   & aluRla, -- 33 iRLA (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- 34 iNOP zp,x
+	  "1000" & "100010" & readZpX   & aluInT   & aluAnd, -- 35 AND zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluRol, -- 36 ROL zp,x
+	  "1000" & "100011" & rmwZpX    & aluInT   & aluRla, -- 37 iRLA zp,x
+	  "0000" & "000001" & implied   & aluInSet & aluFlg, -- 38 SEC
+	  "1000" & "100010" & readAbsY  & aluInT   & aluAnd, -- 39 AND abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 3A iNOP implied
+	  "1000" & "100011" & rmwAbsY   & aluInT   & aluRla, -- 3B iRLA abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- 3C iNOP abs,x
+	  "1000" & "100010" & readAbsX  & aluInT   & aluAnd, -- 3D AND abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluRol, -- 3E ROL abs,x
+	  "1000" & "100011" & rmwAbsX   & aluInT   & aluRla, -- 3F iRLA abs,x
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "111111" & rti       & aluInT   & aluFlg, -- 40 RTI
+	  "1000" & "100010" & readIndX  & aluInT   & aluEor, -- 41 EOR (zp,x)
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 42 *** JAM ***
+	  "1000" & "100011" & rmwIndX   & aluInT   & aluSre, -- 43 iSRE (zp,x)
+	  "0000" & "000000" & readZp    & aluInXXX & aluXXX, -- 44 iNOP zp
+	  "1000" & "100010" & readZp    & aluInT   & aluEor, -- 45 EOR zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluLsr, -- 46 LSR zp
+	  "1000" & "100011" & rmwZp     & aluInT   & aluSre, -- 47 iSRE zp
+	  "0000" & "000000" & push      & aluInA   & aluInp, -- 48 PHA
+	  "1000" & "100010" & immediate & aluInT   & aluEor, -- 49 EOR imm
+	  "1000" & "100011" & implied   & aluInA   & aluLsr, -- 4A LSR accu
+	  "1000" & "100011" & immediate & aluInAT  & aluLsr, -- 4B iALR imm
+	  "0000" & "000000" & jumpAbs   & aluInXXX & aluXXX, -- 4C JMP abs
+	  "1000" & "100010" & readAbs   & aluInT   & aluEor, -- 4D EOR abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluLsr, -- 4E LSR abs
+	  "1000" & "100011" & rmwAbs    & aluInT   & aluSre, -- 4F iSRE abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 50 BVC
+	  "1000" & "100010" & readIndY  & aluInT   & aluEor, -- 51 EOR (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 52 *** JAM ***
+	  "1000" & "100011" & rmwIndY   & aluInT   & aluSre, -- 53 iSRE (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- 54 iNOP zp,x
+	  "1000" & "100010" & readZpX   & aluInT   & aluEor, -- 55 EOR zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluLsr, -- 56 LSR zp,x
+	  "1000" & "100011" & rmwZpX    & aluInT   & aluSre, -- 57 SRE zp,x
+	  "0000" & "000100" & implied   & aluInClr & aluXXX, -- 58 CLI
+	  "1000" & "100010" & readAbsY  & aluInT   & aluEor, -- 59 EOR abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 5A iNOP implied
+	  "1000" & "100011" & rmwAbsY   & aluInT   & aluSre, -- 5B iSRE abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- 5C iNOP abs,x
+	  "1000" & "100010" & readAbsX  & aluInT   & aluEor, -- 5D EOR abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluLsr, -- 5E LSR abs,x
+	  "1000" & "100011" & rmwAbsX   & aluInT   & aluSre, -- 5F SRE abs,x
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "000000" & rts       & aluInXXX & aluXXX, -- 60 RTS
+	  "1000" & "110011" & readIndX  & aluInT   & aluAdc, -- 61 ADC (zp,x)
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 62 *** JAM ***
+	  "1000" & "110011" & rmwIndX   & aluInT   & aluRra, -- 63 iRRA (zp,x)
+	  "0000" & "000000" & readZp    & aluInXXX & aluXXX, -- 64 iNOP zp
+	  "1000" & "110011" & readZp    & aluInT   & aluAdc, -- 65 ADC zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluRor, -- 66 ROR zp
+	  "1000" & "110011" & rmwZp     & aluInT   & aluRra, -- 67 iRRA zp
+	  "1000" & "100010" & pop       & aluInT   & aluInp, -- 68 PLA
+	  "1000" & "110011" & immediate & aluInT   & aluAdc, -- 69 ADC imm
+	  "1000" & "100011" & implied   & aluInA   & aluRor, -- 6A ROR accu
+	  "1000" & "110011" & immediate & aluInAT  & aluArr, -- 6B iARR imm
+	  "0000" & "000000" & jumpInd   & aluInXXX & aluXXX, -- 6C JMP indirect
+	  "1000" & "110011" & readAbs   & aluInT   & aluAdc, -- 6D ADC abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluRor, -- 6E ROR abs
+	  "1000" & "110011" & rmwAbs    & aluInT   & aluRra, -- 6F iRRA abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 70 BVS
+	  "1000" & "110011" & readIndY  & aluInT   & aluAdc, -- 71 ADC (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 72 *** JAM ***
+	  "1000" & "110011" & rmwIndY   & aluInT   & aluRra, -- 73 iRRA (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- 74 iNOP zp,x
+	  "1000" & "110011" & readZpX   & aluInT   & aluAdc, -- 75 ADC zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluRor, -- 76 ROR zp,x
+	  "1000" & "110011" & rmwZpX    & aluInT   & aluRra, -- 77 iRRA zp,x
+	  "0000" & "000100" & implied   & aluInSet & aluXXX, -- 78 SEI
+	  "1000" & "110011" & readAbsY  & aluInT   & aluAdc, -- 79 ADC abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- 7A iNOP implied
+	  "1000" & "110011" & rmwAbsY   & aluInT   & aluRra, -- 7B iRRA abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- 7C iNOP abs,x
+	  "1000" & "110011" & readAbsX  & aluInT   & aluAdc, -- 7D ADC abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluRor, -- 7E ROR abs,x
+	  "1000" & "110011" & rmwAbsX   & aluInT   & aluRra, -- 7F iRRA abs,x
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 80 iNOP imm
+	  "0000" & "000000" & writeIndX & aluInA   & aluInp, -- 81 STA (zp,x)
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 82 iNOP imm
+	  "0000" & "000000" & writeIndX & aluInAX  & aluInp, -- 83 iSAX (zp,x)
+	  "0000" & "000000" & writeZp   & aluInY   & aluInp, -- 84 STY zp
+	  "0000" & "000000" & writeZp   & aluInA   & aluInp, -- 85 STA zp
+	  "0000" & "000000" & writeZp   & aluInX   & aluInp, -- 86 STX zp
+	  "0000" & "000000" & writeZp   & aluInAX  & aluInp, -- 87 iSAX zp
+	  "0010" & "100010" & implied   & aluInY   & aluDec, -- 88 DEY
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- 84 iNOP imm
+	  "1000" & "100010" & implied   & aluInX   & aluInp, -- 8A TXA
+	  "1000" & "100010" & immediate & aluInEXT & aluInp, -- 8B iANE imm
+	  "0000" & "000000" & writeAbs  & aluInY   & aluInp, -- 8C STY abs
+	  "0000" & "000000" & writeAbs  & aluInA   & aluInp, -- 8D STA abs
+	  "0000" & "000000" & writeAbs  & aluInX   & aluInp, -- 8E STX abs
+	  "0000" & "000000" & writeAbs  & aluInAX  & aluInp, -- 8F iSAX abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- 90 BCC
+	  "0000" & "000000" & writeIndY & aluInA   & aluInp, -- 91 STA (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- 92 *** JAM ***
+	  "0000" & "000000" & writeIndY & aluInAXH & aluInp, -- 93 iAHX (zp),y
+	  "0000" & "000000" & writeZpX  & aluInY   & aluInp, -- 94 STY zp,x
+	  "0000" & "000000" & writeZpX  & aluInA   & aluInp, -- 95 STA zp,x
+	  "0000" & "000000" & writeZpY  & aluInX   & aluInp, -- 96 STX zp,y
+	  "0000" & "000000" & writeZpY  & aluInAX  & aluInp, -- 97 iSAX zp,y
+	  "1000" & "100010" & implied   & aluInY   & aluInp, -- 98 TYA
+	  "0000" & "000000" & writeAbsY & aluInA   & aluInp, -- 99 STA abs,y
+	  "0001" & "000000" & implied   & aluInX   & aluInp, -- 9A TXS
+	  "0001" & "000000" & writeAbsY & aluInAXH & aluInp, -- 9B iSHS abs,y
+	  "0000" & "000000" & writeAbsX & aluInYH  & aluInp, -- 9C iSHY abs,x
+	  "0000" & "000000" & writeAbsX & aluInA   & aluInp, -- 9D STA abs,x
+	  "0000" & "000000" & writeAbsY & aluInXH  & aluInp, -- 9E iSHX abs,y
+	  "0000" & "000000" & writeAbsY & aluInAXH & aluInp, -- 9F iAHX abs,y
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0010" & "100010" & immediate & aluInT   & aluInp, -- A0 LDY imm
+	  "1000" & "100010" & readIndX  & aluInT   & aluInp, -- A1 LDA (zp,x)
+	  "0100" & "100010" & immediate & aluInT   & aluInp, -- A2 LDX imm
+	  "1100" & "100010" & readIndX  & aluInT   & aluInp, -- A3 LAX (zp,x)
+	  "0010" & "100010" & readZp    & aluInT   & aluInp, -- A4 LDY zp
+	  "1000" & "100010" & readZp    & aluInT   & aluInp, -- A5 LDA zp
+	  "0100" & "100010" & readZp    & aluInT   & aluInp, -- A6 LDX zp
+	  "1100" & "100010" & readZp    & aluInT   & aluInp, -- A7 iLAX zp
+	  "0010" & "100010" & implied   & aluInA   & aluInp, -- A8 TAY
+	  "1000" & "100010" & immediate & aluInT   & aluInp, -- A9 LDA imm
+	  "0100" & "100010" & implied   & aluInA   & aluInp, -- AA TAX
+	  "1100" & "100010" & immediate & aluInET  & aluInp, -- AB iLXA imm
+	  "0010" & "100010" & readAbs   & aluInT   & aluInp, -- AC LDY abs
+	  "1000" & "100010" & readAbs   & aluInT   & aluInp, -- AD LDA abs
+	  "0100" & "100010" & readAbs   & aluInT   & aluInp, -- AE LDX abs
+	  "1100" & "100010" & readAbs   & aluInT   & aluInp, -- AF iLAX abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- B0 BCS
+	  "1000" & "100010" & readIndY  & aluInT   & aluInp, -- B1 LDA (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- B2 *** JAM ***
+	  "1100" & "100010" & readIndY  & aluInT   & aluInp, -- B3 iLAX (zp),y
+	  "0010" & "100010" & readZpX   & aluInT   & aluInp, -- B4 LDY zp,x
+	  "1000" & "100010" & readZpX   & aluInT   & aluInp, -- B5 LDA zp,x
+	  "0100" & "100010" & readZpY   & aluInT   & aluInp, -- B6 LDX zp,y
+	  "1100" & "100010" & readZpY   & aluInT   & aluInp, -- B7 iLAX zp,y
+	  "0000" & "010000" & implied   & aluInClr & aluFlg, -- B8 CLV
+	  "1000" & "100010" & readAbsY  & aluInT   & aluInp, -- B9 LDA abs,y
+	  "0100" & "100010" & implied   & aluInS   & aluInp, -- BA TSX
+	  "1101" & "100010" & readAbsY  & aluInST  & aluInp, -- BB iLAS abs,y
+	  "0010" & "100010" & readAbsX  & aluInT   & aluInp, -- BC LDY abs,x
+	  "1000" & "100010" & readAbsX  & aluInT   & aluInp, -- BD LDA abs,x
+	  "0100" & "100010" & readAbsY  & aluInT   & aluInp, -- BE LDX abs,y
+	  "1100" & "100010" & readAbsY  & aluInT   & aluInp, -- BF iLAX abs,y
+	-- AXYS     NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "100011" & immediate & aluInT   & aluCpy, -- C0 CPY imm
+	  "0000" & "100011" & readIndX  & aluInT   & aluCmp, -- C1 CMP (zp,x)
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- C2 iNOP imm
+	  "0000" & "100011" & rmwIndX   & aluInT   & aluDcp, -- C3 iDCP (zp,x)
+	  "0000" & "100011" & readZp    & aluInT   & aluCpy, -- C4 CPY zp
+	  "0000" & "100011" & readZp    & aluInT   & aluCmp, -- C5 CMP zp
+	  "0000" & "100010" & rmwZp     & aluInT   & aluDec, -- C6 DEC zp
+	  "0000" & "100011" & rmwZp     & aluInT   & aluDcp, -- C7 iDCP zp
+	  "0010" & "100010" & implied   & aluInY   & aluInc, -- C8 INY
+	  "0000" & "100011" & immediate & aluInT   & aluCmp, -- C9 CMP imm
+	  "0100" & "100010" & implied   & aluInX   & aluDec, -- CA DEX
+	  "0100" & "100011" & immediate & aluInT   & aluSbx, -- CB SBX imm
+	  "0000" & "100011" & readAbs   & aluInT   & aluCpy, -- CC CPY abs
+	  "0000" & "100011" & readAbs   & aluInT   & aluCmp, -- CD CMP abs
+	  "0000" & "100010" & rmwAbs    & aluInT   & aluDec, -- CE DEC abs
+	  "0000" & "100011" & rmwAbs    & aluInT   & aluDcp, -- CF iDCP abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- D0 BNE
+	  "0000" & "100011" & readIndY  & aluInT   & aluCmp, -- D1 CMP (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- D2 *** JAM ***
+	  "0000" & "100011" & rmwIndY   & aluInT   & aluDcp, -- D3 iDCP (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- D4 iNOP zp,x
+	  "0000" & "100011" & readZpX   & aluInT   & aluCmp, -- D5 CMP zp,x
+	  "0000" & "100010" & rmwZpX    & aluInT   & aluDec, -- D6 DEC zp,x
+	  "0000" & "100011" & rmwZpX    & aluInT   & aluDcp, -- D7 iDCP zp,x
+	  "0000" & "001000" & implied   & aluInClr & aluXXX, -- D8 CLD
+	  "0000" & "100011" & readAbsY  & aluInT   & aluCmp, -- D9 CMP abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- DA iNOP implied
+	  "0000" & "100011" & rmwAbsY   & aluInT   & aluDcp, -- DB iDCP abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- DC iNOP abs,x
+	  "0000" & "100011" & readAbsX  & aluInT   & aluCmp, -- DD CMP abs,x
+	  "0000" & "100010" & rmwAbsX   & aluInT   & aluDec, -- DE DEC abs,x
+	  "0000" & "100011" & rmwAbsX   & aluInT   & aluDcp, -- DF iDCP abs,x
+	-- AXYS    NVDIZC    addressing  aluInput  aluMode
+	  "0000" & "100011" & immediate & aluInT   & aluCpx, -- E0 CPX imm
+	  "1000" & "110011" & readIndX  & aluInT   & aluSbc, -- E1 SBC (zp,x)
+	  "0000" & "000000" & immediate & aluInXXX & aluXXX, -- E2 iNOP imm
+	  "1000" & "110011" & rmwIndX   & aluInT   & aluIsc, -- E3 iISC (zp,x)
+	  "0000" & "100011" & readZp    & aluInT   & aluCpx, -- E4 CPX zp
+	  "1000" & "110011" & readZp    & aluInT   & aluSbc, -- E5 SBC zp
+	  "0000" & "100010" & rmwZp     & aluInT   & aluInc, -- E6 INC zp
+	  "1000" & "110011" & rmwZp     & aluInT   & aluIsc, -- E7 iISC zp
+	  "0100" & "100010" & implied   & aluInX   & aluInc, -- E8 INX
+	  "1000" & "110011" & immediate & aluInT   & aluSbc, -- E9 SBC imm
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- EA NOP
+	  "1000" & "110011" & immediate & aluInT   & aluSbc, -- EB SBC imm (illegal opc)
+	  "0000" & "100011" & readAbs   & aluInT   & aluCpx, -- EC CPX abs
+	  "1000" & "110011" & readAbs   & aluInT   & aluSbc, -- ED SBC abs
+	  "0000" & "100010" & rmwAbs    & aluInT   & aluInc, -- EE INC abs
+	  "1000" & "110011" & rmwAbs    & aluInT   & aluIsc, -- EF iISC abs
+	  "0000" & "000000" & relative  & aluInXXX & aluXXX, -- F0 BEQ
+	  "1000" & "110011" & readIndY  & aluInT   & aluSbc, -- F1 SBC (zp),y
+	  "----" & "------" & xxxxxxxx  & aluInXXX & aluXXX, -- F2 *** JAM ***
+	  "1000" & "110011" & rmwIndY   & aluInT   & aluIsc, -- F3 iISC (zp),y
+	  "0000" & "000000" & readZpX   & aluInXXX & aluXXX, -- F4 iNOP zp,x
+	  "1000" & "110011" & readZpX   & aluInT   & aluSbc, -- F5 SBC zp,x
+	  "0000" & "100010" & rmwZpX    & aluInT   & aluInc, -- F6 INC zp,x
+	  "1000" & "110011" & rmwZpX    & aluInT   & aluIsc, -- F7 iISC zp,x
+	  "0000" & "001000" & implied   & aluInSet & aluXXX, -- F8 SED
+	  "1000" & "110011" & readAbsY  & aluInT   & aluSbc, -- F9 SBC abs,y
+	  "0000" & "000000" & implied   & aluInXXX & aluXXX, -- FA iNOP implied
+	  "1000" & "110011" & rmwAbsY   & aluInT   & aluIsc, -- FB iISC abs,y
+	  "0000" & "000000" & readAbsX  & aluInXXX & aluXXX, -- FC iNOP abs,x
+	  "1000" & "110011" & readAbsX  & aluInT   & aluSbc, -- FD SBC abs,x
+	  "0000" & "100010" & rmwAbsX   & aluInT   & aluInc, -- FE INC abs,x
+	  "1000" & "110011" & rmwAbsX   & aluInT   & aluIsc  -- FF iISC abs,x
+	);
+	signal opcInfo        : decodedBitsDef;
+	signal nextOpcInfo    : decodedBitsDef;	-- Next opcode (decoded)
+	signal nextOpcInfoReg : decodedBitsDef;	-- Next opcode (decoded) pipelined
+	signal theOpcode      : unsigned(7 downto 0);
+	signal nextOpcode     : unsigned(7 downto 0);
+
+-- Program counter
+	signal PC : unsigned(15 downto 0); -- Program counter
+
+-- Address generation
+	type nextAddrDef is (
+		nextAddrHold,
+		nextAddrIncr,
+		nextAddrIncrL, -- Increment low bits only (zeropage accesses)
+		nextAddrIncrH, -- Increment high bits only (page-boundary)
+		nextAddrDecrH, -- Decrement high bits (branch backwards)
+		nextAddrPc,
+		nextAddrIrq,
+		nextAddrReset,
+		nextAddrAbs,
+		nextAddrAbsIndexed,
+		nextAddrZeroPage,
+		nextAddrZPIndexed,
+		nextAddrStack,
+		nextAddrRelative
+	);
+	signal nextAddr : nextAddrDef;
+	signal myAddr : unsigned(15 downto 0);
+	signal myAddrIncr : unsigned(15 downto 0);
+	signal myAddrIncrH : unsigned(7 downto 0);
+	signal myAddrDecrH : unsigned(7 downto 0);
+	signal theWe : std_logic;
+
+	signal irqActive : std_logic;
+	
+-- Output register
+	signal doReg : unsigned(7 downto 0);
+	
+-- Buffer register
+	signal T : unsigned(7 downto 0);
+
+-- General registers
+	signal A: unsigned(7 downto 0); -- Accumulator
+	signal X: unsigned(7 downto 0); -- Index X
+	signal Y: unsigned(7 downto 0); -- Index Y
+	signal S: unsigned(7 downto 0); -- stack pointer
+
+-- Status register
+	signal C: std_logic; -- Carry
+	signal Z: std_logic; -- Zero flag
+	signal I: std_logic; -- Interrupt flag
+	signal D: std_logic; -- Decimal mode
+	signal V: std_logic; -- Overflow
+	signal N: std_logic; -- Negative
+
+-- ALU
+	-- ALU input
+	signal aluInput : unsigned(7 downto 0);
+	signal aluCmpInput : unsigned(7 downto 0);
+	-- ALU output
+	signal aluRegisterOut : unsigned(7 downto 0);
+	signal aluRmwOut : unsigned(7 downto 0);
+	signal aluC : std_logic;
+	signal aluZ : std_logic;
+	signal aluV : std_logic;
+	signal aluN : std_logic;
+	-- Pipeline registers
+	signal aluInputReg : unsigned(7 downto 0);
+	signal aluCmpInputReg : unsigned(7 downto 0);
+	signal aluRmwReg : unsigned(7 downto 0);
+	signal aluNineReg : unsigned(7 downto 0);
+	signal aluCReg : std_logic;
+	signal aluZReg : std_logic;
+	signal aluVReg : std_logic;
+	signal aluNReg : std_logic;
+
+-- Indexing
+	signal indexOut : unsigned(8 downto 0);
+
+begin
+processAluInput: process(clk, opcInfo, A, X, Y, T, S)
+		variable temp : unsigned(7 downto 0);
+	begin
+		temp := (others => '1');
+		if opcInfo(opcInA) = '1' then
+			temp := temp and A;
+		end if;
+		if opcInfo(opcInE) = '1' then
+			temp := temp and (A or X"EE");
+		end if;
+		if opcInfo(opcInX) = '1' then
+			temp := temp and X;
+		end if;
+		if opcInfo(opcInY) = '1' then
+			temp := temp and Y;
+		end if;
+		if opcInfo(opcInS) = '1' then
+			temp := temp and S;
+		end if;
+		if opcInfo(opcInT) = '1' then
+			temp := temp and T;
+		end if;
+		if opcInfo(opcInClear) = '1' then
+			temp := (others => '0');
+		end if;
+		if rising_edge(clk) then
+			aluInputReg <= temp;
+		end if;
+
+		aluInput <= temp;
+		if pipelineAluMux then
+			aluInput <= aluInputReg;
+		end if;
+	end process;
+
+processCmpInput: process(clk, opcInfo, A, X, Y)
+		variable temp : unsigned(7 downto 0);
+	begin
+		temp := (others => '1');
+		if opcInfo(opcInCmp) = '1' then
+			temp := temp and A;
+		end if;
+		if opcInfo(opcInCpx) = '1' then
+			temp := temp and X;
+		end if;
+		if opcInfo(opcInCpy) = '1' then
+			temp := temp and Y;
+		end if;
+		if rising_edge(clk) then
+			aluCmpInputReg <= temp;
+		end if;
+
+		aluCmpInput <= temp;
+		if pipelineAluMux then
+			aluCmpInput <= aluCmpInputReg;
+		end if;
+	end process;
+
+	-- ALU consists of two parts
+	-- Read-Modify-Write or index instructions: INC/DEC/ASL/LSR/ROR/ROL 
+	-- Accumulator instructions: ADC, SBC, EOR, AND, EOR, ORA
+	-- Some instructions are both RMW and accumulator so for most
+	-- instructions the rmw results are routed through accu alu too.
+processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V, D, I, Z, C)
+		variable lowBits: unsigned(5 downto 0);
+		variable nineBits: unsigned(8 downto 0);
+		variable rmwBits: unsigned(8 downto 0);
+		
+		variable varC : std_logic;
+		variable varZ : std_logic;
+		variable varV : std_logic;
+		variable varN : std_logic;
+	begin
+		lowBits := (others => '-');
+		nineBits := (others => '-');
+		rmwBits := (others => '-');
+		varV := aluInput(6); -- Default for BIT / PLP / RTI
+
+		-- Shift unit
+		case opcInfo(aluMode1From to aluMode1To) is
+		when aluModeInp =>
+			rmwBits := C & aluInput;
+		when aluModeP =>
+			rmwBits := C & N & V & '1' & (not irqActive) & D & I & Z & C;
+		when aluModeInc =>
+			rmwBits := C & (aluInput + 1);
+		when aluModeDec =>
+			rmwBits := C & (aluInput - 1);
+		when aluModeAsl =>
+			rmwBits := aluInput & "0";
+		when aluModeFlg =>
+			rmwBits := aluInput(0) & aluInput;
+		when aluModeLsr =>
+			rmwBits := aluInput(0) & "0" & aluInput(7 downto 1);
+		when aluModeRol =>
+			rmwBits := aluInput & C;
+		when aluModeRoR =>
+			rmwBits := aluInput(0) & C & aluInput(7 downto 1);
+		when aluModeAnc =>
+			rmwBits := (aluInput(7) and A(7)) & aluInput;
+		when others =>
+			rmwBits := C & aluInput;
+		end case;
+		
+		-- ALU
+		case opcInfo(aluMode2From to aluMode2To) is
+		when aluModeAdc =>
+			lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & rmwBits(3 downto 0) & "1");
+			ninebits := ("0" & A) + ("0" & rmwBits(7 downto 0)) + (B"00000000" & rmwBits(8));
+		when aluModeSbc =>
+			lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & (not rmwBits(3 downto 0)) & "1");
+			ninebits := ("0" & A) + ("0" & (not rmwBits(7 downto 0))) + (B"00000000" & rmwBits(8));
+		when aluModeCmp =>
+			ninebits := ("0" & aluCmpInput) + ("0" & (not rmwBits(7 downto 0))) + "000000001";
+		when aluModeAnd =>
+			ninebits := rmwBits(8) & (A and rmwBits(7 downto 0));
+		when aluModeEor =>
+			ninebits := rmwBits(8) & (A xor rmwBits(7 downto 0));
+		when aluModeOra =>
+			ninebits := rmwBits(8) & (A or rmwBits(7 downto 0));
+		when others =>
+			ninebits := rmwBits;
+		end case;
+
+		if (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
+			varZ := rmwBits(1);
+		elsif ninebits(7 downto 0) = X"00" then
+			varZ := '1';
+		else
+			varZ := '0';
+		end if;
+
+		case opcInfo(aluMode2From to aluMode2To) is
+		when aluModeAdc =>
+			-- decimal mode low bits correction, is done after setting Z flag.
+			if D = '1' then
+				if lowBits(5 downto 1) > 9 then
+					ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
+					if lowBits(5) = '0'  then
+						ninebits(8 downto 4) := ninebits(8 downto 4) + 1;
+					end if;
+				end if;
+			end if;
+		when others =>
+			null;
+		end case;
+
+		if (opcInfo(aluMode1From to aluMode1To) = aluModeBit)
+		or (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
+			varN := rmwBits(7);
+		else
+			varN := nineBits(7);
+		end if;
+		varC := ninebits(8);
+		if opcInfo(aluMode2From to aluMode2To) = aluModeArr then
+			varC := aluInput(7);
+			varV := aluInput(7) xor aluInput(6);
+		end if;
+
+		case opcInfo(aluMode2From to aluMode2To) is
+		when aluModeAdc =>
+			-- decimal mode high bits correction, is done after setting Z and N flags
+			varV := (A(7) xor ninebits(7)) and (rmwBits(7) xor ninebits(7));
+			if D = '1' then
+				if ninebits(8 downto 4) > 9 then
+					ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
+					varC := '1';
+				end if;
+			end if;
+		when aluModeSbc =>
+			varV := (A(7) xor ninebits(7)) and ((not rmwBits(7)) xor ninebits(7));
+			if D = '1' then
+				-- Check for borrow (lower 4 bits)
+				if lowBits(5) = '0' then
+					ninebits(3 downto 0) := ninebits(3 downto 0) - 6;
+				end if;
+				-- Check for borrow (upper 4 bits)
+				if ninebits(8) = '0' then
+					ninebits(8 downto 4) := ninebits(8 downto 4) - 6;
+				end if;
+			end if;
+		when aluModeArr =>
+			if D = '1' then
+				if (("0" & aluInput(3 downto 0)) + ("0000" & aluInput(0))) > 5 then
+					ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
+				end if;
+				if (("0" & aluInput(7 downto 4)) + ("0000" & aluInput(4))) > 5 then
+					ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
+					varC := '1';
+				else
+					varC := '0';
+				end if;
+			end if;
+		when others =>
+			null;
+		end case;
+
+		if rising_edge(clk) then
+			aluRmwReg <= rmwBits(7 downto 0);
+			aluNineReg <= ninebits(7 downto 0);
+			aluCReg <= varC;
+			aluZReg <= varZ;
+			aluVReg <= varV;
+			aluNReg <= varN;
+		end if;
+
+		aluRmwOut <= rmwBits(7 downto 0);
+		aluRegisterOut <= ninebits(7 downto 0);
+		aluC <= varC;
+		aluZ <= varZ;
+		aluV <= varV;
+		aluN <= varN;
+		if pipelineAluOut then
+			aluRmwOut <= aluRmwReg;
+			aluRegisterOut <= aluNineReg;
+			aluC <= aluCReg;
+			aluZ <= aluZReg;
+			aluV <= aluVReg;
+			aluN <= aluNReg;
+		end if;
+	end process;
+
+calcInterrupt: process(clk)
+	begin
+		if rising_edge(clk) then
+			if enable = '1' then
+				if theCpuCycle = cycleStack4
+				or reset = '1' then
+					nmiReg <= '1';
+				end if;
+
+				if nextCpuCycle /= cycleBranchTaken
+				and nextCpuCycle /= opcodeFetch then
+					irqReg <= irq_n;
+					nmiEdge <= nmi_n;
+					if (nmiEdge = '1') and (nmi_n = '0') then
+						nmiReg <= '0';
+					end if;
+				end if;
+				-- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ.
+				-- Presumably this is done in the real 6502/6510 to prevent a double IRQ.
+				processIrq <= not ((nmiReg and (irqReg or I)) or opcInfo(opcIRQ));
+			end if;
+		end if;
+	end process;
+
+calcNextOpcode: process(clk, di, reset, processIrq)
+		variable myNextOpcode : unsigned(7 downto 0);
+	begin
+		-- Next opcode is read from input unless a reset or IRQ is pending.
+		myNextOpcode := di;
+		if reset = '1' then
+			myNextOpcode := X"4C";
+		elsif processIrq = '1' then
+			myNextOpcode := X"00";
+		end if;
+		
+		nextOpcode <= myNextOpcode;
+	end process;
+
+	nextOpcInfo <= opcodeInfoTable(to_integer(nextOpcode));
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			nextOpcInfoReg <= nextOpcInfo;
+		end if;
+	end process;
+
+	-- Read bits and flags from opcodeInfoTable and store in opcInfo.
+	-- This info is used to control the execution of the opcode.
+calcOpcInfo: process(clk)
+	begin
+		if rising_edge(clk) then
+			if enable = '1' then
+				if (reset = '1') or (theCpuCycle = opcodeFetch) then
+					opcInfo <= nextOpcInfo;
+					if pipelineOpcode then
+						opcInfo <= nextOpcInfoReg;
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+calcTheOpcode:	process(clk)
+	begin	
+		if rising_edge(clk) then
+			if enable = '1' then
+				if theCpuCycle = opcodeFetch then
+					irqActive <= '0';
+					if processIrq = '1' then
+						irqActive <= '1';
+					end if;
+					-- Fetch opcode
+					theOpcode <= nextOpcode;
+				end if;
+			end if;
+		end if;
+	end process;
+	
+-- -----------------------------------------------------------------------
+-- State machine
+-- -----------------------------------------------------------------------
+	process(enable, theCpuCycle, opcInfo)
+	begin
+		updateRegisters <= false;
+		if enable = '1' then
+			if opcInfo(opcRti) = '1' then
+				if theCpuCycle = cycleRead then
+					updateRegisters <= true;
+				end if;
+			elsif theCpuCycle = opcodeFetch then
+				updateRegisters <= true;
+			end if;
+		end if;
+	end process;
+
+	debugOpcode <= theOpcode;
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if enable = '1' then
+				theCpuCycle <= nextCpuCycle;
+			end if;
+			if reset = '1' then
+				theCpuCycle <= cycle2;
+			end if;				
+		end if;			
+	end process;
+
+	-- Determine the next cpu cycle. After the last cycle we always
+	-- go to opcodeFetch to get the next opcode.
+calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, indexOut, T, N, V, C, Z)
+	begin
+		nextCpuCycle <= opcodeFetch;
+
+		case theCpuCycle is
+		when opcodeFetch =>
+			nextCpuCycle <= cycle2;
+		when cycle2 =>
+			if opcInfo(opcBranch) = '1' then
+				if (N = theOpcode(5) and theOpcode(7 downto 6) = "00")
+				or (V = theOpcode(5) and theOpcode(7 downto 6) = "01")
+				or (C = theOpcode(5) and theOpcode(7 downto 6) = "10")
+				or (Z = theOpcode(5) and theOpcode(7 downto 6) = "11") then
+					-- Branch condition is true
+					nextCpuCycle <= cycleBranchTaken;
+				end if;
+			elsif (opcInfo(opcStackUp) = '1') then
+				nextCpuCycle <= cycleStack1;
+			elsif opcInfo(opcStackAddr) = '1'
+			and opcInfo(opcStackData) = '1' then
+				nextCpuCycle <= cycleStack2;
+			elsif opcInfo(opcStackAddr) = '1' then
+				nextCpuCycle <= cycleStack1;
+			elsif opcInfo(opcStackData) = '1' then
+				nextCpuCycle <= cycleWrite;
+			elsif opcInfo(opcAbsolute) = '1' then
+				nextCpuCycle <= cycle3;
+			elsif opcInfo(opcIndirect) = '1' then
+				if opcInfo(indexX) = '1' then
+					nextCpuCycle <= cyclePreIndirect;			
+				else
+					nextCpuCycle <= cycleIndirect;
+				end if;					
+			elsif opcInfo(opcZeroPage) = '1' then
+				if opcInfo(opcWrite) = '1' then
+					if (opcInfo(indexX) = '1')
+					or (opcInfo(indexY) = '1') then
+						nextCpuCycle <= cyclePreWrite;
+					else						
+						nextCpuCycle <= cycleWrite;
+					end if;						
+				else
+					if (opcInfo(indexX) = '1')
+					or (opcInfo(indexY) = '1') then
+						nextCpuCycle <= cyclePreRead;
+					else						
+						nextCpuCycle <= cycleRead2;
+					end if;						
+				end if;					
+			elsif opcInfo(opcJump) = '1' then
+				nextCpuCycle <= cycleJump;
+			end if;
+		when cycle3 =>
+			nextCpuCycle <= cycleRead;
+			if opcInfo(opcWrite) = '1' then
+				if (opcInfo(indexX) = '1')
+				or (opcInfo(indexY) = '1') then
+					nextCpuCycle <= cyclePreWrite;
+				else						
+					nextCpuCycle <= cycleWrite;
+				end if;					
+			end if;
+			if (opcInfo(opcIndirect) = '1')
+			and (opcInfo(indexX) = '1') then
+				if opcInfo(opcWrite) = '1' then
+					nextCpuCycle <= cycleWrite;
+				else					
+					nextCpuCycle <= cycleRead2;
+				end if;
+			end if;									
+		when cyclePreIndirect =>			
+			nextCpuCycle <= cycleIndirect;
+		when cycleIndirect =>
+			nextCpuCycle <= cycle3;
+		when cycleBranchTaken =>
+			if indexOut(8) /= T(7) then
+				-- Page boundary crossing during branch.
+				nextCpuCycle <= cycleBranchPage;
+			end if;
+		when cyclePreRead =>
+			if opcInfo(opcZeroPage) = '1' then
+				nextCpuCycle <= cycleRead2;
+			end if;
+		when cycleRead =>
+			if opcInfo(opcJump) = '1' then
+				nextCpuCycle <= cycleJump;
+			elsif indexOut(8) = '1' then
+				-- Page boundary crossing while indexed addressing.
+				nextCpuCycle <= cycleRead2;
+			elsif opcInfo(opcRmw) = '1' then
+				nextCpuCycle <= cycleRmw;
+				if opcInfo(indexX) = '1'
+				or opcInfo(indexY) = '1' then
+					-- 6510 needs extra cycle for indexed addressing
+					-- combined with RMW indexing
+					nextCpuCycle <= cycleRead2;
+				end if;
+			end if;											
+		when cycleRead2 =>
+			if opcInfo(opcRmw) = '1' then
+				nextCpuCycle <= cycleRmw;
+			end if;											
+		when cycleRmw =>
+			nextCpuCycle <= cycleWrite;
+		when cyclePreWrite =>
+			nextCpuCycle <= cycleWrite;
+		when cycleStack1 =>
+			nextCpuCycle <= cycleRead;
+			if opcInfo(opcStackAddr) = '1' then
+				nextCpuCycle <= cycleStack2;
+			end if;				
+		when cycleStack2 =>
+			nextCpuCycle <= cycleStack3;
+			if opcInfo(opcRti) = '1' then
+				nextCpuCycle <= cycleRead;
+			end if;
+			if opcInfo(opcStackData) = '0'
+			and opcInfo(opcStackUp) = '1' then
+				nextCpuCycle <= cycleJump;
+			end if;
+		when cycleStack3 =>
+			nextCpuCycle <= cycleRead;
+			if opcInfo(opcStackData) = '0'
+			or opcInfo(opcStackUp) = '1' then
+				nextCpuCycle <= cycleJump;
+			elsif opcInfo(opcStackAddr) = '1' then
+				nextCpuCycle <= cycleStack4;				
+			end if;
+		when cycleStack4 =>
+			nextCpuCycle <= cycleRead;
+		when cycleJump =>
+			if opcInfo(opcIncrAfter) = '1' then
+				-- Insert extra cycle
+				nextCpuCycle <= cycleEnd;
+			end if;				
+		when others =>
+			null;
+		end case;
+	end process;		
+
+-- -----------------------------------------------------------------------
+-- T register
+-- -----------------------------------------------------------------------
+calcT: process(clk)
+	begin
+		if rising_edge(clk) then
+			if enable = '1' then
+				case theCpuCycle is
+				when cycle2 =>
+					T <= di;
+				when cycleStack1 | cycleStack2 =>
+					if opcInfo(opcStackUp) = '1' then
+						-- Read from stack
+						T <= di;
+					end if;											
+				when cycleIndirect | cycleRead | cycleRead2 =>
+					T <= di;
+				when others =>
+					null;					
+				end case;
+			end if;
+		end if;		
+	end process;
+
+-- -----------------------------------------------------------------------
+-- A register
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateA) = '1' then
+					A <= aluRegisterOut;
+				end if;					
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- X register
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateX) = '1' then
+					X <= aluRegisterOut;
+				end if;					
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- Y register
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateY) = '1' then
+					Y <= aluRegisterOut;
+				end if;					
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- C flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateC) = '1' then
+					C <= aluC;
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- Z flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateZ) = '1' then
+					Z <= aluZ;
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- I flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateI) = '1' then
+					I <= aluInput(2);
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- D flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateD) = '1' then
+					D <= aluInput(3);
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- V flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateV) = '1' then
+					V <= aluV;
+				end if;
+			end if;
+			if enable = '1' then
+				if soReg = '1' and so_n = '0' then
+					V <= '1';
+				end if;
+				soReg <= so_n;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- N flag
+-- -----------------------------------------------------------------------
+	process(clk)
+	begin
+		if rising_edge(clk) then
+			if updateRegisters then
+				if opcInfo(opcUpdateN) = '1' then
+					N <= aluN;
+				end if;
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- Stack pointer
+-- -----------------------------------------------------------------------
+	process(clk)
+		variable sIncDec : unsigned(7 downto 0);
+		variable updateFlag : boolean;
+	begin
+		if rising_edge(clk) then
+
+			if opcInfo(opcStackUp) = '1' then
+				sIncDec := S + 1;
+			else
+				sIncDec := S - 1;
+			end if;	
+			
+			if enable = '1' then
+				updateFlag := false;			
+				case nextCpuCycle is
+				when cycleStack1 =>
+					if (opcInfo(opcStackUp) = '1')
+					or (opcInfo(opcStackData) = '1') then
+						updateFlag := true;			
+					end if;
+				when cycleStack2 =>
+					updateFlag := true;
+				when cycleStack3 =>
+					updateFlag := true;			
+				when cycleStack4 =>
+					updateFlag := true;
+				when cycleRead =>
+					if opcInfo(opcRti) = '1' then							
+						updateFlag := true;
+					end if;						
+				when cycleWrite =>
+					if opcInfo(opcStackData) = '1' then
+						updateFlag := true;
+					end if;						
+				when others =>
+					null;					
+				end case;
+				if updateFlag then
+					S <= sIncDec;
+				end if;					
+			end if;
+			if updateRegisters then
+				if opcInfo(opcUpdateS) = '1' then
+					S <= aluRegisterOut;
+				end if;					
+			end if;
+		end if;
+	end process;
+
+-- -----------------------------------------------------------------------
+-- Data out
+-- -----------------------------------------------------------------------
+--calcDo: process(cpuNo, theCpuCycle, aluOut, PC, T)
+calcDo: process(clk)
+	begin
+		if rising_edge(clk) then
+			if enable = '1' then
+				doReg <= aluRmwOut;
+				if opcInfo(opcInH) = '1' then
+					-- For illegal opcodes SHA, SHX, SHY, SHS
+					doReg <= aluRmwOut and myAddrIncrH;
+				end if;
+
+				case nextCpuCycle is
+				when cycleStack2 =>
+					if opcInfo(opcIRQ) = '1'
+					and irqActive = '0' then
+						doReg <= myAddrIncr(15 downto 8);
+					else
+						doReg <= PC(15 downto 8);
+					end if;
+				when cycleStack3 =>
+					doReg <= PC(7 downto 0);
+				when cycleRmw =>
+--					do <= T; -- Read-modify-write write old value first.
+					doReg <= di; -- Read-modify-write write old value first.
+				when others => null;
+				end case;
+			end if;			
+		end if;
+	end process;
+	do <= doReg;
+	
+
+
+-- -----------------------------------------------------------------------
+-- Write enable
+-- -----------------------------------------------------------------------
+calcWe: process(clk)
+	begin
+		if rising_edge(clk) then
+			if enable = '1' then
+				theWe <= '0';
+				case nextCpuCycle is
+				when cycleStack1 =>
+					if opcInfo(opcStackUp) = '0'
+					and ((opcInfo(opcStackAddr) = '0')
+					or (opcInfo(opcStackData) = '1')) then
+						theWe <= '1';
+					end if;						
+				when cycleStack2 | cycleStack3 | cycleStack4 =>
+					if opcInfo(opcStackUp) = '0' then
+						theWe <= '1';
+					end if;						
+				when cycleRmw =>
+					theWe <= '1';
+				when cycleWrite =>
+					theWe <= '1';
+				when others =>
+					null;
+				end case;				
+			end if;
+		end if;							
+	end process;
+	we <= theWe;
+
+-- -----------------------------------------------------------------------
+-- Program counter
+-- -----------------------------------------------------------------------
+calcPC: process(clk)
+	begin
+		if rising_edge(clk) then
+			if enable = '1' then
+				case theCpuCycle is
+				when opcodeFetch =>
+					PC <= myAddr;
+				when cycle2 =>
+					if irqActive = '0' then
+						if opcInfo(opcSecondByte) = '1' then
+							PC <= myAddrIncr;
+						else							
+							PC <= myAddr;
+						end if;							
+					end if;						
+				when cycle3 =>
+					if opcInfo(opcAbsolute) = '1' then
+						PC <= myAddrIncr;					
+					end if;
+				when others =>
+					null;
+				end case;
+			end if;
+		end if;
+	end process;
+	debugPc <= PC;
+
+-- -----------------------------------------------------------------------
+-- Address generation
+-- -----------------------------------------------------------------------
+calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset)
+	begin
+		nextAddr <= nextAddrIncr;
+		case theCpuCycle is
+		when cycle2 =>
+			if opcInfo(opcStackAddr) = '1' 
+			or opcInfo(opcStackData) = '1' then
+				nextAddr <= nextAddrStack;
+			elsif opcInfo(opcAbsolute) = '1' then
+				nextAddr <= nextAddrIncr;
+			elsif opcInfo(opcZeroPage) = '1' then
+				nextAddr <= nextAddrZeroPage;
+			elsif opcInfo(opcIndirect) = '1' then
+				nextAddr <= nextAddrZeroPage;
+			elsif opcInfo(opcSecondByte) = '1' then
+				nextAddr <= nextAddrIncr;
+			else
+				nextAddr <= nextAddrHold;
+			end if;
+		when cycle3 =>
+			if (opcInfo(opcIndirect) = '1')
+			and (opcInfo(indexX) = '1') then
+				nextAddr <= nextAddrAbs;
+			else							
+				nextAddr <= nextAddrAbsIndexed;
+			end if;				
+		when cyclePreIndirect =>
+			nextAddr <= nextAddrZPIndexed;
+		when cycleIndirect =>
+			nextAddr <= nextAddrIncrL;
+		when cycleBranchTaken =>
+			nextAddr <= nextAddrRelative;
+		when cycleBranchPage =>
+			if T(7) = '0' then
+				nextAddr <= nextAddrIncrH;
+			else				
+				nextAddr <= nextAddrDecrH;
+			end if;
+		when cyclePreRead =>
+			nextAddr <= nextAddrZPIndexed;
+		when cycleRead =>
+			nextAddr <= nextAddrPc;
+			if opcInfo(opcJump) = '1' then
+				-- Emulate 6510 bug, jmp(xxFF) fetches from same page.
+				-- Replace with nextAddrIncr if emulating 65C02 or later cpu.
+				nextAddr <= nextAddrIncrL; 
+			elsif indexOut(8) = '1' then
+				nextAddr <= nextAddrIncrH;
+			elsif opcInfo(opcRmw) = '1' then
+				nextAddr <= nextAddrHold;
+			end if;
+		when cycleRead2 =>
+			nextAddr <= nextAddrPc;
+			if opcInfo(opcRmw) = '1' then
+				nextAddr <= nextAddrHold;
+			end if;
+		when cycleRmw =>
+			nextAddr <= nextAddrHold;			
+		when cyclePreWrite =>
+			nextAddr <= nextAddrHold;			
+			if opcInfo(opcZeroPage) = '1' then
+				nextAddr <= nextAddrZPIndexed;
+			elsif indexOut(8) = '1' then
+				nextAddr <= nextAddrIncrH;
+			end if;							
+		when cycleWrite =>
+			nextAddr <= nextAddrPc;			
+		when cycleStack1 =>
+			nextAddr <= nextAddrStack;
+		when cycleStack2 =>
+			nextAddr <= nextAddrStack;
+		when cycleStack3 =>
+			nextAddr <= nextAddrStack;
+			if opcInfo(opcStackData) = '0' then
+				nextAddr <= nextAddrPc;
+			end if;				
+		when cycleStack4 =>
+			nextAddr <= nextAddrIrq;
+		when cycleJump =>
+			nextAddr <= nextAddrAbs;
+		when others =>
+			null;
+		end case;										
+		if reset = '1' then
+			nextAddr <= nextAddrReset;
+		end if;			
+	end process;
+	
+indexAlu: process(opcInfo, myAddr, T, X, Y)
+	begin
+		if opcInfo(indexX) = '1' then
+			indexOut <= (B"0" & T) + (B"0" & X);
+		elsif opcInfo(indexY) = '1' then
+			indexOut <= (B"0" & T) + (B"0" & Y);
+		elsif opcInfo(opcBranch) = '1' then			
+			indexOut <= (B"0" & T) + (B"0" & myAddr(7 downto 0));
+		else
+			indexOut <= B"0" & T;
+		end if;
+	end process;
+
+calcAddr: process(clk)
+	begin
+		if rising_edge(clk) then
+			if enable = '1' then
+				case nextAddr is
+				when nextAddrIncr => myAddr <= myAddrIncr;
+				when nextAddrIncrL => myAddr(7 downto 0) <= myAddrIncr(7 downto 0);
+				when nextAddrIncrH => myAddr(15 downto 8) <= myAddrIncrH;
+				when nextAddrDecrH => myAddr(15 downto 8) <= myAddrDecrH;
+				when nextAddrPc => myAddr <= PC;
+				when nextAddrIrq =>
+					myAddr <= X"FFFE";
+					if nmiReg = '0' then
+						myAddr <= X"FFFA";
+					end if;
+				when nextAddrReset => myAddr <= X"FFFC";
+				when nextAddrAbs => myAddr <= di & T;
+				when nextAddrAbsIndexed => myAddr <= di & indexOut(7 downto 0);
+				when nextAddrZeroPage => myAddr <= "00000000" & di;
+				when nextAddrZPIndexed => myAddr <= "00000000" & indexOut(7 downto 0);
+				when nextAddrStack => myAddr <= "00000001" & S;
+				when nextAddrRelative => myAddr(7 downto 0) <= indexOut(7 downto 0);
+				when others => null;
+				end case;
+			end if;
+		end if;							
+	end process;	
+
+	myAddrIncr <= myAddr + 1;
+	myAddrIncrH <= myAddr(15 downto 8) + 1;
+	myAddrDecrH <= myAddr(15 downto 8) - 1;
+
+	addr <= myAddr;
+
+	debugA <= A;
+	debugX <= X;
+	debugY <= Y;
+	debugS <= S;
+	
+end architecture;
+
+
diff --git a/cores/c16/data_io.v b/cores/c16/data_io.v
new file mode 100644
index 0000000..b7c58f9
--- /dev/null
+++ b/cores/c16/data_io.v
@@ -0,0 +1,127 @@
+//
+// data_io.v
+//
+// io controller writable ram for the MiST board
+// http://code.google.com/p/mist-board/
+//
+// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+module data_io (
+	// io controller spi interface
+	input         sck,
+	input         ss,
+	input         sdi,
+
+	output        downloading,   // signal indicating an active download
+	output [15:0] size,          // number of bytes in input buffer
+   output reg [4:0] index,      // menu index used to upload the file
+	 
+	// external ram interface
+	input 			clk,
+	output reg     wr,
+	output reg [15:0] a,
+	output [7:0]   d
+);
+
+assign d = data;
+
+parameter START_ADDR = 16'h0000;
+
+assign size = addr;
+
+// *********************************************************************************
+// spi client
+// *********************************************************************************
+
+// this core supports only the display related OSD commands
+// of the minimig
+reg [6:0]      sbuf;
+reg [7:0]      cmd /* synthesis noprune */;
+reg [7:0]      data /* synthesis noprune */;
+reg [4:0]      cnt /* synthesis noprune */;
+
+reg [15:0]     addr /* synthesis noprune */;
+reg rclk /* synthesis noprune */;
+
+localparam UIO_FILE_TX      = 8'h53;
+localparam UIO_FILE_TX_DAT  = 8'h54;
+localparam UIO_FILE_INDEX   = 8'h55;
+localparam UIO_FILE_INFO    = 8'h56;
+
+assign downloading = downloading_reg;
+reg downloading_reg = 1'b0;
+
+// data_io has its own SPI interface to the io controller
+always@(posedge sck, posedge ss) begin
+	if(ss == 1'b1)
+		cnt <= 5'd0;
+	else begin
+		rclk <= 1'b0;
+
+		// don't shift in last bit. It is evaluated directly
+		// when writing to ram
+		if(cnt != 15)
+			sbuf <= { sbuf[5:0], sdi};
+
+		// increase target address after write
+		if(rclk)
+			addr <= addr + 16'd1;
+	 
+		// count 0-7 8-15 8-15 ... 
+		if(cnt < 15) 	cnt <= cnt + 4'd1;
+		else				cnt <= 4'd8;
+
+		// finished command byte
+      if(cnt == 7)
+			cmd <= {sbuf, sdi};
+
+		// prepare/end transmission
+		if((cmd == UIO_FILE_TX) && (cnt == 15)) begin
+			// prepare
+			if(sdi) begin
+				addr <= START_ADDR;
+				downloading_reg <= 1'b1; 
+			end else
+				downloading_reg <= 1'b0; 
+		end
+		
+		// command 0x54: UIO_FILE_TX
+		if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin
+			data <= {sbuf, sdi};
+			rclk <= 1'b1;
+			a <= addr;
+		end
+		
+      // expose file (menu) index
+      if((cmd == UIO_FILE_INDEX) && (cnt == 15))
+			index <= {sbuf[3:0], sdi};
+							
+	end
+end
+
+reg rclkD, rclkD2;
+always@(posedge clk) begin
+	// bring rclk from spi clock domain into c64 clock domain
+	rclkD <= rclk;
+	rclkD2 <= rclkD;
+	wr <= 1'b0;
+	
+	if(rclkD && !rclkD2) 
+		wr <= 1'b1;
+end
+
+endmodule
\ No newline at end of file
diff --git a/cores/c16/gpl-3.0.txt b/cores/c16/gpl-3.0.txt
new file mode 100644
index 0000000..94a9ed0
--- /dev/null
+++ b/cores/c16/gpl-3.0.txt
@@ -0,0 +1,674 @@
+                    GNU GENERAL PUBLIC LICENSE
+                       Version 3, 29 June 2007
+
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+GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
+USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
+DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
+PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
+EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
+SUCH DAMAGES.
+
+  17. Interpretation of Sections 15 and 16.
+
+  If the disclaimer of warranty and limitation of liability provided
+above cannot be given local legal effect according to their terms,
+reviewing courts shall apply local law that most closely approximates
+an absolute waiver of all civil liability in connection with the
+Program, unless a warranty or assumption of liability accompanies a
+copy of the Program in return for a fee.
+
+                     END OF TERMS AND CONDITIONS
+
+            How to Apply These Terms to Your New Programs
+
+  If you develop a new program, and you want it to be of the greatest
+possible use to the public, the best way to achieve this is to make it
+free software which everyone can redistribute and change under these terms.
+
+  To do so, attach the following notices to the program.  It is safest
+to attach them to the start of each source file to most effectively
+state the exclusion of warranty; and each file should have at least
+the "copyright" line and a pointer to where the full notice is found.
+
+    <one line to give the program's name and a brief idea of what it does.>
+    Copyright (C) <year>  <name of author>
+
+    This program is free software: you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation, either version 3 of the License, or
+    (at your option) any later version.
+
+    This program is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+
+Also add information on how to contact you by electronic and paper mail.
+
+  If the program does terminal interaction, make it output a short
+notice like this when it starts in an interactive mode:
+
+    <program>  Copyright (C) <year>  <name of author>
+    This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
+    This is free software, and you are welcome to redistribute it
+    under certain conditions; type `show c' for details.
+
+The hypothetical commands `show w' and `show c' should show the appropriate
+parts of the General Public License.  Of course, your program's commands
+might be different; for a GUI interface, you would use an "about box".
+
+  You should also get your employer (if you work as a programmer) or school,
+if any, to sign a "copyright disclaimer" for the program, if necessary.
+For more information on this, and how to apply and follow the GNU GPL, see
+<http://www.gnu.org/licenses/>.
+
+  The GNU General Public License does not permit incorporating your program
+into proprietary programs.  If your program is a subroutine library, you
+may consider it more useful to permit linking proprietary applications with
+the library.  If this is what you want to do, use the GNU Lesser General
+Public License instead of this License.  But first, please read
+<http://www.gnu.org/philosophy/why-not-lgpl.html>.
diff --git a/cores/c16/kernal_PAL.hex b/cores/c16/kernal_PAL.hex
new file mode 100644
index 0000000..310caaf
--- /dev/null
+++ b/cores/c16/kernal_PAL.hex
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diff --git a/cores/c16/kernal_rom.v b/cores/c16/kernal_rom.v
new file mode 100644
index 0000000..7131858
--- /dev/null
+++ b/cores/c16/kernal_rom.v
@@ -0,0 +1,78 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+//  Copyright 2013-2016 Istvan Hegedus
+//
+//  FPGATED is free software: you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation, either version 3 of the License, or
+//  (at your option) any later version.
+//
+//  FPGATED is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program.  If not, see <http://www.gnu.org/licenses/>. 
+//
+//	 Create Date:    17:12:57 12/05/2014 
+//  Design Name: 	 Commodore 16/Plus 4 Kernal ROM
+//  Module Name:    kernal_rom 
+//  Project Name: 	 FPGATED
+//  Description:  
+//		Kernal ROM synthetised to FPGA's internal SRAM. Xilinx ISE requires 
+//		ROM_STYLE="BLOCK" parameter next to kernal array. For other vendor's
+//		device syntax refer to the FPGA vendor's documentation.
+//		
+//		Choose the proper Kernal file version depending on NTSC or PAL system
+// 	and comment out the ones which are not needed. 
+//		If you want to convert your own kernal image to compatible version use
+//		bin2hex.pl perl script to convert it to .hex format.
+//////////////////////////////////////////////////////////////////////////////////
+module kernal_rom(
+	 input wire clk,
+    input wire [13:0] address_in,
+    output wire [7:0] data_out,
+    input wire [7:0] data_in,
+    input wire wr,
+    input wire cs
+    );
+
+(* ROM_STYLE="BLOCK" *)
+reg [7:0] kernal [0:16383];
+reg [7:0] data;
+reg cs_prev=1'b1;
+wire enable;
+
+initial begin
+// uncomment the Kernal version to use
+
+//$readmemh("Diag264_PAL.hex",kernal);
+
+//$readmemh("Diag264_NTSC.hex",kernal);
+
+$readmemh("kernal_PAL.hex",kernal);
+
+//$readmemh("kernal_NTSC.hex",kernal);
+
+//$readmemh("Jiffy_PAL.hex",kernal); 
+// Note that Jiffy DOS is not free so Jiffy_PAL.hex is not included with FPGATED source code
+
+end
+
+always@(posedge clk) begin
+	if (wr)
+		kernal[address_in] <= data_in;
+		
+	if(enable)
+		data<=kernal[address_in];
+end
+		
+always@(posedge clk)
+	cs_prev<=cs;
+
+assign enable=~cs&cs_prev;		// cs falling edge detection
+assign data_out=(~cs)?data:8'hff;
+
+
+endmodule
diff --git a/cores/c16/mos6529.v b/cores/c16/mos6529.v
new file mode 100644
index 0000000..40354e0
--- /dev/null
+++ b/cores/c16/mos6529.v
@@ -0,0 +1,54 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+//  Copyright 2013-2016 Istvan Hegedus
+//
+//  FPGATED is free software: you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation, either version 3 of the License, or
+//  (at your option) any later version.
+//
+//  FPGATED is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program.  If not, see <http://www.gnu.org/licenses/>. 
+//
+// Create Date:    09:08:17 12/17/2015 
+// Design Name: 	 FPGATED
+// Module Name:    mos6529.v 
+// Description:	 MOS 6529 IC emulation.
+//	
+// Revision: 
+// 0.1	first release 				
+//	1.0	chip read bug fixed 5/04/2016
+//  
+// Additional Comments: 
+// CS signal is high active while in real IC it is low active.
+//////////////////////////////////////////////////////////////////////////////////
+
+module mos6529(
+	 input clk,
+    input [7:0] data_in,
+    output wire [7:0] data_out,
+    input [7:0] port_in,
+    output wire [7:0] port_out,
+    input rw,
+    input cs
+    );
+
+reg [7:0] iodata=0;
+
+assign port_out=iodata;
+assign data_out=(cs & rw)?iodata:8'hff;
+
+always @(posedge clk)
+	begin
+	if(cs)
+		if(rw)
+			iodata<=port_in;
+		else
+			iodata<=data_in;
+	end
+endmodule
diff --git a/cores/c16/mos8501.v b/cores/c16/mos8501.v
new file mode 100644
index 0000000..e6f7a8c
--- /dev/null
+++ b/cores/c16/mos8501.v
@@ -0,0 +1,188 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+//  Copyright 2013-2016 Istvan Hegedus
+//
+//  FPGATED is free software: you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation, either version 3 of the License, or
+//  (at your option) any later version.
+//
+//  FPGATED is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program.  If not, see <http://www.gnu.org/licenses/>. 
+//
+// Create Date:    16:36:31 12/10/2014 
+// Module Name:    mos8501 
+// Project Name:	 FPGATED 
+// Target Devices: Xilinx Spartan 3E
+//
+// Description: 
+//
+// Dependencies: 
+//	This module contains an instance of Peter Wendrich's 6502 CPU core from FPGA64 project. 
+//	The CPU core is used and included with Peter's permission and not developed by me.
+// The mos8501 shell around the CPU core is written by me, but inspired by fpga64 6510 CPU
+// shell. It might shows certain similarities.
+//
+// Revision history:
+//	0.1	first release using incorrect 6502 core from fpga64 project
+//	1.0	CPU core replaced to cpu65xx_fast.vhd from fpga64 project
+//
+//////////////////////////////////////////////////////////////////////////////////
+module mos8501(
+    input clk,
+    input reset,
+    input enable,
+    input irq_n,
+    input [7:0] data_in,
+	 output wire [7:0] data_out,
+	 output [15:0] address,
+	 input gate_in,
+    output rw,
+	 input [7:0] port_in,
+	 output [7:0] port_out,
+	 input rdy,
+	 input aec
+    );
+
+wire we,enable_cpu;
+wire [15:0] core_address;
+wire [7:0] core_data_out;
+wire port_access;
+reg  [7:0] data_out_reg,core_data_in,port_io;
+reg [7:0] port_dir=8'b0;
+reg [7:0] port_data=8'b0;
+reg rw_reg,aec_reg;
+
+// 6502 CPU core
+
+	cpu65xx #(.pipelineOpcode("\false"),.pipelineAluMux("\false"),.pipelineAluOut("\false")) 
+		cpu_core(
+		.clk(clk), 
+		.reset(reset), 
+		.enable(enable_cpu), 
+		.nmi_n(1'b1), 
+		.irq_n(irq_n), 
+		.di(core_data_in), 
+		.do(core_data_out), 
+		.addr(core_address), 
+		.we(we),
+		.so_n(1'b1),
+		.debugOpcode(),
+		.debugPc(),
+		.debugA(),
+		.debugX(),
+		.debugY(),
+		.debugS()
+	);
+
+assign address=(aec)?core_address:16'hffff;		// address tri state emulated for easy bus signal combining
+
+always @(posedge clk)		
+	begin
+	if(gate_in)				
+		begin							
+		if(port_access==1'b1 && we==1'b1)
+			if(address[0]==1'b0)							// when port direction register is written, data on bus is last read byte which is 0x00
+				data_out_reg<=8'h00;
+			else												// when port register is written, data on bus is last read byte which is 0x01
+				data_out_reg<=8'h01;
+		else
+			data_out_reg<=core_data_out;				// when mux is high, data out register is updated
+		end
+	else
+		begin
+		data_out_reg<=data_out_reg;					// hold off data out during write cycle
+		end
+	end
+
+always @(posedge clk)
+	begin
+	if(gate_in)
+		rw_reg<=~we;		
+	end
+
+always @(posedge clk)									// registering aec for 1 clk cycle delay
+	begin
+	aec_reg<=aec;
+	end
+
+assign rw=(~aec_reg)?1'b1:rw_reg;
+
+assign data_out=(~aec_reg | gate_in | rw)?8'hff:data_out_reg;   		// when mux is low data out register is allowed to outside								
+assign port_access=(address[15:1]==0)?1'b1:1'b0;
+
+// IO port part of cpu
+	
+always @(posedge clk)									//writing port registers
+	begin
+	if(reset)
+		begin
+		port_dir<=0;
+		port_data<=0;
+		end
+	else if (enable)
+			if(port_access & we)
+				if(address[0]==0)
+					port_dir<=core_data_out;
+				else
+					port_data<=core_data_out;
+	end
+	
+always @*													// reading port registers
+	begin
+	core_data_in=data_in;
+	if (port_access & ~we)
+		if(address[0]==0)
+			core_data_in=port_dir;
+		else
+			core_data_in=port_io;
+	end
+	
+// if direction bit is 0 then data is from chip's port
+// if direction bit is 1 then data is from data port register filled earlier by CPU
+
+always @*
+	begin
+		if(port_dir[0]==1'b0)
+				port_io[0]=port_in[0];				
+			else
+				port_io[0]=port_data[0];			
+		if(port_dir[1]==1'b0)
+				port_io[1]=port_in[1];				
+			else
+				port_io[1]=port_data[1];
+		if(port_dir[2]==1'b0)
+				port_io[2]=port_in[2];				
+			else
+				port_io[2]=port_data[2];
+		if(port_dir[3]==1'b0)
+				port_io[3]=port_in[3];				
+			else
+				port_io[3]=port_data[3];
+		if(port_dir[4]==1'b0)
+				port_io[4]=port_in[4];				
+			else
+				port_io[4]=port_data[4];
+		if(port_dir[5]==1'b0)
+				port_io[5]=port_in[5];				
+			else
+				port_io[5]=port_data[5];
+		if(port_dir[6]==1'b0)
+				port_io[6]=port_in[6];				
+			else
+				port_io[6]=port_data[6];
+		if(port_dir[7]==1'b0)
+				port_io[7]=port_in[7];				
+			else
+				port_io[7]=port_data[7];
+	end
+	
+assign port_out=port_data;
+assign enable_cpu=(~rdy & ~we)?1'b0:enable;			// When RDY is low and cpu would do a read, halt cpu									
+					 
+endmodule
diff --git a/cores/c16/osd.v b/cores/c16/osd.v
new file mode 100644
index 0000000..3c5ba47
--- /dev/null
+++ b/cores/c16/osd.v
@@ -0,0 +1,204 @@
+//
+// osd.v
+//
+// A simple OSD implementation. Can be hooked up between a cores
+// VGA output and the physical VGA pins
+//
+// Sinclair QL for the MiST
+// https://github.com/mist-devel
+// 
+// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
+// 
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or 
+// (at your option) any later version. 
+// 
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of 
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License 
+// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
+//
+
+module osd (
+	// OSDs pixel clock, should be synchronous to cores pixel clock to
+	// avoid jitter.
+	input 			pclk,
+
+	// SPI interface
+	input         sck,
+	input         ss,
+	input         sdi,
+
+	// VGA signals coming from core
+	input [5:0]  	red_in,
+	input [5:0]  	green_in,
+	input [5:0]  	blue_in,
+	input				hs_in,
+	input				vs_in,
+	
+	// VGA signals going to video connector
+	output [5:0]  	red_out,
+	output [5:0]  	green_out,
+	output [5:0]  	blue_out,
+	output			hs_out,
+	output			vs_out
+);
+
+parameter OSD_X_OFFSET = 10'd0;
+parameter OSD_Y_OFFSET = 10'd0;
+parameter OSD_COLOR    = 3'd0;
+
+localparam OSD_WIDTH  = 10'd256;
+localparam OSD_HEIGHT = 10'd128;
+
+// *********************************************************************************
+// spi client
+// *********************************************************************************
+
+// this core supports only the display related OSD commands
+// of the minimig
+reg [7:0]      sbuf;
+reg [7:0]      cmd;
+reg [4:0]      cnt;
+reg [10:0]     bcnt;
+reg    			osd_enable;
+
+reg [7:0] osd_buffer [2047:0];  // the OSD buffer itself
+
+// the OSD has its own SPI interface to the io controller
+always@(posedge sck, posedge ss) begin
+  if(ss == 1'b1) begin
+      cnt <= 5'd0;
+      bcnt <= 11'd0;
+  end else begin
+    sbuf <= { sbuf[6:0], sdi};
+
+    // 0:7 is command, rest payload
+    if(cnt < 15)
+      cnt <= cnt + 4'd1;
+    else
+      cnt <= 4'd8;
+
+      if(cnt == 7) begin
+       cmd <= {sbuf[6:0], sdi};
+      
+      // lower three command bits are line address
+      bcnt <= { sbuf[1:0], sdi, 8'h00};
+
+      // command 0x40: OSDCMDENABLE, OSDCMDDISABLE
+      if(sbuf[6:3] == 4'b0100)
+        osd_enable <= sdi;
+    end
+
+    // command 0x20: OSDCMDWRITE
+    if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
+      osd_buffer[bcnt] <= {sbuf[6:0], sdi};
+      bcnt <= bcnt + 11'd1;
+    end
+  end
+end
+
+// *********************************************************************************
+// video timing and sync polarity anaylsis
+// *********************************************************************************
+
+// horizontal counter
+reg [9:0] h_cnt;
+reg hsD, hsD2;
+reg [9:0] hs_low, hs_high;
+wire hs_pol = hs_high < hs_low;
+wire [9:0] h_dsp_width = hs_pol?hs_low:hs_high;
+wire [9:0] h_dsp_ctr = { 1'b0, h_dsp_width[9:1] };
+
+always @(posedge pclk) begin
+	// bring hsync into local clock domain
+	hsD <= hs_in;
+	hsD2 <= hsD;
+
+	// falling edge of hs_in
+	if(!hsD && hsD2) begin	
+		h_cnt <= 10'd0;
+		hs_high <= h_cnt;
+	end
+
+	// rising edge of hs_in
+	else if(hsD && !hsD2) begin	
+		h_cnt <= 10'd0;
+		hs_low <= h_cnt;
+	end 
+	
+	else
+		h_cnt <= h_cnt + 10'd1;
+end
+
+// vertical counter
+reg [9:0] v_cnt;
+reg vsD, vsD2;
+reg [9:0] vs_low, vs_high;
+wire vs_pol = vs_high < vs_low;
+wire [9:0] v_dsp_width = vs_pol?vs_low:vs_high;
+wire [9:0] v_dsp_ctr = { 1'b0, v_dsp_width[9:1] };
+
+always @(posedge hs_in) begin
+	// bring vsync into local clock domain
+	vsD <= vs_in;
+	vsD2 <= vsD;
+
+	// falling edge of vs_in
+	if(!vsD && vsD2) begin	
+		v_cnt <= 10'd0;
+		vs_high <= v_cnt;
+	end
+
+	// rising edge of vs_in
+	else if(vsD && !vsD2) begin	
+		v_cnt <= 10'd0;
+		vs_low <= v_cnt;
+	end 
+	
+	else
+		v_cnt <= v_cnt + 10'd1;
+end
+
+// area in which OSD is being displayed
+wire [9:0] h_osd_start = h_dsp_ctr + OSD_X_OFFSET - (OSD_WIDTH >> 1);
+wire [9:0] h_osd_end   = h_dsp_ctr + OSD_X_OFFSET + (OSD_WIDTH >> 1) - 1;
+wire [9:0] v_osd_start = v_dsp_ctr + OSD_Y_OFFSET - (OSD_HEIGHT >> 1);
+wire [9:0] v_osd_end   = v_dsp_ctr + OSD_Y_OFFSET + (OSD_HEIGHT >> 1) - 1;
+
+reg h_osd_active, v_osd_active;
+always @(posedge pclk) begin
+	if(hs_in != hs_pol) begin
+		if(h_cnt == h_osd_start) h_osd_active <= 1'b1;
+		if(h_cnt == h_osd_end)   h_osd_active <= 1'b0;
+	end
+	if(vs_in != vs_pol) begin
+		if(v_cnt == v_osd_start) v_osd_active <= 1'b1;
+		if(v_cnt == v_osd_end)   v_osd_active <= 1'b0;
+	end
+end
+
+wire osd_de = osd_enable && h_osd_active && v_osd_active;
+
+wire [7:0] osd_hcnt = h_cnt - h_osd_start + 7'd1;  // one pixel offset for osd_byte register
+wire [6:0] osd_vcnt = v_cnt - v_osd_start;
+
+wire osd_pixel = osd_byte[osd_vcnt[3:1]];
+
+reg [7:0] osd_byte; 
+always @(posedge pclk)
+  osd_byte <= osd_buffer[{osd_vcnt[6:4], osd_hcnt}];
+
+wire [2:0] osd_color = OSD_COLOR;
+assign red_out   = !osd_de?red_in:  {osd_pixel, osd_pixel, osd_color[2], red_in[5:3]  };
+assign green_out = !osd_de?green_in:{osd_pixel, osd_pixel, osd_color[1], green_in[5:3]};
+assign blue_out  = !osd_de?blue_in: {osd_pixel, osd_pixel, osd_color[0], blue_in[5:3] };
+
+assign hs_out = hs_in;
+assign vs_out = vs_in;
+
+endmodule
diff --git a/cores/c16/pll.ppf b/cores/c16/pll.ppf
new file mode 100644
index 0000000..b7fa3e1
--- /dev/null
+++ b/cores/c16/pll.ppf
@@ -0,0 +1,11 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
diff --git a/cores/c16/pll_ntsc.qip b/cores/c16/pll_ntsc.qip
new file mode 100644
index 0000000..4a8f47e
--- /dev/null
+++ b/cores/c16/pll_ntsc.qip
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_ntsc.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_ntsc.ppf"]
diff --git a/cores/c16/pll_ntsc.v b/cores/c16/pll_ntsc.v
new file mode 100644
index 0000000..2a6abf2
--- /dev/null
+++ b/cores/c16/pll_ntsc.v
@@ -0,0 +1,309 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: pll_ntsc.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.4 Build 182 03/12/2014 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2014 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll_ntsc (
+	inclk0,
+	c0,
+	locked);
+
+	input	  inclk0;
+	output	  c0;
+	output	  locked;
+
+	wire [4:0] sub_wire0;
+	wire  sub_wire2;
+	wire [0:0] sub_wire5 = 1'h0;
+	wire [0:0] sub_wire1 = sub_wire0[0:0];
+	wire  c0 = sub_wire1;
+	wire  locked = sub_wire2;
+	wire  sub_wire3 = inclk0;
+	wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
+
+	altpll	altpll_component (
+				.inclk (sub_wire4),
+				.clk (sub_wire0),
+				.locked (sub_wire2),
+				.activeclock (),
+				.areset (1'b0),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.bandwidth_type = "AUTO",
+		altpll_component.clk0_divide_by = 270000,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 286363,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 37037,
+		altpll_component.intended_device_family = "Cyclone III",
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_ntsc",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.pll_type = "AUTO",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_UNUSED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_USED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_UNUSED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.self_reset_on_loss_lock = "OFF",
+		altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "183"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "28.636299"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "191"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.63630000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_ntsc.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.000"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "270000"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "286363"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/cores/c16/pll_pal.qip b/cores/c16/pll_pal.qip
new file mode 100644
index 0000000..6c4dccc
--- /dev/null
+++ b/cores/c16/pll_pal.qip
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_pal.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_pal.ppf"]
diff --git a/cores/c16/pll_pal.v b/cores/c16/pll_pal.v
new file mode 100644
index 0000000..4e0e7c0
--- /dev/null
+++ b/cores/c16/pll_pal.v
@@ -0,0 +1,309 @@
+// megafunction wizard: %ALTPLL%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll 
+
+// ============================================================
+// File Name: pll_pal.v
+// Megafunction Name(s):
+// 			altpll
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.4 Build 182 03/12/2014 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2014 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll_pal (
+	inclk0,
+	c0,
+	locked);
+
+	input	  inclk0;
+	output	  c0;
+	output	  locked;
+
+	wire [4:0] sub_wire0;
+	wire  sub_wire2;
+	wire [0:0] sub_wire5 = 1'h0;
+	wire [0:0] sub_wire1 = sub_wire0[0:0];
+	wire  c0 = sub_wire1;
+	wire  locked = sub_wire2;
+	wire  sub_wire3 = inclk0;
+	wire [1:0] sub_wire4 = {sub_wire5, sub_wire3};
+
+	altpll	altpll_component (
+				.inclk (sub_wire4),
+				.clk (sub_wire0),
+				.locked (sub_wire2),
+				.activeclock (),
+				.areset (1'b0),
+				.clkbad (),
+				.clkena ({6{1'b1}}),
+				.clkloss (),
+				.clkswitch (1'b0),
+				.configupdate (1'b0),
+				.enable0 (),
+				.enable1 (),
+				.extclk (),
+				.extclkena ({4{1'b1}}),
+				.fbin (1'b1),
+				.fbmimicbidir (),
+				.fbout (),
+				.fref (),
+				.icdrclk (),
+				.pfdena (1'b1),
+				.phasecounterselect ({4{1'b1}}),
+				.phasedone (),
+				.phasestep (1'b1),
+				.phaseupdown (1'b1),
+				.pllena (1'b1),
+				.scanaclr (1'b0),
+				.scanclk (1'b0),
+				.scanclkena (1'b1),
+				.scandata (1'b0),
+				.scandataout (),
+				.scandone (),
+				.scanread (1'b0),
+				.scanwrite (1'b0),
+				.sclkout0 (),
+				.sclkout1 (),
+				.vcooverrange (),
+				.vcounderrange ());
+	defparam
+		altpll_component.bandwidth_type = "AUTO",
+		altpll_component.clk0_divide_by = 39,
+		altpll_component.clk0_duty_cycle = 50,
+		altpll_component.clk0_multiply_by = 41,
+		altpll_component.clk0_phase_shift = "0",
+		altpll_component.compensate_clock = "CLK0",
+		altpll_component.inclk0_input_frequency = 37037,
+		altpll_component.intended_device_family = "Cyclone III",
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_pal",
+		altpll_component.lpm_type = "altpll",
+		altpll_component.operation_mode = "NORMAL",
+		altpll_component.pll_type = "AUTO",
+		altpll_component.port_activeclock = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_UNUSED",
+		altpll_component.port_clkbad0 = "PORT_UNUSED",
+		altpll_component.port_clkbad1 = "PORT_UNUSED",
+		altpll_component.port_clkloss = "PORT_UNUSED",
+		altpll_component.port_clkswitch = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_fbin = "PORT_UNUSED",
+		altpll_component.port_inclk0 = "PORT_USED",
+		altpll_component.port_inclk1 = "PORT_UNUSED",
+		altpll_component.port_locked = "PORT_USED",
+		altpll_component.port_pfdena = "PORT_UNUSED",
+		altpll_component.port_phasecounterselect = "PORT_UNUSED",
+		altpll_component.port_phasedone = "PORT_UNUSED",
+		altpll_component.port_phasestep = "PORT_UNUSED",
+		altpll_component.port_phaseupdown = "PORT_UNUSED",
+		altpll_component.port_pllena = "PORT_UNUSED",
+		altpll_component.port_scanaclr = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_UNUSED",
+		altpll_component.port_scanclkena = "PORT_UNUSED",
+		altpll_component.port_scandata = "PORT_UNUSED",
+		altpll_component.port_scandataout = "PORT_UNUSED",
+		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanread = "PORT_UNUSED",
+		altpll_component.port_scanwrite = "PORT_UNUSED",
+		altpll_component.port_clk0 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_UNUSED",
+		altpll_component.port_clk2 = "PORT_UNUSED",
+		altpll_component.port_clk3 = "PORT_UNUSED",
+		altpll_component.port_clk4 = "PORT_UNUSED",
+		altpll_component.port_clk5 = "PORT_UNUSED",
+		altpll_component.port_clkena0 = "PORT_UNUSED",
+		altpll_component.port_clkena1 = "PORT_UNUSED",
+		altpll_component.port_clkena2 = "PORT_UNUSED",
+		altpll_component.port_clkena3 = "PORT_UNUSED",
+		altpll_component.port_clkena4 = "PORT_UNUSED",
+		altpll_component.port_clkena5 = "PORT_UNUSED",
+		altpll_component.port_extclk0 = "PORT_UNUSED",
+		altpll_component.port_extclk1 = "PORT_UNUSED",
+		altpll_component.port_extclk2 = "PORT_UNUSED",
+		altpll_component.port_extclk3 = "PORT_UNUSED",
+		altpll_component.self_reset_on_loss_lock = "OFF",
+		altpll_component.width_clock = 5;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "39"
+// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "28.384615"
+// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "41"
+// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.37500000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_pal.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
+// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.000"
+// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "39"
+// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "41"
+// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
+// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/cores/c16/ps2receiver.v b/cores/c16/ps2receiver.v
new file mode 100644
index 0000000..e119f08
--- /dev/null
+++ b/cores/c16/ps2receiver.v
@@ -0,0 +1,76 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+//  Copyright 2013-2016 Istvan Hegedus
+//
+//  FPGATED is free software: you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation, either version 3 of the License, or
+//  (at your option) any later version.
+//
+//  FPGATED is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program.  If not, see <http://www.gnu.org/licenses/>. 
+//
+// Create Date:    11:30:06 12/14/2015 
+// Module Name:    ps2receiver.v
+// Project Name: 	 FPGATED
+// Description: 	 PS2 keyboard receiver
+//
+// 
+//
+// Revision: 
+// Revision 1.0 - File Created
+// Additional Comments: 
+//
+//////////////////////////////////////////////////////////////////////////////////
+module ps2receiver(
+    input clk,
+    input ps2_clk,
+    input ps2_data,
+    output reg rx_done,
+    output reg [7:0] ps2scancode
+    );
+
+reg ps2clkreg=1'b0,prev_ps2clkreg=1'b0;
+reg [3:0] receivedbits=4'b0;
+reg [11:0] watchdog=12'd2900;								// ~ 100us watchdog period with 28MHz clock
+reg [7:0] ps2clkfilter;
+reg [10:0] shiftreg;
+
+always @(posedge clk)										// filtering ps2 clock line glitches
+	begin
+	ps2clkfilter<={ps2clkfilter[6:0],ps2_clk};
+	if(ps2clkfilter==8'h00)
+		ps2clkreg<=0;
+	else if (ps2clkfilter==8'hff)
+		ps2clkreg<=1;
+	prev_ps2clkreg<=ps2clkreg;								// this is needed for clock edge detection
+	end
+
+always @(posedge clk)
+	begin
+	rx_done<=0;													// rx_done is active only for one clk cycle
+	if(watchdog==0)											// when watchdog timer expires, reset received bits
+		receivedbits<=0;
+	else watchdog<=watchdog-1;
+		
+	if(prev_ps2clkreg & ~ps2clkreg)						// falling edge of ps2 clock
+		begin
+		watchdog<=12'd2900;									// reload watchdog timer
+		shiftreg<={ps2_data,shiftreg[10:1]};
+		receivedbits<=receivedbits+1;
+		end
+		
+	if(receivedbits==4'd11)
+		begin
+		ps2scancode<=shiftreg[9:1];
+		rx_done<=1;
+		receivedbits<=0;
+		end
+	end
+
+endmodule
diff --git a/cores/c16/scandoubler.v b/cores/c16/scandoubler.v
new file mode 100644
index 0000000..9915fd2
--- /dev/null
+++ b/cores/c16/scandoubler.v
@@ -0,0 +1,177 @@
+//
+// scandoubler.v
+// 
+// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
+// 
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or 
+// (at your option) any later version. 
+// 
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of 
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License 
+// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
+
+// TODO: Delay vsync one line
+
+module scandoubler
+(
+	// system interface
+	input            clk_sys,
+
+	// scanlines (00-none 01-25% 10-50% 11-75%)
+	input      [1:0] scanlines,
+
+	// shifter video interface
+	input            hs_in,
+	input            vs_in,
+	input      [3:0] r_in,
+	input      [3:0] g_in,
+	input      [3:0] b_in,
+
+	// output interface
+	output reg       hs_out,
+	output reg       vs_out,
+	output reg [5:0] r_out,
+	output reg [5:0] g_out,
+	output reg [5:0] b_out
+);
+
+
+// try to detect changes in input signal and lock input clock gate
+// it
+reg last_hs_in;
+reg [1:0] i_div;
+wire ce_x1 = (i_div == 2'b01);
+wire ce_x2 = i_div[0];
+
+always @(posedge clk_sys) begin
+	if(last_hs_in != hs_in) begin
+		i_div <= 2'b00;
+		last_hs_in <= hs_in;
+	end else begin
+		i_div <= i_div + 2'd1;
+	end
+end	
+
+// --------------------- create output signals -----------------
+// latch everything once more to make it glitch free and apply scanline effect
+reg scanline;
+always @(posedge clk_sys) begin
+	if(ce_x2) begin
+		hs_out <= hs_sd;
+		vs_out <= vs_in;
+
+		// reset scanlines at every new screen
+		if(vs_out != vs_in) scanline <= 0;
+
+		// toggle scanlines at begin of every hsync
+		if(hs_out && !hs_sd) scanline <= !scanline;
+
+		// if no scanlines or not a scanline
+		if(!scanline || !scanlines) begin
+			r_out <= { sd_out[11:8], 2'b00 };
+			g_out <= { sd_out[7:4], 2'b00 };
+			b_out <= { sd_out[3:0], 2'b00 };
+		end else begin
+			case(scanlines)
+				1: begin // reduce 25% = 1/2 + 1/4
+					r_out <= {1'b0, sd_out[11:8], 1'b0} + {2'b00, sd_out[11:8]};
+					g_out <= {1'b0, sd_out[7:4],  1'b0} + {2'b00, sd_out[7:4] };
+					b_out <= {1'b0, sd_out[3:0],  1'b0} + {2'b00, sd_out[3:0]  };
+				end
+
+				2: begin // reduce 50% = 1/2
+					r_out <= {1'b0, sd_out[11:8], 1'b0};
+					g_out <= {1'b0, sd_out[7:4],  1'b0};
+					b_out <= {1'b0, sd_out[3:0],  1'b0};
+				end
+
+				3: begin // reduce 75% = 1/4
+					r_out <= {2'b00, sd_out[11:8]};
+					g_out <= {2'b00, sd_out[7:4]};
+					b_out <= {2'b00, sd_out[3:0]};
+				end
+			endcase
+		end
+	end
+end
+
+// scan doubler output register
+reg [11:0] sd_out;
+
+// ==================================================================
+// ======================== the line buffers ========================
+// ==================================================================
+
+// 2 lines of 512 pixels 3*4 bit RGB
+(* ramstyle = "no_rw_check" *) reg [11:0] sd_buffer[1023:0];
+
+// use alternating sd_buffers when storing/reading data   
+reg        line_toggle;
+
+// total hsync time (in 16MHz cycles), hs_total reaches 1024
+reg  [8:0] hs_max;
+reg  [8:0] hs_rise;
+reg  [8:0] hcnt;
+
+always @(posedge clk_sys) begin
+	reg hsD, vsD;
+
+	if(ce_x1) begin
+		hsD <= hs_in;
+
+		// falling edge of hsync indicates start of line
+		if(hsD && !hs_in) begin
+			hs_max <= hcnt;
+			hcnt <= 9'd0;
+		end else begin
+			hcnt <= hcnt + 9'd1;
+		end
+
+		// save position of rising edge
+		if(!hsD && hs_in) hs_rise <= hcnt;
+
+		vsD <= vs_in;
+		if(vsD != vs_in) line_toggle <= 0;
+
+		// begin of incoming hsync
+		if(hsD && !hs_in) line_toggle <= !line_toggle;
+
+		sd_buffer[{line_toggle, hcnt}] <= {r_in, g_in, b_in};
+	end
+end
+
+// ==================================================================
+// ==================== output timing generation ====================
+// ==================================================================
+
+reg  [8:0] sd_hcnt;
+reg        hs_sd;
+
+// timing generation runs 32 MHz (twice the input signal analysis speed)
+always @(posedge clk_sys) begin
+	reg hsD;
+
+	if(ce_x2) begin
+		hsD <= hs_in;
+
+		// output counter synchronous to input and at twice the rate
+		sd_hcnt <= sd_hcnt + 9'd1;
+		if(hsD && !hs_in)     sd_hcnt <= hs_max;
+		if(sd_hcnt == hs_max) sd_hcnt <= 0;
+
+		// replicate horizontal sync at twice the speed
+		if(sd_hcnt == hs_max)  hs_sd <= 0;
+		if(sd_hcnt == hs_rise) hs_sd <= 1;
+
+		// read data from line sd_buffer
+		sd_out <= sd_buffer[{~line_toggle, sd_hcnt}];
+	end
+end
+
+endmodule
diff --git a/cores/c16/sdram.v b/cores/c16/sdram.v
new file mode 100644
index 0000000..d9fcb0b
--- /dev/null
+++ b/cores/c16/sdram.v
@@ -0,0 +1,150 @@
+//
+// sdram.v
+//
+// sdram controller implementation for the MiST board
+// https://github.com/mist-devel
+// 
+// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
+// 
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or 
+// (at your option) any later version. 
+// 
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of 
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License 
+// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
+//
+
+module sdram (
+
+	// interface to the MT48LC16M16 chip
+	inout [15:0]  		sd_data,    // 16 bit bidirectional data bus
+	output reg [12:0]	sd_addr,    // 13 bit multiplexed address bus
+	output reg [1:0] 	sd_dqm,     // two byte masks
+	output reg[1:0] 	sd_ba,      // two banks
+	output 				sd_cs,      // a single chip select
+	output 				sd_we,      // write enable
+	output 				sd_ras,     // row address select
+	output 				sd_cas,     // columns address select
+
+	// cpu/chipset interface
+	input 		 		init,			// init signal after FPGA config to initialize RAM
+	input 		 		clk,			// sdram is accessed at up to 128MHz
+	input					clkref,		// reference clock to sync to
+	
+	input [15:0]  		din,			// data input from chipset/cpu
+	output [15:0] 		dout,			// data output to chipset/cpu
+	input [24:0]   	addr,       // 25 bit word address
+	input [1:0] 		ds,         // data strobe for hi/low byte
+	input 		 		oe,         // cpu/chipset requests read
+	input 		 		we          // cpu/chipset requests write
+);
+
+// no burst configured
+localparam RASCAS_DELAY   = 3'd2;   // tRCD>=20ns -> 2 cycles@64MHz
+localparam BURST_LENGTH   = 3'b000; // 000=none, 001=2, 010=4, 011=8
+localparam ACCESS_TYPE    = 1'b0;   // 0=sequential, 1=interleaved
+localparam CAS_LATENCY    = 3'd3;   // 2/3 allowed
+localparam OP_MODE        = 2'b00;  // only 00 (standard operation) allowed
+localparam NO_WRITE_BURST = 1'b1;   // 0= write burst enabled, 1=only single access write
+
+localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; 
+
+// ---------------------------------------------------------------------
+// ------------------------ cycle state machine ------------------------
+// ---------------------------------------------------------------------
+
+localparam STATE_IDLE      = 4'd0;    // first state in cycle
+localparam STATE_CMD_START = 4'd1;    // state in which a new command can be started
+localparam STATE_CMD_CONT  = STATE_CMD_START  + RASCAS_DELAY - 3'd1; // 4 command can be continued
+localparam STATE_LAST      = 4'd15;   // last state in cycle
+
+reg [3:0] q /* synthesis noprune */;
+always @(posedge clk) begin
+	// 32Mhz counter synchronous to 4 Mhz clock
+   // force counter to pass state 5->6 exactly after the rising edge of clkref
+	// since clkref is two clocks early
+   if(((q == 14) && ( clkref == 0)) ||
+		((q == 15) && ( clkref == 1)) ||
+      ((q != 14) && (q != 15)))
+			q <= q + 4'd1;
+end
+
+// ---------------------------------------------------------------------
+// --------------------------- startup/reset ---------------------------
+// ---------------------------------------------------------------------
+
+// wait 1ms (32 clkref cycles) after FPGA config is done before going
+// into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0)
+reg [4:0] reset;
+always @(posedge clk) begin
+	if(init)	reset <= 5'h1f;
+	else if((q == STATE_LAST) && (reset != 0))
+		reset <= reset - 5'd1;
+end
+
+// ---------------------------------------------------------------------
+// ------------------ generate ram control signals ---------------------
+// ---------------------------------------------------------------------
+
+// all possible commands
+localparam CMD_INHIBIT         = 4'b1111;
+localparam CMD_NOP             = 4'b0111;
+localparam CMD_ACTIVE          = 4'b0011;
+localparam CMD_READ            = 4'b0101;
+localparam CMD_WRITE           = 4'b0100;
+localparam CMD_BURST_TERMINATE = 4'b0110;
+localparam CMD_PRECHARGE       = 4'b0010;
+localparam CMD_AUTO_REFRESH    = 4'b0001;
+localparam CMD_LOAD_MODE       = 4'b0000;
+
+reg [3:0] sd_cmd;   // current command sent to sd ram
+
+// drive control signals according to current command
+assign sd_cs  = sd_cmd[3];
+assign sd_ras = sd_cmd[2];
+assign sd_cas = sd_cmd[1];
+assign sd_we  = sd_cmd[0];
+
+assign sd_data = we?din:16'bZZZZZZZZZZZZZZZZ;
+
+assign dout = sd_data;
+
+always @(posedge clk) begin
+	sd_cmd <= CMD_INHIBIT;
+
+	if(reset != 0) begin
+		sd_ba <= 2'b00;
+		sd_dqm <= 2'b00;
+			
+		if(reset == 13) sd_addr <= 13'b0010000000000;
+		else   			 sd_addr <= MODE;
+
+		if(q == STATE_IDLE) begin
+			if(reset == 13)  sd_cmd <= CMD_PRECHARGE;
+			if(reset ==  2)  sd_cmd <= CMD_LOAD_MODE;
+		end
+	end else begin
+		if(q <= STATE_CMD_START) begin	
+			sd_addr <= addr[20:8];
+			sd_ba <= addr[22:21];
+			sd_dqm <= { !ds[1], !ds[0] };
+		end else
+			sd_addr <= { 4'b0010, addr[23], addr[7:0]};
+	
+		if(q == STATE_IDLE) begin
+			if(we || oe) sd_cmd <= CMD_ACTIVE;
+			else         sd_cmd <= CMD_AUTO_REFRESH;
+		end else if(q == STATE_CMD_CONT) begin
+			if(we)		 sd_cmd <= CMD_WRITE;
+			else if(oe)  sd_cmd <= CMD_READ;
+		end 
+	end
+end
+
+endmodule
diff --git a/cores/c16/stp1.stp b/cores/c16/stp1.stp
new file mode 100644
index 0000000..1183210
--- /dev/null
+++ b/cores/c16/stp1.stp
@@ -0,0 +1,1186 @@
+<session jtag_chain="USB-Blaster [1-4.2]" jtag_device="@1: EP3C25/EP4CE22 (0x020F30DD)" sof_file="output_files/c16_mist.sof">
+  <display_tree gui_logging_enabled="0">
+    <display_branch instance="auto_signaltap_0" log="USE_GLOBAL_TEMP" signal_set="USE_GLOBAL_TEMP" trigger="USE_GLOBAL_TEMP"/>
+  </display_tree>
+  <instance entity_name="sld_signaltap" is_auto_node="yes" is_expanded="true" name="auto_signaltap_0" source_file="sld_signaltap.vhd">
+    <node_ip_info instance_id="0" mfg_id="110" node_id="0" version="6"/>
+    <position_info>
+      <single attribute="active tab" value="0"/>
+      <single attribute="data horizontal scroll position" value="7"/>
+      <single attribute="data vertical scroll position" value="0"/>
+      <single attribute="setup horizontal scroll position" value="0"/>
+      <single attribute="setup vertical scroll position" value="11"/>
+      <single attribute="zoom level denominator" value="1"/>
+      <single attribute="zoom level numerator" value="4"/>
+      <single attribute="zoom offset denominator" value="1"/>
+      <single attribute="zoom offset numerator" value="32736"/>
+      <multi attribute="timebars" size="1" value="9"/>
+    </position_info>
+    <signal_set global_temp="1" name="signal_set: 2016/07/29 10:48:46  #0">
+      <clock name="clk28" polarity="posedge" tap_mode="classic"/>
+      <config ram_type="AUTO" reserved_data_nodes="0" reserved_storage_qualifier_nodes="0" reserved_trigger_nodes="0" sample_depth="128" trigger_in_enable="no" trigger_out_enable="no"/>
+      <top_entity/>
+      <signal_vec>
+        <trigger_input_vec>
+          <wire name="C16:c16|A[0]" tap_mode="classic"/>
+          <wire name="C16:c16|A[1]" tap_mode="classic"/>
+          <wire name="C16:c16|A[2]" tap_mode="classic"/>
+          <wire name="C16:c16|A[3]" tap_mode="classic"/>
+          <wire name="C16:c16|A[4]" tap_mode="classic"/>
+          <wire name="C16:c16|A[5]" tap_mode="classic"/>
+          <wire name="C16:c16|A[6]" tap_mode="classic"/>
+          <wire name="C16:c16|A[7]" tap_mode="classic"/>
+          <wire name="C16:c16|CAS" tap_mode="classic"/>
+          <wire name="C16:c16|RAS" tap_mode="classic"/>
+          <wire name="C16:c16|RESET" tap_mode="classic"/>
+          <wire name="C16:c16|RW" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|kbus[0]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|kbus[1]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|kbus[2]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|kbus[3]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|kbus[4]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|kbus[5]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|kbus[6]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|kbus[7]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|row[0]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|row[1]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|row[2]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|row[3]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|row[4]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|row[5]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|row[6]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|row[7]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[0]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[10]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[11]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[12]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[13]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[1]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[2]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[3]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[4]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[5]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[6]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[7]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[8]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[9]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_data[0]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_data[1]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_data[2]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_data[3]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_data[4]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_data[5]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_data[6]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_data[7]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_write" tap_mode="classic"/>
+          <wire name="C16:c16|sreset" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[0]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[10]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[11]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[12]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[13]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[14]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[15]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[1]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[2]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[3]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[4]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[5]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[6]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[7]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[8]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[9]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in_reg[0]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in_reg[1]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in_reg[2]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in_reg[3]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in_reg[4]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in_reg[5]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|data_in[0]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|data_in[1]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|data_in[2]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|data_in[3]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|data_in[4]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|data_in[5]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|data_in[6]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|data_in[7]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|phicounter[0]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|phicounter[1]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|phicounter[2]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|phicounter[3]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[0]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[10]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[11]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[12]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[13]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[14]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[15]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[1]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[2]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[3]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[4]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[5]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[6]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[7]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[8]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[9]" tap_mode="classic"/>
+          <wire name="data_io:data_io|d[0]" tap_mode="classic"/>
+          <wire name="data_io:data_io|d[1]" tap_mode="classic"/>
+          <wire name="data_io:data_io|d[2]" tap_mode="classic"/>
+          <wire name="data_io:data_io|d[3]" tap_mode="classic"/>
+          <wire name="data_io:data_io|d[4]" tap_mode="classic"/>
+          <wire name="data_io:data_io|d[5]" tap_mode="classic"/>
+          <wire name="data_io:data_io|d[6]" tap_mode="classic"/>
+          <wire name="data_io:data_io|d[7]" tap_mode="classic"/>
+          <wire name="data_io:data_io|wr" tap_mode="classic"/>
+          <wire name="rom_download" tap_mode="classic"/>
+        </trigger_input_vec>
+        <data_input_vec>
+          <wire name="C16:c16|A[0]" tap_mode="classic"/>
+          <wire name="C16:c16|A[1]" tap_mode="classic"/>
+          <wire name="C16:c16|A[2]" tap_mode="classic"/>
+          <wire name="C16:c16|A[3]" tap_mode="classic"/>
+          <wire name="C16:c16|A[4]" tap_mode="classic"/>
+          <wire name="C16:c16|A[5]" tap_mode="classic"/>
+          <wire name="C16:c16|A[6]" tap_mode="classic"/>
+          <wire name="C16:c16|A[7]" tap_mode="classic"/>
+          <wire name="C16:c16|CAS" tap_mode="classic"/>
+          <wire name="C16:c16|RAS" tap_mode="classic"/>
+          <wire name="C16:c16|RESET" tap_mode="classic"/>
+          <wire name="C16:c16|RW" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|kbus[0]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|kbus[1]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|kbus[2]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|kbus[3]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|kbus[4]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|kbus[5]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|kbus[6]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|kbus[7]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|row[0]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|row[1]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|row[2]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|row[3]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|row[4]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|row[5]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|row[6]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|row[7]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[0]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[10]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[11]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[12]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[13]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[1]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[2]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[3]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[4]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[5]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[6]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[7]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[8]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[9]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_data[0]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_data[1]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_data[2]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_data[3]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_data[4]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_data[5]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_data[6]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_data[7]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_write" tap_mode="classic"/>
+          <wire name="C16:c16|sreset" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[0]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[10]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[11]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[12]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[13]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[14]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[15]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[1]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[2]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[3]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[4]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[5]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[6]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[7]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[8]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[9]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in_reg[0]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in_reg[1]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in_reg[2]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in_reg[3]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in_reg[4]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in_reg[5]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|data_in[0]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|data_in[1]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|data_in[2]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|data_in[3]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|data_in[4]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|data_in[5]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|data_in[6]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|data_in[7]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|phicounter[0]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|phicounter[1]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|phicounter[2]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|phicounter[3]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[0]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[10]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[11]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[12]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[13]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[14]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[15]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[1]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[2]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[3]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[4]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[5]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[6]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[7]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[8]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[9]" tap_mode="classic"/>
+          <wire name="data_io:data_io|d[0]" tap_mode="classic"/>
+          <wire name="data_io:data_io|d[1]" tap_mode="classic"/>
+          <wire name="data_io:data_io|d[2]" tap_mode="classic"/>
+          <wire name="data_io:data_io|d[3]" tap_mode="classic"/>
+          <wire name="data_io:data_io|d[4]" tap_mode="classic"/>
+          <wire name="data_io:data_io|d[5]" tap_mode="classic"/>
+          <wire name="data_io:data_io|d[6]" tap_mode="classic"/>
+          <wire name="data_io:data_io|d[7]" tap_mode="classic"/>
+          <wire name="data_io:data_io|wr" tap_mode="classic"/>
+          <wire name="rom_download" tap_mode="classic"/>
+        </data_input_vec>
+        <storage_qualifier_input_vec>
+          <wire name="C16:c16|A[0]" tap_mode="classic"/>
+          <wire name="C16:c16|A[1]" tap_mode="classic"/>
+          <wire name="C16:c16|A[2]" tap_mode="classic"/>
+          <wire name="C16:c16|A[3]" tap_mode="classic"/>
+          <wire name="C16:c16|A[4]" tap_mode="classic"/>
+          <wire name="C16:c16|A[5]" tap_mode="classic"/>
+          <wire name="C16:c16|A[6]" tap_mode="classic"/>
+          <wire name="C16:c16|A[7]" tap_mode="classic"/>
+          <wire name="C16:c16|CAS" tap_mode="classic"/>
+          <wire name="C16:c16|RAS" tap_mode="classic"/>
+          <wire name="C16:c16|RESET" tap_mode="classic"/>
+          <wire name="C16:c16|RW" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|kbus[0]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|kbus[1]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|kbus[2]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|kbus[3]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|kbus[4]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|kbus[5]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|kbus[6]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|kbus[7]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|row[0]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|row[1]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|row[2]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|row[3]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|row[4]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|row[5]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|row[6]" tap_mode="classic"/>
+          <wire name="C16:c16|c16_keymatrix:keyboard|row[7]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[0]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[10]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[11]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[12]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[13]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[1]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[2]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[3]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[4]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[5]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[6]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[7]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[8]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_addr[9]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_data[0]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_data[1]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_data[2]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_data[3]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_data[4]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_data[5]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_data[6]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_data[7]" tap_mode="classic"/>
+          <wire name="C16:c16|kernal_dl_write" tap_mode="classic"/>
+          <wire name="C16:c16|sreset" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[0]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[10]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[11]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[12]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[13]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[14]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[15]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[1]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[2]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[3]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[4]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[5]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[6]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[7]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[8]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in[9]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in_reg[0]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in_reg[1]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in_reg[2]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in_reg[3]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in_reg[4]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|addr_in_reg[5]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|data_in[0]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|data_in[1]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|data_in[2]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|data_in[3]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|data_in[4]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|data_in[5]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|data_in[6]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|data_in[7]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|phicounter[0]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|phicounter[1]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|phicounter[2]" tap_mode="classic"/>
+          <wire name="C16:c16|ted:mos8360|phicounter[3]" tap_mode="classic"/>
+          <wire name="SDRAM_nCAS" tap_mode="classic"/>
+          <wire name="SDRAM_nCS" tap_mode="classic"/>
+          <wire name="SDRAM_nRAS" tap_mode="classic"/>
+          <wire name="SDRAM_nWE" tap_mode="classic"/>
+          <wire name="c16_wait" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[0]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[10]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[11]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[12]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[13]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[14]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[15]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[1]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[2]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[3]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[4]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[5]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[6]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[7]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[8]" tap_mode="classic"/>
+          <wire name="data_io:data_io|a[9]" tap_mode="classic"/>
+          <wire name="data_io:data_io|d[0]" tap_mode="classic"/>
+          <wire name="data_io:data_io|d[1]" tap_mode="classic"/>
+          <wire name="data_io:data_io|d[2]" tap_mode="classic"/>
+          <wire name="data_io:data_io|d[3]" tap_mode="classic"/>
+          <wire name="data_io:data_io|d[4]" tap_mode="classic"/>
+          <wire name="data_io:data_io|d[5]" tap_mode="classic"/>
+          <wire name="data_io:data_io|d[6]" tap_mode="classic"/>
+          <wire name="data_io:data_io|d[7]" tap_mode="classic"/>
+          <wire name="data_io:data_io|downloading" tap_mode="classic"/>
+          <wire name="data_io:data_io|wr" tap_mode="classic"/>
+          <wire name="ioctl_load_addr[0]" tap_mode="classic"/>
+          <wire name="ioctl_load_addr[10]" tap_mode="classic"/>
+          <wire name="ioctl_load_addr[11]" tap_mode="classic"/>
+          <wire name="ioctl_load_addr[12]" tap_mode="classic"/>
+          <wire name="ioctl_load_addr[13]" tap_mode="classic"/>
+          <wire name="ioctl_load_addr[14]" tap_mode="classic"/>
+          <wire name="ioctl_load_addr[15]" tap_mode="classic"/>
+          <wire name="ioctl_load_addr[1]" tap_mode="classic"/>
+          <wire name="ioctl_load_addr[2]" tap_mode="classic"/>
+          <wire name="ioctl_load_addr[3]" tap_mode="classic"/>
+          <wire name="ioctl_load_addr[4]" tap_mode="classic"/>
+          <wire name="ioctl_load_addr[5]" tap_mode="classic"/>
+          <wire name="ioctl_load_addr[6]" tap_mode="classic"/>
+          <wire name="ioctl_load_addr[7]" tap_mode="classic"/>
+          <wire name="ioctl_load_addr[8]" tap_mode="classic"/>
+          <wire name="ioctl_load_addr[9]" tap_mode="classic"/>
+          <wire name="ioctl_ram_wr" tap_mode="classic"/>
+          <wire name="ioctl_sdram_addr[0]" tap_mode="classic"/>
+          <wire name="ioctl_sdram_addr[10]" tap_mode="classic"/>
+          <wire name="ioctl_sdram_addr[11]" tap_mode="classic"/>
+          <wire name="ioctl_sdram_addr[12]" tap_mode="classic"/>
+          <wire name="ioctl_sdram_addr[13]" tap_mode="classic"/>
+          <wire name="ioctl_sdram_addr[14]" tap_mode="classic"/>
+          <wire name="ioctl_sdram_addr[15]" tap_mode="classic"/>
+          <wire name="ioctl_sdram_addr[1]" tap_mode="classic"/>
+          <wire name="ioctl_sdram_addr[2]" tap_mode="classic"/>
+          <wire name="ioctl_sdram_addr[3]" tap_mode="classic"/>
+          <wire name="ioctl_sdram_addr[4]" tap_mode="classic"/>
+          <wire name="ioctl_sdram_addr[5]" tap_mode="classic"/>
+          <wire name="ioctl_sdram_addr[6]" tap_mode="classic"/>
+          <wire name="ioctl_sdram_addr[7]" tap_mode="classic"/>
+          <wire name="ioctl_sdram_addr[8]" tap_mode="classic"/>
+          <wire name="ioctl_sdram_addr[9]" tap_mode="classic"/>
+          <wire name="ioctl_sdram_data[0]" tap_mode="classic"/>
+          <wire name="ioctl_sdram_data[1]" tap_mode="classic"/>
+          <wire name="ioctl_sdram_data[2]" tap_mode="classic"/>
+          <wire name="ioctl_sdram_data[3]" tap_mode="classic"/>
+          <wire name="ioctl_sdram_data[4]" tap_mode="classic"/>
+          <wire name="ioctl_sdram_data[5]" tap_mode="classic"/>
+          <wire name="ioctl_sdram_data[6]" tap_mode="classic"/>
+          <wire name="ioctl_sdram_data[7]" tap_mode="classic"/>
+          <wire name="ioctl_sdram_write" tap_mode="classic"/>
+          <wire name="rom_download" tap_mode="classic"/>
+          <wire name="sdram:sdram|addr[0]" tap_mode="classic"/>
+          <wire name="sdram:sdram|addr[10]" tap_mode="classic"/>
+          <wire name="sdram:sdram|addr[11]" tap_mode="classic"/>
+          <wire name="sdram:sdram|addr[12]" tap_mode="classic"/>
+          <wire name="sdram:sdram|addr[13]" tap_mode="classic"/>
+          <wire name="sdram:sdram|addr[14]" tap_mode="classic"/>
+          <wire name="sdram:sdram|addr[15]" tap_mode="classic"/>
+          <wire name="sdram:sdram|addr[16]" tap_mode="classic"/>
+          <wire name="sdram:sdram|addr[17]" tap_mode="classic"/>
+          <wire name="sdram:sdram|addr[18]" tap_mode="classic"/>
+          <wire name="sdram:sdram|addr[19]" tap_mode="classic"/>
+          <wire name="sdram:sdram|addr[1]" tap_mode="classic"/>
+          <wire name="sdram:sdram|addr[20]" tap_mode="classic"/>
+          <wire name="sdram:sdram|addr[21]" tap_mode="classic"/>
+          <wire name="sdram:sdram|addr[22]" tap_mode="classic"/>
+          <wire name="sdram:sdram|addr[23]" tap_mode="classic"/>
+          <wire name="sdram:sdram|addr[24]" tap_mode="classic"/>
+          <wire name="sdram:sdram|addr[2]" tap_mode="classic"/>
+          <wire name="sdram:sdram|addr[3]" tap_mode="classic"/>
+          <wire name="sdram:sdram|addr[4]" tap_mode="classic"/>
+          <wire name="sdram:sdram|addr[5]" tap_mode="classic"/>
+          <wire name="sdram:sdram|addr[6]" tap_mode="classic"/>
+          <wire name="sdram:sdram|addr[7]" tap_mode="classic"/>
+          <wire name="sdram:sdram|addr[8]" tap_mode="classic"/>
+          <wire name="sdram:sdram|addr[9]" tap_mode="classic"/>
+          <wire name="sdram:sdram|clkref" tap_mode="classic"/>
+          <wire name="sdram:sdram|dout[0]" tap_mode="classic"/>
+          <wire name="sdram:sdram|dout[10]" tap_mode="classic"/>
+          <wire name="sdram:sdram|dout[11]" tap_mode="classic"/>
+          <wire name="sdram:sdram|dout[12]" tap_mode="classic"/>
+          <wire name="sdram:sdram|dout[13]" tap_mode="classic"/>
+          <wire name="sdram:sdram|dout[14]" tap_mode="classic"/>
+          <wire name="sdram:sdram|dout[15]" tap_mode="classic"/>
+          <wire name="sdram:sdram|dout[1]" tap_mode="classic"/>
+          <wire name="sdram:sdram|dout[2]" tap_mode="classic"/>
+          <wire name="sdram:sdram|dout[3]" tap_mode="classic"/>
+          <wire name="sdram:sdram|dout[4]" tap_mode="classic"/>
+          <wire name="sdram:sdram|dout[5]" tap_mode="classic"/>
+          <wire name="sdram:sdram|dout[6]" tap_mode="classic"/>
+          <wire name="sdram:sdram|dout[7]" tap_mode="classic"/>
+          <wire name="sdram:sdram|dout[8]" tap_mode="classic"/>
+          <wire name="sdram:sdram|dout[9]" tap_mode="classic"/>
+          <wire name="sdram:sdram|q[0]" tap_mode="classic"/>
+          <wire name="sdram:sdram|q[1]" tap_mode="classic"/>
+          <wire name="sdram:sdram|q[2]" tap_mode="classic"/>
+          <wire name="sdram:sdram|q[3]" tap_mode="classic"/>
+          <wire name="sdram_din[0]" tap_mode="classic"/>
+          <wire name="sdram_din[10]" tap_mode="classic"/>
+          <wire name="sdram_din[11]" tap_mode="classic"/>
+          <wire name="sdram_din[12]" tap_mode="classic"/>
+          <wire name="sdram_din[13]" tap_mode="classic"/>
+          <wire name="sdram_din[14]" tap_mode="classic"/>
+          <wire name="sdram_din[15]" tap_mode="classic"/>
+          <wire name="sdram_din[1]" tap_mode="classic"/>
+          <wire name="sdram_din[2]" tap_mode="classic"/>
+          <wire name="sdram_din[3]" tap_mode="classic"/>
+          <wire name="sdram_din[4]" tap_mode="classic"/>
+          <wire name="sdram_din[5]" tap_mode="classic"/>
+          <wire name="sdram_din[6]" tap_mode="classic"/>
+          <wire name="sdram_din[7]" tap_mode="classic"/>
+          <wire name="sdram_din[8]" tap_mode="classic"/>
+          <wire name="sdram_din[9]" tap_mode="classic"/>
+        </storage_qualifier_input_vec>
+      </signal_vec>
+      <presentation>
+        <unified_setup_data_view>
+          <node name="C16:c16|A" order="msb_to_lsb" state="collapse" type="combinatorial">
+            <node data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|A[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/>
+            <node data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|A[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/>
+            <node data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|A[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/>
+            <node data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|A[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/>
+            <node data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|A[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/>
+            <node data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|A[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/>
+            <node data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|A[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/>
+            <node data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|A[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/>
+          </node>
+          <node data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|RAS" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/>
+          <node data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|CAS" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/>
+          <node data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|RW" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="unknown"/>
+          <node data_index="40" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|clkref" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="185" tap_mode="classic" trigger_index="40" type="unknown"/>
+          <node name="sdram:sdram|q" order="msb_to_lsb" type="register">
+            <node data_index="60" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|q[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="205" tap_mode="classic" trigger_index="60" type="unknown"/>
+            <node data_index="59" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|q[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="204" tap_mode="classic" trigger_index="59" type="unknown"/>
+            <node data_index="58" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|q[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="203" tap_mode="classic" trigger_index="58" type="unknown"/>
+            <node data_index="57" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|q[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="202" tap_mode="classic" trigger_index="57" type="unknown"/>
+          </node>
+          <node data_index="12" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="SDRAM_nCS" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="87" tap_mode="classic" trigger_index="12" type="unknown"/>
+          <node data_index="13" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="SDRAM_nRAS" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="88" tap_mode="classic" trigger_index="13" type="unknown"/>
+          <node data_index="11" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="SDRAM_nCAS" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="86" tap_mode="classic" trigger_index="11" type="unknown"/>
+          <node data_index="14" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="SDRAM_nWE" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="89" tap_mode="classic" trigger_index="14" type="unknown"/>
+          <node name="sdram:sdram|addr" order="msb_to_lsb" type="combinatorial">
+            <node data_index="100" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="176" tap_mode="classic" trigger_index="100" type="unknown"/>
+            <node data_index="99" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="175" tap_mode="classic" trigger_index="99" type="unknown"/>
+            <node data_index="98" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="174" tap_mode="classic" trigger_index="98" type="unknown"/>
+            <node data_index="97" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="173" tap_mode="classic" trigger_index="97" type="unknown"/>
+            <node data_index="96" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="172" tap_mode="classic" trigger_index="96" type="unknown"/>
+            <node data_index="94" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="170" tap_mode="classic" trigger_index="94" type="unknown"/>
+            <node data_index="93" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="169" tap_mode="classic" trigger_index="93" type="unknown"/>
+            <node data_index="92" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="168" tap_mode="classic" trigger_index="92" type="unknown"/>
+            <node data_index="91" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="167" tap_mode="classic" trigger_index="91" type="unknown"/>
+            <node data_index="90" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="166" tap_mode="classic" trigger_index="90" type="unknown"/>
+            <node data_index="89" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="165" tap_mode="classic" trigger_index="89" type="unknown"/>
+            <node data_index="88" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="164" tap_mode="classic" trigger_index="88" type="unknown"/>
+            <node data_index="87" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="163" tap_mode="classic" trigger_index="87" type="unknown"/>
+            <node data_index="86" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="162" tap_mode="classic" trigger_index="86" type="unknown"/>
+            <node data_index="85" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="161" tap_mode="classic" trigger_index="85" type="unknown"/>
+            <node data_index="108" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="184" tap_mode="classic" trigger_index="108" type="unknown"/>
+            <node data_index="107" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="183" tap_mode="classic" trigger_index="107" type="unknown"/>
+            <node data_index="106" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="182" tap_mode="classic" trigger_index="106" type="unknown"/>
+            <node data_index="105" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="181" tap_mode="classic" trigger_index="105" type="unknown"/>
+            <node data_index="104" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="180" tap_mode="classic" trigger_index="104" type="unknown"/>
+            <node data_index="103" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="179" tap_mode="classic" trigger_index="103" type="unknown"/>
+            <node data_index="102" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="178" tap_mode="classic" trigger_index="102" type="unknown"/>
+            <node data_index="101" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="177" tap_mode="classic" trigger_index="101" type="unknown"/>
+            <node data_index="95" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="171" tap_mode="classic" trigger_index="95" type="unknown"/>
+            <node data_index="84" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="160" tap_mode="classic" trigger_index="84" type="unknown"/>
+          </node>
+          <node name="sdram_din" order="msb_to_lsb" state="collapse" type="combinatorial">
+            <node data_index="67" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="212" tap_mode="classic" trigger_index="67" type="unknown"/>
+            <node data_index="66" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="211" tap_mode="classic" trigger_index="66" type="unknown"/>
+            <node data_index="65" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="210" tap_mode="classic" trigger_index="65" type="unknown"/>
+            <node data_index="64" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="209" tap_mode="classic" trigger_index="64" type="unknown"/>
+            <node data_index="63" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="208" tap_mode="classic" trigger_index="63" type="unknown"/>
+            <node data_index="62" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="207" tap_mode="classic" trigger_index="62" type="unknown"/>
+            <node data_index="76" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="221" tap_mode="classic" trigger_index="76" type="unknown"/>
+            <node data_index="75" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="220" tap_mode="classic" trigger_index="75" type="unknown"/>
+            <node data_index="74" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="219" tap_mode="classic" trigger_index="74" type="unknown"/>
+            <node data_index="73" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="218" tap_mode="classic" trigger_index="73" type="unknown"/>
+            <node data_index="72" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="217" tap_mode="classic" trigger_index="72" type="unknown"/>
+            <node data_index="71" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="216" tap_mode="classic" trigger_index="71" type="unknown"/>
+            <node data_index="70" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="215" tap_mode="classic" trigger_index="70" type="unknown"/>
+            <node data_index="69" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="214" tap_mode="classic" trigger_index="69" type="unknown"/>
+            <node data_index="68" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="213" tap_mode="classic" trigger_index="68" type="unknown"/>
+            <node data_index="61" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="206" tap_mode="classic" trigger_index="61" type="unknown"/>
+          </node>
+          <node name="sdram:sdram|dout" order="msb_to_lsb" state="collapse" type="combinatorial">
+            <node data_index="47" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="192" tap_mode="classic" trigger_index="47" type="unknown"/>
+            <node data_index="46" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="191" tap_mode="classic" trigger_index="46" type="unknown"/>
+            <node data_index="45" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="190" tap_mode="classic" trigger_index="45" type="unknown"/>
+            <node data_index="44" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="189" tap_mode="classic" trigger_index="44" type="unknown"/>
+            <node data_index="43" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="188" tap_mode="classic" trigger_index="43" type="unknown"/>
+            <node data_index="42" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="187" tap_mode="classic" trigger_index="42" type="unknown"/>
+            <node data_index="56" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="201" tap_mode="classic" trigger_index="56" type="unknown"/>
+            <node data_index="55" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="200" tap_mode="classic" trigger_index="55" type="unknown"/>
+            <node data_index="54" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="199" tap_mode="classic" trigger_index="54" type="unknown"/>
+            <node data_index="53" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="198" tap_mode="classic" trigger_index="53" type="unknown"/>
+            <node data_index="52" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="197" tap_mode="classic" trigger_index="52" type="unknown"/>
+            <node data_index="51" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="196" tap_mode="classic" trigger_index="51" type="unknown"/>
+            <node data_index="50" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="195" tap_mode="classic" trigger_index="50" type="unknown"/>
+            <node data_index="49" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="194" tap_mode="classic" trigger_index="49" type="unknown"/>
+            <node data_index="48" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="193" tap_mode="classic" trigger_index="48" type="unknown"/>
+            <node data_index="41" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="186" tap_mode="classic" trigger_index="41" type="unknown"/>
+          </node>
+          <node name="ioctl_load_addr" order="msb_to_lsb" state="collapse" type="register">
+            <node data_index="48" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="123" tap_mode="classic" trigger_index="48" type="unknown"/>
+            <node data_index="47" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="122" tap_mode="classic" trigger_index="47" type="unknown"/>
+            <node data_index="46" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="121" tap_mode="classic" trigger_index="46" type="unknown"/>
+            <node data_index="45" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="120" tap_mode="classic" trigger_index="45" type="unknown"/>
+            <node data_index="44" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="119" tap_mode="classic" trigger_index="44" type="unknown"/>
+            <node data_index="43" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="118" tap_mode="classic" trigger_index="43" type="unknown"/>
+            <node data_index="57" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="132" tap_mode="classic" trigger_index="57" type="unknown"/>
+            <node data_index="56" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="131" tap_mode="classic" trigger_index="56" type="unknown"/>
+            <node data_index="55" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="130" tap_mode="classic" trigger_index="55" type="unknown"/>
+            <node data_index="54" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="129" tap_mode="classic" trigger_index="54" type="unknown"/>
+            <node data_index="53" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="128" tap_mode="classic" trigger_index="53" type="unknown"/>
+            <node data_index="52" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="127" tap_mode="classic" trigger_index="52" type="unknown"/>
+            <node data_index="51" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="126" tap_mode="classic" trigger_index="51" type="unknown"/>
+            <node data_index="50" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="125" tap_mode="classic" trigger_index="50" type="unknown"/>
+            <node data_index="49" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="124" tap_mode="classic" trigger_index="49" type="unknown"/>
+            <node data_index="42" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="117" tap_mode="classic" trigger_index="42" type="unknown"/>
+          </node>
+          <node name="data_io:data_io|a" order="msb_to_lsb" state="collapse" type="combinatorial">
+            <node data_index="92" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="97" tap_mode="classic" trigger_index="92" type="unknown"/>
+            <node data_index="91" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="96" tap_mode="classic" trigger_index="91" type="unknown"/>
+            <node data_index="90" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="95" tap_mode="classic" trigger_index="90" type="unknown"/>
+            <node data_index="89" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="94" tap_mode="classic" trigger_index="89" type="unknown"/>
+            <node data_index="88" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="93" tap_mode="classic" trigger_index="88" type="unknown"/>
+            <node data_index="87" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="92" tap_mode="classic" trigger_index="87" type="unknown"/>
+            <node data_index="101" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="106" tap_mode="classic" trigger_index="101" type="unknown"/>
+            <node data_index="100" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="105" tap_mode="classic" trigger_index="100" type="unknown"/>
+            <node data_index="99" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="104" tap_mode="classic" trigger_index="99" type="unknown"/>
+            <node data_index="98" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="103" tap_mode="classic" trigger_index="98" type="unknown"/>
+            <node data_index="97" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="102" tap_mode="classic" trigger_index="97" type="unknown"/>
+            <node data_index="96" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="101" tap_mode="classic" trigger_index="96" type="unknown"/>
+            <node data_index="95" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="100" tap_mode="classic" trigger_index="95" type="unknown"/>
+            <node data_index="94" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="99" tap_mode="classic" trigger_index="94" type="unknown"/>
+            <node data_index="93" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="98" tap_mode="classic" trigger_index="93" type="unknown"/>
+            <node data_index="86" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="91" tap_mode="classic" trigger_index="86" type="unknown"/>
+          </node>
+          <node name="data_io:data_io|d" order="msb_to_lsb" type="combinatorial">
+            <node data_index="109" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|d[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="114" tap_mode="classic" trigger_index="109" type="unknown"/>
+            <node data_index="108" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|d[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="113" tap_mode="classic" trigger_index="108" type="unknown"/>
+            <node data_index="107" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|d[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="112" tap_mode="classic" trigger_index="107" type="unknown"/>
+            <node data_index="106" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|d[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="111" tap_mode="classic" trigger_index="106" type="unknown"/>
+            <node data_index="105" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|d[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="110" tap_mode="classic" trigger_index="105" type="unknown"/>
+            <node data_index="104" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|d[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="109" tap_mode="classic" trigger_index="104" type="unknown"/>
+            <node data_index="103" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|d[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="108" tap_mode="classic" trigger_index="103" type="unknown"/>
+            <node data_index="102" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|d[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="107" tap_mode="classic" trigger_index="102" type="unknown"/>
+          </node>
+          <node data_index="40" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="data_io:data_io|downloading" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="115" tap_mode="classic" trigger_index="40" type="unknown"/>
+          <node data_index="110" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|wr" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="116" tap_mode="classic" trigger_index="110" type="unknown"/>
+          <node data_index="15" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="c16_wait" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="90" tap_mode="classic" trigger_index="15" type="unknown"/>
+          <node data_index="58" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_ram_wr" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="133" tap_mode="classic" trigger_index="58" type="unknown"/>
+          <node name="ioctl_sdram_addr" order="msb_to_lsb" type="register">
+            <node data_index="65" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="140" tap_mode="classic" trigger_index="65" type="unknown"/>
+            <node data_index="64" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="139" tap_mode="classic" trigger_index="64" type="unknown"/>
+            <node data_index="63" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="138" tap_mode="classic" trigger_index="63" type="unknown"/>
+            <node data_index="62" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="137" tap_mode="classic" trigger_index="62" type="unknown"/>
+            <node data_index="61" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="136" tap_mode="classic" trigger_index="61" type="unknown"/>
+            <node data_index="60" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="135" tap_mode="classic" trigger_index="60" type="unknown"/>
+            <node data_index="74" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="149" tap_mode="classic" trigger_index="74" type="unknown"/>
+            <node data_index="73" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="148" tap_mode="classic" trigger_index="73" type="unknown"/>
+            <node data_index="72" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="147" tap_mode="classic" trigger_index="72" type="unknown"/>
+            <node data_index="71" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="146" tap_mode="classic" trigger_index="71" type="unknown"/>
+            <node data_index="70" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="145" tap_mode="classic" trigger_index="70" type="unknown"/>
+            <node data_index="69" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="144" tap_mode="classic" trigger_index="69" type="unknown"/>
+            <node data_index="68" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="143" tap_mode="classic" trigger_index="68" type="unknown"/>
+            <node data_index="67" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="142" tap_mode="classic" trigger_index="67" type="unknown"/>
+            <node data_index="66" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="141" tap_mode="classic" trigger_index="66" type="unknown"/>
+            <node data_index="59" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="134" tap_mode="classic" trigger_index="59" type="unknown"/>
+          </node>
+          <node name="ioctl_sdram_data" order="msb_to_lsb" type="register">
+            <node data_index="82" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_data[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="157" tap_mode="classic" trigger_index="82" type="unknown"/>
+            <node data_index="81" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_data[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="156" tap_mode="classic" trigger_index="81" type="unknown"/>
+            <node data_index="80" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_data[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="155" tap_mode="classic" trigger_index="80" type="unknown"/>
+            <node data_index="79" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_data[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="154" tap_mode="classic" trigger_index="79" type="unknown"/>
+            <node data_index="78" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_data[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="153" tap_mode="classic" trigger_index="78" type="unknown"/>
+            <node data_index="77" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_data[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="152" tap_mode="classic" trigger_index="77" type="unknown"/>
+            <node data_index="76" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_data[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="151" tap_mode="classic" trigger_index="76" type="unknown"/>
+            <node data_index="75" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_data[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="150" tap_mode="classic" trigger_index="75" type="unknown"/>
+          </node>
+          <node data_index="83" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="rising edge" name="ioctl_sdram_write" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="158" tap_mode="classic" trigger_index="83" type="unknown"/>
+          <node name="C16:c16|c16_keymatrix:keyboard|kbus" order="msb_to_lsb" type="combinatorial">
+            <node data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|kbus[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="unknown"/>
+            <node data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|kbus[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="unknown"/>
+            <node data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|kbus[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="unknown"/>
+            <node data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|kbus[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="unknown"/>
+            <node data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|kbus[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="unknown"/>
+            <node data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|kbus[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="unknown"/>
+            <node data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|kbus[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="unknown"/>
+            <node data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|kbus[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="unknown"/>
+          </node>
+          <node name="C16:c16|c16_keymatrix:keyboard|row" order="msb_to_lsb" type="combinatorial">
+            <node data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|row[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="unknown"/>
+            <node data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|row[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="unknown"/>
+            <node data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|row[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="unknown"/>
+            <node data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|row[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="unknown"/>
+            <node data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|row[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="unknown"/>
+            <node data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|row[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="unknown"/>
+            <node data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|row[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="unknown"/>
+            <node data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|row[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="unknown"/>
+          </node>
+          <node name="C16:c16|ted:mos8360|addr_in_reg" order="msb_to_lsb" type="register">
+            <node data_index="73" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in_reg[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="73" tap_mode="classic" trigger_index="73" type="unknown"/>
+            <node data_index="72" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in_reg[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="72" tap_mode="classic" trigger_index="72" type="unknown"/>
+            <node data_index="71" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in_reg[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="71" tap_mode="classic" trigger_index="71" type="unknown"/>
+            <node data_index="70" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in_reg[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="70" tap_mode="classic" trigger_index="70" type="unknown"/>
+            <node data_index="69" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in_reg[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="69" tap_mode="classic" trigger_index="69" type="unknown"/>
+            <node data_index="68" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in_reg[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="68" tap_mode="classic" trigger_index="68" type="unknown"/>
+          </node>
+          <node name="C16:c16|ted:mos8360|phicounter" order="msb_to_lsb" type="register">
+            <node data_index="85" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|phicounter[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="85" tap_mode="classic" trigger_index="85" type="unknown"/>
+            <node data_index="84" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|phicounter[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="84" tap_mode="classic" trigger_index="84" type="unknown"/>
+            <node data_index="83" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|phicounter[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="83" tap_mode="classic" trigger_index="83" type="unknown"/>
+            <node data_index="82" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|phicounter[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="82" tap_mode="classic" trigger_index="82" type="unknown"/>
+          </node>
+          <node name="C16:c16|ted:mos8360|addr_in" order="msb_to_lsb" type="combinatorial">
+            <node data_index="58" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="58" tap_mode="classic" trigger_index="58" type="unknown"/>
+            <node data_index="57" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="57" tap_mode="classic" trigger_index="57" type="unknown"/>
+            <node data_index="56" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="56" tap_mode="classic" trigger_index="56" type="unknown"/>
+            <node data_index="55" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="55" type="unknown"/>
+            <node data_index="54" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="54" tap_mode="classic" trigger_index="54" type="unknown"/>
+            <node data_index="53" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="53" tap_mode="classic" trigger_index="53" type="unknown"/>
+            <node data_index="67" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="67" tap_mode="classic" trigger_index="67" type="unknown"/>
+            <node data_index="66" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="66" tap_mode="classic" trigger_index="66" type="unknown"/>
+            <node data_index="65" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="65" tap_mode="classic" trigger_index="65" type="unknown"/>
+            <node data_index="64" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="64" tap_mode="classic" trigger_index="64" type="unknown"/>
+            <node data_index="63" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="63" tap_mode="classic" trigger_index="63" type="unknown"/>
+            <node data_index="62" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="62" tap_mode="classic" trigger_index="62" type="unknown"/>
+            <node data_index="61" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="61" tap_mode="classic" trigger_index="61" type="unknown"/>
+            <node data_index="60" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="60" type="unknown"/>
+            <node data_index="59" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="59" tap_mode="classic" trigger_index="59" type="unknown"/>
+            <node data_index="52" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="classic" trigger_index="52" type="unknown"/>
+          </node>
+          <node name="C16:c16|ted:mos8360|data_in" order="msb_to_lsb" state="collapse" type="combinatorial">
+            <node data_index="81" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|data_in[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="81" tap_mode="classic" trigger_index="81" type="unknown"/>
+            <node data_index="80" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|data_in[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="80" tap_mode="classic" trigger_index="80" type="unknown"/>
+            <node data_index="79" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|data_in[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="79" tap_mode="classic" trigger_index="79" type="unknown"/>
+            <node data_index="78" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|data_in[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="78" tap_mode="classic" trigger_index="78" type="unknown"/>
+            <node data_index="77" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|data_in[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="77" tap_mode="classic" trigger_index="77" type="unknown"/>
+            <node data_index="76" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|data_in[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="76" tap_mode="classic" trigger_index="76" type="unknown"/>
+            <node data_index="75" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|data_in[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="75" tap_mode="classic" trigger_index="75" type="unknown"/>
+            <node data_index="74" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|data_in[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="74" tap_mode="classic" trigger_index="74" type="unknown"/>
+          </node>
+          <node name="C16:c16|kernal_dl_addr" order="msb_to_lsb" type="combinatorial">
+            <node data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[13]" storage_index="32" tap_mode="classic" trigger_index="32" type="unknown"/>
+            <node data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[12]" storage_index="31" tap_mode="classic" trigger_index="31" type="unknown"/>
+            <node data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[11]" storage_index="30" tap_mode="classic" trigger_index="30" type="unknown"/>
+            <node data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[10]" storage_index="29" tap_mode="classic" trigger_index="29" type="unknown"/>
+            <node data_index="41" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[9]" storage_index="41" tap_mode="classic" trigger_index="41" type="unknown"/>
+            <node data_index="40" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[8]" storage_index="40" tap_mode="classic" trigger_index="40" type="unknown"/>
+            <node data_index="39" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[7]" storage_index="39" tap_mode="classic" trigger_index="39" type="unknown"/>
+            <node data_index="38" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[6]" storage_index="38" tap_mode="classic" trigger_index="38" type="unknown"/>
+            <node data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[5]" storage_index="37" tap_mode="classic" trigger_index="37" type="unknown"/>
+            <node data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[4]" storage_index="36" tap_mode="classic" trigger_index="36" type="unknown"/>
+            <node data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[3]" storage_index="35" tap_mode="classic" trigger_index="35" type="unknown"/>
+            <node data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[2]" storage_index="34" tap_mode="classic" trigger_index="34" type="unknown"/>
+            <node data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[1]" storage_index="33" tap_mode="classic" trigger_index="33" type="unknown"/>
+            <node data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[0]" storage_index="28" tap_mode="classic" trigger_index="28" type="unknown"/>
+          </node>
+          <node name="C16:c16|kernal_dl_data" order="msb_to_lsb" type="combinatorial">
+            <node data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_data[7]" storage_index="49" tap_mode="classic" trigger_index="49" type="unknown"/>
+            <node data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_data[6]" storage_index="48" tap_mode="classic" trigger_index="48" type="unknown"/>
+            <node data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_data[5]" storage_index="47" tap_mode="classic" trigger_index="47" type="unknown"/>
+            <node data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_data[4]" storage_index="46" tap_mode="classic" trigger_index="46" type="unknown"/>
+            <node data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_data[3]" storage_index="45" tap_mode="classic" trigger_index="45" type="unknown"/>
+            <node data_index="44" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_data[2]" storage_index="44" tap_mode="classic" trigger_index="44" type="unknown"/>
+            <node data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_data[1]" storage_index="43" tap_mode="classic" trigger_index="43" type="unknown"/>
+            <node data_index="42" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_data[0]" storage_index="42" tap_mode="classic" trigger_index="42" type="unknown"/>
+          </node>
+          <node data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="rising edge" name="C16:c16|kernal_dl_write" storage_index="50" tap_mode="classic" trigger_index="50" type="unknown"/>
+          <node data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|sreset" storage_index="51" tap_mode="classic" trigger_index="51" type="unknown"/>
+          <node data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|RESET" storage_index="10" tap_mode="classic" trigger_index="10" type="unknown"/>
+          <node data_index="111" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="rom_download" storage_index="159" tap_mode="classic" trigger_index="111" type="unknown"/>
+        </unified_setup_data_view>
+        <data_view>
+          <bus name="C16:c16|A" order="msb_to_lsb" state="collapse" type="combinatorial">
+            <net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|A[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/>
+            <net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|A[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/>
+            <net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|A[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/>
+            <net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|A[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/>
+            <net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|A[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/>
+            <net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|A[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/>
+            <net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|A[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/>
+            <net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|A[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/>
+          </bus>
+          <net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|RAS" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/>
+          <net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|CAS" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/>
+          <net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|RW" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="unknown"/>
+          <bus name="data_io:data_io|a" order="msb_to_lsb" state="collapse" type="combinatorial">
+            <net data_index="92" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="97" tap_mode="classic" trigger_index="92" type="unknown"/>
+            <net data_index="91" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="96" tap_mode="classic" trigger_index="91" type="unknown"/>
+            <net data_index="90" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="95" tap_mode="classic" trigger_index="90" type="unknown"/>
+            <net data_index="89" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="94" tap_mode="classic" trigger_index="89" type="unknown"/>
+            <net data_index="88" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="93" tap_mode="classic" trigger_index="88" type="unknown"/>
+            <net data_index="87" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="92" tap_mode="classic" trigger_index="87" type="unknown"/>
+            <net data_index="101" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="106" tap_mode="classic" trigger_index="101" type="unknown"/>
+            <net data_index="100" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="105" tap_mode="classic" trigger_index="100" type="unknown"/>
+            <net data_index="99" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="104" tap_mode="classic" trigger_index="99" type="unknown"/>
+            <net data_index="98" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="103" tap_mode="classic" trigger_index="98" type="unknown"/>
+            <net data_index="97" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="102" tap_mode="classic" trigger_index="97" type="unknown"/>
+            <net data_index="96" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="101" tap_mode="classic" trigger_index="96" type="unknown"/>
+            <net data_index="95" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="100" tap_mode="classic" trigger_index="95" type="unknown"/>
+            <net data_index="94" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="99" tap_mode="classic" trigger_index="94" type="unknown"/>
+            <net data_index="93" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="98" tap_mode="classic" trigger_index="93" type="unknown"/>
+            <net data_index="86" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="91" tap_mode="classic" trigger_index="86" type="unknown"/>
+          </bus>
+          <bus name="data_io:data_io|d" order="msb_to_lsb" type="combinatorial">
+            <net data_index="109" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|d[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="114" tap_mode="classic" trigger_index="109" type="unknown"/>
+            <net data_index="108" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|d[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="113" tap_mode="classic" trigger_index="108" type="unknown"/>
+            <net data_index="107" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|d[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="112" tap_mode="classic" trigger_index="107" type="unknown"/>
+            <net data_index="106" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|d[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="111" tap_mode="classic" trigger_index="106" type="unknown"/>
+            <net data_index="105" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|d[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="110" tap_mode="classic" trigger_index="105" type="unknown"/>
+            <net data_index="104" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|d[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="109" tap_mode="classic" trigger_index="104" type="unknown"/>
+            <net data_index="103" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|d[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="108" tap_mode="classic" trigger_index="103" type="unknown"/>
+            <net data_index="102" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|d[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="107" tap_mode="classic" trigger_index="102" type="unknown"/>
+          </bus>
+          <net data_index="110" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|wr" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="116" tap_mode="classic" trigger_index="110" type="unknown"/>
+          <bus name="C16:c16|c16_keymatrix:keyboard|kbus" order="msb_to_lsb" type="combinatorial">
+            <net data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|kbus[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="unknown"/>
+            <net data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|kbus[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="unknown"/>
+            <net data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|kbus[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="unknown"/>
+            <net data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|kbus[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="unknown"/>
+            <net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|kbus[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="unknown"/>
+            <net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|kbus[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="unknown"/>
+            <net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|kbus[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="unknown"/>
+            <net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|kbus[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="unknown"/>
+          </bus>
+          <bus name="C16:c16|c16_keymatrix:keyboard|row" order="msb_to_lsb" type="combinatorial">
+            <net data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|row[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="unknown"/>
+            <net data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|row[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="unknown"/>
+            <net data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|row[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="unknown"/>
+            <net data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|row[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="unknown"/>
+            <net data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|row[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="unknown"/>
+            <net data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|row[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="unknown"/>
+            <net data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|row[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="unknown"/>
+            <net data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|row[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="unknown"/>
+          </bus>
+          <bus name="C16:c16|ted:mos8360|addr_in_reg" order="msb_to_lsb" type="register">
+            <net data_index="73" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in_reg[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="73" tap_mode="classic" trigger_index="73" type="unknown"/>
+            <net data_index="72" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in_reg[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="72" tap_mode="classic" trigger_index="72" type="unknown"/>
+            <net data_index="71" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in_reg[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="71" tap_mode="classic" trigger_index="71" type="unknown"/>
+            <net data_index="70" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in_reg[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="70" tap_mode="classic" trigger_index="70" type="unknown"/>
+            <net data_index="69" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in_reg[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="69" tap_mode="classic" trigger_index="69" type="unknown"/>
+            <net data_index="68" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in_reg[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="68" tap_mode="classic" trigger_index="68" type="unknown"/>
+          </bus>
+          <bus name="C16:c16|ted:mos8360|phicounter" order="msb_to_lsb" type="register">
+            <net data_index="85" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|phicounter[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="85" tap_mode="classic" trigger_index="85" type="unknown"/>
+            <net data_index="84" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|phicounter[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="84" tap_mode="classic" trigger_index="84" type="unknown"/>
+            <net data_index="83" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|phicounter[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="83" tap_mode="classic" trigger_index="83" type="unknown"/>
+            <net data_index="82" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|phicounter[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="82" tap_mode="classic" trigger_index="82" type="unknown"/>
+          </bus>
+          <bus name="C16:c16|ted:mos8360|addr_in" order="msb_to_lsb" type="combinatorial">
+            <net data_index="58" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="58" tap_mode="classic" trigger_index="58" type="unknown"/>
+            <net data_index="57" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="57" tap_mode="classic" trigger_index="57" type="unknown"/>
+            <net data_index="56" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="56" tap_mode="classic" trigger_index="56" type="unknown"/>
+            <net data_index="55" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="55" type="unknown"/>
+            <net data_index="54" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="54" tap_mode="classic" trigger_index="54" type="unknown"/>
+            <net data_index="53" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="53" tap_mode="classic" trigger_index="53" type="unknown"/>
+            <net data_index="67" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="67" tap_mode="classic" trigger_index="67" type="unknown"/>
+            <net data_index="66" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="66" tap_mode="classic" trigger_index="66" type="unknown"/>
+            <net data_index="65" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="65" tap_mode="classic" trigger_index="65" type="unknown"/>
+            <net data_index="64" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="64" tap_mode="classic" trigger_index="64" type="unknown"/>
+            <net data_index="63" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="63" tap_mode="classic" trigger_index="63" type="unknown"/>
+            <net data_index="62" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="62" tap_mode="classic" trigger_index="62" type="unknown"/>
+            <net data_index="61" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="61" tap_mode="classic" trigger_index="61" type="unknown"/>
+            <net data_index="60" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="60" type="unknown"/>
+            <net data_index="59" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="59" tap_mode="classic" trigger_index="59" type="unknown"/>
+            <net data_index="52" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="classic" trigger_index="52" type="unknown"/>
+          </bus>
+          <bus name="C16:c16|ted:mos8360|data_in" order="msb_to_lsb" state="collapse" type="combinatorial">
+            <net data_index="81" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|data_in[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="81" tap_mode="classic" trigger_index="81" type="unknown"/>
+            <net data_index="80" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|data_in[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="80" tap_mode="classic" trigger_index="80" type="unknown"/>
+            <net data_index="79" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|data_in[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="79" tap_mode="classic" trigger_index="79" type="unknown"/>
+            <net data_index="78" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|data_in[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="78" tap_mode="classic" trigger_index="78" type="unknown"/>
+            <net data_index="77" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|data_in[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="77" tap_mode="classic" trigger_index="77" type="unknown"/>
+            <net data_index="76" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|data_in[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="76" tap_mode="classic" trigger_index="76" type="unknown"/>
+            <net data_index="75" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|data_in[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="75" tap_mode="classic" trigger_index="75" type="unknown"/>
+            <net data_index="74" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|data_in[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="74" tap_mode="classic" trigger_index="74" type="unknown"/>
+          </bus>
+          <bus name="C16:c16|kernal_dl_addr" order="msb_to_lsb" type="combinatorial">
+            <net data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[13]" storage_index="32" tap_mode="classic" trigger_index="32" type="unknown"/>
+            <net data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[12]" storage_index="31" tap_mode="classic" trigger_index="31" type="unknown"/>
+            <net data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[11]" storage_index="30" tap_mode="classic" trigger_index="30" type="unknown"/>
+            <net data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[10]" storage_index="29" tap_mode="classic" trigger_index="29" type="unknown"/>
+            <net data_index="41" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[9]" storage_index="41" tap_mode="classic" trigger_index="41" type="unknown"/>
+            <net data_index="40" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[8]" storage_index="40" tap_mode="classic" trigger_index="40" type="unknown"/>
+            <net data_index="39" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[7]" storage_index="39" tap_mode="classic" trigger_index="39" type="unknown"/>
+            <net data_index="38" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[6]" storage_index="38" tap_mode="classic" trigger_index="38" type="unknown"/>
+            <net data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[5]" storage_index="37" tap_mode="classic" trigger_index="37" type="unknown"/>
+            <net data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[4]" storage_index="36" tap_mode="classic" trigger_index="36" type="unknown"/>
+            <net data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[3]" storage_index="35" tap_mode="classic" trigger_index="35" type="unknown"/>
+            <net data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[2]" storage_index="34" tap_mode="classic" trigger_index="34" type="unknown"/>
+            <net data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[1]" storage_index="33" tap_mode="classic" trigger_index="33" type="unknown"/>
+            <net data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[0]" storage_index="28" tap_mode="classic" trigger_index="28" type="unknown"/>
+          </bus>
+          <bus name="C16:c16|kernal_dl_data" order="msb_to_lsb" type="combinatorial">
+            <net data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_data[7]" storage_index="49" tap_mode="classic" trigger_index="49" type="unknown"/>
+            <net data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_data[6]" storage_index="48" tap_mode="classic" trigger_index="48" type="unknown"/>
+            <net data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_data[5]" storage_index="47" tap_mode="classic" trigger_index="47" type="unknown"/>
+            <net data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_data[4]" storage_index="46" tap_mode="classic" trigger_index="46" type="unknown"/>
+            <net data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_data[3]" storage_index="45" tap_mode="classic" trigger_index="45" type="unknown"/>
+            <net data_index="44" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_data[2]" storage_index="44" tap_mode="classic" trigger_index="44" type="unknown"/>
+            <net data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_data[1]" storage_index="43" tap_mode="classic" trigger_index="43" type="unknown"/>
+            <net data_index="42" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_data[0]" storage_index="42" tap_mode="classic" trigger_index="42" type="unknown"/>
+          </bus>
+          <net data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="rising edge" name="C16:c16|kernal_dl_write" storage_index="50" tap_mode="classic" trigger_index="50" type="unknown"/>
+          <net data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|sreset" storage_index="51" tap_mode="classic" trigger_index="51" type="unknown"/>
+          <net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|RESET" storage_index="10" tap_mode="classic" trigger_index="10" type="unknown"/>
+          <net data_index="111" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="rom_download" storage_index="159" tap_mode="classic" trigger_index="111" type="unknown"/>
+        </data_view>
+        <setup_view>
+          <bus name="C16:c16|A" order="msb_to_lsb" state="collapse" type="combinatorial">
+            <net data_index="7" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|A[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="7" tap_mode="classic" trigger_index="7" type="unknown"/>
+            <net data_index="6" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|A[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="6" tap_mode="classic" trigger_index="6" type="unknown"/>
+            <net data_index="5" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|A[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="5" tap_mode="classic" trigger_index="5" type="unknown"/>
+            <net data_index="4" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|A[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="4" tap_mode="classic" trigger_index="4" type="unknown"/>
+            <net data_index="3" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|A[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="3" tap_mode="classic" trigger_index="3" type="unknown"/>
+            <net data_index="2" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|A[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="2" tap_mode="classic" trigger_index="2" type="unknown"/>
+            <net data_index="1" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|A[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="1" tap_mode="classic" trigger_index="1" type="unknown"/>
+            <net data_index="0" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|A[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="0" tap_mode="classic" trigger_index="0" type="unknown"/>
+          </bus>
+          <net data_index="9" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|RAS" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="9" tap_mode="classic" trigger_index="9" type="unknown"/>
+          <net data_index="8" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|CAS" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="8" tap_mode="classic" trigger_index="8" type="unknown"/>
+          <net data_index="11" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|RW" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="11" tap_mode="classic" trigger_index="11" type="unknown"/>
+          <net data_index="40" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|clkref" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="185" tap_mode="classic" trigger_index="40" type="unknown"/>
+          <bus name="sdram:sdram|q" order="msb_to_lsb" type="register">
+            <net data_index="60" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|q[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="205" tap_mode="classic" trigger_index="60" type="unknown"/>
+            <net data_index="59" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|q[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="204" tap_mode="classic" trigger_index="59" type="unknown"/>
+            <net data_index="58" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|q[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="203" tap_mode="classic" trigger_index="58" type="unknown"/>
+            <net data_index="57" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|q[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="202" tap_mode="classic" trigger_index="57" type="unknown"/>
+          </bus>
+          <net data_index="12" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="SDRAM_nCS" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="87" tap_mode="classic" trigger_index="12" type="unknown"/>
+          <net data_index="13" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="SDRAM_nRAS" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="88" tap_mode="classic" trigger_index="13" type="unknown"/>
+          <net data_index="11" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="SDRAM_nCAS" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="86" tap_mode="classic" trigger_index="11" type="unknown"/>
+          <net data_index="14" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="SDRAM_nWE" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="89" tap_mode="classic" trigger_index="14" type="unknown"/>
+          <bus name="sdram:sdram|addr" order="msb_to_lsb" type="combinatorial">
+            <net data_index="100" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[24]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="176" tap_mode="classic" trigger_index="100" type="unknown"/>
+            <net data_index="99" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[23]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="175" tap_mode="classic" trigger_index="99" type="unknown"/>
+            <net data_index="98" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[22]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="174" tap_mode="classic" trigger_index="98" type="unknown"/>
+            <net data_index="97" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[21]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="173" tap_mode="classic" trigger_index="97" type="unknown"/>
+            <net data_index="96" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[20]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="172" tap_mode="classic" trigger_index="96" type="unknown"/>
+            <net data_index="94" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[19]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="170" tap_mode="classic" trigger_index="94" type="unknown"/>
+            <net data_index="93" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[18]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="169" tap_mode="classic" trigger_index="93" type="unknown"/>
+            <net data_index="92" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[17]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="168" tap_mode="classic" trigger_index="92" type="unknown"/>
+            <net data_index="91" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[16]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="167" tap_mode="classic" trigger_index="91" type="unknown"/>
+            <net data_index="90" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="166" tap_mode="classic" trigger_index="90" type="unknown"/>
+            <net data_index="89" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="165" tap_mode="classic" trigger_index="89" type="unknown"/>
+            <net data_index="88" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="164" tap_mode="classic" trigger_index="88" type="unknown"/>
+            <net data_index="87" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="163" tap_mode="classic" trigger_index="87" type="unknown"/>
+            <net data_index="86" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="162" tap_mode="classic" trigger_index="86" type="unknown"/>
+            <net data_index="85" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="161" tap_mode="classic" trigger_index="85" type="unknown"/>
+            <net data_index="108" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="184" tap_mode="classic" trigger_index="108" type="unknown"/>
+            <net data_index="107" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="183" tap_mode="classic" trigger_index="107" type="unknown"/>
+            <net data_index="106" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="182" tap_mode="classic" trigger_index="106" type="unknown"/>
+            <net data_index="105" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="181" tap_mode="classic" trigger_index="105" type="unknown"/>
+            <net data_index="104" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="180" tap_mode="classic" trigger_index="104" type="unknown"/>
+            <net data_index="103" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="179" tap_mode="classic" trigger_index="103" type="unknown"/>
+            <net data_index="102" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="178" tap_mode="classic" trigger_index="102" type="unknown"/>
+            <net data_index="101" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="177" tap_mode="classic" trigger_index="101" type="unknown"/>
+            <net data_index="95" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="171" tap_mode="classic" trigger_index="95" type="unknown"/>
+            <net data_index="84" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="160" tap_mode="classic" trigger_index="84" type="unknown"/>
+          </bus>
+          <bus name="sdram_din" order="msb_to_lsb" state="collapse" type="combinatorial">
+            <net data_index="67" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="212" tap_mode="classic" trigger_index="67" type="unknown"/>
+            <net data_index="66" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="211" tap_mode="classic" trigger_index="66" type="unknown"/>
+            <net data_index="65" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="210" tap_mode="classic" trigger_index="65" type="unknown"/>
+            <net data_index="64" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="209" tap_mode="classic" trigger_index="64" type="unknown"/>
+            <net data_index="63" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="208" tap_mode="classic" trigger_index="63" type="unknown"/>
+            <net data_index="62" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="207" tap_mode="classic" trigger_index="62" type="unknown"/>
+            <net data_index="76" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="221" tap_mode="classic" trigger_index="76" type="unknown"/>
+            <net data_index="75" duplicate_name_allowed="false" is_data_input="false" is_node_valid="false" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="220" tap_mode="classic" trigger_index="75" type="unknown"/>
+            <net data_index="74" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="219" tap_mode="classic" trigger_index="74" type="unknown"/>
+            <net data_index="73" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="218" tap_mode="classic" trigger_index="73" type="unknown"/>
+            <net data_index="72" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="217" tap_mode="classic" trigger_index="72" type="unknown"/>
+            <net data_index="71" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="216" tap_mode="classic" trigger_index="71" type="unknown"/>
+            <net data_index="70" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="215" tap_mode="classic" trigger_index="70" type="unknown"/>
+            <net data_index="69" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="214" tap_mode="classic" trigger_index="69" type="unknown"/>
+            <net data_index="68" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="213" tap_mode="classic" trigger_index="68" type="unknown"/>
+            <net data_index="61" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram_din[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="206" tap_mode="classic" trigger_index="61" type="unknown"/>
+          </bus>
+          <bus name="sdram:sdram|dout" order="msb_to_lsb" state="collapse" type="combinatorial">
+            <net data_index="47" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="192" tap_mode="classic" trigger_index="47" type="unknown"/>
+            <net data_index="46" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="191" tap_mode="classic" trigger_index="46" type="unknown"/>
+            <net data_index="45" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="190" tap_mode="classic" trigger_index="45" type="unknown"/>
+            <net data_index="44" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="189" tap_mode="classic" trigger_index="44" type="unknown"/>
+            <net data_index="43" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="188" tap_mode="classic" trigger_index="43" type="unknown"/>
+            <net data_index="42" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="187" tap_mode="classic" trigger_index="42" type="unknown"/>
+            <net data_index="56" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="201" tap_mode="classic" trigger_index="56" type="unknown"/>
+            <net data_index="55" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="200" tap_mode="classic" trigger_index="55" type="unknown"/>
+            <net data_index="54" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="199" tap_mode="classic" trigger_index="54" type="unknown"/>
+            <net data_index="53" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="198" tap_mode="classic" trigger_index="53" type="unknown"/>
+            <net data_index="52" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="197" tap_mode="classic" trigger_index="52" type="unknown"/>
+            <net data_index="51" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="196" tap_mode="classic" trigger_index="51" type="unknown"/>
+            <net data_index="50" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="195" tap_mode="classic" trigger_index="50" type="unknown"/>
+            <net data_index="49" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="194" tap_mode="classic" trigger_index="49" type="unknown"/>
+            <net data_index="48" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="193" tap_mode="classic" trigger_index="48" type="unknown"/>
+            <net data_index="41" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="sdram:sdram|dout[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="186" tap_mode="classic" trigger_index="41" type="unknown"/>
+          </bus>
+          <bus name="ioctl_load_addr" order="msb_to_lsb" state="collapse" type="register">
+            <net data_index="48" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="123" tap_mode="classic" trigger_index="48" type="unknown"/>
+            <net data_index="47" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="122" tap_mode="classic" trigger_index="47" type="unknown"/>
+            <net data_index="46" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="121" tap_mode="classic" trigger_index="46" type="unknown"/>
+            <net data_index="45" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="120" tap_mode="classic" trigger_index="45" type="unknown"/>
+            <net data_index="44" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="119" tap_mode="classic" trigger_index="44" type="unknown"/>
+            <net data_index="43" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="118" tap_mode="classic" trigger_index="43" type="unknown"/>
+            <net data_index="57" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="132" tap_mode="classic" trigger_index="57" type="unknown"/>
+            <net data_index="56" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="131" tap_mode="classic" trigger_index="56" type="unknown"/>
+            <net data_index="55" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="130" tap_mode="classic" trigger_index="55" type="unknown"/>
+            <net data_index="54" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="129" tap_mode="classic" trigger_index="54" type="unknown"/>
+            <net data_index="53" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="128" tap_mode="classic" trigger_index="53" type="unknown"/>
+            <net data_index="52" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="127" tap_mode="classic" trigger_index="52" type="unknown"/>
+            <net data_index="51" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="126" tap_mode="classic" trigger_index="51" type="unknown"/>
+            <net data_index="50" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="125" tap_mode="classic" trigger_index="50" type="unknown"/>
+            <net data_index="49" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="124" tap_mode="classic" trigger_index="49" type="unknown"/>
+            <net data_index="42" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_load_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="117" tap_mode="classic" trigger_index="42" type="unknown"/>
+          </bus>
+          <bus name="data_io:data_io|a" order="msb_to_lsb" state="collapse" type="combinatorial">
+            <net data_index="92" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="97" tap_mode="classic" trigger_index="92" type="unknown"/>
+            <net data_index="91" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="96" tap_mode="classic" trigger_index="91" type="unknown"/>
+            <net data_index="90" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="95" tap_mode="classic" trigger_index="90" type="unknown"/>
+            <net data_index="89" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="94" tap_mode="classic" trigger_index="89" type="unknown"/>
+            <net data_index="88" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="93" tap_mode="classic" trigger_index="88" type="unknown"/>
+            <net data_index="87" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="92" tap_mode="classic" trigger_index="87" type="unknown"/>
+            <net data_index="101" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="106" tap_mode="classic" trigger_index="101" type="unknown"/>
+            <net data_index="100" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="105" tap_mode="classic" trigger_index="100" type="unknown"/>
+            <net data_index="99" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="104" tap_mode="classic" trigger_index="99" type="unknown"/>
+            <net data_index="98" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="103" tap_mode="classic" trigger_index="98" type="unknown"/>
+            <net data_index="97" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="102" tap_mode="classic" trigger_index="97" type="unknown"/>
+            <net data_index="96" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="101" tap_mode="classic" trigger_index="96" type="unknown"/>
+            <net data_index="95" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="100" tap_mode="classic" trigger_index="95" type="unknown"/>
+            <net data_index="94" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="99" tap_mode="classic" trigger_index="94" type="unknown"/>
+            <net data_index="93" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="98" tap_mode="classic" trigger_index="93" type="unknown"/>
+            <net data_index="86" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|a[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="91" tap_mode="classic" trigger_index="86" type="unknown"/>
+          </bus>
+          <bus name="data_io:data_io|d" order="msb_to_lsb" type="combinatorial">
+            <net data_index="109" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|d[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="114" tap_mode="classic" trigger_index="109" type="unknown"/>
+            <net data_index="108" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|d[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="113" tap_mode="classic" trigger_index="108" type="unknown"/>
+            <net data_index="107" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|d[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="112" tap_mode="classic" trigger_index="107" type="unknown"/>
+            <net data_index="106" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|d[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="111" tap_mode="classic" trigger_index="106" type="unknown"/>
+            <net data_index="105" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|d[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="110" tap_mode="classic" trigger_index="105" type="unknown"/>
+            <net data_index="104" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|d[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="109" tap_mode="classic" trigger_index="104" type="unknown"/>
+            <net data_index="103" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|d[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="108" tap_mode="classic" trigger_index="103" type="unknown"/>
+            <net data_index="102" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|d[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="107" tap_mode="classic" trigger_index="102" type="unknown"/>
+          </bus>
+          <net data_index="40" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="data_io:data_io|downloading" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="115" tap_mode="classic" trigger_index="40" type="unknown"/>
+          <net data_index="110" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="data_io:data_io|wr" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="116" tap_mode="classic" trigger_index="110" type="unknown"/>
+          <net data_index="15" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="c16_wait" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="90" tap_mode="classic" trigger_index="15" type="unknown"/>
+          <net data_index="58" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_ram_wr" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="133" tap_mode="classic" trigger_index="58" type="unknown"/>
+          <bus name="ioctl_sdram_addr" order="msb_to_lsb" type="register">
+            <net data_index="65" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="140" tap_mode="classic" trigger_index="65" type="unknown"/>
+            <net data_index="64" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="139" tap_mode="classic" trigger_index="64" type="unknown"/>
+            <net data_index="63" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="138" tap_mode="classic" trigger_index="63" type="unknown"/>
+            <net data_index="62" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="137" tap_mode="classic" trigger_index="62" type="unknown"/>
+            <net data_index="61" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="136" tap_mode="classic" trigger_index="61" type="unknown"/>
+            <net data_index="60" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="135" tap_mode="classic" trigger_index="60" type="unknown"/>
+            <net data_index="74" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="149" tap_mode="classic" trigger_index="74" type="unknown"/>
+            <net data_index="73" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="148" tap_mode="classic" trigger_index="73" type="unknown"/>
+            <net data_index="72" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="147" tap_mode="classic" trigger_index="72" type="unknown"/>
+            <net data_index="71" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="146" tap_mode="classic" trigger_index="71" type="unknown"/>
+            <net data_index="70" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="145" tap_mode="classic" trigger_index="70" type="unknown"/>
+            <net data_index="69" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="144" tap_mode="classic" trigger_index="69" type="unknown"/>
+            <net data_index="68" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="143" tap_mode="classic" trigger_index="68" type="unknown"/>
+            <net data_index="67" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="142" tap_mode="classic" trigger_index="67" type="unknown"/>
+            <net data_index="66" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="141" tap_mode="classic" trigger_index="66" type="unknown"/>
+            <net data_index="59" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_addr[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="134" tap_mode="classic" trigger_index="59" type="unknown"/>
+          </bus>
+          <bus name="ioctl_sdram_data" order="msb_to_lsb" type="register">
+            <net data_index="82" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_data[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="157" tap_mode="classic" trigger_index="82" type="unknown"/>
+            <net data_index="81" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_data[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="156" tap_mode="classic" trigger_index="81" type="unknown"/>
+            <net data_index="80" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_data[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="155" tap_mode="classic" trigger_index="80" type="unknown"/>
+            <net data_index="79" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_data[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="154" tap_mode="classic" trigger_index="79" type="unknown"/>
+            <net data_index="78" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_data[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="153" tap_mode="classic" trigger_index="78" type="unknown"/>
+            <net data_index="77" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_data[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="152" tap_mode="classic" trigger_index="77" type="unknown"/>
+            <net data_index="76" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_data[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="151" tap_mode="classic" trigger_index="76" type="unknown"/>
+            <net data_index="75" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="dont_care" name="ioctl_sdram_data[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="150" tap_mode="classic" trigger_index="75" type="unknown"/>
+          </bus>
+          <net data_index="83" duplicate_name_allowed="false" is_data_input="false" is_node_valid="true" is_storage_input="true" is_trigger_input="false" level-0="rising edge" name="ioctl_sdram_write" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="158" tap_mode="classic" trigger_index="83" type="unknown"/>
+          <bus name="C16:c16|c16_keymatrix:keyboard|kbus" order="msb_to_lsb" type="combinatorial">
+            <net data_index="19" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|kbus[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="19" tap_mode="classic" trigger_index="19" type="unknown"/>
+            <net data_index="18" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|kbus[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="18" tap_mode="classic" trigger_index="18" type="unknown"/>
+            <net data_index="17" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|kbus[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="17" tap_mode="classic" trigger_index="17" type="unknown"/>
+            <net data_index="16" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|kbus[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="16" tap_mode="classic" trigger_index="16" type="unknown"/>
+            <net data_index="15" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|kbus[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="15" tap_mode="classic" trigger_index="15" type="unknown"/>
+            <net data_index="14" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|kbus[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="14" tap_mode="classic" trigger_index="14" type="unknown"/>
+            <net data_index="13" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|kbus[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="13" tap_mode="classic" trigger_index="13" type="unknown"/>
+            <net data_index="12" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|kbus[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="12" tap_mode="classic" trigger_index="12" type="unknown"/>
+          </bus>
+          <bus name="C16:c16|c16_keymatrix:keyboard|row" order="msb_to_lsb" type="combinatorial">
+            <net data_index="27" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|row[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="27" tap_mode="classic" trigger_index="27" type="unknown"/>
+            <net data_index="26" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|row[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="26" tap_mode="classic" trigger_index="26" type="unknown"/>
+            <net data_index="25" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|row[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="25" tap_mode="classic" trigger_index="25" type="unknown"/>
+            <net data_index="24" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|row[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="24" tap_mode="classic" trigger_index="24" type="unknown"/>
+            <net data_index="23" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|row[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="23" tap_mode="classic" trigger_index="23" type="unknown"/>
+            <net data_index="22" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|row[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="22" tap_mode="classic" trigger_index="22" type="unknown"/>
+            <net data_index="21" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|row[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="21" tap_mode="classic" trigger_index="21" type="unknown"/>
+            <net data_index="20" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|c16_keymatrix:keyboard|row[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="20" tap_mode="classic" trigger_index="20" type="unknown"/>
+          </bus>
+          <bus name="C16:c16|ted:mos8360|addr_in_reg" order="msb_to_lsb" type="register">
+            <net data_index="73" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in_reg[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="73" tap_mode="classic" trigger_index="73" type="unknown"/>
+            <net data_index="72" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in_reg[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="72" tap_mode="classic" trigger_index="72" type="unknown"/>
+            <net data_index="71" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in_reg[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="71" tap_mode="classic" trigger_index="71" type="unknown"/>
+            <net data_index="70" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in_reg[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="70" tap_mode="classic" trigger_index="70" type="unknown"/>
+            <net data_index="69" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in_reg[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="69" tap_mode="classic" trigger_index="69" type="unknown"/>
+            <net data_index="68" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in_reg[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="68" tap_mode="classic" trigger_index="68" type="unknown"/>
+          </bus>
+          <bus name="C16:c16|ted:mos8360|phicounter" order="msb_to_lsb" type="register">
+            <net data_index="85" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|phicounter[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="85" tap_mode="classic" trigger_index="85" type="unknown"/>
+            <net data_index="84" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|phicounter[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="84" tap_mode="classic" trigger_index="84" type="unknown"/>
+            <net data_index="83" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|phicounter[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="83" tap_mode="classic" trigger_index="83" type="unknown"/>
+            <net data_index="82" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|phicounter[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="82" tap_mode="classic" trigger_index="82" type="unknown"/>
+          </bus>
+          <bus name="C16:c16|ted:mos8360|addr_in" order="msb_to_lsb" type="combinatorial">
+            <net data_index="58" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[15]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="58" tap_mode="classic" trigger_index="58" type="unknown"/>
+            <net data_index="57" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[14]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="57" tap_mode="classic" trigger_index="57" type="unknown"/>
+            <net data_index="56" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[13]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="56" tap_mode="classic" trigger_index="56" type="unknown"/>
+            <net data_index="55" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[12]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="55" tap_mode="classic" trigger_index="55" type="unknown"/>
+            <net data_index="54" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[11]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="54" tap_mode="classic" trigger_index="54" type="unknown"/>
+            <net data_index="53" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[10]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="53" tap_mode="classic" trigger_index="53" type="unknown"/>
+            <net data_index="67" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[9]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="67" tap_mode="classic" trigger_index="67" type="unknown"/>
+            <net data_index="66" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[8]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="66" tap_mode="classic" trigger_index="66" type="unknown"/>
+            <net data_index="65" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="65" tap_mode="classic" trigger_index="65" type="unknown"/>
+            <net data_index="64" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="64" tap_mode="classic" trigger_index="64" type="unknown"/>
+            <net data_index="63" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="63" tap_mode="classic" trigger_index="63" type="unknown"/>
+            <net data_index="62" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="62" tap_mode="classic" trigger_index="62" type="unknown"/>
+            <net data_index="61" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="61" tap_mode="classic" trigger_index="61" type="unknown"/>
+            <net data_index="60" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="60" tap_mode="classic" trigger_index="60" type="unknown"/>
+            <net data_index="59" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="59" tap_mode="classic" trigger_index="59" type="unknown"/>
+            <net data_index="52" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|addr_in[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="52" tap_mode="classic" trigger_index="52" type="unknown"/>
+          </bus>
+          <bus name="C16:c16|ted:mos8360|data_in" order="msb_to_lsb" state="collapse" type="combinatorial">
+            <net data_index="81" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|data_in[7]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="81" tap_mode="classic" trigger_index="81" type="unknown"/>
+            <net data_index="80" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|data_in[6]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="80" tap_mode="classic" trigger_index="80" type="unknown"/>
+            <net data_index="79" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|data_in[5]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="79" tap_mode="classic" trigger_index="79" type="unknown"/>
+            <net data_index="78" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|data_in[4]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="78" tap_mode="classic" trigger_index="78" type="unknown"/>
+            <net data_index="77" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|data_in[3]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="77" tap_mode="classic" trigger_index="77" type="unknown"/>
+            <net data_index="76" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|data_in[2]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="76" tap_mode="classic" trigger_index="76" type="unknown"/>
+            <net data_index="75" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|data_in[1]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="75" tap_mode="classic" trigger_index="75" type="unknown"/>
+            <net data_index="74" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="dont_care" name="C16:c16|ted:mos8360|data_in[0]" pwr_level-0="dont_care" pwr_storage-0="dont_care" pwr_storage-1="dont_care" pwr_storage-2="dont_care" storage-0="dont_care" storage-1="dont_care" storage-2="dont_care" storage_index="74" tap_mode="classic" trigger_index="74" type="unknown"/>
+          </bus>
+          <bus name="C16:c16|kernal_dl_addr" order="msb_to_lsb" type="combinatorial">
+            <net data_index="32" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[13]" storage_index="32" tap_mode="classic" trigger_index="32" type="unknown"/>
+            <net data_index="31" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[12]" storage_index="31" tap_mode="classic" trigger_index="31" type="unknown"/>
+            <net data_index="30" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[11]" storage_index="30" tap_mode="classic" trigger_index="30" type="unknown"/>
+            <net data_index="29" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[10]" storage_index="29" tap_mode="classic" trigger_index="29" type="unknown"/>
+            <net data_index="41" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[9]" storage_index="41" tap_mode="classic" trigger_index="41" type="unknown"/>
+            <net data_index="40" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[8]" storage_index="40" tap_mode="classic" trigger_index="40" type="unknown"/>
+            <net data_index="39" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[7]" storage_index="39" tap_mode="classic" trigger_index="39" type="unknown"/>
+            <net data_index="38" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[6]" storage_index="38" tap_mode="classic" trigger_index="38" type="unknown"/>
+            <net data_index="37" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[5]" storage_index="37" tap_mode="classic" trigger_index="37" type="unknown"/>
+            <net data_index="36" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[4]" storage_index="36" tap_mode="classic" trigger_index="36" type="unknown"/>
+            <net data_index="35" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[3]" storage_index="35" tap_mode="classic" trigger_index="35" type="unknown"/>
+            <net data_index="34" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[2]" storage_index="34" tap_mode="classic" trigger_index="34" type="unknown"/>
+            <net data_index="33" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[1]" storage_index="33" tap_mode="classic" trigger_index="33" type="unknown"/>
+            <net data_index="28" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_addr[0]" storage_index="28" tap_mode="classic" trigger_index="28" type="unknown"/>
+          </bus>
+          <bus name="C16:c16|kernal_dl_data" order="msb_to_lsb" type="combinatorial">
+            <net data_index="49" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_data[7]" storage_index="49" tap_mode="classic" trigger_index="49" type="unknown"/>
+            <net data_index="48" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_data[6]" storage_index="48" tap_mode="classic" trigger_index="48" type="unknown"/>
+            <net data_index="47" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_data[5]" storage_index="47" tap_mode="classic" trigger_index="47" type="unknown"/>
+            <net data_index="46" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_data[4]" storage_index="46" tap_mode="classic" trigger_index="46" type="unknown"/>
+            <net data_index="45" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_data[3]" storage_index="45" tap_mode="classic" trigger_index="45" type="unknown"/>
+            <net data_index="44" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_data[2]" storage_index="44" tap_mode="classic" trigger_index="44" type="unknown"/>
+            <net data_index="43" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_data[1]" storage_index="43" tap_mode="classic" trigger_index="43" type="unknown"/>
+            <net data_index="42" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|kernal_dl_data[0]" storage_index="42" tap_mode="classic" trigger_index="42" type="unknown"/>
+          </bus>
+          <net data_index="50" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" level-0="rising edge" name="C16:c16|kernal_dl_write" storage_index="50" tap_mode="classic" trigger_index="50" type="unknown"/>
+          <net data_index="51" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|sreset" storage_index="51" tap_mode="classic" trigger_index="51" type="unknown"/>
+          <net data_index="10" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="C16:c16|RESET" storage_index="10" tap_mode="classic" trigger_index="10" type="unknown"/>
+          <net data_index="111" duplicate_name_allowed="false" is_data_input="true" is_node_valid="true" is_storage_input="true" is_trigger_input="true" name="rom_download" storage_index="159" tap_mode="classic" trigger_index="111" type="unknown"/>
+        </setup_view>
+        <trigger_in_editor/>
+        <trigger_out_editor/>
+      </presentation>
+      <trigger CRC="A5BFA185" attribute_mem_mode="false" gap_record="true" global_temp="1" name="trigger: 2016/07/29 10:48:46  #1" position="pre" power_up_trigger_mode="false" record_data_gap="true" segment_size="1" storage_mode="off" storage_qualifier_disabled="no" storage_qualifier_port_is_pin="true" storage_qualifier_port_name="auto_stp_external_storage_qualifier" storage_qualifier_port_tap_mode="classic" trigger_type="circular">
+        <power_up_trigger position="pre" storage_qualifier_disabled="no"/>
+        <events use_custom_flow_control="no">
+          <level enabled="yes" name="condition1" type="basic">'C16:c16|kernal_dl_write' == rising edge
+            <power_up enabled="yes">
+            </power_up>
+            <op_node/>
+          </level>
+        </events>
+        <storage_qualifier_events>
+          <transitional>111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000011111111111111111111111101000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000
+            <pwr_up_transitional>111111111111111111111111111111111111111111111111111111111111111111111111111111111111110000011111111111111111111111101000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000</pwr_up_transitional>
+          </transitional>
+          <storage_qualifier_level type="basic">
+            <power_up>
+            </power_up>
+            <op_node/>
+          </storage_qualifier_level>
+          <storage_qualifier_level type="basic">
+            <power_up>
+            </power_up>
+            <op_node/>
+          </storage_qualifier_level>
+          <storage_qualifier_level type="basic">
+            <power_up>
+            </power_up>
+            <op_node/>
+          </storage_qualifier_level>
+        </storage_qualifier_events>
+        <log>
+          <data global_temp="1" name="log: Trig @ 2016/07/29 10:55:58 (0:0:0.1 elapsed)" power_up_mode="false" sample_depth="128" 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+          <extradata>1111111111111111T111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111</extradata>
+        </log>
+      </trigger>
+    </signal_set>
+  </instance>
+  <mnemonics/>
+  <static_plugin_mnemonics/>
+  <global_info>
+    <single attribute="active instance" value="0"/>
+    <single attribute="config widget visible" value="1"/>
+    <single attribute="data log widget visible" value="0"/>
+    <single attribute="hierarchy widget height" value="82"/>
+    <single attribute="hierarchy widget visible" value="0"/>
+    <single attribute="instance widget visible" value="1"/>
+    <single attribute="jtag widget visible" value="1"/>
+    <multi attribute="frame size" size="2" value="1189,895"/>
+    <multi attribute="jtag widget size" size="2" value="372,135"/>
+  </global_info>
+</session>
diff --git a/cores/c16/ted.v b/cores/c16/ted.v
new file mode 100644
index 0000000..8841adf
--- /dev/null
+++ b/cores/c16/ted.v
@@ -0,0 +1,1752 @@
+`timescale 1ns / 1ps
+//////////////////////////////////////////////////////////////////////////////////
+//  Copyright 2013-2016 Istvan Hegedus
+//
+//  FPGATED is free software: you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation, either version 3 of the License, or
+//  (at your option) any later version.
+//
+//  FPGATED is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program.  If not, see <http://www.gnu.org/licenses/>. 
+//
+// Create Date:   12/18/2013 - 31/03/2016
+// Design Name: 	MOS 8360 video chip
+// Module Name:   ted.v 
+// Project Name:  FPGATED
+// Description: 	Cycle exact MOS 8360 TED display chip
+//
+// Revision history:  
+//	0.2	 12/11/2015			diag 264 runs, all screenmodes implemented, external dram works, scroll bug in diag264
+// 0.3	 22/01/2016			DRAM resfresh horizontal events improved (increment start/stop, counter reset),vertical scroll bug in Invincible, FF1E write bug in New FLI, FLI incorrect 	 				
+// 0.4	 03/02/2016			VertSub counter fixed for Invincible start screen
+// 0.5	 22/02/2016			Raster interrupt fixed, Invincible does not freeze now
+// 0.6	 03/03/2016			Multicolor Character mode bug fixed in pixelgenerator. Majesty Of Sprites looks good now
+// 0.7	 30/03/2016			Audio sound generator and audio D/A implemented
+// 1.0	 14/07/2016			First public release, functionally equivalent to 0.7, code cleaned up, license information added
+//////////////////////////////////////////////////////////////////////////////////
+
+module ted(
+    input wire clk,								// clk must be 4*dot clk so 28.375152MHz for PAL (1.6*PAL system's clock) and 28.63636 for NTSC (2*NTSC system's clock) 
+	 input wire [15:0] addr_in,
+	 output wire [15:0] addr_out,
+	 input wire [7:0] data_in,
+	 output wire [7:0] data_out,
+	 input wire rw,
+	 output wire cpuclk,							// this is a CPU clock for external real CPU
+	 output wire [6:0] color,					// 7 bits color code
+	 output wire csync,
+	 output reg hsync,
+	 output reg vsync,
+	 output wire irq,
+	 output wire ba,
+	 output reg mux,
+	 output reg ras,
+	 output reg cas,
+	 output reg cs0,
+	 output reg cs1,
+	 output reg aec,
+	 output wire snd,
+	 output wire pal,
+	 input wire [7:0] k,
+	 output wire cpuenable						// this TED signals is needed only for FPGA bustiming and FPGA internal cpu. If external CPU is used, it is not needed.
+    );
+
+
+	 
+// TED register addresses
+
+parameter TIMER1LO=6'h00;
+parameter TIMER1HI=6'h01;
+parameter TIMER2LO=6'h02;
+parameter TIMER2HI=6'h03;
+parameter TIMER3LO=6'h04;
+parameter TIMER3HI=6'h05;
+parameter CONTROL1=6'h06;
+parameter CONTROL2=6'h07;
+parameter KEYLATCH=6'h08;
+parameter IRQ		=6'h09;
+parameter IRQEN	=6'h0A;
+parameter RASTER	=6'h0B;
+parameter CURPOSHI=6'h0C;
+parameter CURPOSLO=6'h0D;
+parameter CH1FREQLO=6'h0E;
+parameter CH2FREQLO=6'h0F;
+parameter CH2FREQHI=6'h10;
+parameter SOUNDCTRL=6'h11;
+parameter BMAPBASE=6'h12;
+parameter CHARBASE=6'h13;
+parameter VIDEOBASE=6'h14;
+parameter BGCOLOR0=6'h15;
+parameter BGCOLOR1=6'h16;
+parameter BGCOLOR2=6'h17;
+parameter BGCOLOR3=6'h18;
+parameter EXCOLOR=6'h19;
+parameter CHARPOSRELOADHI=6'h1A;
+parameter CHARPOSRELOADLO=6'h1B;
+parameter VSCANPOSHI=6'h1C;
+parameter VSCANPOSLO=6'h1D;
+parameter HSCANPOS=6'h1E;
+parameter FLASH_VERTSUB=6'h1F;
+parameter ROMEN=6'h3E;
+parameter RAMEN=6'h3F;
+
+// DMA FSM states
+
+localparam IDLE=3'b000,THALT1=3'b001,THALT2=3'b010,THALT3=3'b011,TDMA=3'b100;
+reg [2:0] dma_state=IDLE,dma_nextstate;			// DMA FSM state register
+
+// TED user accessible registers
+// These registers are the actual TED registers accessible by end users
+
+reg [15:0] timer1=16'b0,timer1_reload=16'b0;													// $FF00/01
+reg [15:0] timer2=16'b0;																			// $FF02/03
+reg [15:0] timer3=16'b0;																			// $FF04/05
+reg test=1'b0,ecm=1'b0,bmm=1'b0,den=1'b0,rsel=1'b0;										// $FF06 control1 register bits
+reg [2:0] yscroll=3'b0;																				// $FF06 bits 0-2, vertical scroll register
+reg bmm_reg=1'b0,ecm_reg=1'b0;																	// delayed registered values of BMM and ECM
+reg reverse=1'b0,stop=1'b0,mcm=1'b0,csel=1'b0;									         // $FF07 control2 register bits
+reg [2:0] xscroll=3'b0;																				// $FF07 bits 0-2, horizontal scroll regitser
+reg reverse_reg=1'b0,mcm_reg=1'b0;																// delayed registered values of REVERSE and ECM
+reg [7:0] keylatch=8'hff;																			// $FF08 keyboard latch
+reg Cnt1Irq=1'b0,Cnt2Irq=1'b0,Cnt3Irq=1'b0,RasterIrq=1'b0,LPIrq=1'b1;				// $FF09 IRQ register
+reg enCnt1Irq=1'b0,enCnt2Irq=1'b0,enCnt3Irq=1'b0,enRasterIrq=1'b0,enLPIrq=1'b0; 	// $FF0A IRQ enable register
+reg [8:0] RasterCmp=9'b0;																			// $FF0B
+reg [9:0] CursorPos=10'b0;																			// $FF0C/0D
+reg [9:0] Ch1Freq=10'b0;																			// $FF0E, $FF12 bits 0-1
+reg [9:0] Ch2Freq=10'b0;																			// $FF0F, $FF10 bits 0-1
+reg damode=1'b0,ch2noise=1'b0,ch2en=1'b0,ch1en=1'b0;										// $FF11 bits 4-7
+reg [3:0] volume=4'b0;																				// $FF11 bits 0-3
+reg [2:0] bmapbase=3'b0;																			// $FF12 bits 3-5, Bitmap base address
+reg charrom=1'b0;																						// $FF12 bit 2
+reg [5:0] charbase=6'b0;																			// $FF13 bits 2-7, Character memory base address
+reg clkmode=1'b0;																						// $FF13 bit 1, force single clock mode
+reg [4:0] vmbase=5'b0;																				// $FF14 bits 3-7, Video RAM base address register 
+reg [6:0] bgcolor0=7'b0,bgcolor1=7'b0,bgcolor2=7'b0,bgcolor3=7'b0,excolor=7'b0;	// $FF15-19 color registers
+reg [9:0] CharPosReload=10'b0;																	// $FF1A/B, Character Position Reload increments by 40 for each character row completed
+reg [8:0] vcounter=9'b0;							   											// $FF1C/D, Vertical line counter
+reg [8:0] hcounter=9'b0;							   											// $FF1E, Horizontal dot counter. In real TED it is 11bit. Counts from 0 to 455
+reg [4:0] FlashCount=5'b0;																			// $FF1F bits 3-6, Flash counter's 5th bit is the actual flash state and is not user accessible
+reg [2:0] VertSubCount=3'b0;																		// $FF1f bits 0-2, Vertical Character scan line position
+
+// TED internal operational registers
+// These are needed for the internal operation 
+
+reg [7:0] refreshcounter=8'h00;
+reg refresh=1'b0;
+reg [3:0] phicounter=4'b0;				    			// CPU single clock generator counter
+reg phi=1'b0;												// CPU single clock
+reg singleclock=1'b0;									// signals single clock mode
+
+reg [8:0] hcounter_next;
+reg [8:0] vcounter_next;
+reg [8:0] videoline=9'b0;								// vcounter latched at start of each scanline
+reg [7:0] dataout_reg=8'hff;							// TED's databus out register
+reg [7:0] data_in_reg;									// TED databus in register
+reg [5:0] addr_in_reg;									// TED address in register
+
+reg [6:0] colorreg=7'b0;								// video out register
+reg ramen=1'b0;											// High memory address RAM enable register (above $8000)
+reg t1stop=1'b0,t2stop=1'b0,t3stop=1'b0;			// Timer disable signals
+reg resetRasterIrq,resetLpIrq,resetCnt1Irq,resetCnt2Irq,resetCnt3Irq; // Interrupt reset signals
+reg RasterIrqDone=1'b0;									// Signals that raster interrupt has already happened in this line
+reg enabledisplay=1'b0;									// DEN register changes enabledisplay signal on first scanline only
+reg badline2=1'b0;										// signals 2nd badline (1st badline signal is a wire)
+reg ext_fetch=1'b0;										// signals external fetch window inside scanline
+reg char_fetch=1'b0;										// signals character fetch window inside scanline
+reg dma_window=1'b0;										// signals active dma range inside a scanline
+reg char_window=1'b0;									// signals when character/pixel data can be latched from data bus inside a scanline
+reg inc_flashcount_window=1'b0;						// signals flash counter increase window
+reg inc_vertsub_window=1'b0;							// active for one single clock cycle, signals vertsub register incrementation point (thus actual increment point is delayed with a single clock cycle)
+reg inc_vertline_window=1'b0;							// active for one single clock cycle, signals vertical line incrementation point (thus actual increment point is delayed with a single clock cycle)
+
+// horizontal event positions used for the horizontal event decoder. They don't necessarily reflect the values seen in documentation 
+reg hpos_0,hpos_8,hpos_154,hpos_172,hpos_288,hpos_295,hpos_296,hpos_303,hpos_304;
+reg hpos_312,hpos_320,hpos_336,hpos_343,hpos_348,hpos_353,hpos_359,hpos_380,hpos_382;
+reg hpos_384,hpos_391,hpos_392,hpos_400,hpos_407,hpos_423,hpos_431,hpos_432,hpos_440;
+
+reg inc_charpos=1'b0;									// signals internal character position register (not user accessible) increment range inside scanline (not same as $FF1A/$FF1B) 
+reg [15:0] addr_out_reg;								// TED's address out register
+reg [15:0] tedaddress;									// this is a non registered TED address (although register variable but used in combinational logic)
+reg datahold=1'b0;										// signals whether TED should hold its data on the databus 
+reg VertSubActive=1'b0;									// signals the scanline ranges when Vertsub counter is active
+reg tedwrite_delay=1'b0;								// this signal was needed to emulate a one dot clock delay when TED writes data to its internal registers. Although most probably this delay exist at
+																// all TED register writes, in FPGATED we use it only for hcounter/vcounter and color register writes. This emulates white pixel bug too.
+reg csyncreg=1'b0,palreg=1'b0,equalization=1'b0,eq1=1'b1,eq2=1'b1;		// PAL/NTSC video screen signals
+reg [9:0] videocounter=10'b0;							// videocounter is the actual DMA counter.
+reg inc_videocounter=1'b0;								// signals videocounter increment window
+reg [9:0] videocounter_reload=10'b0;				// videocounter is reloaded with this value at the beginning of each displayed line
+reg [9:0] CharPosition=10'b0;							// CharPosition is loaded by $FF1A/$FF1B and is similar to videocounter. It is used for pixel data fetch from memory. 
+reg CharPosLatch=1'b0;									// Signals latching position of CharPosition and videocounter
+reg latch_window=1'b0;									// CharPosition and videocounter latch delay window
+reg latch_charposition=1'b0;							// Charposition and videocounter latch position
+
+reg [7:0] attr_buf [0:39];								// TED internal videomatrix attribute memory
+reg [7:0] char_buf [0:39];								// TED internal videomatrix character pointer memory
+reg [7:0] nextchar=8'b0,currentchar=8'b0,waitingchar=8'b0,pixelchar=8'b0;	// next...,current... is a 2 bytes shiftregister to keep data until rendering. waiting... is waiting to be loaded to rendering shiftregister
+reg [7:0] nextattr=8'b0,currentattr=8'b0,waitingattr=8'b0,pixelattr=8'b0;	
+reg [7:0] nextpixels=8'b0,currentpixels=8'b0,waitingpixels=8'b0;
+reg [7:0] pixelshiftreg=8'b0;							// This register contains pixel data and shifts it during rendering
+reg [5:0] shiftcount=6'b0;								// Used by the videomatrix shift register to count number of shifts
+reg verticalscreen=1'b0;								// Signals which lines are in screen area (top/bottom border control)
+reg widescreen=1'b0,narrowscreen=1'b0;				// Signals horizontal screen area (left/right border control)
+reg videoshift=1'b0;										// Signals when vide shoft register is active
+reg nextcursor=1'b0,currentcursor=1'b0,waitingcursor=1'b0;  // cursor state internal storage for 3 signle clock cycles
+
+reg [6:0] pixelcolor;									// Color of a pixel
+reg doubleshift=1'b0;									// During multicolor mode 2 pixels identify one pixel, so this register signals to pixel generator wheter to shift one or two pixels to get color data
+reg dotfetch;												// Signals when TED is fetching pixeldata from databus
+reg dotfetch_reg=1'b0;									// Registered version of dotfetch
+reg [2:0] xscroll_latch=3'b0;							// Registered version of xscroll register
+reg [2:0] yscroll_latch=3'b0;							// Registered version of yscroll register
+reg hblank=1'b0,vblank=1'b0;							// Signals blanking area
+reg refresh_inc=1'b0;									// Dram refresh counter increment window
+reg stopreg=1'b0;											// This is a latched version of stop register. Latched at single cycle end
+
+// audio part registers
+
+reg [1:0] audiocycle=2'b0;								// Audio cycle counter divides single clock by 4 and generates audio clock
+reg [9:0] ch1count=10'b0,ch2count=10'b0;			// Audio channel1 and channel2 counters
+reg ch1state=1'b0,ch2state=1'b0;						// State register of audio channels
+reg ch1stateclk_prev=1'b0,ch2stateclk_prev=1'b0;
+reg [7:0] noisegen=8'b0;								// Noise generator register
+reg [4:0] pwmcounter1=5'b0,pwmcounter2=5'b0;		// PWM D/A counters
+reg ch1pwm=0,ch2pwm=0;									// continous square wave with proportional duty cycle to volume
+reg [4:0] digivolume=5'b0;								// A digital value signaling at which pwmclock cycle PWM signal high value starts. A digitized version of volume level
+reg [17:0] watchdog_ch1=18'b0,watchdog_ch2=18'b0;	// Watchdog timer to emulate sound decay of TED's dynamic latch behaviour
+
+
+integer i;
+integer j;
+integer n;
+
+// Internal wires, flags
+
+wire dphi;													// double phi clock
+wire [8:0] EOS,VS_START,VS_STOP,EQ_START,EQ_STOP,VBLANK_START,VBLANK_STOP;		//video signal generation constants. Vertical Sync, Equalization, Blank 
+wire tick8;													// enable tick for pixelclock (8MHz)
+wire blanking;												// screen blanking area flag
+wire lowrom,highrom;										// TED low and high rom area flags
+wire irqpos;												// IRQ position flag inside clock cycle. Emulates real TED's IRQ signal activation position
+wire io,tedreg,tedwrite;								// IO area flag, TED user registers area flag, TED write cycle flag (signals when TED register is written by CPU)
+wire badline;												// badline flag
+wire attr_fetch_line;									// Visible screen area flag (signals active window)
+wire tedlatch;												// tedlatch simulates at which exact position TED latches value into its internal register from the databus
+wire [7:0] charpointer,attrpointer;
+wire multicolor;											// multicolor mode flag
+wire pixelscreen;											// visible pixelscreen area flag (excluding borders)
+wire ch1clk,ch2clk;										// Audio channel clocks
+wire ch1stateclk,ch2stateclk;							// Audio state register change clock
+wire ch1audio,ch2audio;									// Audio channel square waves not modulated by volume (before PWM)
+wire noise;													// Noise
+wire watchdog_ch1max,watchdog_ch2max;				// Audio watchdog timer maximum values. Actual value is taken from plus4emu
+
+// Initializing internal video matrix
+
+initial
+	begin
+	for(i=0;i<=39;i=i+1)
+		begin
+		char_buf[i]=0;
+		attr_buf[i]=0;
+		end
+	end
+
+
+//-----------------------------------------------------------------------
+// Often used combinational signals
+//-----------------------------------------------------------------------
+
+assign cycle_end=(phicounter==15)?1'b1:1'b0;				// high pulse at the end of each double clock cycle
+assign single_cycle_end=(cycle_end & phi)?1'b1:1'b0;	// high pulse at the end of each single clock cycle
+
+//-----------------------------------------------------------------------
+// Clock signal driver phi=Single Clock  dphi=Double Clock
+//-----------------------------------------------------------------------
+
+always @(posedge clk)											// Counting FPGA clock cycles during double clock. phicounter is mod16 counter, 16*clk=half phi
+	begin
+	phicounter<=phicounter+1;
+	end
+	
+assign cpuclk = singleclock?phi:dphi;						// Generated CPU clock. Used only when real 8501 CPU is connected to FPGA
+assign dphi = phicounter[3];									// Internal double clock signal
+assign cpuenable=(single_cycle_end)?1'b1:					// Generated CPU enable signal. Used only when FPGA CPU is used
+						(cycle_end && !singleclock)?1'b1:
+						1'b0;
+			
+always @(posedge clk)											// Internal single clock signal is always generated
+	begin
+		if (cycle_end)
+				phi<=~phi;											
+	end
+
+always @(posedge clk)											// clock mode controller. Single or double clock multiplex for the CPU.
+	begin
+	if(single_cycle_end)											// clock mode change happens only at single clock boundary
+		singleclock<=((enabledisplay & ext_fetch) | refresh | clkmode | stop);		// there are 4 criterias to generate single clock: display area,dram refresh,forced 1Mhz,TED stop
+	end
+
+always @(posedge clk)
+	begin
+	if(single_cycle_end)
+		stopreg<=stop;
+	end
+
+//--------------------------------------------------------------------------
+// Attribute Fetch
+//--------------------------------------------------------------------------
+
+always @(posedge clk)											// flip flop to signal external fetch single clock window, delayed with 1 single clock cycle
+	begin
+	if(hpos_296)
+		ext_fetch<=0;
+	else if(hpos_400)
+		ext_fetch<=1;
+	end
+
+assign attr_fetch_line=(videoline>=0 && videoline<203);
+
+//--------------------------------------------------------------------------
+// DRAM Refresh
+//--------------------------------------------------------------------------	
+
+always @(posedge clk)											// refresh single clock control
+	begin
+	if(hpos_336)
+		refresh<=0;
+	else if(hpos_296)
+		refresh<=1;
+	end
+
+always @(posedge clk)											// refresh counter increment control
+	begin
+	if(hpos_343)
+		refresh_inc<=0;
+	else if(hpos_303)
+		refresh_inc<=1;
+	end
+
+always @(posedge clk)
+	begin
+		if(single_cycle_end & (refresh_inc|stopreg))
+					refreshcounter<=refreshcounter+1;
+		else	if(hpos_431 & (videoline==0|refresh_inc|stopreg))
+			refreshcounter<=8'h00;
+	end
+
+//-------------------------------------------------------------------------------------------
+// Horizontal counter running on ~8Mhz and vertical counter qualified by horizontal counter
+//-------------------------------------------------------------------------------------------
+
+assign tick8=(phicounter[1:0]==3)?1'b1:1'b0; //8Mhz clock tick for pixelclock. tick8 must activate one fastclk cycle earlier to use it for hcounter 
+
+
+always @(posedge clk)
+	begin
+		hcounter<=hcounter_next;
+		vcounter<=vcounter_next;
+		if(hpos_392)
+			videoline<=vcounter;
+	end
+	
+always @*									//horizontal counter next state logic
+	begin
+	hcounter_next=hcounter;
+		if (tedlatch & addr_in_reg[5:0]==HSCANPOS)								// horizontal counter is written by CPU 
+			begin
+				hcounter_next=hcounter+1;
+				hcounter_next[8:3]=~data_in_reg[7:2];		// bit 0-2 are not modified by user write to prevent clock phase change
+			end
+		else if (tick8 & ~stopreg)
+			begin
+				if (hcounter==9'd455)
+					hcounter_next=9'd0;
+				else
+					hcounter_next=hcounter+1;
+			end
+	end
+
+always @*									//vertical counter next state logic
+	begin
+	vcounter_next=vcounter;
+		if(tedwrite & addr_in[5:1]==5'b01110)								// $ff1c or $ff1d register write (VSCAN HI and LO)
+			begin
+			if(addr_in[0]==0)
+				vcounter_next={data_in[0],vcounter[7:0]};
+			else vcounter_next={vcounter[8],data_in};
+			end
+		else if(inc_vertline_window & single_cycle_end)
+				begin
+					if (vcounter==EOS)
+							vcounter_next=0;
+					else	vcounter_next=vcounter+1;
+				end
+	end
+	
+always @(posedge clk)
+	begin
+	if(hpos_384)
+		inc_vertline_window<=1;
+	else if (single_cycle_end)
+		inc_vertline_window<=0;
+	end
+	
+
+//---------------------------------------------------------------------------
+// Timer 1
+//---------------------------------------------------------------------------
+// timer 1 decrements during odd single clock cycle (phi=0)
+// exact counter change position is unknown but can be estimated based on IRQ place and reading counter values every cycle on a real hardware
+// timer 1 changes approximately at half of phi low cycle after IRQ position (IRQ position is 160ns after phi low cycle start).
+//   
+
+always @(posedge clk)
+	begin
+	if(tedwrite)												// load timer 1 at cycle border
+		begin
+		if (addr_in[5:0]==TIMER1LO)
+			begin
+				timer1[7:0]<=data_in;
+				timer1_reload[7:0]<=data_in;
+				t1stop<=1;
+			end
+		if (addr_in[5:0]==TIMER1HI)
+			begin
+				timer1[15:8]<=data_in;
+				timer1_reload[15:8]<=data_in;
+				t1stop<=0;
+			end
+		end
+	if(phicounter==7 && ~phi & ~t1stop & ~stopreg)			// decrement or reload timer 1
+		begin															
+		if(timer1==0)											
+			timer1<=timer1_reload-1;
+		else
+			timer1<=timer1-1;
+		end
+	end
+	
+//---------------------------------------------------------------------------
+// Timer 2
+//---------------------------------------------------------------------------
+// timer 2 decrements during even single clock cycle (phi=1)
+// timer 2 changes approximately at odd-even single clock cycle boundary (phi low - high transition)
+
+always @(posedge clk)
+	begin
+	if(tedwrite)													// load timer 2 at cycle border
+		begin
+		if (addr_in[5:0]==TIMER2LO)
+			begin
+				timer2[7:0]<=data_in;
+				t2stop<=1;
+			end
+		if (addr_in[5:0]==TIMER2HI)
+			begin
+				timer2[15:8]<=data_in;
+				t2stop<=0;
+			end
+		end
+	else if(phicounter==15 && phi==0 && t2stop==0 && stopreg==0)		// if not loaded, decrement timer 2 at odd-even cycle border
+		begin
+		timer2<=timer2-1;
+		end
+	end
+
+//---------------------------------------------------------------------------
+// Timer 3
+//---------------------------------------------------------------------------
+// timer 3 decrements during even single clock cycle (phi=1)
+// timer 3 changes approximately at half of phi high cycle (contrary to timer 1)
+
+always @(posedge clk)
+	begin
+	if(tedwrite)
+		begin
+		if (addr_in[5:0]==TIMER3LO)							// load timer 3 at cycle border
+			begin
+				timer3[7:0]<=data_in;
+				t3stop<=1;
+			end
+		if (addr_in[5:0]==TIMER3HI)
+			begin
+				timer3[15:8]<=data_in;
+				t3stop<=0;
+			end
+		end
+	if(phicounter==7 && phi==1 && t3stop==0 && stopreg==0)				// decrement timer 3
+		begin
+		timer3<=timer3-1;
+		end
+	end
+	
+//---------------------------------------------------------------------------
+// Timer IRQs
+//---------------------------------------------------------------------------
+//
+
+assign irqpos=(phicounter==4 & ~phi)?1'b1:1'b0;
+
+always @(posedge clk)
+	begin
+	if(resetCnt1Irq)
+		Cnt1Irq<=0;
+	else if(irqpos && timer1==0)
+		Cnt1Irq<=1;
+	end
+	
+always @(posedge clk)
+	begin
+	if(resetCnt2Irq)
+		Cnt2Irq<=0;
+	else if(irqpos && timer2==0)
+		Cnt2Irq<=1;
+	end
+
+always @(posedge clk)
+	begin
+	if(resetCnt3Irq)
+		Cnt3Irq<=0;
+	else if(irqpos && timer3==0) 
+		Cnt3Irq<=1;
+	end
+	
+
+//---------------------------------------------------------------------------
+// Raster IRQ
+//---------------------------------------------------------------------------
+	
+always @(posedge clk)
+	begin
+	if (resetRasterIrq)
+		RasterIrq<=0;
+	else	if (RasterCmp==vcounter)
+		begin
+		if(~RasterIrqDone & tick8)			// do raster interrupt only 1 time per raster line and interrupt happens when phi or dphi is low and about 170ns after cycle start
+			begin
+			RasterIrq<=1;
+			RasterIrqDone<=1;
+			end
+		end
+	else RasterIrqDone<=0;
+	end
+	
+//---------------------------------------------------------------------------
+// IRQ signal
+//---------------------------------------------------------------------------
+ 
+assign irq=~((enCnt1Irq & Cnt1Irq)|(enCnt2Irq & Cnt2Irq)| (enCnt3Irq & Cnt3Irq) | (enRasterIrq & RasterIrq) | (enLPIrq & LPIrq));
+
+//---------------------------------------------------------------------------
+// AEC signal generating
+//---------------------------------------------------------------------------
+
+always @(posedge clk)
+	begin
+		if((singleclock & ~phi) | (dma_state==TDMA))
+			aec<=0;
+		else aec<=1;
+	end
+
+//---------------------------------------------------------------------------
+// BA signal 	(RDY)
+//---------------------------------------------------------------------------
+
+assign ba=(dma_state==IDLE)?1'b1:1'b0;
+
+//---------------------------------------------------------------------------
+// badline
+//---------------------------------------------------------------------------
+
+assign badline=((yscroll_latch==videoline[2:0]) & enabledisplay & attr_fetch_line)?1'b1:1'b0;			// signal 1st badline
+
+always @(posedge clk)
+	begin
+	if(inc_vertline_window & single_cycle_end)
+		begin
+		if(badline)
+			badline2<=1;
+		else if(badline2)
+			badline2<=0;
+		end
+/*	else if(badline & ~hpos_392)							//when yscroll changed to generate badline, abort an already started badline2 (except at start of line)
+		badline2<=0;*/
+	end
+
+always @(posedge clk)										// synchronize yscroll changes to single cycle border
+	begin
+	if(single_cycle_end)
+		yscroll_latch<=yscroll;
+	end
+
+//---------------------------------------------------------------------------
+// EnableDisplay signal
+//---------------------------------------------------------------------------
+
+always @(posedge clk)
+	begin
+	if(videoline==0 && den==1)
+		enabledisplay<=1;
+	if(videoline==204)
+		enabledisplay<=0;
+	end
+
+//---------------------------------------------------------------------------
+// Bitmapmask fetch signal
+//---------------------------------------------------------------------------
+
+always @(posedge clk)					// character fetch window starts at first badline2 and stops at line 204. It signals that character fetches can happen in these lines.
+	begin
+	if(videoline==9'd204)
+		char_fetch<=0;
+	else if(badline2)
+		char_fetch<=1;
+	end
+//----------------------------------------------------------------------------
+// Character Position register $FF1A/$FF1B
+//----------------------------------------------------------------------------
+
+always @(posedge clk)					// character fetch position increase from horizontal count 432 to horizontal count 296
+	begin
+	if(hpos_296)
+		inc_charpos<=0;
+	else if(hpos_432)
+		inc_charpos<=1;
+	end
+
+always @(posedge clk)					// DMA and Charpos latch delay trick
+	begin
+	latch_charposition<=0;
+	if(hpos_288)
+		latch_window<=1;
+	else if(single_cycle_end & latch_window)
+		begin
+		latch_window<=0;
+		latch_charposition<=1;			// 1 FPGA cycle long latch enable signal used for Character position and videocounter position reload latch
+		end
+	end
+
+always @(posedge clk)
+	begin
+	if(latch_charposition)
+		begin
+		if(VertSubCount==6)
+			CharPosLatch<=1;				// CharPosLatch signal activates in line 6 and signals that videocounter (DMA counter) has been latched. It is used in line 7 for character position latch.
+		else 
+			CharPosLatch<=0;
+		end
+	end
+
+always @(posedge clk)					// Character Position Reload register $FF1A/$FF1B
+	begin
+	if(tedwrite & addr_in[5:0]==CHARPOSRELOADHI)
+			CharPosReload[9:8]<=data_in[1:0];
+	else if(tedwrite & addr_in[5:0]==CHARPOSRELOADLO)
+			CharPosReload[7:0]<=data_in;
+	else if(hpos_392 & videoline==EOS)		// clear character position reload at last line
+			CharPosReload<=0;
+	else if(CharPosLatch & latch_charposition & VertSubActive)				// latch character position at 7th line of a character row if videocunter was latched in previous 6th row
+			CharPosReload<=CharPosition;
+	end
+
+always @(posedge clk)									// Character Position counter (not user accessible)
+	begin
+	if(hpos_392)											// clear character position in each line at 392
+		CharPosition<=0;
+	else
+		begin
+		if(hpos_432 & enabledisplay & VertSubActive)										// FIXME this might need delay
+			CharPosition<=CharPosReload;
+		else if(inc_charpos & single_cycle_end)
+			CharPosition<=CharPosition+1;
+		end
+	end
+
+
+//---------------------------------------------------------------------------
+// Attribute fetch (DMA) 
+//---------------------------------------------------------------------------
+// DMA FSM
+
+always @(posedge clk)
+	begin
+	dma_state<=dma_nextstate;
+	end
+
+always @*
+	begin
+	dma_nextstate=dma_state;
+	case(dma_state)
+	IDLE:		begin	
+				if((badline|badline2) & dma_window)
+					dma_nextstate=THALT1;
+				end
+	THALT1:	begin
+				if((badline|badline2) & dma_window & single_cycle_end)
+					dma_nextstate=THALT2;
+				else if (~dma_window | ~(badline|badline2))
+					dma_nextstate=IDLE;
+				end
+	THALT2:	begin
+				if((badline|badline2) & dma_window & single_cycle_end)
+					dma_nextstate=THALT3;
+				else if (~dma_window | ~(badline|badline2))
+					dma_nextstate=IDLE;
+				end
+	THALT3:	begin
+				if((badline|badline2) & dma_window & single_cycle_end)
+					dma_nextstate=TDMA;
+				else if (~dma_window | ~(badline|badline2))
+					dma_nextstate=IDLE;
+				end
+	TDMA:		begin
+				if (~dma_window | ~(badline|badline2))
+					dma_nextstate=IDLE;
+				end
+	default:	dma_nextstate=IDLE;
+	endcase	
+	end
+
+always @(posedge clk)
+	begin
+	if(hpos_407 & tick8)
+		dma_window<=1;
+	else if(hpos_295 & tick8)
+		dma_window<=0;
+	end
+
+
+//-------------
+// Attribute fetch address generation (videocounter is DMA position counter)
+//-------------
+
+always @(posedge clk)				// videocounter increase window				
+	begin
+	if(enabledisplay)
+		begin
+		if(hpos_296 | shiftcount==6'd40)
+			inc_videocounter<=0;
+		else if(hpos_432)
+			inc_videocounter<=1;
+		end
+	end
+
+always @(posedge clk)
+	begin
+	if(hpos_392 & videoline==EOS)	// clear videocounter reload register at last line
+		videocounter_reload<=0;
+	else if(VertSubCount==6 && latch_charposition && VertSubActive)			// Latch videocounter position at 6th line of a character row
+		videocounter_reload<=videocounter;
+	end	
+	
+always @(posedge clk)						// videocounter used for attribute and character pointer fetches (DMA counter)
+	begin
+	if(enabledisplay)
+		begin
+		if(hpos_432)
+			videocounter<=videocounter_reload;
+		else if(inc_videocounter & single_cycle_end)							// increase videocounter at cycle border
+			videocounter<=videocounter+1;
+		end
+	end
+
+//------------------------------------
+// Internal VideoMatrix (DMA buffers)	
+//------------------------------------
+
+	
+always @(posedge clk)
+	begin
+	if(single_cycle_end)
+		begin
+		if(inc_videocounter)
+			begin
+			if(badline)	begin									// in 1st badline fetch attribute from databus and place to buffer's start
+				attr_buf[0]<=data_in;
+				end
+			else begin
+				attr_buf[0]<=attr_buf[39];
+				end
+			for(i=1;i<40;i=i+1) begin
+				attr_buf[i]<=attr_buf[i-1];
+				end
+			nextattr<=attr_buf[39];
+			shiftcount<=shiftcount+1;
+			
+			if(((CursorPos==CharPosition) && VertSubActive) || (CursorPos==0 && CharPosition==0))					// cursor position must be checked here 
+				nextcursor<=1;
+			else nextcursor<=0;
+			
+			end
+		else begin
+			nextattr<=0;
+			shiftcount<=0;
+			end
+		end
+	end
+	
+always @(posedge clk)
+	begin
+	if(single_cycle_end)
+		begin
+		if(inc_videocounter)
+			begin
+			if(badline2) begin
+				char_buf[0]<=data_in;
+				nextchar<=data_in;
+				end
+			else begin
+				char_buf[0]<=char_buf[39];
+				nextchar<=char_buf[39];
+				end
+			for(j=1;j<40;j=j+1) begin
+				char_buf[j]<=char_buf[j-1];
+				end
+			end 	
+		else begin
+			nextchar<=0;
+			end
+		end
+	end
+
+
+always @(posedge clk)							// character window flag is needed for fetching pixel data from bus
+	begin
+	if(hpos_304)
+		char_window<=0;
+	else if(hpos_440 & enabledisplay)
+		char_window<=1;
+	end
+
+always @(posedge clk)								// latch pixel data from data bus at phi0 change from 0 to 1
+	begin
+	if(char_window)
+		begin
+		if(hpos_440)
+			nextpixels<=0;
+		else if(cycle_end & ~phi)
+			nextpixels<=data_in;
+		end
+	end
+
+//---------------------------------------------------------------------------
+// Vertical Sub register represents actual raster line inside character
+//---------------------------------------------------------------------------
+
+always @(posedge clk)
+	begin
+	if(hpos_392)					
+		inc_vertsub_window<=1;
+	else if(single_cycle_end)
+		inc_vertsub_window<=0;
+	
+			
+	if (hpos_380 & badline)													// ... activates at 1st badline of the frame
+		VertSubActive<=1;
+	else if (~enabledisplay)												// ... inactivates at line 204
+		VertSubActive<=0;
+	end
+		
+always @(posedge clk)
+		begin
+			if(tedwrite && addr_in[5:0]==FLASH_VERTSUB)					// if it is written by user
+				VertSubCount<=data_in[2:0];
+			else 
+				if(inc_vertsub_window & single_cycle_end)					// if it is time to change VertSub
+						if (videoline==0)											// ... changes to 7 at line 0 FIXME: between cycle $C8 and $CA
+							VertSubCount<=3'd7;
+						else if(enabledisplay & VertSubActive) 
+							VertSubCount<=VertSubCount+1;					// ... increases between line 0 and 204
+		end
+
+//---------------------------------------------------------------------------
+// Flash counter
+// 5th bit of FlashCount contains flash status and not accessible via FF1F register
+//---------------------------------------------------------------------------
+
+always @(posedge clk)
+	begin
+	if(hpos_348)
+		inc_flashcount_window<=1;
+	else if(single_cycle_end)
+		inc_flashcount_window<=0;
+
+	if(tedwrite && addr_in[5:0]==FLASH_VERTSUB)
+			FlashCount[3:0]<=data_in[6:3];
+	else if(videoline==205 & inc_flashcount_window & single_cycle_end)
+			FlashCount<=FlashCount+1;
+	end
+
+//---------------------------------------------------------------------------
+// Horizontal event decodes
+//---------------------------------------------------------------------------
+
+always @(hcounter)
+	begin
+	hpos_0=0;
+	hpos_8=0;
+	hpos_154=0;
+	hpos_172=0;
+	hpos_288=0;
+	hpos_295=0;
+	hpos_296=0;
+	hpos_303=0;
+	hpos_304=0;
+	hpos_312=0;
+	hpos_320=0;
+	hpos_336=0;
+	hpos_343=0;
+	hpos_348=0;
+	hpos_353=0;
+	hpos_359=0;
+	hpos_380=0;
+	hpos_382=0;
+	hpos_384=0;
+	hpos_391=0;
+	hpos_392=0;
+	hpos_400=0;
+	hpos_407=0;
+	hpos_423=0;
+	hpos_431=0;
+	hpos_432=0;
+	hpos_440=0;
+	case (hcounter)
+				0:		hpos_0=1;				// Start of 40 column screen
+				8:		hpos_8=1;				// Start of 38 column screen
+				154:  hpos_154=1;				// Equalization pulse 1 start
+				172:	hpos_172=1;				// Equalization pulse 1 end
+				288:	hpos_288=1;				//	CharPosition and Videocounter latch position delayed by 1 cycle (starts at 296)
+				295:	hpos_295=1;				// Attribute fetch (DMA) FSM stop
+				296:	hpos_296=1;				// Stop external fetch single clock delayed by 1 cycle
+													// Start refresh singleclock delayed by 1 cycle (actual start at 304)
+				303:	hpos_303=1;				// Start refresh counter increment (304 in real TED)
+				304:  hpos_304=1;				// End of character window
+				312:	hpos_312=1;				// End of 38 column screen
+				320: 	hpos_320=1;				// End of 40 column screen
+				336:  hpos_336=1;				// Stop refresh singleclock but delayed by 2 cycle (actual stop at 344)
+				343:	hpos_343=1;				// Stop refresh counter increment (344 in real TED)
+				348:	hpos_348=1;				// Flash (blink) counter increment point delayed by 2 cycles (increments at 352)
+				353:	hpos_353=1;				// Horizontal blanking start
+				359:	hpos_359=1;				// Horizontal sync start (358 in real TED however line change takes time thus the delay)				
+				380:	hpos_380=1;
+				382:	hpos_382=1;				// Equalization pulse 2 start
+				384:	hpos_384=1;				// End Of Screen. Clear vertical line,refresh counters and character reload register, increase vertical line after 1 cycle delay
+				391: 	hpos_391=1;	
+				392:	hpos_392=1;				// VertSub register increment (delayed), Hsync end
+				400:  hpos_400=1;				// Start external fetch single clock (delayed), Equalization pulse 2 end
+				407:	hpos_407=1;				// Attribute fetch (DMA) FSM start
+				423:	hpos_423=1;				// Horizontal blanking stop
+				431:	hpos_431=1;				// Refresh counter reset point
+				432:	hpos_432=1;				// Start videocounter increment
+				440:  hpos_440=1;				// Start video shiftregister
+	endcase				
+end
+
+//---------------------------------------------------------------------------
+// Border control
+//---------------------------------------------------------------------------
+
+always @(posedge clk)									// 25/24 row select and top/bottom borders
+	begin
+		if(rsel==1) begin
+			if(videoline==9'd4)					// if 25 rows mode, screen starts at line 4
+				verticalscreen<=1;
+			else if (videoline==9'd204)			// stops at line 204
+				verticalscreen<=0;
+		 end
+		else begin
+			if(videoline==9'd8)					// if 24 rows mode, screen starts at line 8
+				verticalscreen<=1;
+			else if(videoline==9'd200)			// stops at line 200
+				verticalscreen<=0;
+		end
+	end
+
+always @(posedge clk)									// 38/40 columns select and side borders
+	begin
+		if(enabledisplay & verticalscreen) 
+			begin 
+				if(hpos_320 & tick8)
+					widescreen<=0;
+				else if (hpos_0 & tick8)
+					widescreen<=1;
+				if(hpos_312 & tick8)
+					narrowscreen<=0;
+				else if (hpos_8 & tick8)
+					narrowscreen<=1;
+			end
+	end
+
+	
+
+
+//---------------------------------------------------------------------------
+// VideoShift Register	
+//---------------------------------------------------------------------------
+	
+always @(posedge clk)
+	begin
+	if (hpos_312)
+		videoshift<=0;
+	else if(enabledisplay & hpos_440)
+		videoshift<=1;
+	end
+
+always @(posedge clk)						// video shift register stores fetched video data until pixelshiftregister is loaded
+	begin
+	if(hpos_440)
+		begin
+		waitingattr<=0;
+		waitingchar<=0;
+		waitingpixels<=0;
+		currentattr<=0;
+		currentchar<=0;
+		currentpixels<=0;
+		end
+	else if(cycle_end & videoshift)
+		begin
+		if(phi)
+			begin
+			currentchar<=nextchar;
+			waitingchar<=currentchar;
+			currentattr<=nextattr;
+			waitingattr<=currentattr;
+			waitingpixels<=currentpixels;
+			currentcursor<=nextcursor;
+			waitingcursor<=currentcursor;
+			end
+		else if(~phi)
+			currentpixels<=nextpixels;
+		end
+	end
+	
+assign cursor=(waitingcursor & ~FlashCount[4]);
+
+//---------------------------------------------------------------------------
+// Pixel Generator
+// Final screen is delayed by 2 pixels 
+//---------------------------------------------------------------------------
+always @(posedge clk)										// synchronize xscroll and display mode changes to single cycle border
+	begin
+	if (single_cycle_end)
+		begin
+		xscroll_latch<=xscroll;
+		ecm<=ecm_reg;
+		bmm<=bmm_reg;
+		reverse<=reverse_reg;
+		mcm<=mcm_reg;
+		end
+	end
+
+always @(posedge clk)										// video pixel shift tregister
+	begin
+	if(videoshift | widescreen)												// shift register works only when beam is on wide screen area
+		begin
+		if(tick8)									
+			begin
+				doubleshift<=~doubleshift;
+				if(hcounter[2:0] == xscroll_latch)				// load register based on xscroll
+					begin
+					doubleshift<=0;
+					if(cursor & ~bmm & ~ecm & ~mcm)		// when character is at cursor position and in Standard Character mode, load the invert of character mask
+						pixelshiftreg<=waitingpixels^8'hFF;
+					else pixelshiftreg<=waitingpixels;
+					pixelattr<=waitingattr;					// latch attribute and charpointer for pixelgenerator
+					pixelchar<=waitingchar;
+					end
+				else
+					begin
+					if(~multicolor)
+						pixelshiftreg<={pixelshiftreg[6:0],1'b0};
+					else if(doubleshift)											// double pixel shifting
+						pixelshiftreg<={pixelshiftreg[5:0],2'b0};
+					end
+			end
+		end
+	else pixelshiftreg<=0;									// clear shiftreg at the end of screen line to avoid shifting in its content at next line		
+	end
+
+
+assign pixelscreen=(csel)?widescreen:narrowscreen;					// change between narrow and wide screens plus 1 pixel delay due to latch
+
+
+assign multicolor= mcm & (ecm | pixelattr[3] | bmm);			// multicolor rendering is initiated when mcm=1 and either ecm,bmm or character attribute's 4th bit is 1
+
+
+always @*									// video pixel color generator
+	begin
+	pixelcolor=bgcolor0;
+	if(pixelscreen & enabledisplay)
+		begin
+			if (~bmm & ~ecm) 				// Standard and Multicolor Character modes
+				begin
+				if(~multicolor)					// Standard Character mode
+					begin
+					if((reverse|mcm)?pixelshiftreg[7]:(pixelshiftreg[7]& ~(pixelattr[7] & FlashCount[4]))^pixelchar[7])
+						pixelcolor=pixelattr[6:0];
+					end
+				else 
+					begin						// Multicolor Character mode
+						case(pixelshiftreg[7:6])
+							2'b00:	pixelcolor=bgcolor0;
+							2'b01:	pixelcolor=bgcolor1;
+							2'b10:	pixelcolor=bgcolor2;
+							2'b11:	pixelcolor={pixelattr[6:4],1'b0,pixelattr[2:0]};
+						endcase
+					end				
+				end
+			else if (~mcm & ~bmm & ecm)		// Extended Color Character mode
+				begin
+					if(pixelshiftreg[7])
+						pixelcolor=pixelattr[6:0];
+					else begin
+						case(pixelchar[7:6])
+							2'b00:	pixelcolor=bgcolor0;
+							2'b01:	pixelcolor=bgcolor1;
+							2'b10:	pixelcolor=bgcolor2;
+							2'b11:	pixelcolor=bgcolor3;
+						endcase
+					end	
+				end
+			else if(~mcm & bmm & ~ecm)			// Standard Bitmap mode
+				begin
+				if(pixelshiftreg[7])
+					pixelcolor={pixelattr[2:0],pixelchar[7:4]};
+				else pixelcolor={pixelattr[6:4],pixelchar[3:0]};
+				end
+			else if(mcm & bmm & ~ecm)		 // Multicolor bitmap mode
+				begin
+				case(pixelshiftreg[7:6])
+							2'b00:	pixelcolor=bgcolor0;
+							2'b01:	pixelcolor={pixelattr[2:0],pixelchar[7:4]};
+							2'b10:	pixelcolor={pixelattr[6:4],pixelchar[3:0]};
+							2'b11:	pixelcolor=bgcolor1;
+						endcase
+				end
+			else										// invalid mode
+				begin
+				pixelcolor=7'b0;
+				end
+		end
+	else
+			pixelcolor=excolor;
+	end
+
+always @(posedge clk)						// latch pixelcolor and multiplex it with blank signal
+	begin
+	if (tick8)
+		if(~blanking)
+		colorreg<=pixelcolor;
+		else colorreg<=0;
+	end
+
+
+//---------------------------------------------------------------------------
+// Screen signals generation
+//---------------------------------------------------------------------------
+	
+// PAL/NTSC screen constants 
+assign pal = !palreg;
+
+assign EOS = pal?9'd311:9'd261;					// End of Screen scanline
+assign VS_START = pal?9'd254:9'd229;			// Vertical sync start
+assign VS_STOP = pal?9'd257:9'd232; 			// Vertical sync stop 
+assign EQ_START = pal?9'd251:9'd226;			// Equalization start
+assign EQ_STOP = pal?9'd260:9'd235;				// Equalization stop
+assign VBLANK_START = pal?9'd251:9'd226; 		// Screen blanking start
+assign VBLANK_STOP = pal?9'd269:9'd244;		// Screen blanking stop// Composite Sync signal
+
+always @(posedge clk)								// composite synchron is either hsync or equalization+vsync
+	begin
+	csyncreg<=(equalization)?(eq1&eq2)^vsync:hsync;
+	end
+
+always @(posedge clk)								// vsync signal inverts equalization signal
+	begin
+	if (videoline==VS_START && hpos_400)
+		vsync<=1;
+	else if (videoline==VS_STOP && hpos_400)
+		vsync<=0;
+	end
+
+always @(posedge clk)								// equalization signal active during actual vsync+equalization window
+	begin
+	if(videoline==EQ_START && hpos_400)
+		equalization<=1;
+	else if (videoline==EQ_STOP && hpos_400)
+		equalization<=0;
+	end
+
+always @(posedge clk)								// Equalization pulses generated by horizontal decoder events
+	begin
+	if(hpos_154)
+		eq1<=0;
+	else if (hpos_172)
+		eq1<=1;
+	if(hpos_382)
+		eq2<=0;
+	else if (hpos_400)
+		eq2<=1;
+	end
+	
+always @(posedge clk)								//	Horizontal sync pulse (due to original HMOS technology signal change takes 2 pixels long thus these change positions differ from the specification)
+	begin
+	if(hpos_359)
+		hsync<=0;
+	else if (hpos_391)
+		hsync<=1;
+	end
+
+always @(posedge clk)							// horizontal blanking zone
+	begin
+	if(hpos_423)										
+		hblank<=0;
+	else if(hpos_353)								// in real TED it starts at 352 but slew rate takes 2 pixels. 353 is at halfway. FIXME: Might be initiated at 344.
+		hblank<=1;
+	end
+
+always @(posedge clk)							// vertical blanking zone
+	begin
+	if(videoline==VBLANK_STOP)
+		vblank<=0;
+	else if(videoline==VBLANK_START)
+		vblank<=1;
+	end
+
+assign blanking=hblank|vblank;
+assign csync=csyncreg;
+assign color=colorreg;
+
+//-----------------------------------------------------------------------------------------------
+// Memory Controller
+//-----------------------------------------------------------------------------------------------
+
+always @(posedge clk)		// Generating RAS, internal CAS and MUX signals based on clk28 cycle numbers. Not 100% precise reproduction of original TED timing but still in dram specifications
+	case (phicounter)			// one clk28 cycle is 35.35ns
+	1:		begin	
+			ras<=1;
+			cas<=1;
+			mux<=1;
+			cs0<=1;
+			cs1<=1;
+			end
+	6: 	ras<=0;				// RAS goes low 35ns before MUX (20ns on real system)
+	7:		begin
+			mux<=0;				// MUX goes low when double phi changes to high at half double clock cycle, CS0,CS1 changes together with MUX when needed
+			if(rw)				// CS0,CS1 generation only on read cycles
+				begin
+				if((~ramen & ~dotfetch_reg) | (charrom & dotfetch_reg ))		// ROM chip select is controlled by ramen register or by charrom register depending on whether dot data is fetched from bus
+					begin
+					if(lowrom)	// Basic area
+						cs0<=0;
+					if(highrom & ~io & ~tedreg)	// Kernal area
+						cs1<=0;
+					end
+				end
+			end
+// TH: relax write timing a little bit
+//	8:		if (rw & cs0 & cs1 & ~io & ~tedreg)				// when read cycle, CAS goes low 35ns after MUX (40ns on real system)
+//				cas<=0;
+//	11:	if (~rw & ~io & ~tedreg)								// when write cycle, CAS goes low 160ns after MUX
+//				cas<=0;
+	8:		if ((rw & cs0 & cs1 & ~io & ~tedreg) || (~rw & ~io & ~tedreg))
+				cas<=0;
+				
+	default: 					// otherwise they don't change
+			begin
+			ras<=ras;
+			mux<=mux;
+			cas<=cas;
+			cs0<=cs0;
+			cs1<=cs1;
+			end
+	endcase
+
+
+// Generating memory area flags. 
+
+assign lowrom=(addr_in[15:14]==2'b10)?1'b1:1'b0;								//$8000-$bfff		low rom area (Basic)
+assign highrom=(addr_in[15:14]==2'b11)?1'b1:1'b0;								//$c000-$ffff		high rom area (Kernal, IO and TED area)
+assign io=(addr_in[15:8]==8'hFD || addr_in[15:8]==8'hFE)?1'b1:1'b0;		//$fd00-$feff		IO space
+assign tedreg=(addr_in[15:6]==10'b1111111100 && (addr_in[5]==0 || addr_in[5:1]==7'b11111))?1'b1:1'b0;						//$ff00-$ff1f  & $ff3e-$ff3f		TED registers
+
+//-----------------------------------------------------------------------------------------------
+// Generating TED address out
+//-----------------------------------------------------------------------------------------------
+
+assign addr_out=(~aec)?addr_out_reg:16'hffff;
+
+always @(posedge clk)
+	begin
+		if(cycle_end)
+			begin
+			addr_out_reg<=tedaddress;
+			dotfetch_reg<=dotfetch;
+			end
+	end
+
+assign charpointer=(inc_videocounter)?((badline2)?data_in:char_buf[39]):0;	
+assign attrpointer=attr_buf[39];
+	
+always @*
+	begin
+	tedaddress=16'hffff;
+	dotfetch=0;
+	if(phi==0)						// generating address for phi1 phase (will be clocked and valid in phi1)
+		begin
+		if(dma_state==TDMA)
+			tedaddress={vmbase,(badline)?1'b0:1'b1,videocounter};				// attribute or character pointer fetch address
+		end
+	else if(~test)	
+		begin						 // generating address for phi0 phase (will be clocked and valid in phi0)
+		if(refresh_inc|stopreg)				// dram refresh address
+			tedaddress={8'hff,refreshcounter};
+		else if(inc_charpos & char_fetch)
+			begin
+			dotfetch=1;
+			if(~bmm)				// Text mode fetch address
+				begin
+				tedaddress=(~reverse)?{charbase[5:0],charpointer[6:0],VertSubCount}:{charbase[5:1],charpointer,VertSubCount};
+				tedaddress[10:9]=(ecm)?2'b00:tedaddress[10:9];
+				end
+			else
+				tedaddress={bmapbase,CharPosition,VertSubCount};	// bitmap mode fetch address
+			end
+		end
+	else begin					// IC test mode fetch addresses
+			dotfetch=1;
+			if(~bmm)
+				tedaddress={5'hF8,attrpointer,VertSubCount};				// test mode character screen
+			else tedaddress={3'b111,(CharPosition && {2'b11,attrpointer}),VertSubCount};
+			end
+	end
+
+//-----------------------------------------------------------------------------------------------
+// TED registers write
+//-----------------------------------------------------------------------------------------------
+
+assign tedwrite=tedreg&~rw&cycle_end;		// It signals TED register write which happens always when rw is low and end of double clock cycle
+assign tedlatch=tedwrite_delay & (phicounter==3);		// trying to simulate when exactly the hcounter is written by TED
+
+always @(posedge clk)
+	begin
+		if(tedwrite)
+			tedwrite_delay<=1;
+		else if (phicounter==3)
+			tedwrite_delay<=0;
+	end
+
+always @(posedge clk)
+	begin
+	resetRasterIrq<=1'b0;
+	resetLpIrq<=1'b0;
+	resetCnt1Irq<=1'b0;
+	resetCnt2Irq<=1'b0;
+	resetCnt3Irq<=1'b0;
+	if (tedwrite)											// when TED registers are addressed		
+		begin
+		data_in_reg<=data_in;
+		addr_in_reg<=addr_in[5:0];
+			case(addr_in[5:0])
+				CONTROL1:	// $FF06	
+							begin
+							test<=data_in[7];
+							ecm_reg<=data_in[6];
+							bmm_reg<=data_in[5];
+							den<=data_in[4];
+							rsel<=data_in[3];
+							yscroll<=data_in[2:0];
+							end
+				CONTROL2:	// $FF07
+							begin
+							reverse_reg<=data_in[7];
+							palreg<=data_in[6];
+							stop<=data_in[5];
+							mcm_reg<=data_in[4];
+							csel<=data_in[3];
+							xscroll<=data_in[2:0];
+							end
+				KEYLATCH:	// $FF08
+							keylatch<=k[7:0];
+				IRQ:			// $FF09
+							begin
+							resetCnt3Irq<=data_in[6];
+							resetCnt2Irq<=data_in[4];
+							resetCnt1Irq<=data_in[3];
+							resetLpIrq<=data_in[2];
+							resetRasterIrq<=data_in[1];
+							end
+				IRQEN:		// $FF0A
+							begin
+							enCnt3Irq<=data_in[6];
+							enCnt2Irq<=data_in[4];
+							enCnt1Irq<=data_in[3];
+							enRasterIrq<=data_in[1];
+							RasterCmp[8]<=data_in[0];
+							end
+				RASTER:		// $FF0B
+							RasterCmp[7:0]<=data_in;
+				CURPOSHI:	// $FF0C
+							CursorPos[9:8]<=data_in[1:0];
+				CURPOSLO:	// $FF0D
+							CursorPos[7:0]<=data_in;
+				CH1FREQLO:	// $FF0E
+							Ch1Freq[7:0]<=data_in;
+				CH2FREQLO:	// $FF0F
+							Ch2Freq[7:0]<=data_in;
+				CH2FREQHI:	// $FF10
+							Ch2Freq[9:8]<=data_in[1:0];
+				SOUNDCTRL:	// $FF11
+							begin
+							damode<=data_in[7];
+							ch2noise<=data_in[6];
+							ch2en<=data_in[5];
+							ch1en<=data_in[4];
+							volume<=data_in[3:0];
+							end
+				BMAPBASE:	// $FF12
+							begin
+							bmapbase<=data_in[5:3];
+							charrom<=data_in[2];
+							Ch1Freq[9:8]<=data_in[1:0];
+							end
+				CHARBASE:	// $FF13
+							begin
+							charbase<=data_in[7:2];
+							clkmode<=data_in[1];
+							end
+				VIDEOBASE:	// $FF14
+							vmbase<=data_in[7:3];
+				BGCOLOR0:	// $FF15 , color change at cycle start, emulating white pixel bug (for all 5 color registers)
+							bgcolor0<=8'hff;
+				BGCOLOR1:	// $FF16
+							bgcolor1<=8'hff;
+				BGCOLOR2:	// $FF17
+							bgcolor2<=8'hff;
+				BGCOLOR3:	// $FF18
+							bgcolor3<=8'hff;
+				EXCOLOR:		// $FF19
+							excolor<=8'hff;
+				ROMEN:		ramen<=1'b0;
+				RAMEN:		ramen<=1'b1;
+				default:;
+			endcase
+		end
+									    // Color registers write (white pixel bug emulation)
+	else if (tedlatch)			// these events happen 1 pixel later after cycle start, setting the proper color to color registers
+		case(addr_in_reg[5:0])
+				BGCOLOR0:	// $FF15
+							bgcolor0<=data_in_reg[6:0];
+				BGCOLOR1:	// $FF16
+							bgcolor1<=data_in_reg[6:0];
+				BGCOLOR2:	// $FF17
+							bgcolor2<=data_in_reg[6:0];
+				BGCOLOR3:	// $FF18
+							bgcolor3<=data_in_reg[6:0];
+				EXCOLOR:		// $FF19
+							excolor<=data_in_reg[6:0];
+				default:;
+		endcase
+	end
+
+// TED register read
+
+always @(posedge clk)
+	begin
+	if(tedreg & rw)
+		begin
+		if(phicounter==7)										// latch register contents to dataout reg at mux change
+			begin
+				case(addr_in[5:0])
+				TIMER1LO:	// $FF00
+							dataout_reg<=timer1[7:0];
+				TIMER1HI:	// $FF01
+							dataout_reg<=timer1[15:8];
+				TIMER2LO:	// $FF02
+							dataout_reg<=timer2[7:0];
+				TIMER2HI:	// $FF03
+							dataout_reg<=timer2[15:8];
+				TIMER3LO:	// $FF04
+							dataout_reg<=timer3[7:0];
+				TIMER3HI:	// $FF05
+							dataout_reg<=timer3[15:8];
+				CONTROL1:	// $FF06
+							begin
+							dataout_reg[7]<=test;
+							dataout_reg[6]<=ecm;
+							dataout_reg[5]<=bmm;
+							dataout_reg[4]<=den;
+							dataout_reg[3]<=rsel;
+							dataout_reg[2:0]<=yscroll;
+							end
+				CONTROL2:	// $FF07
+							begin
+							dataout_reg[7]<=reverse;
+							dataout_reg[6]<=palreg;
+							dataout_reg[5]<=stop;
+							dataout_reg[4]<=mcm;
+							dataout_reg[3]<=csel;
+							dataout_reg[2:0]<=xscroll;
+							end
+				KEYLATCH:	// $FF08
+							begin
+							dataout_reg<=keylatch;
+							end
+				
+				IRQ:			// $FF09		
+							begin
+							dataout_reg[7]<=~irq;
+							dataout_reg[6]<=Cnt3Irq;
+							dataout_reg[4]<=Cnt2Irq;
+							dataout_reg[3]<=Cnt1Irq;
+							dataout_reg[2]<=LPIrq;			// Lightpen irq is always 1 as it is not implemented in TED
+							dataout_reg[1]<=RasterIrq;
+							end
+				IRQEN:		// $FF0A
+							begin
+							dataout_reg[6]<=enCnt3Irq;
+							dataout_reg[4]<=enCnt2Irq;
+							dataout_reg[3]<=enCnt1Irq;
+							dataout_reg[2]<=enLPIrq;			// lightpen irq enable bit is implemented in TED
+							dataout_reg[1]<=enRasterIrq;
+							dataout_reg[0]<=RasterCmp[8];
+							end
+				RASTER:		// $FF0B
+							dataout_reg<=RasterCmp[7:0];
+				CURPOSHI:	// $FF0C
+							dataout_reg[1:0]<=CursorPos[9:8];
+				CURPOSLO:	// $FF0D
+							dataout_reg<=CursorPos[7:0];
+				CH1FREQLO:	// $FF0E
+							dataout_reg<=Ch1Freq[7:0];
+				CH2FREQLO:	// $FF0F
+							dataout_reg<=Ch2Freq[7:0];
+				CH2FREQHI:	// $FF10
+							begin
+							dataout_reg[7]<=1'b0;				// the 8th unused bit is always 0
+							dataout_reg[1:0]<=Ch2Freq[9:8];
+							end
+				SOUNDCTRL: //$FF11
+							begin
+							dataout_reg[7]<=damode;
+							dataout_reg[6]<=ch2noise;
+							dataout_reg[5]<=ch2en;
+							dataout_reg[4]<=ch1en;
+							dataout_reg[3:0]<=volume;
+							end
+				BMAPBASE:  // $FF12
+							begin
+							dataout_reg[5:3]<=bmapbase;
+							dataout_reg[2]<=charrom;
+							dataout_reg[1:0]<=Ch1Freq[9:8];
+							end
+				CHARBASE:  // $FF13
+							begin
+							dataout_reg[7:2]<=charbase;
+							dataout_reg[1]<=clkmode;
+							dataout_reg[0]<=~ramen;
+							end
+				VIDEOBASE: // $FF14
+							dataout_reg[7:3]<=vmbase;
+				BGCOLOR0: // $FF15
+							dataout_reg[6:0]<=bgcolor0;
+				BGCOLOR1: // $FF16
+							dataout_reg[6:0]<=bgcolor1;
+				BGCOLOR2: // $FF17
+							dataout_reg[6:0]<=bgcolor2;
+				BGCOLOR3: // $FF18
+							dataout_reg[6:0]<=bgcolor3;
+				EXCOLOR: // $FF19
+							dataout_reg[6:0]<=excolor;
+				CHARPOSRELOADHI: //$FF1A
+							dataout_reg[1:0]<=CharPosReload[9:8];
+				CHARPOSRELOADLO: //$FF1B
+							dataout_reg<=CharPosReload[7:0];
+				VSCANPOSHI:	// $FF1C
+							dataout_reg[0]<=vcounter[8];
+				VSCANPOSLO: // $FF1D
+							dataout_reg<=vcounter[7:0];
+				HSCANPOS:	// $FF1E
+							dataout_reg<={hcounter[8:2],1'b0};
+				FLASH_VERTSUB: //$FF1F
+							begin
+							dataout_reg[6:3]<=FlashCount[3:0];
+							dataout_reg[2:0]<=VertSubCount;
+							end
+				ROMEN:	// $FF3E
+							dataout_reg<=8'h00;
+				RAMEN:	// $FF3F
+							dataout_reg<=8'h00;
+				default:;
+				endcase
+			end
+		else if(phicounter==10)								// put dataout register content to databus at this moment
+			datahold<=1;
+		end
+	if(phicounter==1)
+		begin
+		datahold<=0;
+		dataout_reg<=8'hff;
+		end
+	end
+
+assign data_out=(datahold)?dataout_reg:8'hff;
+
+//--------------------------------------------------------------------------------
+// TED audio generator
+//--------------------------------------------------------------------------------
+
+assign snd=(ch1audio&ch1pwm)|(ch2audio&ch2pwm);		// mixing audio channel signals
+
+
+always @(posedge clk)						//	audio cycle counter divides single clock by 4
+	begin
+	if(single_cycle_end)
+		audiocycle<=audiocycle+1;
+	end
+
+assign ch1clk=single_cycle_end&(audiocycle==2'b11);		// Channel1 clock 
+assign ch2clk=single_cycle_end&(audiocycle==2'b01);		// Channel2 clock
+
+// Channel 1
+
+always @(posedge clk)
+	begin
+	if(ch1clk)
+		begin
+		if((ch1count==10'h3ff) || damode)
+			ch1count<=Ch1Freq+1;
+		else	ch1count<=ch1count+1;
+		end
+	end
+
+assign ch1stateclk=(ch1count==10'h3ff)?1'b1:1'b0;
+
+always @(posedge clk)	// Channel 1 state clock rising edge detection 
+	begin
+	ch1stateclk_prev<=ch1stateclk;
+	if(damode|watchdog_ch1max)							// reset ch1state if damode is enabled or watchdog timer expires
+		ch1state<=0;
+	else if(~ch1stateclk_prev & ch1stateclk)		// if rising edge
+				ch1state<=~ch1state;						// change channel 1 state
+	end
+	
+assign ch1audio=(ch1en)?~ch1state:1'b0;		// ch1audio before D/A conversion
+
+always @(posedge clk)									// emulating dynamic latch behaviour using watchdog timer (forgets setting after 188416 * audio clock cycles)
+	begin
+	if((~ch1stateclk_prev & ch1stateclk)|watchdog_ch1max)		// reset watchdog timer at channel1 state change or when maximum time reached
+		watchdog_ch1<=0;
+	else if(ch1clk)										// watchdog timer counts with audio clock cycles
+		watchdog_ch1<=watchdog_ch1+1;
+	end
+
+assign watchdog_ch1max=(watchdog_ch1==18'd188416)?1'b1:1'b0;	
+
+// Channel 2
+
+always @(posedge clk)
+	begin
+	if(ch2clk)
+		begin
+		if((ch2count==10'h3ff) || damode)
+			ch2count<=Ch2Freq+1;
+		else	ch2count<=ch2count+1;
+		end
+	end
+
+assign ch2stateclk=(ch2count==10'h3ff)?1'b1:1'b0;
+
+always @(posedge clk)	// Channel 2 state clock rising edge detection 
+	begin
+	ch2stateclk_prev<=ch2stateclk;
+	if(damode)												// reset ch2state if damode is enabled
+		ch2state<=0;
+	else if(~ch2stateclk_prev & ch2stateclk)		// if rising edge
+				ch2state<=~ch2state;						// change channel 2 state
+	end
+	
+assign ch2audio=(ch2en)?~ch2state:noise;		// ch2audio combined with noise before D/A conversion
+
+always @(posedge clk)									// emulating dynamic latch behaviour using watchdog timer (forgets setting after 188416 * audio clock cycles)
+	begin
+	if((~ch2stateclk_prev & ch2stateclk)|watchdog_ch2max)		// reset watchdog timer at channel1 state change or when maximum time reached
+		watchdog_ch2<=0;
+	else if(ch2clk)										// watchdog timer counts with audio clock cycles
+		watchdog_ch2<=watchdog_ch2+1;
+	end
+
+assign watchdog_ch2max=(watchdog_ch2==18'd188416)?1'b1:1'b0;	
+
+
+// Noise generator
+
+always @(posedge clk)
+	begin
+	if(damode)
+		noisegen<=0;
+	else if(~ch2stateclk_prev & ch2stateclk)
+		begin
+		for(n=1;n<8;n=n+1)
+			begin
+			noisegen[n]<=noisegen[n-1];
+			end
+		noisegen[0]<=1^noisegen[7]^noisegen[5]^noisegen[4]^noisegen[1];
+		end
+	end
+
+assign noise=(ch2noise)?noisegen[0]:1'b0;		// noise signal
+
+// D/A converter
+
+always @*								// volume value conversion to pwmcounter numbers where PWM signal high value starts
+	begin
+	case (volume)
+		0:		digivolume=31;
+		1:		digivolume=30;
+		2:		digivolume=28;
+		3:		digivolume=26;
+		4:		digivolume=24;
+		5:		digivolume=22;
+		6:		digivolume=20;
+		7:		digivolume=18;
+		8:		digivolume=16;
+		default:	digivolume=16;
+	endcase
+	end
+
+always @(posedge clk)					// generating PWM pulses for channel1
+	begin
+	if(tick8)
+		begin
+		if(ch1clk)							// synchronizing channel1 PWM signal to channel1 audio 
+			pwmcounter1<=0;
+		else pwmcounter1<=pwmcounter1+1;
+		
+		if ( pwmcounter1 < digivolume || pwmcounter1==31 )		// set pwm signal duty cycle based on modified volume value
+				ch1pwm<=0;
+		else	ch1pwm<=1;
+		end
+	end
+
+always @(posedge clk)					// generating PWM pulses for channel2
+	begin
+	if(tick8)
+		begin
+		if(ch2clk)							// synchronizing channel2 PWM signal to channel2 audio (it is shifted by 2 single clock cycles compared to channel1)
+			pwmcounter2<=0;
+		else pwmcounter2<=pwmcounter2+1;
+		
+		if ( pwmcounter2 < digivolume || pwmcounter2==31 )		// set pwm signal duty cycle based on modified volume value
+				ch2pwm<=0;
+		else	ch2pwm<=1;
+		end
+	end
+	
+endmodule
\ No newline at end of file
diff --git a/cores/c16/user_io.v b/cores/c16/user_io.v
new file mode 100644
index 0000000..e679e00
--- /dev/null
+++ b/cores/c16/user_io.v
@@ -0,0 +1,418 @@
+//
+// user_io.v - interface to MIST arm io controller
+//
+// Sinclair QL for the MiST
+// https://github.com/mist-devel
+// 
+// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
+// 
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or 
+// (at your option) any later version. 
+// 
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of 
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License 
+// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
+//
+
+// parameter STRLEN and the actual length of conf_str have to match
+ 
+module user_io #(parameter STRLEN=0) (
+	input [(8*STRLEN)-1:0] conf_str,
+
+	input      		SPI_CLK,
+	input      		SPI_SS_IO,
+	output     		reg SPI_MISO,
+	input      		SPI_MOSI,
+	
+	output reg [7:0] 	joystick_0,
+	output reg [7:0] 	joystick_1,
+	output reg [15:0] joystick_analog_0,
+	output reg [15:0] joystick_analog_1,
+	output [1:0] 		buttons,
+	output [1:0] 		switches,
+	output  				scandoubler_disable,
+
+	output reg [7:0]   status,
+
+	// connection to sd card emulation
+	input [31:0]  sd_lba,
+	input         sd_rd,
+	input         sd_wr,
+	output reg	  sd_ack,
+	input         sd_conf,
+	input         sd_sdhc,
+	output [7:0]  sd_dout,  // valid on rising edge of sd_dout_strobe
+	output reg	  sd_dout_strobe,
+	input [7:0]   sd_din,
+	output reg 	  sd_din_strobe,
+	output reg    sd_change,
+
+	// ps2 keyboard emulation
+	input 	  		ps2_clk,				// 12-16khz provided by core
+	output	 		ps2_kbd_clk,
+	output reg 		ps2_kbd_data,
+	output	 		ps2_mouse_clk,
+	output reg 		ps2_mouse_data,
+
+	// serial com port 
+	input [7:0]		serial_data,
+	input				serial_strobe
+);
+
+reg [6:0]         sbuf;
+reg [7:0]         cmd;
+reg [2:0] 	      bit_cnt;    // counts bits 0-7 0-7 ...
+reg [7:0]         byte_cnt;   // counts bytes
+reg [5:0]         joystick0;
+reg [5:0]         joystick1;
+reg [7:0] 	      but_sw;
+reg [2:0]         stick_idx;
+
+assign buttons = but_sw[1:0];
+assign switches = but_sw[3:2];
+assign scandoubler_disable = but_sw[4];
+assign sd_dout = { sbuf, SPI_MOSI};
+
+// this variant of user_io is for 8 bit cores (type == a4) only
+wire [7:0] core_type = 8'ha4;
+
+// command byte read by the io controller
+wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
+
+// filter spi clock. the 8 bit gate delay is ~2.5ns in total
+wire [7:0] spi_sck_D = { spi_sck_D[6:0], SPI_CLK } /* synthesis keep */;
+wire spi_sck = (spi_sck && spi_sck_D != 8'h00) || (!spi_sck && spi_sck_D == 8'hff);
+
+// drive MISO only when transmitting core id
+always@(negedge spi_sck or posedge SPI_SS_IO) begin
+	if(SPI_SS_IO == 1) begin
+	   SPI_MISO <= 1'bZ;
+	end else begin
+
+		// first byte returned is always core type, further bytes are 
+		// command dependent
+      if(byte_cnt == 0) begin
+		  SPI_MISO <= core_type[~bit_cnt];
+
+		end else begin
+			// reading serial fifo
+		   if(cmd == 8'h1b) begin
+				// send alternating flag byte and data
+				if(byte_cnt[0]) 	SPI_MISO <= serial_out_status[~bit_cnt];
+				else					SPI_MISO <= serial_out_byte[~bit_cnt];
+			end
+			
+			// reading config string
+		   else if(cmd == 8'h14) begin
+				// returning a byte from string
+				if(byte_cnt < STRLEN + 1)
+					SPI_MISO <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
+				else
+					SPI_MISO <= 1'b0;
+			end
+			
+			// reading sd card status
+		   else if(cmd == 8'h16) begin
+				if(byte_cnt == 1)
+					SPI_MISO <= sd_cmd[~bit_cnt];
+				else if((byte_cnt >= 2) && (byte_cnt < 6))
+					SPI_MISO <= sd_lba[{5-byte_cnt, ~bit_cnt}];
+				else
+					SPI_MISO <= 1'b0;
+			end
+			
+			// reading sd card write data
+		   else if(cmd == 8'h18)
+				SPI_MISO <= sd_din[~bit_cnt];
+				
+			else
+				SPI_MISO <= 1'b0;
+		end
+   end
+end
+
+// ---------------- PS2 ---------------------
+
+// 8 byte fifos to store ps2 bytes
+localparam PS2_FIFO_BITS = 3;
+
+// keyboard
+reg [7:0] ps2_kbd_fifo [(2**PS2_FIFO_BITS)-1:0];
+reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
+reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
+
+// ps2 transmitter state machine
+reg [3:0] ps2_kbd_tx_state;
+reg [7:0] ps2_kbd_tx_byte;
+reg ps2_kbd_parity;
+
+assign ps2_kbd_clk = ps2_clk || (ps2_kbd_tx_state == 0);
+
+// ps2 transmitter
+// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
+reg ps2_kbd_r_inc;
+always@(posedge ps2_clk) begin
+	ps2_kbd_r_inc <= 1'b0;
+	
+	if(ps2_kbd_r_inc)
+		ps2_kbd_rptr <= ps2_kbd_rptr + 1;
+
+	// transmitter is idle?
+	if(ps2_kbd_tx_state == 0) begin
+		// data in fifo present?
+		if(ps2_kbd_wptr != ps2_kbd_rptr) begin
+			// load tx register from fifo
+			ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
+			ps2_kbd_r_inc <= 1'b1;
+			
+			// reset parity
+			ps2_kbd_parity <= 1'b1;
+			
+			// start transmitter
+			ps2_kbd_tx_state <= 4'd1;
+
+			// put start bit on data line
+			ps2_kbd_data <= 1'b0;			// start bit is 0
+		end
+	end else begin
+	
+		// transmission of 8 data bits
+		if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
+			ps2_kbd_data <= ps2_kbd_tx_byte[0];			  // data bits
+			ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
+			if(ps2_kbd_tx_byte[0]) 
+				ps2_kbd_parity <= !ps2_kbd_parity;
+		end
+
+		// transmission of parity
+		if(ps2_kbd_tx_state == 9)
+			ps2_kbd_data <= ps2_kbd_parity;
+			
+		// transmission of stop bit
+		if(ps2_kbd_tx_state == 10)
+			ps2_kbd_data <= 1'b1;			// stop bit is 1
+
+		// advance state machine
+		if(ps2_kbd_tx_state < 11)
+			ps2_kbd_tx_state <= ps2_kbd_tx_state + 4'd1;
+		else	
+			ps2_kbd_tx_state <= 4'd0;
+	
+	end
+end
+  
+// mouse
+reg [7:0] ps2_mouse_fifo [(2**PS2_FIFO_BITS)-1:0];
+reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
+reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
+
+// ps2 transmitter state machine
+reg [3:0] ps2_mouse_tx_state;
+reg [7:0] ps2_mouse_tx_byte;
+reg ps2_mouse_parity;
+
+assign ps2_mouse_clk = ps2_clk || (ps2_mouse_tx_state == 0);
+
+// ps2 transmitter
+// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
+reg ps2_mouse_r_inc;
+always@(posedge ps2_clk) begin
+	ps2_mouse_r_inc <= 1'b0;
+	
+	if(ps2_mouse_r_inc)
+		ps2_mouse_rptr <= ps2_mouse_rptr + 1;
+
+	// transmitter is idle?
+	if(ps2_mouse_tx_state == 0) begin
+		// data in fifo present?
+		if(ps2_mouse_wptr != ps2_mouse_rptr) begin
+			// load tx register from fifo
+			ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
+			ps2_mouse_r_inc <= 1'b1;
+			
+			// reset parity
+			ps2_mouse_parity <= 1'b1;
+			
+			// start transmitter
+			ps2_mouse_tx_state <= 4'd1;
+
+			// put start bit on data line
+			ps2_mouse_data <= 1'b0;			// start bit is 0
+		end
+	end else begin
+	
+		// transmission of 8 data bits
+		if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
+			ps2_mouse_data <= ps2_mouse_tx_byte[0];			  // data bits
+			ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
+			if(ps2_mouse_tx_byte[0]) 
+				ps2_mouse_parity <= !ps2_mouse_parity;
+		end
+
+		// transmission of parity
+		if(ps2_mouse_tx_state == 9)
+			ps2_mouse_data <= ps2_mouse_parity;
+			
+		// transmission of stop bit
+		if(ps2_mouse_tx_state == 10)
+			ps2_mouse_data <= 1'b1;			// stop bit is 1
+
+		// advance state machine
+		if(ps2_mouse_tx_state < 11)
+			ps2_mouse_tx_state <= ps2_mouse_tx_state + 4'd1;
+		else	
+			ps2_mouse_tx_state <= 4'd0;
+	
+	end
+end
+
+// fifo to receive serial data from core to be forwarded to io controller
+
+// 16 byte fifo to store serial bytes
+localparam SERIAL_OUT_FIFO_BITS = 6;
+reg [7:0] serial_out_fifo [(2**SERIAL_OUT_FIFO_BITS)-1:0];
+reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_wptr;
+reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_rptr;
+ 
+wire serial_out_data_available = serial_out_wptr != serial_out_rptr;
+wire [7:0] serial_out_byte = serial_out_fifo[serial_out_rptr] /* synthesis keep */;
+wire [7:0] serial_out_status = { 7'b1000000, serial_out_data_available};
+
+// status[0] is reset signal from io controller and is thus used to flush
+// the fifo
+always @(posedge serial_strobe or posedge status[0]) begin
+	if(status[0] == 1) begin
+		serial_out_wptr <= 0;
+	end else begin 
+		serial_out_fifo[serial_out_wptr] <= serial_data;
+		serial_out_wptr <= serial_out_wptr + 1;
+	end
+end 
+
+always@(negedge spi_sck or posedge status[0]) begin
+	if(status[0] == 1) begin
+		serial_out_rptr <= 0;
+	end else begin
+		if((byte_cnt != 0) && (cmd == 8'h1b)) begin
+			// read last bit -> advance read pointer
+			if((bit_cnt == 7) && !byte_cnt[0] && serial_out_data_available)
+				serial_out_rptr <= serial_out_rptr + 1;
+		end
+	end
+end
+
+// SPI receiver
+always@(posedge spi_sck or posedge SPI_SS_IO) begin
+
+	if(SPI_SS_IO == 1) begin
+	   bit_cnt <= 3'd0;
+	   byte_cnt <= 8'd0;
+		sd_ack <= 1'b0;
+		sd_dout_strobe <= 1'b0;
+		sd_din_strobe <= 1'b0;
+		sd_change <= 1'b0;
+	end else begin
+		sd_dout_strobe <= 1'b0;
+		sd_din_strobe <= 1'b0;
+		
+		if(bit_cnt != 7)
+			sbuf[6:0] <= { sbuf[5:0], SPI_MOSI };
+			
+		bit_cnt <= bit_cnt + 3'd1;
+		if((bit_cnt == 7)&&(byte_cnt != 8'd255)) 
+			byte_cnt <= byte_cnt + 8'd1;
+
+		// finished reading command byte
+      if(bit_cnt == 7) begin
+			if(byte_cnt == 0) begin
+				cmd <= { sbuf, SPI_MOSI};
+			
+				// fetch first byte when sectore FPGA->IO command has been seen
+				if({ sbuf, SPI_MOSI} == 8'h18)
+					sd_din_strobe <= 1'b1;
+					
+				if(({ sbuf, SPI_MOSI} == 8'h17) || ({ sbuf, SPI_MOSI} == 8'h18))
+					sd_ack <= 1'b1;
+					
+			end else begin
+			
+				// buttons and switches
+				if(cmd == 8'h01)
+					but_sw <= { sbuf, SPI_MOSI }; 
+
+				if(cmd == 8'h02)
+					joystick_0 <= { sbuf, SPI_MOSI };
+				 
+				if(cmd == 8'h03)
+					joystick_1 <= { sbuf, SPI_MOSI };
+				 
+				if(cmd == 8'h04) begin
+					// store incoming ps2 mouse bytes 
+					ps2_mouse_fifo[ps2_mouse_wptr] <= { sbuf, SPI_MOSI }; 
+					ps2_mouse_wptr <= ps2_mouse_wptr + 1;
+				end
+
+				if(cmd == 8'h05) begin
+					// store incoming ps2 keyboard bytes 
+					ps2_kbd_fifo[ps2_kbd_wptr] <= { sbuf, SPI_MOSI }; 
+					ps2_kbd_wptr <= ps2_kbd_wptr + 1;
+				end
+				
+				if(cmd == 8'h15)
+					status <= { sbuf[6:0], SPI_MOSI };
+				
+				// send sector IO -> FPGA
+				if(cmd == 8'h17) begin
+					// flag that download begins
+					sd_dout_strobe <= 1'b1;
+				end
+				
+				// send sector FPGA -> IO
+				if(cmd == 8'h18)
+					sd_din_strobe <= 1'b1;
+				
+				// send SD config IO -> FPGA
+				if(cmd == 8'h19) begin
+					// flag that download begins
+					// sd card knows data is config if sd_dout_strobe is asserted
+					// with sd_ack still being inactive (low)
+					sd_dout_strobe <= 1'b1;
+				end
+				
+				// joystick analog
+				if(cmd == 8'h1a) begin
+					// first byte is joystick indes
+					if(byte_cnt == 1)
+						stick_idx <= { sbuf[1:0], SPI_MOSI };
+					else if(byte_cnt == 2) begin
+						// second byte is x axis
+						if(stick_idx == 0)
+							joystick_analog_0[15:8] <= { sbuf, SPI_MOSI };
+						else if(stick_idx == 1)
+							joystick_analog_1[15:8] <= { sbuf, SPI_MOSI };
+					end else if(byte_cnt == 3) begin
+						// third byte is y axis
+						if(stick_idx == 0)
+							joystick_analog_0[7:0] <= { sbuf, SPI_MOSI };
+						else if(stick_idx == 1)
+							joystick_analog_1[7:0] <= { sbuf, SPI_MOSI };
+					end
+				end
+				
+				// set sd card status. The fact that this register is being	
+				// set by the arm controller indicates a possible disk change
+				if(cmd == 8'h1c)
+					sd_change <= 1'b1;
+
+			end
+		end
+	end
+end
+   
+endmodule