diff --git a/cores/archie/fpga/mist/archimedes_mist_top.sdc b/cores/archie/fpga/mist/archimedes_mist_top.sdc
index c1ade17..d27ec51 100644
--- a/cores/archie/fpga/mist/archimedes_mist_top.sdc
+++ b/cores/archie/fpga/mist/archimedes_mist_top.sdc
@@ -47,6 +47,11 @@ create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_port
 
 derive_pll_clocks
 
+set sdram_clk "CLOCKS|altpll_component|auto_generated|pll1|clk[3]"
+set mem_clk   "CLOCKS|altpll_component|auto_generated|pll1|clk[1]"
+set sys_clk   "CLOCKS|altpll_component|auto_generated|pll1|clk[0]"
+set vidc_clk  "CLOCKS_VIDC|altpll_component|auto_generated|pll1|clk[0]"
+
 #**************************************************************
 # Set Clock Latency
 #**************************************************************
@@ -62,35 +67,33 @@ derive_clock_uncertainty;
 # Set Input Delay
 #**************************************************************
 
-set_input_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -max 6.4 [get_ports DRAM_DQ[*]]
-set_input_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -min 3.2 [get_ports DRAM_DQ[*]]
+set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports DRAM_CLK] -max 6.4 [get_ports DRAM_DQ[*]]
+set_input_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports DRAM_CLK] -min 3.2 [get_ports DRAM_DQ[*]]
 
 
 #**************************************************************
 # Set Output Delay
 #**************************************************************
 
-set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -max 1.5 [get_ports {DRAM_A* DRAM_BA* DRAM_CAS_N DRAM_CKE DRAM_CS_N DRAM_D* DRAM_RAS_N DRAM_WE_N}]
-set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -min -0.8 [get_ports {DRAM_A* DRAM_BA* DRAM_CAS_N DRAM_CKE DRAM_CS_N DRAM_D* DRAM_RAS_N DRAM_WE_N}]
-set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[3]}] -max 1.5 [get_ports DRAM_CLK]
-set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[3]}] -min -0.8 [get_ports DRAM_CLK]
+set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports DRAM_CLK] -max 1.5 [get_ports {DRAM_A* DRAM_BA* DRAM_CAS_N DRAM_CKE DRAM_CS_N DRAM_D* DRAM_RAS_N DRAM_WE_N}]
+set_output_delay -clock [get_clocks $sdram_clk] -reference_pin [get_ports DRAM_CLK] -min -0.8 [get_ports {DRAM_A* DRAM_BA* DRAM_CAS_N DRAM_CKE DRAM_CS_N DRAM_D* DRAM_RAS_N DRAM_WE_N}]
 
-set_output_delay -clock [get_clocks {CLOCKS_VIDC|altpll_component|auto_generated|pll1|clk[0]}] -max 0 [get_ports {VGA_*}]
-set_output_delay -clock [get_clocks {CLOCKS_VIDC|altpll_component|auto_generated|pll1|clk[0]}] -min -5 [get_ports {VGA_*}]
+set_output_delay -clock [get_clocks $vidc_clk] -max 0 [get_ports {VGA_*}]
+set_output_delay -clock [get_clocks $vidc_clk] -min -5 [get_ports {VGA_*}]
 
 #**************************************************************
 # Set Clock Groups
 #**************************************************************
 
 set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {CLOCKS|*}]
-set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {CLOCKS_VIDC|*}]
-set_clock_groups -asynchronous -group [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[0]}] -group [get_clocks {CLOCKS_VIDC|altpll_component|auto_generated|pll1|clk[0]}]
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks $vidc_clk]
+set_clock_groups -asynchronous -group [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[*]}] -group [get_clocks $vidc_clk]
 
 #**************************************************************
 # Set False Path
 #**************************************************************
 
-#set_false_path -to [get_ports {VGA_*}]
+set_false_path -to [get_ports {DRAM_CLK}]
 set_false_path -to [get_ports {UART_TX}]
 set_false_path -to [get_ports {AUDIO_L}]
 set_false_path -to [get_ports {AUDIO_R}]
@@ -99,9 +102,13 @@ set_false_path -to [get_ports {LED}]
 #**************************************************************
 # Set Multicycle Path
 #**************************************************************
+# SDRAM_CLK to internal sdram clock
+set_multicycle_path -from [get_clocks $sdram_clk] -to [get_clocks $mem_clk] -setup 2
+set_multicycle_path -from [get_clocks $sdram_clk] -to [get_clocks $mem_clk] -hold 1
 
-set_multicycle_path -from [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -setup 3
-set_multicycle_path -from [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -hold 2
+# system clock to internal sdram clock
+set_multicycle_path -from [get_clocks $sys_clk] -to [get_clocks $mem_clk] -setup 3
+set_multicycle_path -from [get_clocks $sys_clk] -to [get_clocks $mem_clk] -hold 2
 
 set_multicycle_path -to {VGA_*[*]} -setup 4
 set_multicycle_path -to {VGA_*[*]} -hold 3