diff --git a/cores/c64/rtl/fpga64_sid_iec.vhd b/cores/c64/rtl/fpga64_sid_iec.vhd
index f651b20..f81f3b9 100644
--- a/cores/c64/rtl/fpga64_sid_iec.vhd
+++ b/cores/c64/rtl/fpga64_sid_iec.vhd
@@ -125,6 +125,7 @@ entity fpga64_sid_iec is
 
 		-- CIA
 		cia_mode    : in std_logic;
+		todclk      : in std_logic;
 
 		disk_num    : out std_logic_vector(7 downto 0);
 
@@ -693,7 +694,7 @@ div1m: process(clk32)				-- this process devides 32 MHz to 1MHz (for the SID)
             cnt_out => cnt1_out,
 
             pc_n => open,
-            tod => vicVSync,
+            tod => todclk,
             irq_n => irq_cia1
 		);
 
@@ -723,7 +724,7 @@ div1m: process(clk32)				-- this process devides 32 MHz to 1MHz (for the SID)
             cnt_out => cnt2_out,
 
             pc_n => pc2_n,
-            tod => vicVSync,
+            tod => todclk,
             irq_n => irq_cia2
 		);
 
diff --git a/cores/c64/rtl/mist/c64_mist.vhd b/cores/c64/rtl/mist/c64_mist.vhd
index 2d426c1..05f86fa 100644
--- a/cores/c64/rtl/mist/c64_mist.vhd
+++ b/cores/c64/rtl/mist/c64_mist.vhd
@@ -456,6 +456,9 @@ end component cartridge;
 	signal hq2x160 : std_logic;
 	signal osdclk : std_logic;
 	signal clkdiv : std_logic_vector(9 downto 0);
+	signal todclk : std_logic;
+	signal toddiv : std_logic_vector(19 downto 0);
+	signal toddiv3 : std_logic_vector(1 downto 0);
 
 	signal ram_ce : std_logic;
 	signal ram_we : std_logic;
@@ -978,6 +981,7 @@ begin
 		pb_in => pb_in,
 		pb_out => pb_out,
 		flag2_n => flag2_n,
+		todclk => todclk,
 		cia_mode => status(4),
 		disk_num => open,
 		c64rom_addr => c64rom_addr,
@@ -1010,6 +1014,25 @@ begin
 		end if;
 	end process;
 
+	-- generate TOD clock from stable 32 MHz
+	process(clk32, reset_n)
+	begin
+		if reset_n = '0' then
+			todclk <= '0';
+			toddiv <= (others => '0');
+		elsif rising_edge(clk32) then
+			toddiv <= toddiv + 1;
+			if (ntsc_init_mode_d2 = '1' and toddiv = 266665 and toddiv3 = "00") or
+			   (ntsc_init_mode_d2 = '1' and toddiv = 266666 and toddiv3 /= "00") or
+			    toddiv = 319999 then
+				toddiv <= (others => '0');
+				todclk <= not todclk;
+				toddiv3 <= toddiv3 + 1;
+				if toddiv3 = "10" then toddiv3 <= "00"; end if;
+			end if;
+		end if;
+	end process;
+
 	disk_readonly <= status(16);
 
     c64_iec_data_i <= c1541_iec_data_o;