diff --git a/cores/c16/c16_mist.qsf b/cores/c16/c16_mist.qsf
index 85f6097..5d54c9f 100644
--- a/cores/c16/c16_mist.qsf
+++ b/cores/c16/c16_mist.qsf
@@ -127,7 +127,7 @@ set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
# Analysis & Synthesis Assignments
# ================================
-set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
set_global_assignment -name FAMILY "Cyclone III"
set_global_assignment -name TOP_LEVEL_ENTITY c16_mist
set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
@@ -144,7 +144,7 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
set_global_assignment -name DEVICE EP3C25E144C8
set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
@@ -324,8 +324,6 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CONF_DATA0
set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001
set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
set_global_assignment -name VHDL_FILE gen_ram.vhd
-set_global_assignment -name QIP_FILE pll_ntsc.qip
-set_global_assignment -name QIP_FILE pll_pal.qip
set_global_assignment -name VERILOG_FILE data_io.v
set_global_assignment -name VERILOG_FILE sdram.v
set_global_assignment -name VERILOG_FILE osd.v
@@ -353,4 +351,10 @@ set_global_assignment -name VHDL_FILE t65/T65_ALU.vhd
set_global_assignment -name VHDL_FILE t65/T65.vhd
set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
set_global_assignment -name SYSTEMVERILOG_FILE rgb2ypbpr.sv
+set_global_assignment -name QIP_FILE pll_c1541.qip
+set_global_assignment -name QIP_FILE pll_c16.qip
+set_global_assignment -name QIP_FILE rom_reconfig_pal.qip
+set_global_assignment -name QIP_FILE rom_reconfig_ntsc.qip
+set_global_assignment -name QIP_FILE pll_reconfig.qip
+set_global_assignment -name ENABLE_DRC_SETTINGS ON
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/cores/c16/c16_mist.sdc b/cores/c16/c16_mist.sdc
index 45e736e..f80a943 100644
--- a/cores/c16/c16_mist.sdc
+++ b/cores/c16/c16_mist.sdc
@@ -33,21 +33,22 @@ derive_pll_clocks -create_base_clocks
derive_clock_uncertainty
# Clock groups
-set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[*]}]
-set_clock_groups -asynchronous -group [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[1]}] -group [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[0]}]
-set_clock_groups -asynchronous -group [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[1]}] -group [get_clocks {pll_ntsc|altpll_component|auto_generated|pll1|clk[0]}]
-
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll_c1541|altpll_component|auto_generated|pll1|clk[*]}]
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[*]}]
+set_clock_groups -asynchronous -group [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[*]}] -group [get_clocks {pll_c1541|altpll_component|auto_generated|pll1|clk[*]}]
# Some relaxed constrain to the VGA pins. The signals should arrive together, the delay is not really important.
-set_output_delay -clock [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[0]}] -max 0 [get_ports {VGA_*}]
-set_output_delay -clock [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[0]}] -min -5 [get_ports {VGA_*}]
+set_output_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -max 0 [get_ports {VGA_*}]
+set_output_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -min -5 [get_ports {VGA_*}]
# SDRAM delays
-set_input_delay -clock [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[0]}] -max 6.4 [get_ports SDRAM_DQ[*]]
-set_input_delay -clock [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[0]}] -min 3.2 [get_ports SDRAM_DQ[*]]
+set_input_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -max 6.4 [get_ports SDRAM_DQ[*]]
+set_input_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -min 3.2 [get_ports SDRAM_DQ[*]]
-set_output_delay -clock [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
-set_output_delay -clock [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[0]}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+set_output_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+set_output_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+set_output_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_ports {SDRAM_CLK}]
+set_output_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -min -0.8 [get_ports {SDRAM_CLK}]
set_false_path -to [get_ports {AUDIO_L}]
set_false_path -to [get_ports {AUDIO_R}]
diff --git a/cores/c16/c16_mist.v b/cores/c16/c16_mist.v
index 8d477b1..e987b49 100644
--- a/cores/c16/c16_mist.v
+++ b/cores/c16/c16_mist.v
@@ -57,7 +57,6 @@ module c16_mist (
output [5:0] VGA_B
);
-parameter MODE_PAL = 1'b1;
// -------------------------------------------------------------------------
// ------------------------------ user_io ----------------------------------
// -------------------------------------------------------------------------
@@ -519,7 +518,7 @@ always @(negedge clk28) begin
end
// include the c16 itself
-C16 #(.MODE_PAL(MODE_PAL)) c16 (
+C16 c16 (
.CLK28 ( clk28 ),
.RESET ( reset ),
.WAIT ( c16_wait ),
@@ -571,8 +570,8 @@ C16 #(.MODE_PAL(MODE_PAL)) c16 (
// the FPGATED uses two different clocks for NTSC and PAL mode.
// Switching the clocks may crash the system. We might need to force a reset it.
-wire clk28 = MODE_PAL?clk28_pal:clk28_ntsc;
-wire pll_locked = pll_pal_locked && pll_ntsc_locked;
+wire pll_locked = pll_c1541_locked && pll_c16_locked;
+wire ntsc = ~c16_pal;
// tv15hkz has quarter the pixel rate, so we need a 7mhz clock for the OSD
reg clk7;
@@ -588,22 +587,127 @@ always @(posedge clk28) begin
end
// A PLL to derive the system clock from the MiSTs 27MHz
-wire clk32;
-wire pll_pal_locked, clk28_pal;
-pll_pal pll_pal (
- .inclk0( CLOCK_27 ),
- .c0( clk28_pal ),
- .c1( clk32 ),
- .locked( pll_pal_locked )
+wire pll_c1541_locked, clk32;
+pll_c1541 pll_c1541 (
+ .inclk0 ( CLOCK_27 ),
+ .c0 ( clk32 ),
+ .locked ( pll_c1541_locked )
);
-wire pll_ntsc_locked, clk28_ntsc;
-pll_ntsc pll_ntsc (
- .inclk0( CLOCK_27 ),
- .c0( clk28_ntsc ),
- .locked( pll_ntsc_locked )
+wire pll_c16_locked, clk28;
+pll_c16 pll_c16 (
+ .inclk0(CLOCK_27),
+ .c0(clk28),
+ .areset(pll_areset),
+ .scanclk(pll_scanclk),
+ .scandata(pll_scandata),
+ .scanclkena(pll_scanclkena),
+ .configupdate(pll_configupdate),
+ .scandataout(pll_scandataout),
+ .scandone(pll_scandone),
+ .locked(pll_c16_locked)
);
+wire pll_reconfig_busy;
+wire pll_areset;
+wire pll_configupdate;
+wire pll_scanclk;
+wire pll_scanclkena;
+wire pll_scandata;
+wire pll_scandataout;
+wire pll_scandone;
+reg pll_reconfig_reset;
+wire [7:0] pll_rom_address;
+wire pll_rom_q;
+reg pll_write_from_rom;
+wire pll_write_rom_ena;
+reg pll_reconfig;
+wire q_reconfig_ntsc;
+wire q_reconfig_pal;
+
+rom_reconfig_pal rom_reconfig_pal
+(
+ .address(pll_rom_address),
+ .clock(clk32),
+ .rden(pll_write_rom_ena),
+ .q(q_reconfig_pal)
+);
+
+rom_reconfig_ntsc rom_reconfig_ntsc
+(
+ .address(pll_rom_address),
+ .clock(clk32),
+ .rden(pll_write_rom_ena),
+ .q(q_reconfig_ntsc)
+);
+
+assign pll_rom_q = ntsc ? q_reconfig_ntsc : q_reconfig_pal;
+
+pll_reconfig pll_reconfig_inst
+(
+ .busy(pll_reconfig_busy),
+ .clock(clk32),
+ .counter_param(0),
+ .counter_type(0),
+ .data_in(0),
+ .pll_areset(pll_areset),
+ .pll_areset_in(0),
+ .pll_configupdate(pll_configupdate),
+ .pll_scanclk(pll_scanclk),
+ .pll_scanclkena(pll_scanclkena),
+ .pll_scandata(pll_scandata),
+ .pll_scandataout(pll_scandataout),
+ .pll_scandone(pll_scandone),
+ .read_param(0),
+ .reconfig(pll_reconfig),
+ .reset(pll_reconfig_reset),
+ .reset_rom_address(0),
+ .rom_address_out(pll_rom_address),
+ .rom_data_in(pll_rom_q),
+ .write_from_rom(pll_write_from_rom),
+ .write_param(0),
+ .write_rom_ena(pll_write_rom_ena)
+);
+
+always @(posedge clk32) begin
+ reg ntsc_d, ntsc_d2, ntsc_d3;
+ reg [1:0] pll_reconfig_state = 0;
+ reg [9:0] pll_reconfig_timeout;
+
+ ntsc_d <= ntsc;
+ ntsc_d2 <= ntsc_d;
+ pll_write_from_rom <= 0;
+ pll_reconfig <= 0;
+ pll_reconfig_reset <= 0;
+ case (pll_reconfig_state)
+ 2'b00:
+ begin
+ ntsc_d3 <= ntsc_d2;
+ if (ntsc_d2 ^ ntsc_d3) begin
+ pll_write_from_rom <= 1;
+ pll_reconfig_state <= 2'b01;
+ end
+ end
+ 2'b01: pll_reconfig_state <= 2'b10;
+ 2'b10:
+ if (~pll_reconfig_busy) begin
+ pll_reconfig <= 1;
+ pll_reconfig_state <= 2'b11;
+ pll_reconfig_timeout <= 10'd1000;
+ end
+ 2'b11:
+ begin
+ pll_reconfig_timeout <= pll_reconfig_timeout - 1'd1;
+ if (pll_reconfig_timeout == 10'd1) begin
+ // pll_reconfig stuck in busy state
+ pll_reconfig_reset <= 1;
+ pll_reconfig_state <= 2'b00;
+ end
+ if (~pll_reconfig & ~pll_reconfig_busy) pll_reconfig_state <= 2'b00;
+ end
+ default: ;
+ endcase
+end
// ---------------------------------------------------------------------------------
// ----------------------------------- floppy 1541 ---------------------------------
// ---------------------------------------------------------------------------------
diff --git a/cores/c16/pll_c1541.ppf b/cores/c16/pll_c1541.ppf
new file mode 100644
index 0000000..f99f613
--- /dev/null
+++ b/cores/c16/pll_c1541.ppf
@@ -0,0 +1,10 @@
+
+
+
+
+
+
+
+
+
+
diff --git a/cores/c16/pll_ntsc.qip b/cores/c16/pll_c1541.qip
similarity index 82%
rename from cores/c16/pll_ntsc.qip
rename to cores/c16/pll_c1541.qip
index 4a8f47e..6cb00bc 100644
--- a/cores/c16/pll_ntsc.qip
+++ b/cores/c16/pll_c1541.qip
@@ -1,4 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_ntsc.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_ntsc.ppf"]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_c1541.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_c1541.ppf"]
diff --git a/cores/c16/pll_ntsc.v b/cores/c16/pll_c1541.v
similarity index 92%
rename from cores/c16/pll_ntsc.v
rename to cores/c16/pll_c1541.v
index 2a6abf2..2502ece 100644
--- a/cores/c16/pll_ntsc.v
+++ b/cores/c16/pll_c1541.v
@@ -4,7 +4,7 @@
// MODULE: altpll
// ============================================================
-// File Name: pll_ntsc.v
+// File Name: pll_c1541.v
// Megafunction Name(s):
// altpll
//
@@ -36,7 +36,7 @@
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
-module pll_ntsc (
+module pll_c1541 (
inclk0,
c0,
locked);
@@ -94,14 +94,14 @@ module pll_ntsc (
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
- altpll_component.clk0_divide_by = 270000,
+ altpll_component.clk0_divide_by = 27,
altpll_component.clk0_duty_cycle = 50,
- altpll_component.clk0_multiply_by = 286363,
+ altpll_component.clk0_multiply_by = 32,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
- altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_ntsc",
+ altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_c1541",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
@@ -171,9 +171,9 @@ endmodule
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "183"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "28.636299"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "32.000000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -196,9 +196,9 @@ endmodule
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "191"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.63630000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "32.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
@@ -216,7 +216,7 @@ endmodule
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_ntsc.mif"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_c1541.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
@@ -224,7 +224,7 @@ endmodule
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.000"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
@@ -237,9 +237,9 @@ endmodule
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "270000"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "286363"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "32"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
@@ -298,12 +298,12 @@ endmodule
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.ppf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c1541.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c1541.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c1541.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c1541.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c1541.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c1541_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c1541_bb.v FALSE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/cores/c16/pll_c16.ppf b/cores/c16/pll_c16.ppf
new file mode 100644
index 0000000..d91f722
--- /dev/null
+++ b/cores/c16/pll_c16.ppf
@@ -0,0 +1,17 @@
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/cores/c16/pll_pal.qip b/cores/c16/pll_c16.qip
similarity index 84%
rename from cores/c16/pll_pal.qip
rename to cores/c16/pll_c16.qip
index 6c4dccc..4814ee0 100644
--- a/cores/c16/pll_pal.qip
+++ b/cores/c16/pll_c16.qip
@@ -1,4 +1,4 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_pal.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_pal.ppf"]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_c16.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_c16.ppf"]
diff --git a/cores/c16/pll_pal.v b/cores/c16/pll_c16.v
similarity index 73%
rename from cores/c16/pll_pal.v
rename to cores/c16/pll_c16.v
index d2028ba..5f36cd0 100644
--- a/cores/c16/pll_pal.v
+++ b/cores/c16/pll_c16.v
@@ -4,7 +4,7 @@
// MODULE: altpll
// ============================================================
-// File Name: pll_pal.v
+// File Name: pll_c16.v
// Megafunction Name(s):
// altpll
//
@@ -36,39 +36,68 @@
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
-module pll_pal (
+module pll_c16 (
+ areset,
+ configupdate,
inclk0,
+ scanclk,
+ scanclkena,
+ scandata,
c0,
- c1,
- locked);
+ locked,
+ scandataout,
+ scandone);
+ input areset;
+ input configupdate;
input inclk0;
+ input scanclk;
+ input scanclkena;
+ input scandata;
output c0;
- output c1;
output locked;
+ output scandataout;
+ output scandone;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 areset;
+ tri0 configupdate;
+ tri0 scanclkena;
+ tri0 scandata;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
wire [4:0] sub_wire0;
wire sub_wire2;
- wire [0:0] sub_wire6 = 1'h0;
- wire [0:0] sub_wire3 = sub_wire0[0:0];
- wire [1:1] sub_wire1 = sub_wire0[1:1];
- wire c1 = sub_wire1;
- wire locked = sub_wire2;
- wire c0 = sub_wire3;
- wire sub_wire4 = inclk0;
- wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
+ wire sub_wire3;
+ wire sub_wire4;
+ wire [0:0] sub_wire7 = 1'h0;
+ wire [0:0] sub_wire1 = sub_wire0[0:0];
+ wire c0 = sub_wire1;
+ wire scandataout = sub_wire2;
+ wire scandone = sub_wire3;
+ wire locked = sub_wire4;
+ wire sub_wire5 = inclk0;
+ wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
altpll altpll_component (
- .inclk (sub_wire5),
+ .areset (areset),
+ .configupdate (configupdate),
+ .inclk (sub_wire6),
+ .scanclk (scanclk),
+ .scanclkena (scanclkena),
+ .scandata (scandata),
.clk (sub_wire0),
- .locked (sub_wire2),
+ .scandataout (sub_wire2),
+ .scandone (sub_wire3),
+ .locked (sub_wire4),
.activeclock (),
- .areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
- .configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
@@ -85,11 +114,6 @@ module pll_pal (
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
- .scanclk (1'b0),
- .scanclkena (1'b1),
- .scandata (1'b0),
- .scandataout (),
- .scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
@@ -98,28 +122,24 @@ module pll_pal (
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
- altpll_component.clk0_divide_by = 39,
+ altpll_component.clk0_divide_by = 27000000,
altpll_component.clk0_duty_cycle = 50,
- altpll_component.clk0_multiply_by = 41,
+ altpll_component.clk0_multiply_by = 28375151,
altpll_component.clk0_phase_shift = "0",
- altpll_component.clk1_divide_by = 27,
- altpll_component.clk1_duty_cycle = 50,
- altpll_component.clk1_multiply_by = 32,
- altpll_component.clk1_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 37037,
altpll_component.intended_device_family = "Cyclone III",
- altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_pal",
+ altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_c16",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
- altpll_component.port_areset = "PORT_UNUSED",
+ altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
- altpll_component.port_configupdate = "PORT_UNUSED",
+ altpll_component.port_configupdate = "PORT_USED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
@@ -131,15 +151,15 @@ module pll_pal (
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
- altpll_component.port_scanclk = "PORT_UNUSED",
- altpll_component.port_scanclkena = "PORT_UNUSED",
- altpll_component.port_scandata = "PORT_UNUSED",
- altpll_component.port_scandataout = "PORT_UNUSED",
- altpll_component.port_scandone = "PORT_UNUSED",
+ altpll_component.port_scanclk = "PORT_USED",
+ altpll_component.port_scanclkena = "PORT_USED",
+ altpll_component.port_scandata = "PORT_USED",
+ altpll_component.port_scandataout = "PORT_USED",
+ altpll_component.port_scandone = "PORT_USED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
- altpll_component.port_clk1 = "PORT_USED",
+ altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
@@ -155,7 +175,8 @@ module pll_pal (
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.self_reset_on_loss_lock = "OFF",
- altpll_component.width_clock = 5;
+ altpll_component.width_clock = 5,
+ altpll_component.scan_chain_mif_file = "pll_c16_pal.mif";
endmodule
@@ -179,12 +200,9 @@ endmodule
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "39"
-// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "28.384615"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "32.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "28.375153"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -205,28 +223,20 @@ endmodule
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "41"
-// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.37500000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "32.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.37515200"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
@@ -235,38 +245,31 @@ endmodule
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_pal.mif"
-// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_c16_pal.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.000"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "39"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27000000"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "41"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "28375151"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
-// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "32"
-// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@@ -274,12 +277,12 @@ endmodule
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
@@ -291,15 +294,15 @@ endmodule
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
@@ -316,22 +319,38 @@ endmodule
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
// Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: CONSTANT: scan_chain_mif_file STRING "pll_c16_pal.mif"
// Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: configupdate 0 0 0 0 INPUT GND "configupdate"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
+// Retrieval info: USED_PORT: scanclkena 0 0 0 0 INPUT GND "scanclkena"
+// Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata"
+// Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout"
+// Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone"
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
+// Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
+// Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.ppf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_bb.v FALSE
+// Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0
+// Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16.mif FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16_ntsc.mif TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16_pal.mif TRUE
// Retrieval info: LIB_FILE: altera_mf
// Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/cores/c16/pll_c16_ntsc.mif b/cores/c16/pll_c16_ntsc.mif
new file mode 100644
index 0000000..cf24b53
--- /dev/null
+++ b/cores/c16/pll_c16_ntsc.mif
@@ -0,0 +1,174 @@
+-- Copyright (C) 1991-2014 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- MIF file representing initial state of PLL Scan Chain
+-- Device Family: Cyclone III
+-- Device Part: -
+-- Device Speed Grade: 8
+-- PLL Scan Chain: Fast PLL (144 bits)
+-- File Name: /home/gyurco/git/mist-board/cores/c16/pll_c16_ntsc.mif
+-- Generated: Thu Feb 14 11:24:12 2019
+
+WIDTH=1;
+DEPTH=144;
+
+ADDRESS_RADIX=UNS;
+DATA_RADIX=UNS;
+
+CONTENT BEGIN
+ 0 : 0; -- Reserved Bits = 0 (1 bit(s))
+ 1 : 0; -- Reserved Bits = 0 (1 bit(s))
+ 2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
+ 3 : 0;
+ 4 : 1; -- Loop Filter Resistance = 16 (5 bit(s)) (Setting 16)
+ 5 : 0;
+ 6 : 0;
+ 7 : 0;
+ 8 : 0;
+ 9 : 0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2)
+ 10 : 0; -- Reserved Bits = 0 (5 bit(s))
+ 11 : 0;
+ 12 : 0;
+ 13 : 0;
+ 14 : 0;
+ 15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
+ 16 : 0;
+ 17 : 1;
+ 18 : 0; -- N counter: Bypass = 0 (1 bit(s))
+ 19 : 0; -- N counter: High Count = 2 (8 bit(s))
+ 20 : 0;
+ 21 : 0;
+ 22 : 0;
+ 23 : 0;
+ 24 : 0;
+ 25 : 1;
+ 26 : 0;
+ 27 : 1; -- N counter: Odd Division = 1 (1 bit(s))
+ 28 : 0; -- N counter: Low Count = 1 (8 bit(s))
+ 29 : 0;
+ 30 : 0;
+ 31 : 0;
+ 32 : 0;
+ 33 : 0;
+ 34 : 0;
+ 35 : 1;
+ 36 : 0; -- M counter: Bypass = 0 (1 bit(s))
+ 37 : 0; -- M counter: High Count = 35 (8 bit(s))
+ 38 : 0;
+ 39 : 1;
+ 40 : 0;
+ 41 : 0;
+ 42 : 0;
+ 43 : 1;
+ 44 : 1;
+ 45 : 0; -- M counter: Odd Division = 0 (1 bit(s))
+ 46 : 0; -- M counter: Low Count = 35 (8 bit(s))
+ 47 : 0;
+ 48 : 1;
+ 49 : 0;
+ 50 : 0;
+ 51 : 0;
+ 52 : 1;
+ 53 : 1;
+ 54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s))
+ 55 : 0; -- clk0 counter: High Count = 11 (8 bit(s))
+ 56 : 0;
+ 57 : 0;
+ 58 : 0;
+ 59 : 1;
+ 60 : 0;
+ 61 : 1;
+ 62 : 1;
+ 63 : 0; -- clk0 counter: Odd Division = 0 (1 bit(s))
+ 64 : 0; -- clk0 counter: Low Count = 11 (8 bit(s))
+ 65 : 0;
+ 66 : 0;
+ 67 : 0;
+ 68 : 1;
+ 69 : 0;
+ 70 : 1;
+ 71 : 1;
+ 72 : 1; -- clk1 counter: Bypass = 1 (1 bit(s))
+ 73 : 0; -- clk1 counter: High Count = 0 (8 bit(s))
+ 74 : 0;
+ 75 : 0;
+ 76 : 0;
+ 77 : 0;
+ 78 : 0;
+ 79 : 0;
+ 80 : 0;
+ 81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s))
+ 82 : 0; -- clk1 counter: Low Count = 0 (8 bit(s))
+ 83 : 0;
+ 84 : 0;
+ 85 : 0;
+ 86 : 0;
+ 87 : 0;
+ 88 : 0;
+ 89 : 0;
+ 90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s))
+ 91 : 0; -- clk2 counter: High Count = 0 (8 bit(s))
+ 92 : 0;
+ 93 : 0;
+ 94 : 0;
+ 95 : 0;
+ 96 : 0;
+ 97 : 0;
+ 98 : 0;
+ 99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s))
+ 100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s))
+ 101 : 0;
+ 102 : 0;
+ 103 : 0;
+ 104 : 0;
+ 105 : 0;
+ 106 : 0;
+ 107 : 0;
+ 108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s))
+ 109 : 0; -- clk3 counter: High Count = 0 (8 bit(s))
+ 110 : 0;
+ 111 : 0;
+ 112 : 0;
+ 113 : 0;
+ 114 : 0;
+ 115 : 0;
+ 116 : 0;
+ 117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s))
+ 118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s))
+ 119 : 0;
+ 120 : 0;
+ 121 : 0;
+ 122 : 0;
+ 123 : 0;
+ 124 : 0;
+ 125 : 0;
+ 126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s))
+ 127 : 0; -- clk4 counter: High Count = 0 (8 bit(s))
+ 128 : 0;
+ 129 : 0;
+ 130 : 0;
+ 131 : 0;
+ 132 : 0;
+ 133 : 0;
+ 134 : 0;
+ 135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s))
+ 136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s))
+ 137 : 0;
+ 138 : 0;
+ 139 : 0;
+ 140 : 0;
+ 141 : 0;
+ 142 : 0;
+ 143 : 0;
+END;
diff --git a/cores/c16/pll_c16_pal.mif b/cores/c16/pll_c16_pal.mif
new file mode 100644
index 0000000..1e58c39
--- /dev/null
+++ b/cores/c16/pll_c16_pal.mif
@@ -0,0 +1,174 @@
+-- Copyright (C) 1991-2014 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions
+-- and other software and tools, and its AMPP partner logic
+-- functions, and any output files from any of the foregoing
+-- (including device programming or simulation files), and any
+-- associated documentation or information are expressly subject
+-- to the terms and conditions of the Altera Program License
+-- Subscription Agreement, Altera MegaCore Function License
+-- Agreement, or other applicable license agreement, including,
+-- without limitation, that your use is for the sole purpose of
+-- programming logic devices manufactured by Altera and sold by
+-- Altera or its authorized distributors. Please refer to the
+-- applicable agreement for further details.
+
+-- MIF file representing initial state of PLL Scan Chain
+-- Device Family: Cyclone III
+-- Device Part: -
+-- Device Speed Grade: 8
+-- PLL Scan Chain: Fast PLL (144 bits)
+-- File Name: /home/gyurco/git/mist-board/cores/c16/pll_c16_pal.mif
+-- Generated: Thu Feb 14 11:25:48 2019
+
+WIDTH=1;
+DEPTH=144;
+
+ADDRESS_RADIX=UNS;
+DATA_RADIX=UNS;
+
+CONTENT BEGIN
+ 0 : 0; -- Reserved Bits = 0 (1 bit(s))
+ 1 : 0; -- Reserved Bits = 0 (1 bit(s))
+ 2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
+ 3 : 0;
+ 4 : 1; -- Loop Filter Resistance = 20 (5 bit(s)) (Setting 20)
+ 5 : 0;
+ 6 : 1;
+ 7 : 0;
+ 8 : 0;
+ 9 : 0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2)
+ 10 : 0; -- Reserved Bits = 0 (5 bit(s))
+ 11 : 0;
+ 12 : 0;
+ 13 : 0;
+ 14 : 0;
+ 15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
+ 16 : 0;
+ 17 : 1;
+ 18 : 0; -- N counter: Bypass = 0 (1 bit(s))
+ 19 : 0; -- N counter: High Count = 2 (8 bit(s))
+ 20 : 0;
+ 21 : 0;
+ 22 : 0;
+ 23 : 0;
+ 24 : 0;
+ 25 : 1;
+ 26 : 0;
+ 27 : 1; -- N counter: Odd Division = 1 (1 bit(s))
+ 28 : 0; -- N counter: Low Count = 1 (8 bit(s))
+ 29 : 0;
+ 30 : 0;
+ 31 : 0;
+ 32 : 0;
+ 33 : 0;
+ 34 : 0;
+ 35 : 1;
+ 36 : 0; -- M counter: Bypass = 0 (1 bit(s))
+ 37 : 0; -- M counter: High Count = 21 (8 bit(s))
+ 38 : 0;
+ 39 : 0;
+ 40 : 1;
+ 41 : 0;
+ 42 : 1;
+ 43 : 0;
+ 44 : 1;
+ 45 : 1; -- M counter: Odd Division = 1 (1 bit(s))
+ 46 : 0; -- M counter: Low Count = 20 (8 bit(s))
+ 47 : 0;
+ 48 : 0;
+ 49 : 1;
+ 50 : 0;
+ 51 : 1;
+ 52 : 0;
+ 53 : 0;
+ 54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s))
+ 55 : 0; -- clk0 counter: High Count = 7 (8 bit(s))
+ 56 : 0;
+ 57 : 0;
+ 58 : 0;
+ 59 : 0;
+ 60 : 1;
+ 61 : 1;
+ 62 : 1;
+ 63 : 1; -- clk0 counter: Odd Division = 1 (1 bit(s))
+ 64 : 0; -- clk0 counter: Low Count = 6 (8 bit(s))
+ 65 : 0;
+ 66 : 0;
+ 67 : 0;
+ 68 : 0;
+ 69 : 1;
+ 70 : 1;
+ 71 : 0;
+ 72 : 1; -- clk1 counter: Bypass = 1 (1 bit(s))
+ 73 : 0; -- clk1 counter: High Count = 0 (8 bit(s))
+ 74 : 0;
+ 75 : 0;
+ 76 : 0;
+ 77 : 0;
+ 78 : 0;
+ 79 : 0;
+ 80 : 0;
+ 81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s))
+ 82 : 0; -- clk1 counter: Low Count = 0 (8 bit(s))
+ 83 : 0;
+ 84 : 0;
+ 85 : 0;
+ 86 : 0;
+ 87 : 0;
+ 88 : 0;
+ 89 : 0;
+ 90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s))
+ 91 : 0; -- clk2 counter: High Count = 0 (8 bit(s))
+ 92 : 0;
+ 93 : 0;
+ 94 : 0;
+ 95 : 0;
+ 96 : 0;
+ 97 : 0;
+ 98 : 0;
+ 99 : 0; -- clk2 counter: Odd Division = 0 (1 bit(s))
+ 100 : 0; -- clk2 counter: Low Count = 0 (8 bit(s))
+ 101 : 0;
+ 102 : 0;
+ 103 : 0;
+ 104 : 0;
+ 105 : 0;
+ 106 : 0;
+ 107 : 0;
+ 108 : 1; -- clk3 counter: Bypass = 1 (1 bit(s))
+ 109 : 0; -- clk3 counter: High Count = 0 (8 bit(s))
+ 110 : 0;
+ 111 : 0;
+ 112 : 0;
+ 113 : 0;
+ 114 : 0;
+ 115 : 0;
+ 116 : 0;
+ 117 : 0; -- clk3 counter: Odd Division = 0 (1 bit(s))
+ 118 : 0; -- clk3 counter: Low Count = 0 (8 bit(s))
+ 119 : 0;
+ 120 : 0;
+ 121 : 0;
+ 122 : 0;
+ 123 : 0;
+ 124 : 0;
+ 125 : 0;
+ 126 : 1; -- clk4 counter: Bypass = 1 (1 bit(s))
+ 127 : 0; -- clk4 counter: High Count = 0 (8 bit(s))
+ 128 : 0;
+ 129 : 0;
+ 130 : 0;
+ 131 : 0;
+ 132 : 0;
+ 133 : 0;
+ 134 : 0;
+ 135 : 0; -- clk4 counter: Odd Division = 0 (1 bit(s))
+ 136 : 0; -- clk4 counter: Low Count = 0 (8 bit(s))
+ 137 : 0;
+ 138 : 0;
+ 139 : 0;
+ 140 : 0;
+ 141 : 0;
+ 142 : 0;
+ 143 : 0;
+END;
diff --git a/cores/c16/pll_reconfig.qip b/cores/c16/pll_reconfig.qip
new file mode 100644
index 0000000..7754768
--- /dev/null
+++ b/cores/c16/pll_reconfig.qip
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL_RECONFIG"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_reconfig.v"]
diff --git a/cores/c16/pll_reconfig.v b/cores/c16/pll_reconfig.v
new file mode 100644
index 0000000..e3f99c8
--- /dev/null
+++ b/cores/c16/pll_reconfig.v
@@ -0,0 +1,1624 @@
+// megafunction wizard: %ALTPLL_RECONFIG%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll_reconfig
+
+// ============================================================
+// File Name: pll_reconfig.v
+// Megafunction Name(s):
+// altpll_reconfig
+//
+// Simulation Library Files(s):
+// altera_mf;cycloneiii;lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.4 Build 182 03/12/2014 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2014 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+//altpll_reconfig CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone III" init_from_rom="NO" scan_init_file="./pll_c16_pal.mif" busy clock counter_param counter_type data_in data_out pll_areset pll_areset_in pll_configupdate pll_scanclk pll_scanclkena pll_scandata pll_scandataout pll_scandone read_param reconfig reset reset_rom_address rom_address_out rom_data_in write_from_rom write_param write_rom_ena
+//VERSION_BEGIN 13.1 cbx_altpll_reconfig 2014:03:12:19:24:28:SJ cbx_altsyncram 2014:03:12:19:24:28:SJ cbx_cycloneii 2014:03:12:19:24:28:SJ cbx_lpm_add_sub 2014:03:12:19:24:28:SJ cbx_lpm_compare 2014:03:12:19:24:28:SJ cbx_lpm_counter 2014:03:12:19:24:28:SJ cbx_lpm_decode 2014:03:12:19:24:28:SJ cbx_lpm_mux 2014:03:12:19:24:28:SJ cbx_mgl 2014:03:12:19:35:38:SJ cbx_stratix 2014:03:12:19:24:28:SJ cbx_stratixii 2014:03:12:19:24:28:SJ cbx_stratixiii 2014:03:12:19:24:28:SJ cbx_stratixv 2014:03:12:19:24:28:SJ cbx_util_mgl 2014:03:12:19:24:28:SJ VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+//synthesis_resources = altsyncram 1 lpm_add_sub 2 lpm_compare 1 lpm_counter 8 lpm_decode 1 lut 3 reg 102
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+(* ALTERA_ATTRIBUTE = {"ADV_NETLIST_OPT_ALLOWED=\"NEVER_ALLOW\";suppress_da_rule_internal=C106;{-to le_comb10} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=2;{-to le_comb8} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=0;{-to le_comb9} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=1"} *)
+module pll_reconfig_pllrcfg_dc61
+ (
+ busy,
+ clock,
+ counter_param,
+ counter_type,
+ data_in,
+ data_out,
+ pll_areset,
+ pll_areset_in,
+ pll_configupdate,
+ pll_scanclk,
+ pll_scanclkena,
+ pll_scandata,
+ pll_scandataout,
+ pll_scandone,
+ read_param,
+ reconfig,
+ reset,
+ reset_rom_address,
+ rom_address_out,
+ rom_data_in,
+ write_from_rom,
+ write_param,
+ write_rom_ena) /* synthesis synthesis_clearbox=2 */;
+ output busy;
+ input clock;
+ input [2:0] counter_param;
+ input [3:0] counter_type;
+ input [8:0] data_in;
+ output [8:0] data_out;
+ output pll_areset;
+ input pll_areset_in;
+ output pll_configupdate;
+ output pll_scanclk;
+ output pll_scanclkena;
+ output pll_scandata;
+ input pll_scandataout;
+ input pll_scandone;
+ input read_param;
+ input reconfig;
+ input reset;
+ input reset_rom_address;
+ output [7:0] rom_address_out;
+ input rom_data_in;
+ input write_from_rom;
+ input write_param;
+ output write_rom_ena;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 [2:0] counter_param;
+ tri0 [3:0] counter_type;
+ tri0 [8:0] data_in;
+ tri0 pll_areset_in;
+ tri0 pll_scandataout;
+ tri0 pll_scandone;
+ tri0 read_param;
+ tri0 reconfig;
+ tri0 reset_rom_address;
+ tri0 rom_data_in;
+ tri0 write_from_rom;
+ tri0 write_param;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ wire [0:0] wire_altsyncram4_q_a;
+ wire wire_le_comb10_combout;
+ wire wire_le_comb8_combout;
+ wire wire_le_comb9_combout;
+ reg [7:0] addr_from_rom;
+ reg [7:0] addr_from_rom2;
+ reg areset_init_state_1;
+ reg areset_state;
+ reg C0_data_state;
+ reg C0_ena_state;
+ reg C1_data_state;
+ reg C1_ena_state;
+ reg C2_data_state;
+ reg C2_ena_state;
+ reg C3_data_state;
+ reg C3_ena_state;
+ reg C4_data_state;
+ reg C4_ena_state;
+ reg configupdate2_state;
+ reg configupdate3_state;
+ reg configupdate_state;
+ reg [2:0] counter_param_latch_reg;
+ reg [3:0] counter_type_latch_reg;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg idle_state;
+ reg [0:0] nominal_data0;
+ reg [0:0] nominal_data1;
+ reg [0:0] nominal_data2;
+ reg [0:0] nominal_data3;
+ reg [0:0] nominal_data4;
+ reg [0:0] nominal_data5;
+ reg [0:0] nominal_data6;
+ reg [0:0] nominal_data7;
+ reg [0:0] nominal_data8;
+ reg [0:0] nominal_data9;
+ reg [0:0] nominal_data10;
+ reg [0:0] nominal_data11;
+ reg [0:0] nominal_data12;
+ reg [0:0] nominal_data13;
+ reg [0:0] nominal_data14;
+ reg [0:0] nominal_data15;
+ reg [0:0] nominal_data16;
+ reg [0:0] nominal_data17;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg read_data_nominal_state;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg read_data_state;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg read_first_nominal_state;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg read_first_state;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg read_init_nominal_state;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg read_init_state;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg read_last_nominal_state;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg read_last_state;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg reconfig_counter_state;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg reconfig_init_state;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg reconfig_post_state;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg reconfig_seq_data_state;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg reconfig_seq_ena_state;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg reconfig_wait_state;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
+ reg reset_state;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg rom_data_state;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg rom_first_state;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg rom_init_state;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg rom_last_state;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg rom_second_last_state;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg rom_second_state;
+ reg [0:0] shift_reg0;
+ reg [0:0] shift_reg1;
+ reg [0:0] shift_reg2;
+ reg [0:0] shift_reg3;
+ reg [0:0] shift_reg4;
+ reg [0:0] shift_reg5;
+ reg [0:0] shift_reg6;
+ reg [0:0] shift_reg7;
+ reg [0:0] shift_reg8;
+ reg [0:0] shift_reg9;
+ reg [0:0] shift_reg10;
+ reg [0:0] shift_reg11;
+ reg [0:0] shift_reg12;
+ reg [0:0] shift_reg13;
+ reg [0:0] shift_reg14;
+ reg [0:0] shift_reg15;
+ reg [0:0] shift_reg16;
+ reg [0:0] shift_reg17;
+ wire [17:0] wire_shift_reg_ena;
+ reg tmp_nominal_data_out_state;
+ reg tmp_seq_ena_state;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg write_data_state;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg write_init_nominal_state;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg write_init_state;
+ (* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+ reg write_nominal_state;
+ wire [8:0] wire_add_sub5_result;
+ wire [7:0] wire_add_sub6_result;
+ wire wire_cmpr7_aeb;
+ wire [7:0] wire_cntr1_q;
+ wire [7:0] wire_cntr12_q;
+ wire [5:0] wire_cntr13_q;
+ wire [7:0] wire_cntr14_q;
+ wire [4:0] wire_cntr15_q;
+ wire [7:0] wire_cntr16_q;
+ wire [7:0] wire_cntr2_q;
+ wire [4:0] wire_cntr3_q;
+ wire [4:0] wire_decode11_eq;
+ wire addr_counter_enable;
+ wire [7:0] addr_counter_out;
+ wire addr_counter_sload;
+ wire [7:0] addr_counter_sload_value;
+ wire [7:0] addr_decoder_out;
+ wire [7:0] c0_wire;
+ wire [7:0] c1_wire;
+ wire [7:0] c2_wire;
+ wire [7:0] c3_wire;
+ wire [7:0] c4_wire;
+ wire [7:0] const_scan_chain_size;
+ wire [2:0] counter_param_latch;
+ wire [3:0] counter_type_latch;
+ wire [2:0] cuda_combout_wire;
+ wire dummy_scandataout;
+ wire [2:0] encode_out;
+ wire input_latch_enable;
+ wire power_up;
+ wire read_addr_counter_done;
+ wire read_addr_counter_enable;
+ wire [7:0] read_addr_counter_out;
+ wire read_addr_counter_sload;
+ wire [7:0] read_addr_counter_sload_value;
+ wire [7:0] read_addr_decoder_out;
+ wire read_nominal_out;
+ wire reconfig_addr_counter_enable;
+ wire [7:0] reconfig_addr_counter_out;
+ wire reconfig_addr_counter_sload;
+ wire [7:0] reconfig_addr_counter_sload_value;
+ wire reconfig_done;
+ wire reconfig_post_done;
+ wire reconfig_width_counter_done;
+ wire reconfig_width_counter_enable;
+ wire reconfig_width_counter_sload;
+ wire [5:0] reconfig_width_counter_sload_value;
+ wire rom_width_counter_done;
+ wire rom_width_counter_enable;
+ wire rom_width_counter_sload;
+ wire [7:0] rom_width_counter_sload_value;
+ wire rotate_addr_counter_enable;
+ wire [7:0] rotate_addr_counter_out;
+ wire rotate_addr_counter_sload;
+ wire [7:0] rotate_addr_counter_sload_value;
+ wire [4:0] rotate_decoder_wires;
+ wire rotate_width_counter_done;
+ wire rotate_width_counter_enable;
+ wire rotate_width_counter_sload;
+ wire [4:0] rotate_width_counter_sload_value;
+ wire [7:0] scan_cache_address;
+ wire scan_cache_in;
+ wire scan_cache_out;
+ wire scan_cache_write_enable;
+ wire sel_param_bypass_LF_unused;
+ wire sel_param_c;
+ wire sel_param_high_i_postscale;
+ wire sel_param_low_r;
+ wire sel_param_nominal_count;
+ wire sel_param_odd_CP_unused;
+ wire sel_type_c0;
+ wire sel_type_c1;
+ wire sel_type_c2;
+ wire sel_type_c3;
+ wire sel_type_c4;
+ wire sel_type_cplf;
+ wire sel_type_m;
+ wire sel_type_n;
+ wire sel_type_vco;
+ wire [7:0] seq_addr_wire;
+ wire [5:0] seq_sload_value;
+ wire shift_reg_clear;
+ wire shift_reg_load_enable;
+ wire shift_reg_load_nominal_enable;
+ wire shift_reg_serial_in;
+ wire shift_reg_serial_out;
+ wire shift_reg_shift_enable;
+ wire shift_reg_shift_nominal_enable;
+ wire [7:0] shift_reg_width_select;
+ wire w1565w;
+ wire w1592w;
+ wire w64w;
+ wire width_counter_done;
+ wire width_counter_enable;
+ wire width_counter_sload;
+ wire [4:0] width_counter_sload_value;
+ wire [4:0] width_decoder_out;
+ wire [7:0] width_decoder_select;
+
+ altsyncram altsyncram4
+ (
+ .address_a(scan_cache_address),
+ .clock0(clock),
+ .data_a({scan_cache_in}),
+ .eccstatus(),
+ .q_a(wire_altsyncram4_q_a),
+ .q_b(),
+ .wren_a(scan_cache_write_enable)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr0(1'b0),
+ .aclr1(1'b0),
+ .address_b({1{1'b1}}),
+ .addressstall_a(1'b0),
+ .addressstall_b(1'b0),
+ .byteena_a({1{1'b1}}),
+ .byteena_b({1{1'b1}}),
+ .clock1(1'b1),
+ .clocken0(1'b1),
+ .clocken1(1'b1),
+ .clocken2(1'b1),
+ .clocken3(1'b1),
+ .data_b({1{1'b1}}),
+ .rden_a(1'b1),
+ .rden_b(1'b1),
+ .wren_b(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ altsyncram4.init_file = "./pll_c16_pal.mif",
+ altsyncram4.numwords_a = 144,
+ altsyncram4.operation_mode = "SINGLE_PORT",
+ altsyncram4.width_a = 1,
+ altsyncram4.width_byteena_a = 1,
+ altsyncram4.widthad_a = 8,
+ altsyncram4.intended_device_family = "Cyclone III",
+ altsyncram4.lpm_type = "altsyncram";
+ cycloneiii_lcell_comb le_comb10
+ (
+ .combout(wire_le_comb10_combout),
+ .cout(),
+ .dataa(encode_out[0]),
+ .datab(encode_out[1]),
+ .datac(encode_out[2]),
+ .cin(1'b0),
+ .datad(1'b0)
+ );
+ defparam
+ le_comb10.dont_touch = "on",
+ le_comb10.lut_mask = 16'hF0F0,
+ le_comb10.sum_lutc_input = "datac",
+ le_comb10.lpm_type = "cycloneiii_lcell_comb";
+ cycloneiii_lcell_comb le_comb8
+ (
+ .combout(wire_le_comb8_combout),
+ .cout(),
+ .dataa(encode_out[0]),
+ .datab(encode_out[1]),
+ .datac(encode_out[2]),
+ .cin(1'b0),
+ .datad(1'b0)
+ );
+ defparam
+ le_comb8.dont_touch = "on",
+ le_comb8.lut_mask = 16'hAAAA,
+ le_comb8.sum_lutc_input = "datac",
+ le_comb8.lpm_type = "cycloneiii_lcell_comb";
+ cycloneiii_lcell_comb le_comb9
+ (
+ .combout(wire_le_comb9_combout),
+ .cout(),
+ .dataa(encode_out[0]),
+ .datab(encode_out[1]),
+ .datac(encode_out[2]),
+ .cin(1'b0),
+ .datad(1'b0)
+ );
+ defparam
+ le_comb9.dont_touch = "on",
+ le_comb9.lut_mask = 16'hCCCC,
+ le_comb9.sum_lutc_input = "datac",
+ le_comb9.lpm_type = "cycloneiii_lcell_comb";
+ // synopsys translate_off
+ initial
+ addr_from_rom = 0;
+ // synopsys translate_on
+ always @ ( posedge clock)
+ addr_from_rom <= read_addr_counter_out;
+ // synopsys translate_off
+ initial
+ addr_from_rom2 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock)
+ addr_from_rom2 <= addr_from_rom;
+ // synopsys translate_off
+ initial
+ areset_init_state_1 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock)
+ areset_init_state_1 <= pll_scandone;
+ // synopsys translate_off
+ initial
+ areset_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock)
+ areset_state <= (areset_init_state_1 & (~ reset));
+ // synopsys translate_off
+ initial
+ C0_data_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock)
+ C0_data_state <= (C0_ena_state | (C0_data_state & (~ rotate_width_counter_done)));
+ // synopsys translate_off
+ initial
+ C0_ena_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock)
+ C0_ena_state <= (C1_data_state & rotate_width_counter_done);
+ // synopsys translate_off
+ initial
+ C1_data_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock)
+ C1_data_state <= (C1_ena_state | (C1_data_state & (~ rotate_width_counter_done)));
+ // synopsys translate_off
+ initial
+ C1_ena_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock)
+ C1_ena_state <= (C2_data_state & rotate_width_counter_done);
+ // synopsys translate_off
+ initial
+ C2_data_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock)
+ C2_data_state <= (C2_ena_state | (C2_data_state & (~ rotate_width_counter_done)));
+ // synopsys translate_off
+ initial
+ C2_ena_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock)
+ C2_ena_state <= (C3_data_state & rotate_width_counter_done);
+ // synopsys translate_off
+ initial
+ C3_data_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock)
+ C3_data_state <= (C3_ena_state | (C3_data_state & (~ rotate_width_counter_done)));
+ // synopsys translate_off
+ initial
+ C3_ena_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock)
+ C3_ena_state <= (C4_data_state & rotate_width_counter_done);
+ // synopsys translate_off
+ initial
+ C4_data_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock)
+ C4_data_state <= (C4_ena_state | (C4_data_state & (~ rotate_width_counter_done)));
+ // synopsys translate_off
+ initial
+ C4_ena_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock)
+ C4_ena_state <= reconfig_init_state;
+ // synopsys translate_off
+ initial
+ configupdate2_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock)
+ configupdate2_state <= configupdate_state;
+ // synopsys translate_off
+ initial
+ configupdate3_state = 0;
+ // synopsys translate_on
+ always @ ( negedge clock)
+ configupdate3_state <= configupdate2_state;
+ // synopsys translate_off
+ initial
+ configupdate_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock)
+ configupdate_state <= reconfig_post_state;
+ // synopsys translate_off
+ initial
+ counter_param_latch_reg = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) counter_param_latch_reg <= 3'b0;
+ else if (input_latch_enable == 1'b1) counter_param_latch_reg <= counter_param;
+ // synopsys translate_off
+ initial
+ counter_type_latch_reg = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) counter_type_latch_reg <= 4'b0;
+ else if (input_latch_enable == 1'b1) counter_type_latch_reg <= counter_type;
+ // synopsys translate_off
+ initial
+ idle_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) idle_state <= 1'b0;
+ else idle_state <= (((((((((((((idle_state & (~ read_param)) & (~ write_param)) & (~ reconfig)) & (~ write_from_rom)) | read_last_state) | (write_data_state & width_counter_done)) | (write_nominal_state & width_counter_done)) | read_last_nominal_state) | (reconfig_wait_state & reconfig_done)) | ((rom_data_state & rom_width_counter_done) & (~ reset_rom_address))) | (rom_second_last_state & (~ reset_rom_address))) | (rom_last_state & (~ reset_rom_address))) | reset_state);
+ // synopsys translate_off
+ initial
+ nominal_data0 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) nominal_data0 <= 1'b0;
+ else nominal_data0 <= wire_add_sub6_result[0];
+ // synopsys translate_off
+ initial
+ nominal_data1 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) nominal_data1 <= 1'b0;
+ else nominal_data1 <= wire_add_sub6_result[1];
+ // synopsys translate_off
+ initial
+ nominal_data2 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) nominal_data2 <= 1'b0;
+ else nominal_data2 <= wire_add_sub6_result[2];
+ // synopsys translate_off
+ initial
+ nominal_data3 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) nominal_data3 <= 1'b0;
+ else nominal_data3 <= wire_add_sub6_result[3];
+ // synopsys translate_off
+ initial
+ nominal_data4 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) nominal_data4 <= 1'b0;
+ else nominal_data4 <= wire_add_sub6_result[4];
+ // synopsys translate_off
+ initial
+ nominal_data5 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) nominal_data5 <= 1'b0;
+ else nominal_data5 <= wire_add_sub6_result[5];
+ // synopsys translate_off
+ initial
+ nominal_data6 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) nominal_data6 <= 1'b0;
+ else nominal_data6 <= wire_add_sub6_result[6];
+ // synopsys translate_off
+ initial
+ nominal_data7 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) nominal_data7 <= 1'b0;
+ else nominal_data7 <= wire_add_sub6_result[7];
+ // synopsys translate_off
+ initial
+ nominal_data8 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) nominal_data8 <= 1'b0;
+ else nominal_data8 <= data_in[0];
+ // synopsys translate_off
+ initial
+ nominal_data9 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) nominal_data9 <= 1'b0;
+ else nominal_data9 <= data_in[1];
+ // synopsys translate_off
+ initial
+ nominal_data10 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) nominal_data10 <= 1'b0;
+ else nominal_data10 <= data_in[2];
+ // synopsys translate_off
+ initial
+ nominal_data11 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) nominal_data11 <= 1'b0;
+ else nominal_data11 <= data_in[3];
+ // synopsys translate_off
+ initial
+ nominal_data12 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) nominal_data12 <= 1'b0;
+ else nominal_data12 <= data_in[4];
+ // synopsys translate_off
+ initial
+ nominal_data13 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) nominal_data13 <= 1'b0;
+ else nominal_data13 <= data_in[5];
+ // synopsys translate_off
+ initial
+ nominal_data14 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) nominal_data14 <= 1'b0;
+ else nominal_data14 <= data_in[6];
+ // synopsys translate_off
+ initial
+ nominal_data15 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) nominal_data15 <= 1'b0;
+ else nominal_data15 <= data_in[7];
+ // synopsys translate_off
+ initial
+ nominal_data16 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) nominal_data16 <= 1'b0;
+ else nominal_data16 <= data_in[8];
+ // synopsys translate_off
+ initial
+ nominal_data17 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) nominal_data17 <= 1'b0;
+ else nominal_data17 <= wire_cmpr7_aeb;
+ // synopsys translate_off
+ initial
+ read_data_nominal_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) read_data_nominal_state <= 1'b0;
+ else read_data_nominal_state <= ((read_first_nominal_state & (~ width_counter_done)) | (read_data_nominal_state & (~ width_counter_done)));
+ // synopsys translate_off
+ initial
+ read_data_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) read_data_state <= 1'b0;
+ else read_data_state <= ((read_first_state & (~ width_counter_done)) | (read_data_state & (~ width_counter_done)));
+ // synopsys translate_off
+ initial
+ read_first_nominal_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) read_first_nominal_state <= 1'b0;
+ else read_first_nominal_state <= read_init_nominal_state;
+ // synopsys translate_off
+ initial
+ read_first_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) read_first_state <= 1'b0;
+ else read_first_state <= read_init_state;
+ // synopsys translate_off
+ initial
+ read_init_nominal_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) read_init_nominal_state <= 1'b0;
+ else read_init_nominal_state <= ((idle_state & read_param) & ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0]));
+ // synopsys translate_off
+ initial
+ read_init_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) read_init_state <= 1'b0;
+ else read_init_state <= ((idle_state & read_param) & (~ ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0])));
+ // synopsys translate_off
+ initial
+ read_last_nominal_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) read_last_nominal_state <= 1'b0;
+ else read_last_nominal_state <= ((read_first_nominal_state & width_counter_done) | (read_data_nominal_state & width_counter_done));
+ // synopsys translate_off
+ initial
+ read_last_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) read_last_state <= 1'b0;
+ else read_last_state <= ((read_first_state & width_counter_done) | (read_data_state & width_counter_done));
+ // synopsys translate_off
+ initial
+ reconfig_counter_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) reconfig_counter_state <= 1'b0;
+ else reconfig_counter_state <= ((((((((((reconfig_init_state | C0_data_state) | C1_data_state) | C2_data_state) | C3_data_state) | C4_data_state) | C0_ena_state) | C1_ena_state) | C2_ena_state) | C3_ena_state) | C4_ena_state);
+ // synopsys translate_off
+ initial
+ reconfig_init_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) reconfig_init_state <= 1'b0;
+ else reconfig_init_state <= (idle_state & reconfig);
+ // synopsys translate_off
+ initial
+ reconfig_post_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) reconfig_post_state <= 1'b0;
+ else reconfig_post_state <= ((reconfig_seq_data_state & reconfig_width_counter_done) | (reconfig_post_state & (~ reconfig_post_done)));
+ // synopsys translate_off
+ initial
+ reconfig_seq_data_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) reconfig_seq_data_state <= 1'b0;
+ else reconfig_seq_data_state <= (reconfig_seq_ena_state | (reconfig_seq_data_state & (~ reconfig_width_counter_done)));
+ // synopsys translate_off
+ initial
+ reconfig_seq_ena_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) reconfig_seq_ena_state <= 1'b0;
+ else reconfig_seq_ena_state <= tmp_seq_ena_state;
+ // synopsys translate_off
+ initial
+ reconfig_wait_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) reconfig_wait_state <= 1'b0;
+ else reconfig_wait_state <= ((reconfig_post_state & reconfig_post_done) | (reconfig_wait_state & (~ reconfig_done)));
+ // synopsys translate_off
+ initial
+ reset_state = {1{1'b1}};
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) reset_state <= {1{1'b1}};
+ else reset_state <= power_up;
+ // synopsys translate_off
+ initial
+ rom_data_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) rom_data_state <= 1'b0;
+ else rom_data_state <= (rom_second_state | ((rom_data_state & (~ read_addr_counter_done)) & (~ reset_rom_address)));
+ // synopsys translate_off
+ initial
+ rom_first_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) rom_first_state <= 1'b0;
+ else rom_first_state <= rom_init_state;
+ // synopsys translate_off
+ initial
+ rom_init_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) rom_init_state <= 1'b0;
+ else rom_init_state <= (((((idle_state & write_from_rom) | (rom_first_state & reset_rom_address)) | (rom_second_state & reset_rom_address)) | (rom_data_state & reset_rom_address)) | (rom_second_last_state & reset_rom_address));
+ // synopsys translate_off
+ initial
+ rom_last_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) rom_last_state <= 1'b0;
+ else rom_last_state <= (rom_second_last_state & (~ reset_rom_address));
+ // synopsys translate_off
+ initial
+ rom_second_last_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) rom_second_last_state <= 1'b0;
+ else rom_second_last_state <= ((rom_data_state & read_addr_counter_done) & (~ reset_rom_address));
+ // synopsys translate_off
+ initial
+ rom_second_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) rom_second_state <= 1'b0;
+ else rom_second_state <= (rom_first_state & (~ reset_rom_address));
+ // synopsys translate_off
+ initial
+ shift_reg0 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) shift_reg0 <= 1'b0;
+ else if (wire_shift_reg_ena[0:0] == 1'b1)
+ if (shift_reg_clear == 1'b1) shift_reg0 <= 1'b0;
+ else shift_reg0 <= ((((shift_reg_load_nominal_enable & nominal_data17[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg_serial_in)) | (shift_reg_shift_nominal_enable & shift_reg_serial_in));
+ // synopsys translate_off
+ initial
+ shift_reg1 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) shift_reg1 <= 1'b0;
+ else if (wire_shift_reg_ena[1:1] == 1'b1)
+ if (shift_reg_clear == 1'b1) shift_reg1 <= 1'b0;
+ else shift_reg1 <= ((((shift_reg_load_nominal_enable & nominal_data16[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg0[0:0])) | (shift_reg_shift_nominal_enable & shift_reg0[0:0]));
+ // synopsys translate_off
+ initial
+ shift_reg2 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) shift_reg2 <= 1'b0;
+ else if (wire_shift_reg_ena[2:2] == 1'b1)
+ if (shift_reg_clear == 1'b1) shift_reg2 <= 1'b0;
+ else shift_reg2 <= ((((shift_reg_load_nominal_enable & nominal_data15[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg1[0:0])) | (shift_reg_shift_nominal_enable & shift_reg1[0:0]));
+ // synopsys translate_off
+ initial
+ shift_reg3 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) shift_reg3 <= 1'b0;
+ else if (wire_shift_reg_ena[3:3] == 1'b1)
+ if (shift_reg_clear == 1'b1) shift_reg3 <= 1'b0;
+ else shift_reg3 <= ((((shift_reg_load_nominal_enable & nominal_data14[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg2[0:0])) | (shift_reg_shift_nominal_enable & shift_reg2[0:0]));
+ // synopsys translate_off
+ initial
+ shift_reg4 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) shift_reg4 <= 1'b0;
+ else if (wire_shift_reg_ena[4:4] == 1'b1)
+ if (shift_reg_clear == 1'b1) shift_reg4 <= 1'b0;
+ else shift_reg4 <= ((((shift_reg_load_nominal_enable & nominal_data13[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg3[0:0])) | (shift_reg_shift_nominal_enable & shift_reg3[0:0]));
+ // synopsys translate_off
+ initial
+ shift_reg5 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) shift_reg5 <= 1'b0;
+ else if (wire_shift_reg_ena[5:5] == 1'b1)
+ if (shift_reg_clear == 1'b1) shift_reg5 <= 1'b0;
+ else shift_reg5 <= ((((shift_reg_load_nominal_enable & nominal_data12[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg4[0:0])) | (shift_reg_shift_nominal_enable & shift_reg4[0:0]));
+ // synopsys translate_off
+ initial
+ shift_reg6 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) shift_reg6 <= 1'b0;
+ else if (wire_shift_reg_ena[6:6] == 1'b1)
+ if (shift_reg_clear == 1'b1) shift_reg6 <= 1'b0;
+ else shift_reg6 <= ((((shift_reg_load_nominal_enable & nominal_data11[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg5[0:0])) | (shift_reg_shift_nominal_enable & shift_reg5[0:0]));
+ // synopsys translate_off
+ initial
+ shift_reg7 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) shift_reg7 <= 1'b0;
+ else if (wire_shift_reg_ena[7:7] == 1'b1)
+ if (shift_reg_clear == 1'b1) shift_reg7 <= 1'b0;
+ else shift_reg7 <= ((((shift_reg_load_nominal_enable & nominal_data10[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg6[0:0])) | (shift_reg_shift_nominal_enable & shift_reg6[0:0]));
+ // synopsys translate_off
+ initial
+ shift_reg8 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) shift_reg8 <= 1'b0;
+ else if (wire_shift_reg_ena[8:8] == 1'b1)
+ if (shift_reg_clear == 1'b1) shift_reg8 <= 1'b0;
+ else shift_reg8 <= ((((shift_reg_load_nominal_enable & nominal_data9[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg7[0:0])) | (shift_reg_shift_nominal_enable & shift_reg7[0:0]));
+ // synopsys translate_off
+ initial
+ shift_reg9 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) shift_reg9 <= 1'b0;
+ else if (wire_shift_reg_ena[9:9] == 1'b1)
+ if (shift_reg_clear == 1'b1) shift_reg9 <= 1'b0;
+ else shift_reg9 <= ((((shift_reg_load_nominal_enable & nominal_data8[0:0]) | (shift_reg_load_enable & data_in[8])) | (shift_reg_shift_enable & shift_reg8[0:0])) | (shift_reg_shift_nominal_enable & shift_reg8[0:0]));
+ // synopsys translate_off
+ initial
+ shift_reg10 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) shift_reg10 <= 1'b0;
+ else if (wire_shift_reg_ena[10:10] == 1'b1)
+ if (shift_reg_clear == 1'b1) shift_reg10 <= 1'b0;
+ else shift_reg10 <= ((((shift_reg_load_nominal_enable & nominal_data7[0:0]) | (shift_reg_load_enable & data_in[7])) | (shift_reg_shift_enable & shift_reg9[0:0])) | (shift_reg_shift_nominal_enable & shift_reg9[0:0]));
+ // synopsys translate_off
+ initial
+ shift_reg11 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) shift_reg11 <= 1'b0;
+ else if (wire_shift_reg_ena[11:11] == 1'b1)
+ if (shift_reg_clear == 1'b1) shift_reg11 <= 1'b0;
+ else shift_reg11 <= ((((shift_reg_load_nominal_enable & nominal_data6[0:0]) | (shift_reg_load_enable & data_in[6])) | (shift_reg_shift_enable & shift_reg10[0:0])) | (shift_reg_shift_nominal_enable & shift_reg10[0:0]));
+ // synopsys translate_off
+ initial
+ shift_reg12 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) shift_reg12 <= 1'b0;
+ else if (wire_shift_reg_ena[12:12] == 1'b1)
+ if (shift_reg_clear == 1'b1) shift_reg12 <= 1'b0;
+ else shift_reg12 <= ((((shift_reg_load_nominal_enable & nominal_data5[0:0]) | (shift_reg_load_enable & data_in[5])) | (shift_reg_shift_enable & shift_reg11[0:0])) | (shift_reg_shift_nominal_enable & shift_reg11[0:0]));
+ // synopsys translate_off
+ initial
+ shift_reg13 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) shift_reg13 <= 1'b0;
+ else if (wire_shift_reg_ena[13:13] == 1'b1)
+ if (shift_reg_clear == 1'b1) shift_reg13 <= 1'b0;
+ else shift_reg13 <= ((((shift_reg_load_nominal_enable & nominal_data4[0:0]) | (shift_reg_load_enable & data_in[4])) | (shift_reg_shift_enable & shift_reg12[0:0])) | (shift_reg_shift_nominal_enable & shift_reg12[0:0]));
+ // synopsys translate_off
+ initial
+ shift_reg14 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) shift_reg14 <= 1'b0;
+ else if (wire_shift_reg_ena[14:14] == 1'b1)
+ if (shift_reg_clear == 1'b1) shift_reg14 <= 1'b0;
+ else shift_reg14 <= ((((shift_reg_load_nominal_enable & nominal_data3[0:0]) | (shift_reg_load_enable & data_in[3])) | (shift_reg_shift_enable & shift_reg13[0:0])) | (shift_reg_shift_nominal_enable & shift_reg13[0:0]));
+ // synopsys translate_off
+ initial
+ shift_reg15 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) shift_reg15 <= 1'b0;
+ else if (wire_shift_reg_ena[15:15] == 1'b1)
+ if (shift_reg_clear == 1'b1) shift_reg15 <= 1'b0;
+ else shift_reg15 <= ((((shift_reg_load_nominal_enable & nominal_data2[0:0]) | (shift_reg_load_enable & data_in[2])) | (shift_reg_shift_enable & shift_reg14[0:0])) | (shift_reg_shift_nominal_enable & shift_reg14[0:0]));
+ // synopsys translate_off
+ initial
+ shift_reg16 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) shift_reg16 <= 1'b0;
+ else if (wire_shift_reg_ena[16:16] == 1'b1)
+ if (shift_reg_clear == 1'b1) shift_reg16 <= 1'b0;
+ else shift_reg16 <= ((((shift_reg_load_nominal_enable & nominal_data1[0:0]) | (shift_reg_load_enable & data_in[1])) | (shift_reg_shift_enable & shift_reg15[0:0])) | (shift_reg_shift_nominal_enable & shift_reg15[0:0]));
+ // synopsys translate_off
+ initial
+ shift_reg17 = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) shift_reg17 <= 1'b0;
+ else if (wire_shift_reg_ena[17:17] == 1'b1)
+ if (shift_reg_clear == 1'b1) shift_reg17 <= 1'b0;
+ else shift_reg17 <= ((((shift_reg_load_nominal_enable & nominal_data0[0:0]) | (shift_reg_load_enable & data_in[0])) | (shift_reg_shift_enable & shift_reg16[0:0])) | (shift_reg_shift_nominal_enable & shift_reg16[0:0]));
+ assign
+ wire_shift_reg_ena = {18{((((shift_reg_load_enable | shift_reg_shift_enable) | shift_reg_load_nominal_enable) | shift_reg_shift_nominal_enable) | shift_reg_clear)}};
+ // synopsys translate_off
+ initial
+ tmp_nominal_data_out_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock)
+ tmp_nominal_data_out_state <= ((read_last_nominal_state & (~ idle_state)) | (tmp_nominal_data_out_state & idle_state));
+ // synopsys translate_off
+ initial
+ tmp_seq_ena_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock)
+ tmp_seq_ena_state <= (reconfig_counter_state & (C0_data_state & rotate_width_counter_done));
+ // synopsys translate_off
+ initial
+ write_data_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) write_data_state <= 1'b0;
+ else write_data_state <= (write_init_state | (write_data_state & (~ width_counter_done)));
+ // synopsys translate_off
+ initial
+ write_init_nominal_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) write_init_nominal_state <= 1'b0;
+ else write_init_nominal_state <= ((idle_state & write_param) & ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0]));
+ // synopsys translate_off
+ initial
+ write_init_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) write_init_state <= 1'b0;
+ else write_init_state <= ((idle_state & write_param) & (~ ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0])));
+ // synopsys translate_off
+ initial
+ write_nominal_state = 0;
+ // synopsys translate_on
+ always @ ( posedge clock or posedge reset)
+ if (reset == 1'b1) write_nominal_state <= 1'b0;
+ else write_nominal_state <= (write_init_nominal_state | (write_nominal_state & (~ width_counter_done)));
+ lpm_add_sub add_sub5
+ (
+ .cin(1'b0),
+ .cout(),
+ .dataa({1'b0, shift_reg8[0:0], shift_reg7[0:0], shift_reg6[0:0], shift_reg5[0:0], shift_reg4[0:0], shift_reg3[0:0], shift_reg2[0:0], shift_reg1[0:0]}),
+ .datab({1'b0, shift_reg17[0:0], shift_reg16[0:0], shift_reg15[0:0], shift_reg14[0:0], shift_reg13[0:0], shift_reg12[0:0], shift_reg11[0:0], shift_reg10[0:0]}),
+ .overflow(),
+ .result(wire_add_sub5_result)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .add_sub(1'b1),
+ .clken(1'b1),
+ .clock(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ add_sub5.lpm_width = 9,
+ add_sub5.lpm_type = "lpm_add_sub";
+ lpm_add_sub add_sub6
+ (
+ .cin(data_in[0]),
+ .cout(),
+ .dataa({data_in[8:1]}),
+ .overflow(),
+ .result(wire_add_sub6_result)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .add_sub(1'b1),
+ .clken(1'b1),
+ .clock(1'b0),
+ .datab({8{1'b0}})
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ add_sub6.lpm_width = 8,
+ add_sub6.lpm_type = "lpm_add_sub";
+ lpm_compare cmpr7
+ (
+ .aeb(wire_cmpr7_aeb),
+ .agb(),
+ .ageb(),
+ .alb(),
+ .aleb(),
+ .aneb(),
+ .dataa({data_in[7:0]}),
+ .datab(8'b00000001)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .clken(1'b1),
+ .clock(1'b0)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cmpr7.lpm_width = 8,
+ cmpr7.lpm_type = "lpm_compare";
+ lpm_counter cntr1
+ (
+ .clock(clock),
+ .cnt_en(addr_counter_enable),
+ .cout(),
+ .data(addr_counter_sload_value),
+ .eq(),
+ .q(wire_cntr1_q),
+ .sload(addr_counter_sload)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .aset(1'b0),
+ .cin(1'b1),
+ .clk_en(1'b1),
+ .sclr(1'b0),
+ .sset(1'b0),
+ .updown(1'b1)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cntr1.lpm_direction = "DOWN",
+ cntr1.lpm_modulus = 144,
+ cntr1.lpm_port_updown = "PORT_UNUSED",
+ cntr1.lpm_width = 8,
+ cntr1.lpm_type = "lpm_counter";
+ lpm_counter cntr12
+ (
+ .clock(clock),
+ .cnt_en(reconfig_addr_counter_enable),
+ .cout(),
+ .data(reconfig_addr_counter_sload_value),
+ .eq(),
+ .q(wire_cntr12_q),
+ .sload(reconfig_addr_counter_sload)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .aset(1'b0),
+ .cin(1'b1),
+ .clk_en(1'b1),
+ .sclr(1'b0),
+ .sset(1'b0),
+ .updown(1'b1)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cntr12.lpm_direction = "DOWN",
+ cntr12.lpm_modulus = 144,
+ cntr12.lpm_port_updown = "PORT_UNUSED",
+ cntr12.lpm_width = 8,
+ cntr12.lpm_type = "lpm_counter";
+ lpm_counter cntr13
+ (
+ .clock(clock),
+ .cnt_en(reconfig_width_counter_enable),
+ .cout(),
+ .data(reconfig_width_counter_sload_value),
+ .eq(),
+ .q(wire_cntr13_q),
+ .sload(reconfig_width_counter_sload)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .aset(1'b0),
+ .cin(1'b1),
+ .clk_en(1'b1),
+ .sclr(1'b0),
+ .sset(1'b0),
+ .updown(1'b1)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cntr13.lpm_direction = "DOWN",
+ cntr13.lpm_port_updown = "PORT_UNUSED",
+ cntr13.lpm_width = 6,
+ cntr13.lpm_type = "lpm_counter";
+ lpm_counter cntr14
+ (
+ .clock(clock),
+ .cnt_en(rom_width_counter_enable),
+ .cout(),
+ .data(rom_width_counter_sload_value),
+ .eq(),
+ .q(wire_cntr14_q),
+ .sload(rom_width_counter_sload)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .aset(1'b0),
+ .cin(1'b1),
+ .clk_en(1'b1),
+ .sclr(1'b0),
+ .sset(1'b0),
+ .updown(1'b1)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cntr14.lpm_direction = "DOWN",
+ cntr14.lpm_port_updown = "PORT_UNUSED",
+ cntr14.lpm_width = 8,
+ cntr14.lpm_type = "lpm_counter";
+ lpm_counter cntr15
+ (
+ .clock(clock),
+ .cnt_en(rotate_width_counter_enable),
+ .cout(),
+ .data(rotate_width_counter_sload_value),
+ .eq(),
+ .q(wire_cntr15_q),
+ .sload(rotate_width_counter_sload)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .aset(1'b0),
+ .cin(1'b1),
+ .clk_en(1'b1),
+ .sclr(1'b0),
+ .sset(1'b0),
+ .updown(1'b1)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cntr15.lpm_direction = "DOWN",
+ cntr15.lpm_port_updown = "PORT_UNUSED",
+ cntr15.lpm_width = 5,
+ cntr15.lpm_type = "lpm_counter";
+ lpm_counter cntr16
+ (
+ .clock(clock),
+ .cnt_en(rotate_addr_counter_enable),
+ .cout(),
+ .data(rotate_addr_counter_sload_value),
+ .eq(),
+ .q(wire_cntr16_q),
+ .sload(rotate_addr_counter_sload)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .aset(1'b0),
+ .cin(1'b1),
+ .clk_en(1'b1),
+ .sclr(1'b0),
+ .sset(1'b0),
+ .updown(1'b1)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cntr16.lpm_direction = "DOWN",
+ cntr16.lpm_modulus = 144,
+ cntr16.lpm_port_updown = "PORT_UNUSED",
+ cntr16.lpm_width = 8,
+ cntr16.lpm_type = "lpm_counter";
+ lpm_counter cntr2
+ (
+ .clock(clock),
+ .cnt_en(read_addr_counter_enable),
+ .cout(),
+ .data(read_addr_counter_sload_value),
+ .eq(),
+ .q(wire_cntr2_q),
+ .sload(read_addr_counter_sload)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .aset(1'b0),
+ .cin(1'b1),
+ .clk_en(1'b1),
+ .sclr(1'b0),
+ .sset(1'b0),
+ .updown(1'b1)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cntr2.lpm_direction = "UP",
+ cntr2.lpm_port_updown = "PORT_UNUSED",
+ cntr2.lpm_width = 8,
+ cntr2.lpm_type = "lpm_counter";
+ lpm_counter cntr3
+ (
+ .clock(clock),
+ .cnt_en(width_counter_enable),
+ .cout(),
+ .data(width_counter_sload_value),
+ .eq(),
+ .q(wire_cntr3_q),
+ .sload(width_counter_sload)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .aload(1'b0),
+ .aset(1'b0),
+ .cin(1'b1),
+ .clk_en(1'b1),
+ .sclr(1'b0),
+ .sset(1'b0),
+ .updown(1'b1)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ cntr3.lpm_direction = "DOWN",
+ cntr3.lpm_port_updown = "PORT_UNUSED",
+ cntr3.lpm_width = 5,
+ cntr3.lpm_type = "lpm_counter";
+ lpm_decode decode11
+ (
+ .data(cuda_combout_wire),
+ .eq(wire_decode11_eq)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_off
+ `endif
+ ,
+ .aclr(1'b0),
+ .clken(1'b1),
+ .clock(1'b0),
+ .enable(1'b1)
+ `ifndef FORMAL_VERIFICATION
+ // synopsys translate_on
+ `endif
+ );
+ defparam
+ decode11.lpm_decodes = 5,
+ decode11.lpm_width = 3,
+ decode11.lpm_type = "lpm_decode";
+ assign
+ addr_counter_enable = (write_data_state | write_nominal_state),
+ addr_counter_out = wire_cntr1_q,
+ addr_counter_sload = (write_init_state | write_init_nominal_state),
+ addr_counter_sload_value = (addr_decoder_out & {8{(write_init_state | write_init_nominal_state)}}),
+ addr_decoder_out = ((((((((((((((((((((((((((((((((((({{7{1'b0}}, (sel_type_cplf & sel_param_bypass_LF_unused)} | {{6{1'b0}}, {2{(sel_type_cplf & sel_param_c)}}}) | {{4{1'b0}}, (sel_type_cplf & sel_param_low_r), {3{1'b0}}}) | {{4{1'b0}}, (sel_type_vco & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_vco & sel_param_high_i_postscale)}) | {{4{1'b0}}, {3{(sel_type_cplf & sel_param_odd_CP_unused)}}, 1'b0}) | {{3{1'b0}}, (sel_type_cplf & sel_param_high_i_postscale), {3{1'b0}}, (sel_type_cplf & sel_param_high_i_postscale)}) | {{3{1'b0}}, (sel_type_n & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_n & sel_param_bypass_LF_unused), 1'b0}) | {{3{1'b0}}, {2{(sel_type_n & sel_param_high_i_postscale)}}, 1'b0, (sel_type_n & sel_param_high_i_postscale), 1'b0}) | {{3{1'b0}}, {2{(sel_type_n & sel_param_odd_CP_unused)}}, 1'b0, {2{(sel_type_n & sel_param_odd_CP_unused)}}}) | {{2{1'b0}}, (sel_type_n & sel_param_low_r), {3{1'b0}}, {2{(sel_type_n & sel_param_low_r)}}}) | {{2{1'b0}}, (sel_type_n & sel_param_nominal_count), {3{1'b0}}, {2{(sel_type_n & sel_param_nominal_count)}}}) | {{2{1'b0}}, (sel_type_m & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_m & sel_param_bypass_LF_unused), {2{1'b0}}}) | {{2{1'b0}}, (sel_type_m & sel_param_high_i_postscale), 1'b0, {2{(sel_type_m & sel_param_high_i_postscale)}}, {2{1'b0}}}) | {{2{1'b0}}, (sel_type_m & sel_param_odd_CP_unused), 1'b0, {2{(sel_type_m & sel_param_odd_CP_unused)}}, 1'b0, (sel_type_m & sel_param_odd_CP_unused)}) | {{2{1'b0}}, {2{(sel_type_m & sel_param_low_r)}}, 1'b0, (sel_type_m & sel_param_low_r), 1'b0, (sel_type_m & sel_param_low_r)}) | {{2{1'b0}}, {2{(sel_type_m & sel_param_nominal_count)}}, 1'b0, (sel_type_m & sel_param_nominal_count), 1'b0, (sel_type_m & sel_param_nominal_count)}) | {{2{1'b0}}, {2{(sel_type_c0 & sel_param_bypass_LF_unused)}}, 1'b0, {2{(sel_type_c0 & sel_param_bypass_LF_unused)}}, 1'b0}) | {{2{1'b0}}, {5{(sel_type_c0 & sel_param_high_i_postscale)}}, 1'b0}) | {{2{1'b0}}, {6{(sel_type_c0 & sel_param_odd_CP_unused)}}}) | {1'b0, (sel_type_c0 & sel_param_low_r
+), {3{1'b0}}, {3{(sel_type_c0 & sel_param_low_r)}}}) | {1'b0, (sel_type_c1 & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_c1 & sel_param_bypass_LF_unused), {3{1'b0}}}) | {1'b0, (sel_type_c1 & sel_param_high_i_postscale), 1'b0, (sel_type_c1 & sel_param_high_i_postscale), {4{1'b0}}}) | {1'b0, (sel_type_c1 & sel_param_odd_CP_unused), 1'b0, (sel_type_c1 & sel_param_odd_CP_unused), {3{1'b0}}, (sel_type_c1 & sel_param_odd_CP_unused)}) | {1'b0, (sel_type_c1 & sel_param_low_r), 1'b0, {2{(sel_type_c1 & sel_param_low_r)}}, {2{1'b0}}, (sel_type_c1 & sel_param_low_r)}) | {1'b0, (sel_type_c2 & sel_param_bypass_LF_unused), 1'b0, {2{(sel_type_c2 & sel_param_bypass_LF_unused)}}, 1'b0, (sel_type_c2 & sel_param_bypass_LF_unused), 1'b0}) | {1'b0, {2{(sel_type_c2 & sel_param_high_i_postscale)}}, {3{1'b0}}, (sel_type_c2 & sel_param_high_i_postscale), 1'b0}) | {1'b0, {2{(sel_type_c2 & sel_param_odd_CP_unused)}}, {3{1'b0}}, {2{(sel_type_c2 & sel_param_odd_CP_unused)}}}) | {1'b0, {2{(sel_type_c2 & sel_param_low_r)}}, 1'b0, (sel_type_c2 & sel_param_low_r), 1'b0, {2{(sel_type_c2 & sel_param_low_r)}}}) | {1'b0, {2{(sel_type_c3 & sel_param_bypass_LF_unused)}}, 1'b0, {2{(sel_type_c3 & sel_param_bypass_LF_unused)}}, {2{1'b0}}}) | {1'b0, {3{(sel_type_c3 & sel_param_high_i_postscale)}}, 1'b0, (sel_type_c3 & sel_param_high_i_postscale), {2{1'b0}}}) | {1'b0, {3{(sel_type_c3 & sel_param_odd_CP_unused)}}, 1'b0, (sel_type_c3 & sel_param_odd_CP_unused), 1'b0, (sel_type_c3 & sel_param_odd_CP_unused)}) | {1'b0, {5{(sel_type_c3 & sel_param_low_r)}}, 1'b0, (sel_type_c3 & sel_param_low_r)}) | {1'b0, {6{(sel_type_c4 & sel_param_bypass_LF_unused)}}, 1'b0}) | {(sel_type_c4 & sel_param_high_i_postscale), {4{1'b0}}, {2{(sel_type_c4 & sel_param_high_i_postscale)}}, 1'b0}) | {(sel_type_c4 & sel_param_odd_CP_unused), {4{1'b0}}, {3{(sel_type_c4 & sel_param_odd_CP_unused)}}}) | {(sel_type_c4 & sel_param_low_r), {3{1'b0}}, {4{(sel_type_c4 & sel_param_low_r)}}}),
+ busy = ((~ idle_state) | areset_state),
+ c0_wire = 8'b01000111,
+ c1_wire = 8'b01011001,
+ c2_wire = 8'b01101011,
+ c3_wire = 8'b01111101,
+ c4_wire = 8'b10001111,
+ const_scan_chain_size = 8'b10001111,
+ counter_param_latch = counter_param_latch_reg,
+ counter_type_latch = counter_type_latch_reg,
+ cuda_combout_wire = {wire_le_comb10_combout, wire_le_comb9_combout, wire_le_comb8_combout},
+ data_out = {((shift_reg8[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[8] & read_nominal_out)), ((shift_reg7[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[7] & read_nominal_out)), ((shift_reg6[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[6] & read_nominal_out)), ((shift_reg5[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[5] & read_nominal_out)), ((shift_reg4[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[4] & read_nominal_out)), ((shift_reg3[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[3] & read_nominal_out)), ((shift_reg2[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[2] & read_nominal_out)), ((shift_reg1[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[1] & read_nominal_out)), ((shift_reg0[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[0] & read_nominal_out))},
+ dummy_scandataout = pll_scandataout,
+ encode_out = {C4_ena_state, (C2_ena_state | C3_ena_state), (C1_ena_state | C3_ena_state)},
+ input_latch_enable = (idle_state & (write_param | read_param)),
+ pll_areset = (pll_areset_in | (areset_state & reconfig_wait_state)),
+ pll_configupdate = (configupdate_state & (~ configupdate3_state)),
+ pll_scanclk = clock,
+ pll_scanclkena = ((rotate_width_counter_enable & (~ rotate_width_counter_done)) | reconfig_seq_data_state),
+ pll_scandata = (scan_cache_out & ((rotate_width_counter_enable | reconfig_seq_data_state) | reconfig_post_state)),
+ power_up = ((((((((((((((((((((((((((~ reset_state) & (~ idle_state)) & (~ read_init_state)) & (~ read_first_state)) & (~ read_data_state)) & (~ read_last_state)) & (~ read_init_nominal_state)) & (~ read_first_nominal_state)) & (~ read_data_nominal_state)) & (~ read_last_nominal_state)) & (~ write_init_state)) & (~ write_data_state)) & (~ write_init_nominal_state)) & (~ write_nominal_state)) & (~ reconfig_init_state)) & (~ reconfig_counter_state)) & (~ reconfig_seq_ena_state)) & (~ reconfig_seq_data_state)) & (~ reconfig_post_state)) & (~ reconfig_wait_state)) & (~ rom_init_state)) & (~ rom_first_state)) & (~ rom_second_state)) & (~ rom_data_state)) & (~ rom_second_last_state)) & (~ rom_last_state)),
+ read_addr_counter_done = (((((((wire_cntr2_q[0] & wire_cntr2_q[1]) & wire_cntr2_q[2]) & wire_cntr2_q[3]) & (~ wire_cntr2_q[4])) & (~ wire_cntr2_q[5])) & (~ wire_cntr2_q[6])) & wire_cntr2_q[7]),
+ read_addr_counter_enable = ((((read_first_state | read_data_state) | read_first_nominal_state) | read_data_nominal_state) | ((rom_data_state | rom_first_state) | rom_second_state)),
+ read_addr_counter_out = wire_cntr2_q,
+ read_addr_counter_sload = ((read_init_state | read_init_nominal_state) | rom_init_state),
+ read_addr_counter_sload_value = (read_addr_decoder_out & {8{(read_init_state | read_init_nominal_state)}}),
+ read_addr_decoder_out = ((((((((((((((((((((((((((((((((((({8{1'b0}} | {{6{1'b0}}, (sel_type_cplf & sel_param_c), 1'b0}) | {{5{1'b0}}, (sel_type_cplf & sel_param_low_r), {2{1'b0}}}) | {{4{1'b0}}, (sel_type_vco & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_vco & sel_param_high_i_postscale)}) | {{4{1'b0}}, (sel_type_cplf & sel_param_odd_CP_unused), 1'b0, (sel_type_cplf & sel_param_odd_CP_unused), 1'b0}) | {{4{1'b0}}, {4{(sel_type_cplf & sel_param_high_i_postscale)}}}) | {{3{1'b0}}, (sel_type_n & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_n & sel_param_bypass_LF_unused), 1'b0}) | {{3{1'b0}}, (sel_type_n & sel_param_high_i_postscale), {2{1'b0}}, {2{(sel_type_n & sel_param_high_i_postscale)}}}) | {{3{1'b0}}, {2{(sel_type_n & sel_param_odd_CP_unused)}}, 1'b0, {2{(sel_type_n & sel_param_odd_CP_unused)}}}) | {{3{1'b0}}, {3{(sel_type_n & sel_param_low_r)}}, {2{1'b0}}}) | {{3{1'b0}}, (sel_type_n & sel_param_nominal_count), {2{1'b0}}, (sel_type_n & sel_param_nominal_count), 1'b0}) | {{2{1'b0}}, (sel_type_m & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_m & sel_param_bypass_LF_unused), {2{1'b0}}}) | {{2{1'b0}}, (sel_type_m & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_m & sel_param_high_i_postscale), 1'b0, (sel_type_m & sel_param_high_i_postscale)}) | {{2{1'b0}}, (sel_type_m & sel_param_odd_CP_unused), 1'b0, {2{(sel_type_m & sel_param_odd_CP_unused)}}, 1'b0, (sel_type_m & sel_param_odd_CP_unused)}) | {{2{1'b0}}, (sel_type_m & sel_param_low_r), 1'b0, {3{(sel_type_m & sel_param_low_r)}}, 1'b0}) | {{2{1'b0}}, (sel_type_m & sel_param_nominal_count), {2{1'b0}}, (sel_type_m & sel_param_nominal_count), {2{1'b0}}}) | {{2{1'b0}}, {2{(sel_type_c0 & sel_param_bypass_LF_unused)}}, 1'b0, {2{(sel_type_c0 & sel_param_bypass_LF_unused)}}, 1'b0}) | {{2{1'b0}}, {2{(sel_type_c0 & sel_param_high_i_postscale)}}, 1'b0, {3{(sel_type_c0 & sel_param_high_i_postscale)}}}) | {{2{1'b0}}, {6{(sel_type_c0 & sel_param_odd_CP_unused)}}}) | {1'b0, (sel_type_c0 & sel_param_low_r), {6{1'b0}}}) | {1'b0, (sel_type_c1 & sel_param_bypass_LF_unused
+), {2{1'b0}}, (sel_type_c1 & sel_param_bypass_LF_unused), {3{1'b0}}}) | {1'b0, (sel_type_c1 & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_c1 & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_c1 & sel_param_high_i_postscale)}) | {1'b0, (sel_type_c1 & sel_param_odd_CP_unused), 1'b0, (sel_type_c1 & sel_param_odd_CP_unused), {3{1'b0}}, (sel_type_c1 & sel_param_odd_CP_unused)}) | {1'b0, (sel_type_c1 & sel_param_low_r), 1'b0, (sel_type_c1 & sel_param_low_r), {2{1'b0}}, (sel_type_c1 & sel_param_low_r), 1'b0}) | {1'b0, (sel_type_c2 & sel_param_bypass_LF_unused), 1'b0, {2{(sel_type_c2 & sel_param_bypass_LF_unused)}}, 1'b0, (sel_type_c2 & sel_param_bypass_LF_unused), 1'b0}) | {1'b0, (sel_type_c2 & sel_param_high_i_postscale), 1'b0, {2{(sel_type_c2 & sel_param_high_i_postscale)}}, 1'b0, {2{(sel_type_c2 & sel_param_high_i_postscale)}}}) | {1'b0, {2{(sel_type_c2 & sel_param_odd_CP_unused)}}, {3{1'b0}}, {2{(sel_type_c2 & sel_param_odd_CP_unused)}}}) | {1'b0, {2{(sel_type_c2 & sel_param_low_r)}}, {2{1'b0}}, (sel_type_c2 & sel_param_low_r), {2{1'b0}}}) | {1'b0, {2{(sel_type_c3 & sel_param_bypass_LF_unused)}}, 1'b0, {2{(sel_type_c3 & sel_param_bypass_LF_unused)}}, {2{1'b0}}}) | {1'b0, {2{(sel_type_c3 & sel_param_high_i_postscale)}}, 1'b0, {2{(sel_type_c3 & sel_param_high_i_postscale)}}, 1'b0, (sel_type_c3 & sel_param_high_i_postscale)}) | {1'b0, {3{(sel_type_c3 & sel_param_odd_CP_unused)}}, 1'b0, (sel_type_c3 & sel_param_odd_CP_unused), 1'b0, (sel_type_c3 & sel_param_odd_CP_unused)}) | {1'b0, {3{(sel_type_c3 & sel_param_low_r)}}, 1'b0, {2{(sel_type_c3 & sel_param_low_r)}}, 1'b0}) | {1'b0, {6{(sel_type_c4 & sel_param_bypass_LF_unused)}}, 1'b0}) | {1'b0, {7{(sel_type_c4 & sel_param_high_i_postscale)}}}) | {(sel_type_c4 & sel_param_odd_CP_unused), {4{1'b0}}, {3{(sel_type_c4 & sel_param_odd_CP_unused)}}}) | {(sel_type_c4 & sel_param_low_r), {3{1'b0}}, (sel_type_c4 & sel_param_low_r), {3{1'b0}}}),
+ read_nominal_out = tmp_nominal_data_out_state,
+ reconfig_addr_counter_enable = reconfig_seq_data_state,
+ reconfig_addr_counter_out = wire_cntr12_q,
+ reconfig_addr_counter_sload = reconfig_seq_ena_state,
+ reconfig_addr_counter_sload_value = ({8{reconfig_seq_ena_state}} & seq_addr_wire),
+ reconfig_done = ((~ pll_scandone) & (dummy_scandataout | (~ dummy_scandataout))),
+ reconfig_post_done = pll_scandone,
+ reconfig_width_counter_done = ((((((~ wire_cntr13_q[0]) & (~ wire_cntr13_q[1])) & (~ wire_cntr13_q[2])) & (~ wire_cntr13_q[3])) & (~ wire_cntr13_q[4])) & (~ wire_cntr13_q[5])),
+ reconfig_width_counter_enable = reconfig_seq_data_state,
+ reconfig_width_counter_sload = reconfig_seq_ena_state,
+ reconfig_width_counter_sload_value = ({6{reconfig_seq_ena_state}} & seq_sload_value),
+ rom_address_out = (read_addr_counter_out & {8{((rom_first_state | rom_second_state) | rom_data_state)}}),
+ rom_width_counter_done = ((((((((~ wire_cntr14_q[0]) & (~ wire_cntr14_q[1])) & (~ wire_cntr14_q[2])) & (~ wire_cntr14_q[3])) & (~ wire_cntr14_q[4])) & (~ wire_cntr14_q[5])) & (~ wire_cntr14_q[6])) & (~ wire_cntr14_q[7])),
+ rom_width_counter_enable = ((rom_data_state | rom_last_state) | rom_second_last_state),
+ rom_width_counter_sload = rom_init_state,
+ rom_width_counter_sload_value = const_scan_chain_size,
+ rotate_addr_counter_enable = ((((C0_data_state | C1_data_state) | C2_data_state) | C3_data_state) | C4_data_state),
+ rotate_addr_counter_out = wire_cntr16_q,
+ rotate_addr_counter_sload = ((((C0_ena_state | C1_ena_state) | C2_ena_state) | C3_ena_state) | C4_ena_state),
+ rotate_addr_counter_sload_value = (((((c0_wire & {8{rotate_decoder_wires[0]}}) | (c1_wire & {8{rotate_decoder_wires[1]}})) | (c2_wire & {8{rotate_decoder_wires[2]}})) | (c3_wire & {8{rotate_decoder_wires[3]}})) | (c4_wire & {8{rotate_decoder_wires[4]}})),
+ rotate_decoder_wires = wire_decode11_eq,
+ rotate_width_counter_done = (((((~ wire_cntr15_q[0]) & (~ wire_cntr15_q[1])) & (~ wire_cntr15_q[2])) & (~ wire_cntr15_q[3])) & (~ wire_cntr15_q[4])),
+ rotate_width_counter_enable = ((((C0_data_state | C1_data_state) | C2_data_state) | C3_data_state) | C4_data_state),
+ rotate_width_counter_sload = ((((C0_ena_state | C1_ena_state) | C2_ena_state) | C3_ena_state) | C4_ena_state),
+ rotate_width_counter_sload_value = 5'b10010,
+ scan_cache_address = (((((addr_counter_out & {8{addr_counter_enable}}) | (rotate_addr_counter_out & {8{rotate_addr_counter_enable}})) | (reconfig_addr_counter_out & {8{reconfig_addr_counter_enable}})) | ((read_addr_counter_out & {8{read_addr_counter_enable}}) & {8{(~ (rom_data_state | rom_first_state))}})) | ({8{(rom_width_counter_enable & ((rom_data_state | rom_second_last_state) | rom_last_state))}} & addr_from_rom2)),
+ scan_cache_in = ((shift_reg_serial_out & (~ (((rom_first_state | rom_data_state) | rom_second_last_state) | rom_last_state))) | (rom_data_in & (((rom_first_state | rom_data_state) | rom_second_last_state) | rom_last_state))),
+ scan_cache_out = wire_altsyncram4_q_a[0],
+ scan_cache_write_enable = ((((write_data_state | write_nominal_state) | rom_data_state) | rom_second_last_state) | rom_last_state),
+ sel_param_bypass_LF_unused = (((~ counter_param_latch[0]) & (~ counter_param_latch[1])) & counter_param_latch[2]),
+ sel_param_c = (((~ counter_param_latch[0]) & counter_param_latch[1]) & (~ counter_param_latch[2])),
+ sel_param_high_i_postscale = (((~ counter_param_latch[0]) & (~ counter_param_latch[1])) & (~ counter_param_latch[2])),
+ sel_param_low_r = ((counter_param_latch[0] & (~ counter_param_latch[1])) & (~ counter_param_latch[2])),
+ sel_param_nominal_count = ((counter_param_latch[0] & counter_param_latch[1]) & counter_param_latch[2]),
+ sel_param_odd_CP_unused = ((counter_param_latch[0] & (~ counter_param_latch[1])) & counter_param_latch[2]),
+ sel_type_c0 = ((((~ counter_type_latch[0]) & (~ counter_type_latch[1])) & counter_type_latch[2]) & (~ counter_type_latch[3])),
+ sel_type_c1 = (((counter_type_latch[0] & (~ counter_type_latch[1])) & counter_type_latch[2]) & (~ counter_type_latch[3])),
+ sel_type_c2 = ((((~ counter_type_latch[0]) & counter_type_latch[1]) & counter_type_latch[2]) & (~ counter_type_latch[3])),
+ sel_type_c3 = (((counter_type_latch[0] & counter_type_latch[1]) & counter_type_latch[2]) & (~ counter_type_latch[3])),
+ sel_type_c4 = ((((~ counter_type_latch[0]) & (~ counter_type_latch[1])) & (~ counter_type_latch[2])) & counter_type_latch[3]),
+ sel_type_cplf = ((((~ counter_type_latch[0]) & counter_type_latch[1]) & (~ counter_type_latch[2])) & (~ counter_type_latch[3])),
+ sel_type_m = (((counter_type_latch[0] & (~ counter_type_latch[1])) & (~ counter_type_latch[2])) & (~ counter_type_latch[3])),
+ sel_type_n = ((((~ counter_type_latch[0]) & (~ counter_type_latch[1])) & (~ counter_type_latch[2])) & (~ counter_type_latch[3])),
+ sel_type_vco = (((counter_type_latch[0] & counter_type_latch[1]) & (~ counter_type_latch[2])) & (~ counter_type_latch[3])),
+ seq_addr_wire = 8'b00110101,
+ seq_sload_value = 6'b110110,
+ shift_reg_clear = (read_init_state | read_init_nominal_state),
+ shift_reg_load_enable = ((idle_state & write_param) & (~ ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0]))),
+ shift_reg_load_nominal_enable = ((idle_state & write_param) & ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0])),
+ shift_reg_serial_in = scan_cache_out,
+ shift_reg_serial_out = ((((((((shift_reg17[0:0] & shift_reg_width_select[0]) | (shift_reg17[0:0] & shift_reg_width_select[1])) | (shift_reg17[0:0] & shift_reg_width_select[2])) | (shift_reg17[0:0] & shift_reg_width_select[3])) | (shift_reg17[0:0] & shift_reg_width_select[4])) | (shift_reg17[0:0] & shift_reg_width_select[5])) | (shift_reg17[0:0] & shift_reg_width_select[6])) | (shift_reg17[0:0] & shift_reg_width_select[7])),
+ shift_reg_shift_enable = ((read_data_state | read_last_state) | write_data_state),
+ shift_reg_shift_nominal_enable = ((read_data_nominal_state | read_last_nominal_state) | write_nominal_state),
+ shift_reg_width_select = width_decoder_select,
+ w1565w = 1'b0,
+ w1592w = 1'b0,
+ w64w = 1'b0,
+ width_counter_done = (((((~ wire_cntr3_q[0]) & (~ wire_cntr3_q[1])) & (~ wire_cntr3_q[2])) & (~ wire_cntr3_q[3])) & (~ wire_cntr3_q[4])),
+ width_counter_enable = ((((read_first_state | read_data_state) | write_data_state) | read_data_nominal_state) | write_nominal_state),
+ width_counter_sload = (((read_init_state | write_init_state) | read_init_nominal_state) | write_init_nominal_state),
+ width_counter_sload_value = width_decoder_out,
+ width_decoder_out = ((((({5{1'b0}} | {width_decoder_select[2], {3{1'b0}}, width_decoder_select[2]}) | {{4{1'b0}}, width_decoder_select[3]}) | {{2{1'b0}}, {3{width_decoder_select[5]}}}) | {{3{1'b0}}, width_decoder_select[6], 1'b0}) | {{2{1'b0}}, width_decoder_select[7], {2{1'b0}}}),
+ width_decoder_select = {((sel_type_cplf & sel_param_low_r) | (sel_type_cplf & sel_param_odd_CP_unused)), (sel_type_cplf & sel_param_high_i_postscale), ((((((((((((((sel_type_n & sel_param_high_i_postscale) | (sel_type_n & sel_param_low_r)) | (sel_type_m & sel_param_high_i_postscale)) | (sel_type_m & sel_param_low_r)) | (sel_type_c0 & sel_param_high_i_postscale)) | (sel_type_c0 & sel_param_low_r)) | (sel_type_c1 & sel_param_high_i_postscale)) | (sel_type_c1 & sel_param_low_r)) | (sel_type_c2 & sel_param_high_i_postscale)) | (sel_type_c2 & sel_param_low_r)) | (sel_type_c3 & sel_param_high_i_postscale)) | (sel_type_c3 & sel_param_low_r)) | (sel_type_c4 & sel_param_high_i_postscale)) | (sel_type_c4 & sel_param_low_r)), w1592w, ((sel_type_cplf & sel_param_bypass_LF_unused) | (sel_type_cplf & sel_param_c)), ((sel_type_n & sel_param_nominal_count) | (sel_type_m & sel_param_nominal_count)), w1565w, (((((((((((((((sel_type_vco & sel_param_high_i_postscale) | (sel_type_n & sel_param_bypass_LF_unused)) | (sel_type_n & sel_param_odd_CP_unused)) | (sel_type_m & sel_param_bypass_LF_unused)) | (sel_type_m & sel_param_odd_CP_unused)) | (sel_type_c0 & sel_param_bypass_LF_unused)) | (sel_type_c0 & sel_param_odd_CP_unused)) | (sel_type_c1 & sel_param_bypass_LF_unused)) | (sel_type_c1 & sel_param_odd_CP_unused)) | (sel_type_c2 & sel_param_bypass_LF_unused)) | (sel_type_c2 & sel_param_odd_CP_unused)) | (sel_type_c3 & sel_param_bypass_LF_unused)) | (sel_type_c3 & sel_param_odd_CP_unused)) | (sel_type_c4 & sel_param_bypass_LF_unused)) | (sel_type_c4 & sel_param_odd_CP_unused))},
+ write_rom_ena = ((rom_first_state | rom_second_state) | (rom_data_state & (~ rom_width_counter_done)));
+endmodule //pll_reconfig_pllrcfg_dc61
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll_reconfig (
+ clock,
+ counter_param,
+ counter_type,
+ data_in,
+ pll_areset_in,
+ pll_scandataout,
+ pll_scandone,
+ read_param,
+ reconfig,
+ reset,
+ reset_rom_address,
+ rom_data_in,
+ write_from_rom,
+ write_param,
+ busy,
+ data_out,
+ pll_areset,
+ pll_configupdate,
+ pll_scanclk,
+ pll_scanclkena,
+ pll_scandata,
+ rom_address_out,
+ write_rom_ena)/* synthesis synthesis_clearbox = 2 */;
+
+ input clock;
+ input [2:0] counter_param;
+ input [3:0] counter_type;
+ input [8:0] data_in;
+ input pll_areset_in;
+ input pll_scandataout;
+ input pll_scandone;
+ input read_param;
+ input reconfig;
+ input reset;
+ input reset_rom_address;
+ input rom_data_in;
+ input write_from_rom;
+ input write_param;
+ output busy;
+ output [8:0] data_out;
+ output pll_areset;
+ output pll_configupdate;
+ output pll_scanclk;
+ output pll_scanclkena;
+ output pll_scandata;
+ output [7:0] rom_address_out;
+ output write_rom_ena;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri0 pll_areset_in;
+ tri0 reset_rom_address;
+ tri0 rom_data_in;
+ tri0 write_from_rom;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ wire sub_wire0;
+ wire [8:0] sub_wire1;
+ wire sub_wire2;
+ wire sub_wire3;
+ wire sub_wire4;
+ wire [7:0] sub_wire5;
+ wire sub_wire6;
+ wire sub_wire7;
+ wire sub_wire8;
+ wire pll_configupdate = sub_wire0;
+ wire [8:0] data_out = sub_wire1[8:0];
+ wire pll_scanclk = sub_wire2;
+ wire pll_scanclkena = sub_wire3;
+ wire pll_scandata = sub_wire4;
+ wire [7:0] rom_address_out = sub_wire5[7:0];
+ wire busy = sub_wire6;
+ wire pll_areset = sub_wire7;
+ wire write_rom_ena = sub_wire8;
+
+ pll_reconfig_pllrcfg_dc61 pll_reconfig_pllrcfg_dc61_component (
+ .counter_param (counter_param),
+ .data_in (data_in),
+ .counter_type (counter_type),
+ .pll_areset_in (pll_areset_in),
+ .pll_scandataout (pll_scandataout),
+ .pll_scandone (pll_scandone),
+ .reset (reset),
+ .write_from_rom (write_from_rom),
+ .write_param (write_param),
+ .clock (clock),
+ .read_param (read_param),
+ .reconfig (reconfig),
+ .reset_rom_address (reset_rom_address),
+ .rom_data_in (rom_data_in),
+ .pll_configupdate (sub_wire0),
+ .data_out (sub_wire1),
+ .pll_scanclk (sub_wire2),
+ .pll_scanclkena (sub_wire3),
+ .pll_scandata (sub_wire4),
+ .rom_address_out (sub_wire5),
+ .busy (sub_wire6),
+ .pll_areset (sub_wire7),
+ .write_rom_ena (sub_wire8))/* synthesis synthesis_clearbox=2
+ clearbox_macroname = altpll_reconfig
+ clearbox_defparam = "init_from_rom=NO;intended_device_family=Cyclone III;scan_init_file=./pll_c16_pal.mif;" */;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: CHAIN_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_NAME STRING "./pll_c16_pal.mif"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_INIT_FILE STRING "1"
+// Retrieval info: CONSTANT: INIT_FROM_ROM STRING "NO"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: SCAN_INIT_FILE STRING "./pll_c16_pal.mif"
+// Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+// Retrieval info: USED_PORT: counter_param 0 0 3 0 INPUT NODEFVAL "counter_param[2..0]"
+// Retrieval info: USED_PORT: counter_type 0 0 4 0 INPUT NODEFVAL "counter_type[3..0]"
+// Retrieval info: USED_PORT: data_in 0 0 9 0 INPUT NODEFVAL "data_in[8..0]"
+// Retrieval info: USED_PORT: data_out 0 0 9 0 OUTPUT NODEFVAL "data_out[8..0]"
+// Retrieval info: USED_PORT: pll_areset 0 0 0 0 OUTPUT NODEFVAL "pll_areset"
+// Retrieval info: USED_PORT: pll_areset_in 0 0 0 0 INPUT GND "pll_areset_in"
+// Retrieval info: USED_PORT: pll_configupdate 0 0 0 0 OUTPUT NODEFVAL "pll_configupdate"
+// Retrieval info: USED_PORT: pll_scanclk 0 0 0 0 OUTPUT NODEFVAL "pll_scanclk"
+// Retrieval info: USED_PORT: pll_scanclkena 0 0 0 0 OUTPUT NODEFVAL "pll_scanclkena"
+// Retrieval info: USED_PORT: pll_scandata 0 0 0 0 OUTPUT NODEFVAL "pll_scandata"
+// Retrieval info: USED_PORT: pll_scandataout 0 0 0 0 INPUT NODEFVAL "pll_scandataout"
+// Retrieval info: USED_PORT: pll_scandone 0 0 0 0 INPUT NODEFVAL "pll_scandone"
+// Retrieval info: USED_PORT: read_param 0 0 0 0 INPUT NODEFVAL "read_param"
+// Retrieval info: USED_PORT: reconfig 0 0 0 0 INPUT NODEFVAL "reconfig"
+// Retrieval info: USED_PORT: reset 0 0 0 0 INPUT NODEFVAL "reset"
+// Retrieval info: USED_PORT: reset_rom_address 0 0 0 0 INPUT GND "reset_rom_address"
+// Retrieval info: USED_PORT: rom_address_out 0 0 8 0 OUTPUT NODEFVAL "rom_address_out[7..0]"
+// Retrieval info: USED_PORT: rom_data_in 0 0 0 0 INPUT GND "rom_data_in"
+// Retrieval info: USED_PORT: write_from_rom 0 0 0 0 INPUT GND "write_from_rom"
+// Retrieval info: USED_PORT: write_param 0 0 0 0 INPUT NODEFVAL "write_param"
+// Retrieval info: USED_PORT: write_rom_ena 0 0 0 0 OUTPUT NODEFVAL "write_rom_ena"
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @counter_param 0 0 3 0 counter_param 0 0 3 0
+// Retrieval info: CONNECT: @counter_type 0 0 4 0 counter_type 0 0 4 0
+// Retrieval info: CONNECT: @data_in 0 0 9 0 data_in 0 0 9 0
+// Retrieval info: CONNECT: @pll_areset_in 0 0 0 0 pll_areset_in 0 0 0 0
+// Retrieval info: CONNECT: @pll_scandataout 0 0 0 0 pll_scandataout 0 0 0 0
+// Retrieval info: CONNECT: @pll_scandone 0 0 0 0 pll_scandone 0 0 0 0
+// Retrieval info: CONNECT: @read_param 0 0 0 0 read_param 0 0 0 0
+// Retrieval info: CONNECT: @reconfig 0 0 0 0 reconfig 0 0 0 0
+// Retrieval info: CONNECT: @reset 0 0 0 0 reset 0 0 0 0
+// Retrieval info: CONNECT: @reset_rom_address 0 0 0 0 reset_rom_address 0 0 0 0
+// Retrieval info: CONNECT: @rom_data_in 0 0 0 0 rom_data_in 0 0 0 0
+// Retrieval info: CONNECT: @write_from_rom 0 0 0 0 write_from_rom 0 0 0 0
+// Retrieval info: CONNECT: @write_param 0 0 0 0 write_param 0 0 0 0
+// Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
+// Retrieval info: CONNECT: data_out 0 0 9 0 @data_out 0 0 9 0
+// Retrieval info: CONNECT: pll_areset 0 0 0 0 @pll_areset 0 0 0 0
+// Retrieval info: CONNECT: pll_configupdate 0 0 0 0 @pll_configupdate 0 0 0 0
+// Retrieval info: CONNECT: pll_scanclk 0 0 0 0 @pll_scanclk 0 0 0 0
+// Retrieval info: CONNECT: pll_scanclkena 0 0 0 0 @pll_scanclkena 0 0 0 0
+// Retrieval info: CONNECT: pll_scandata 0 0 0 0 @pll_scandata 0 0 0 0
+// Retrieval info: CONNECT: rom_address_out 0 0 8 0 @rom_address_out 0 0 8 0
+// Retrieval info: CONNECT: write_rom_ena 0 0 0 0 @write_rom_ena 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_reconfig.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_reconfig.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_reconfig.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_reconfig.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_reconfig_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_reconfig_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: LIB_FILE: cycloneiii
+// Retrieval info: LIB_FILE: lpm
diff --git a/cores/c16/rom_reconfig_ntsc.qip b/cores/c16/rom_reconfig_ntsc.qip
new file mode 100644
index 0000000..8103d80
--- /dev/null
+++ b/cores/c16/rom_reconfig_ntsc.qip
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "rom_reconfig_ntsc.v"]
diff --git a/cores/c16/rom_reconfig_ntsc.v b/cores/c16/rom_reconfig_ntsc.v
new file mode 100644
index 0000000..ebff5a6
--- /dev/null
+++ b/cores/c16/rom_reconfig_ntsc.v
@@ -0,0 +1,164 @@
+// megafunction wizard: %ROM: 1-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram
+
+// ============================================================
+// File Name: rom_reconfig_ntsc.v
+// Megafunction Name(s):
+// altsyncram
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.4 Build 182 03/12/2014 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2014 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module rom_reconfig_ntsc (
+ address,
+ clock,
+ rden,
+ q);
+
+ input [7:0] address;
+ input clock;
+ input rden;
+ output [0:0] q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri1 clock;
+ tri1 rden;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ wire [0:0] sub_wire0;
+ wire [0:0] q = sub_wire0[0:0];
+
+ altsyncram altsyncram_component (
+ .address_a (address),
+ .clock0 (clock),
+ .rden_a (rden),
+ .q_a (sub_wire0),
+ .aclr0 (1'b0),
+ .aclr1 (1'b0),
+ .address_b (1'b1),
+ .addressstall_a (1'b0),
+ .addressstall_b (1'b0),
+ .byteena_a (1'b1),
+ .byteena_b (1'b1),
+ .clock1 (1'b1),
+ .clocken0 (1'b1),
+ .clocken1 (1'b1),
+ .clocken2 (1'b1),
+ .clocken3 (1'b1),
+ .data_a (1'b1),
+ .data_b (1'b1),
+ .eccstatus (),
+ .q_b (),
+ .rden_b (1'b1),
+ .wren_a (1'b0),
+ .wren_b (1'b0));
+ defparam
+ altsyncram_component.address_aclr_a = "NONE",
+ altsyncram_component.clock_enable_input_a = "BYPASS",
+ altsyncram_component.clock_enable_output_a = "BYPASS",
+ altsyncram_component.init_file = "pll_c16_ntsc.mif",
+ altsyncram_component.intended_device_family = "Cyclone III",
+ altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
+ altsyncram_component.lpm_type = "altsyncram",
+ altsyncram_component.numwords_a = 256,
+ altsyncram_component.operation_mode = "ROM",
+ altsyncram_component.outdata_aclr_a = "NONE",
+ altsyncram_component.outdata_reg_a = "CLOCK0",
+ altsyncram_component.widthad_a = 8,
+ altsyncram_component.width_a = 1,
+ altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clken NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING "pll_c16_ntsc.mif"
+// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
+// Retrieval info: PRIVATE: WidthData NUMERIC "1"
+// Retrieval info: PRIVATE: rden NUMERIC "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: INIT_FILE STRING "pll_c16_ntsc.mif"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
+// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
+// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 1 0 @q_a 0 0 1 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/cores/c16/rom_reconfig_pal.qip b/cores/c16/rom_reconfig_pal.qip
new file mode 100644
index 0000000..dee85fc
--- /dev/null
+++ b/cores/c16/rom_reconfig_pal.qip
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "rom_reconfig_pal.v"]
diff --git a/cores/c16/rom_reconfig_pal.v b/cores/c16/rom_reconfig_pal.v
new file mode 100644
index 0000000..7813fa3
--- /dev/null
+++ b/cores/c16/rom_reconfig_pal.v
@@ -0,0 +1,164 @@
+// megafunction wizard: %ROM: 1-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram
+
+// ============================================================
+// File Name: rom_reconfig_pal.v
+// Megafunction Name(s):
+// altsyncram
+//
+// Simulation Library Files(s):
+// altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.4 Build 182 03/12/2014 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2014 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files from any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module rom_reconfig_pal (
+ address,
+ clock,
+ rden,
+ q);
+
+ input [7:0] address;
+ input clock;
+ input rden;
+ output [0:0] q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+ tri1 clock;
+ tri1 rden;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+ wire [0:0] sub_wire0;
+ wire [0:0] q = sub_wire0[0:0];
+
+ altsyncram altsyncram_component (
+ .address_a (address),
+ .clock0 (clock),
+ .rden_a (rden),
+ .q_a (sub_wire0),
+ .aclr0 (1'b0),
+ .aclr1 (1'b0),
+ .address_b (1'b1),
+ .addressstall_a (1'b0),
+ .addressstall_b (1'b0),
+ .byteena_a (1'b1),
+ .byteena_b (1'b1),
+ .clock1 (1'b1),
+ .clocken0 (1'b1),
+ .clocken1 (1'b1),
+ .clocken2 (1'b1),
+ .clocken3 (1'b1),
+ .data_a (1'b1),
+ .data_b (1'b1),
+ .eccstatus (),
+ .q_b (),
+ .rden_b (1'b1),
+ .wren_a (1'b0),
+ .wren_b (1'b0));
+ defparam
+ altsyncram_component.address_aclr_a = "NONE",
+ altsyncram_component.clock_enable_input_a = "BYPASS",
+ altsyncram_component.clock_enable_output_a = "BYPASS",
+ altsyncram_component.init_file = "pll_c16_pal.mif",
+ altsyncram_component.intended_device_family = "Cyclone III",
+ altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
+ altsyncram_component.lpm_type = "altsyncram",
+ altsyncram_component.numwords_a = 256,
+ altsyncram_component.operation_mode = "ROM",
+ altsyncram_component.outdata_aclr_a = "NONE",
+ altsyncram_component.outdata_reg_a = "CLOCK0",
+ altsyncram_component.widthad_a = 8,
+ altsyncram_component.width_a = 1,
+ altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clken NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING "pll_c16_pal.mif"
+// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
+// Retrieval info: PRIVATE: WidthData NUMERIC "1"
+// Retrieval info: PRIVATE: rden NUMERIC "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: INIT_FILE STRING "pll_c16_pal.mif"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
+// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
+// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 1 0 @q_a 0 0 1 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf