diff --git a/cores/bbc/fpga/mist/bbc_mist_top.qsf b/cores/bbc/fpga/mist/bbc_mist_top.qsf index f0905ab..4a4f3d7 100644 --- a/cores/bbc/fpga/mist/bbc_mist_top.qsf +++ b/cores/bbc/fpga/mist/bbc_mist_top.qsf @@ -159,7 +159,14 @@ set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON set_global_assignment -name VERILOG_FILE bbc_mist_top.v +set_global_assignment -name SYSTEMVERILOG_FILE rgb2ypbpr.sv set_global_assignment -name VERILOG_FILE sdram.v set_global_assignment -name VERILOG_FILE sd_card.v set_global_assignment -name VERILOG_FILE user_io.v @@ -199,10 +206,4 @@ set_global_assignment -name QIP_FILE os12.qip set_global_assignment -name QIP_FILE basic2.qip set_global_assignment -name QIP_FILE dfs09.qip set_global_assignment -name SDC_FILE bbc_mist.sdc -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/cores/bbc/fpga/mist/bbc_mist_top.v b/cores/bbc/fpga/mist/bbc_mist_top.v index 7f6b20a..2f2e82e 100755 --- a/cores/bbc/fpga/mist/bbc_mist_top.v +++ b/cores/bbc/fpga/mist/bbc_mist_top.v @@ -109,7 +109,8 @@ always @(posedge clk_24m) clk_12m <= !clk_12m; wire ce_pix = scandoubler_disable?clk_12m:1'd1; - +wire [5:0] osd_r_o, osd_g_o, osd_b_o; + osd #(0,0,4) OSD ( .clk_sys ( clk_24m ), .ce_pix ( ce_pix ), @@ -123,22 +124,37 @@ osd #(0,0,4) OSD ( .green_in ( scandoubler_disable? {5{video_g[0]}} : {3{video_g}} ), .blue_in ( scandoubler_disable? {5{video_b[0]}} : {3{video_b}} ), - .hs_in ( video_hs ), - .vs_in ( video_vs ), + .hs_in ( video_hs ), + .vs_in ( video_vs ), - .red_out ( VGA_R ), - .green_out ( VGA_G ), - .blue_out ( VGA_B ), + .red_out ( osd_r_o ), + .green_out ( osd_g_o ), + .blue_out ( osd_b_o ), .hs_out ( v_hs ), .vs_out ( v_vs ) ); +wire [5:0] Y, Pb, Pr; + +rgb2ypbpr rgb2ypbpr +( + .red ( osd_r_o ), + .green ( osd_g_o ), + .blue ( osd_b_o ), + .y ( Y ), + .pb ( Pb ), + .pr ( Pr ) +); + wire v_hs, v_vs; // create composite sync for 15khz wire csync = !(v_vs ^ v_hs); -assign VGA_HS = scandoubler_disable?csync:v_hs; -assign VGA_VS = scandoubler_disable?1'b1:v_vs; +assign VGA_HS = (scandoubler_disable || ypbpr) ?csync:v_hs; +assign VGA_VS = (scandoubler_disable || ypbpr) ?1'b1:v_vs; +assign VGA_R = ypbpr?Pr:osd_r_o; +assign VGA_G = ypbpr? Y:osd_g_o; +assign VGA_B = ypbpr?Pb:osd_b_o; // conections between user_io (implementing the SPIU communication // to the io controller) and the legacy @@ -163,6 +179,7 @@ wire [15:0] joystick_analog_0; wire [15:0] joystick_analog_1; wire scandoubler_disable; +wire ypbpr; user_io #(.STRLEN(CONF_STR_LEN)) user_io( .conf_str ( CONF_STR ), @@ -185,6 +202,7 @@ user_io #(.STRLEN(CONF_STR_LEN)) user_io( .switches ( switches ), .buttons ( buttons ), .scandoubler_disable ( scandoubler_disable ), + .ypbpr ( ypbpr ), // interface to embedded legacy sd card wrapper .sd_lba ( sd_lba ), diff --git a/cores/bbc/fpga/mist/rgb2ypbpr.sv b/cores/bbc/fpga/mist/rgb2ypbpr.sv new file mode 100644 index 0000000..1e1662e --- /dev/null +++ b/cores/bbc/fpga/mist/rgb2ypbpr.sv @@ -0,0 +1,55 @@ +module rgb2ypbpr ( + input [5:0] red, + input [5:0] green, + input [5:0] blue, + + output [5:0] y, + output [5:0] pb, + output [5:0] pr +); + +wire [5:0] yuv_full[225] = '{ + 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, + 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, + 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, + 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, + 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, + 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, + 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, + 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, + 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, + 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, + 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, + 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, + 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, + 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, + 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, + 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, + 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, + 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, + 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, + 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, + 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, + 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, + 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, + 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, + 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, + 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, + 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, + 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, + 6'd63 +}; + +wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); +wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); +wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); + +wire [7:0] y_i = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; +wire [7:0] pb_i = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; +wire [7:0] pr_i = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; + +assign pr = yuv_full[pr_i - 8'd16]; +assign y = yuv_full[y_i - 8'd16]; +assign pb = yuv_full[pb_i - 8'd16]; + +endmodule