From 362459dbd80e15cb5855dd37a64d0b5960ce90bc Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi Date: Thu, 6 Sep 2018 14:02:24 +0200 Subject: [PATCH] C64: cleanup redundant files --- cores/c64/C64_mist.qsf | 3 - cores/c64/rtl/c64_mist.vhd.bak | 1012 -------------------------------- cores/c64/rtl/m6522.vhd | 919 ----------------------------- cores/c64/rtl/sd_card.sv | 142 ----- 4 files changed, 2076 deletions(-) delete mode 100644 cores/c64/rtl/c64_mist.vhd.bak delete mode 100644 cores/c64/rtl/m6522.vhd delete mode 100644 cores/c64/rtl/sd_card.sv diff --git a/cores/c64/C64_mist.qsf b/cores/c64/C64_mist.qsf index ce3ffd4..b53e259 100644 --- a/cores/c64/C64_mist.qsf +++ b/cores/c64/C64_mist.qsf @@ -328,8 +328,6 @@ set_global_assignment -name VHDL_FILE rtl/fpga64_rgbcolor.vhd set_global_assignment -name VHDL_FILE rtl/fpga64_keyboard_matrix_mark_mcdougall.vhd set_global_assignment -name VHDL_FILE rtl/fpga64_bustiming.vhd set_global_assignment -name VHDL_FILE rtl/fpga64_buslogic_roms_mmu.vhd -set_global_assignment -name VHDL_FILE rtl/cpu65xx_fast.vhd -set_global_assignment -name VHDL_FILE rtl/cpu65xx_e.vhd set_global_assignment -name VHDL_FILE rtl/cia6526.vhd set_global_assignment -name VHDL_FILE rtl/cpu_6510.vhd set_global_assignment -name VERILOG_FILE rtl/cartridge.v @@ -339,7 +337,6 @@ set_global_assignment -name VHDL_FILE rtl/rom_GS64.vhd set_global_assignment -name VERILOG_FILE rtl/sigma_delta_dac.v set_global_assignment -name SYSTEMVERILOG_FILE rtl/video_mixer.sv set_global_assignment -name VERILOG_FILE rtl/sdram.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/sd_card.sv set_global_assignment -name VERILOG_FILE rtl/scandoubler.v set_global_assignment -name VHDL_FILE rtl/pll.vhd set_global_assignment -name VERILOG_FILE rtl/osd.v diff --git a/cores/c64/rtl/c64_mist.vhd.bak b/cores/c64/rtl/c64_mist.vhd.bak deleted file mode 100644 index ece31ca..0000000 --- a/cores/c64/rtl/c64_mist.vhd.bak +++ /dev/null @@ -1,1012 +0,0 @@ ---------------------------------------------------------------------------------- --- DE2-35 Top level for FPGA64_027 by Dar (darfpga@aol.fr) --- http://darfpga.blogspot.fr --- --- FPGA64 is Copyrighted 2005-2008 by Peter Wendrich (pwsoft@syntiac.com) --- http://www.syntiac.com/fpga64.html --- --- Main features --- 15KHz(TV) / 31Khz(VGA) : board switch(0) --- PAL(50Hz) / NTSC(60Hz) : board switch(1) and F12 key --- PS2 keyboard input with portA / portB joystick emulation : F11 key --- wm8731 sound output --- 64Ko of board SRAM used --- External IEC bus available at gpio_1 (for drive 1541 or IEC/SD ...) --- activated by switch(5) (activated with no hardware will stuck IEC bus) --- --- Internal emulated 1541 on raw SD card : D64 images start at 25x6KB boundaries --- Use hexidecimal disk editor such as HxD (www.mh-nexus.de) to build SD card. --- Cut D64 file and paste at 0x00000 (first), 0x40000 (second), 0x80000 (third), --- 0xC0000(fourth), 0x100000(fith), 0x140000 (sixth) and so on. --- BE CAREFUL NOT WRITING ON YOUR OWN HARDDRIVE --- --- Uses only one pll for 32MHz and 18MHz generation from 50MHz --- DE1 and DE0 nano Top level also available --- ---------------------------------------------------------------------------------- - -library IEEE; -use IEEE.std_logic_1164.all; -use IEEE.std_logic_unsigned.ALL; -use IEEE.numeric_std.all; - -entity c64_mist is port -( - -- Clocks - CLOCK_27 : in std_logic; - - -- LED - LED : out std_logic; - - -- VGA - VGA_R : out std_logic_vector(5 downto 0); - VGA_G : out std_logic_vector(5 downto 0); - VGA_B : out std_logic_vector(5 downto 0); - VGA_HS : out std_logic; - VGA_VS : out std_logic; - - -- SDRAM - SDRAM_A : out std_logic_vector(12 downto 0); - SDRAM_DQ : inout std_logic_vector(15 downto 0); - SDRAM_DQML : out std_logic; - SDRAM_DQMH : out std_logic; - SDRAM_nWE : out std_logic; - SDRAM_nCAS : out std_logic; - SDRAM_nRAS : out std_logic; - SDRAM_nCS : out std_logic; - SDRAM_BA : out std_logic_vector(1 downto 0); - SDRAM_CLK : out std_logic; - SDRAM_CKE : out std_logic; - - -- AUDIO - AUDIO_L : out std_logic; - AUDIO_R : out std_logic; - - -- SPI interface to io controller - SPI_SCK : in std_logic; - SPI_DO : inout std_logic; - SPI_DI : in std_logic; - SPI_SS2 : in std_logic; - SPI_SS3 : in std_logic; - CONF_DATA0 : in std_logic -); -end c64_mist; - -architecture struct of c64_mist is - -component sdram is port -( - -- interface to the MT48LC16M16 chip - sd_addr : out std_logic_vector(12 downto 0); - sd_cs : out std_logic; - sd_ba : out std_logic_vector(1 downto 0); - sd_we : out std_logic; - sd_ras : out std_logic; - sd_cas : out std_logic; - - -- system interface - clk : in std_logic; - init : in std_logic; - - -- cpu/chipset interface - addr : in std_logic_vector(24 downto 0); - refresh : in std_logic; - we : in std_logic; - ce : in std_logic -); -end component; - -component sram is port -( - init : in std_logic; - clk : in std_logic; - SDRAM_DQ : inout std_logic_vector(15 downto 0); - SDRAM_A : out std_logic_vector(12 downto 0); - SDRAM_DQML : out std_logic; - SDRAM_DQMH : out std_logic; - SDRAM_BA : out std_logic_vector(1 downto 0); - SDRAM_nCS : out std_logic; - SDRAM_nWE : out std_logic; - SDRAM_nRAS : out std_logic; - SDRAM_nCAS : out std_logic; - SDRAM_CKE : out std_logic; - - wtbt : in std_logic_vector(1 downto 0); - addr : in std_logic_vector(24 downto 0); - dout : out std_logic_vector(15 downto 0); - din : in std_logic_vector(15 downto 0); - we : in std_logic; - rd : in std_logic; - ready : out std_logic -); -end component; - ---------- --- Mist IO ---------- - --- config string used by the io controller to fill the OSD ---constant CONF_STR : string := "C64;PRG;S1,D64;O2,Video standard,PAL,NTSC;O8A,Scandoubler Fx,None,HQ2x-320,HQ2x-160,CRT 25%,CRT 50%;O3,Joysticks,normal,swapped;O6,Audio filter,On,Off;T5,Reset;V0,v0.27.33"; -constant CONF_STR : string := "C64;;"& -"S,D64,Mount Disk;"& -"F,PRG,Load File;"& -"F,CRT,Load Cartridge;" & -"O2,Video standard,PAL,NTSC;"& -"O8A,Scandoubler Fx,None,HQ2x-320,HQ2x-160,CRT 25%,CRT 50%;"& -"O3,Joysticks,normal,swapped;"& -"O6,Audio filter,On,Off;"& ---"OB,BIOS,C64,C64GS;" & ---"T5,Reset;"& -"V0,v0.30.30"; - --- convert string to std_logic_vector to be given to user_io -function to_slv(s: string) return std_logic_vector is - constant ss: string(1 to s'length) := s; - variable rval: std_logic_vector(1 to 8 * s'length); - variable p: integer; - variable c: integer; -begin - for i in ss'range loop - p := 8 * i; - c := character'pos(ss(i)); - rval(p - 7 to p) := std_logic_vector(to_unsigned(c,8)); - end loop; - return rval; -end function; - - -component mist_io generic(STRLEN : integer := 0 ); port -( - clk_sys : in std_logic; - - SPI_SCK : in std_logic; - CONF_DATA0 : in std_logic; - SPI_SS2 : in std_logic; - SPI_DI : in std_logic; - SPI_DO : out std_logic; - conf_str : in std_logic_vector(8*STRLEN-1 downto 0); - - switches : out std_logic_vector(1 downto 0); - buttons : out std_logic_vector(1 downto 0); - scandoubler_disable : out std_logic; - ypbpr : out std_logic; - - joystick_0 : out std_logic_vector(7 downto 0); - joystick_1 : out std_logic_vector(7 downto 0); - joystick_analog_0 : out std_logic_vector(15 downto 0); - joystick_analog_1 : out std_logic_vector(15 downto 0); - status : out std_logic_vector(31 downto 0); - - sd_lba : in std_logic_vector(31 downto 0); - sd_rd : in std_logic; - sd_wr : in std_logic; - sd_ack : out std_logic; - sd_ack_conf : out std_logic; - sd_conf : in std_logic; - sd_sdhc : in std_logic; - img_mounted : out std_logic; - - sd_buff_addr : out std_logic_vector(8 downto 0); - sd_buff_dout : out std_logic_vector(7 downto 0); - sd_buff_din : in std_logic_vector(7 downto 0); - sd_buff_wr : out std_logic; - - ps2_kbd_clk : out std_logic; - ps2_kbd_data : out std_logic; - - ps2_mouse_clk : out std_logic; - ps2_mouse_data : out std_logic; - - ioctl_force_erase : in std_logic; - ioctl_download : out std_logic; - ioctl_erasing : out std_logic; - ioctl_index : out std_logic_vector(7 downto 0); - ioctl_wr : out std_logic; - ioctl_addr : out std_logic_vector(24 downto 0); - ioctl_dout : out std_logic_vector(7 downto 0) - ); -end component mist_io; - -component video_mixer - generic ( LINE_LENGTH : integer := 512; HALF_DEPTH : integer := 0 ); - port ( - clk_sys, ce_pix, ce_pix_actual : in std_logic; - SPI_SCK, SPI_SS3, SPI_DI : in std_logic; - scanlines : in std_logic_vector(1 downto 0); - scandoubler_disable, hq2x, ypbpr, ypbpr_full : in std_logic; - - R, G, B : in std_logic_vector(5 downto 0); - HSync, VSync, line_start, mono : in std_logic; - - VGA_R,VGA_G, VGA_B : out std_logic_vector(5 downto 0); - VGA_VS, VGA_HS : out std_logic - ); -end component video_mixer; - ---------- --- OSD ---------- - -component osd generic ( OSD_COLOR : std_logic_vector(2 downto 0)); port -( - clk_sys : in std_logic; - ce_pix : in std_logic; - - SPI_SCK : in std_logic; - SPI_SS3 : in std_logic; - SPI_DI : in std_logic; - - -- VGA signals coming from core - VGA_Rx : in std_logic_vector(5 downto 0); - VGA_Gx : in std_logic_vector(5 downto 0); - VGA_Bx : in std_logic_vector(5 downto 0); - OSD_HS : in std_logic; - OSD_VS : in std_logic; - - -- VGA signals going to video connector - VGA_R : out std_logic_vector(5 downto 0); - VGA_G : out std_logic_vector(5 downto 0); - VGA_B : out std_logic_vector(5 downto 0) -); -end component osd; - ---------- --- Scan doubler ---------- -component scandoubler is port -( - clk_sys : in std_logic; - ce_x2 : in std_logic; - ce_x1 : in std_logic; - scanlines : in std_logic_vector(1 downto 0); - - -- c64 input - r_in : in std_logic_vector(5 downto 0); - g_in : in std_logic_vector(5 downto 0); - b_in : in std_logic_vector(5 downto 0); - hs_in : in std_logic; - vs_in : in std_logic; - - -- vga output - r_out : out std_logic_vector(5 downto 0); - g_out : out std_logic_vector(5 downto 0); - b_out : out std_logic_vector(5 downto 0); - hs_out : out std_logic; - vs_out : out std_logic -); -end component; - ---------- --- audio ---------- - -component sigma_delta_dac port -( - CLK : in std_logic; - RESET : in std_logic; - DACin : in std_logic_vector(14 downto 0); - DACout : out std_logic -); - -end component sigma_delta_dac; - - --------------------------- --- cartridge - LCA mar17 - --------------------------- -component cartridge port -( - romL : in std_logic; -- romL signal in - romH : in std_logic; -- romH signal in - UMAXromH : in std_logic; -- VIC II ultimax read access flag - mem_write : in std_logic; -- memory write active - mem_ce : in std_logic; - mem_ce_out : out std_logic; - IOE : in std_logic; -- IOE signal &DE00 - IOF : in std_logic; -- IOF signal &DF00 - - clk32 : in std_logic; -- 32mhz clock source - reset : in std_logic; -- reset signal - reset_out : out std_logic; -- reset signal - - cart_id : in std_logic_vector(15 downto 0); -- cart ID or cart type - cart_exrom : in std_logic_vector(7 downto 0); -- CRT file EXROM status - cart_game : in std_logic_vector(7 downto 0); -- CRT file GAME status - - cart_bank_laddr : in std_logic_vector(15 downto 0); -- 1st bank loading address - cart_bank_size : in std_logic_vector(15 downto 0); -- length of each bank - cart_bank_num : in std_logic_vector(15 downto 0); - cart_bank_type : in std_logic_vector(7 downto 0); - cart_bank_raddr : in std_logic_vector(24 downto 0); -- chip packet address - cart_bank_wr : in std_logic; - - cart_attached: in std_logic; -- FLAG to say cart has been loaded - cart_loading : in std_logic; - - c64_mem_address_in: in std_logic_vector(15 downto 0); -- address from cpu - c64_data_out: in std_logic_vector(7 downto 0); -- data from cpu going to sdram - - sdram_address_out: out std_logic_vector(24 downto 0); -- translated address output - exrom : out std_logic; -- exrom line - game : out std_logic; -- game line - IOE_ena : out std_logic; - IOF_ena : out std_logic; - max_ram : out std_logic; - freeze_key : in std_logic; - nmi : out std_logic; - nmi_ack : in std_logic -); - -end component cartridge; - - signal pll_locked_in: std_logic_vector(1 downto 0); - signal pll_locked: std_logic; - signal c1541_reset: std_logic; - signal idle: std_logic; - signal ces: std_logic_vector(3 downto 0); - signal iec_cycle: std_logic; - signal iec_cycleD: std_logic; - signal buttons: std_logic_vector(1 downto 0); - - -- signals to connect "data_io" for direct PRG injection - signal ioctl_wr: std_logic; - signal ioctl_addr: std_logic_vector(24 downto 0); - signal ioctl_data: std_logic_vector(7 downto 0); - signal ioctl_index: std_logic_vector(7 downto 0); - signal ioctl_ram_addr: std_logic_vector(24 downto 0); - signal ioctl_ram_data: std_logic_vector(7 downto 0); - signal ioctl_load_addr : std_logic_vector(24 downto 0); - signal ioctl_ram_wr: std_logic; - signal ioctl_iec_cycle_used: std_logic; - signal ioctl_force_erase: std_logic; - signal ioctl_erasing: std_logic; - signal ioctl_download: std_logic; - signal c64_addr: std_logic_vector(15 downto 0); - signal c64_data_in: std_logic_vector(7 downto 0); - signal c64_data_out: std_logic_vector(7 downto 0); - signal sdram_addr: std_logic_vector(24 downto 0); - signal sdram_data_out: std_logic_vector(7 downto 0); - - - --- cartridge signals LCA - signal cart_id : std_logic_vector(15 downto 0); -- cart ID or cart type - signal cart_bank_laddr : std_logic_vector(15 downto 0) := (others => '0'); -- 1st bank loading address - signal cart_bank_size : std_logic_vector(15 downto 0) := (others => '0'); -- length of each bank - signal cart_bank_num : std_logic_vector(15 downto 0) := (others => '0'); -- bank number - signal cart_bank_type : std_logic_vector(7 downto 0) := (others => '0'); -- bank type - signal cart_exrom : std_logic_vector(7 downto 0); -- CRT file EXROM status - signal cart_game : std_logic_vector(7 downto 0); -- CRT file GAME status - signal cart_attached : std_logic; - signal game : std_logic; -- game line to cpu - signal exrom : std_logic; -- exrom line to cpu - signal IOE_rom : std_logic; - signal IOF_rom : std_logic; - signal max_ram : std_logic; - signal cart_loading : std_logic; - - signal cart_hdr_wr : std_logic; - - signal IOE : std_logic; -- IOE signal - signal IOF : std_logic; -- IOF signal - signal cartridge_reset : std_logic; -- FLAG to reset once cart loaded - signal reset_crt : std_logic; - signal romL : std_logic; -- cart romL from buslogic LCA - signal romH : std_logic; -- cart romH from buslogic LCA - signal UMAXromH : std_logic; -- VIC II Ultimax access - LCA - - signal CPU_hasbus : std_logic; - - signal c1541rom_wr : std_logic; - signal c64rom_wr : std_logic; - - signal joyA : std_logic_vector(7 downto 0); - signal joyB : std_logic_vector(7 downto 0); - signal joyA_int : std_logic_vector(6 downto 0); - signal joyB_int : std_logic_vector(6 downto 0); - signal joyA_c64 : std_logic_vector(6 downto 0); - signal joyB_c64 : std_logic_vector(6 downto 0); - signal reset_key : std_logic; - signal cart_detach_key :std_logic; -- cartridge detach key CTRL-D - LCA - - signal c64_r : std_logic_vector(5 downto 0); - signal c64_g : std_logic_vector(5 downto 0); - signal c64_b : std_logic_vector(5 downto 0); - - signal status : std_logic_vector(31 downto 0); - signal scanlines : std_logic_vector(1 downto 0); - signal hq2x : std_logic; - signal ce_pix_actual : std_logic; - signal sd_lba : std_logic_vector(31 downto 0); - signal sd_rd : std_logic; - signal sd_wr : std_logic; - signal sd_ack : std_logic; - signal sd_ack_conf : std_logic; - signal sd_conf : std_logic; - signal sd_sdhc : std_logic; - signal sd_buff_addr : std_logic_vector(8 downto 0); - signal sd_buff_dout : std_logic_vector(7 downto 0); - signal sd_buff_din : std_logic_vector(7 downto 0); - signal sd_buff_wr : std_logic; - signal sd_change : std_logic; - signal disk_readonly : std_logic; - signal old_download : std_logic; - -- these need to be redirected to the SDRAM - signal sdram_we : std_logic; - signal sdram_ce : std_logic; - - signal ps2_clk : std_logic; - signal ps2_dat : std_logic; - - signal c64_iec_atn_i : std_logic; - signal c64_iec_clk_o : std_logic; - signal c64_iec_data_o : std_logic; - signal c64_iec_atn_o : std_logic; - signal c64_iec_data_i : std_logic; - signal c64_iec_clk_i : std_logic; - - signal c1541_iec_atn_i : std_logic; - signal c1541_iec_clk_o : std_logic; - signal c1541_iec_data_o : std_logic; - signal c1541_iec_atn_o : std_logic; - signal c1541_iec_data_i : std_logic; - signal c1541_iec_clk_i : std_logic; - - signal tv15Khz_mode : std_logic; - signal ypbpr : std_logic; - signal ntsc_init_mode : std_logic; - - alias c64_addr_int : unsigned is unsigned(c64_addr); - alias c64_data_in_int : unsigned is unsigned(c64_data_in); - signal c64_data_in16: std_logic_vector(15 downto 0); - alias c64_data_out_int : unsigned is unsigned(c64_data_out); - - signal clk_ram : std_logic; - signal clk32 : std_logic; - signal clk16 : std_logic; - signal ce_8 : std_logic; - signal ce_4 : std_logic; - signal hq2x160 : std_logic; - signal osdclk : std_logic; - signal clkdiv : std_logic_vector(9 downto 0); - - signal ram_ce : std_logic; - signal ram_we : std_logic; - signal r : unsigned(7 downto 0); - signal g : unsigned(7 downto 0); - signal b : unsigned(7 downto 0); - signal hsync : std_logic; - signal vsync : std_logic; - signal blank : std_logic; - - signal old_vsync : std_logic; - signal hsync_out : std_logic; - signal vsync_out : std_logic; - - signal audio_data : std_logic_vector(17 downto 0); - - signal reset_counter : integer; - signal reset_n : std_logic; - signal led_disk : std_logic; - signal freeze_key : std_logic; - signal nmi : std_logic; - signal nmi_ack : std_logic; - signal erasing : std_logic; --- temporary signal to extend c64_addr to 24bit LCA - signal c64_addr_temp : std_logic_vector(24 downto 0); - signal cart_blk_len : std_logic_vector(31 downto 0); - signal cart_hdr_cnt : std_logic_vector(3 downto 0); - signal erase_cram : std_logic := '0'; - signal force_erase : std_logic; - signal erase_to : std_logic_vector(4 downto 0) := (others => '0'); - signal mem_ce : std_logic; -begin - - -- 1541 activity led - LED <= not led_disk; - - iec_cycle <= '1' when ces = "1011" else '0'; - - -- User io - mist_io_d : mist_io - generic map (STRLEN => CONF_STR'length) - port map ( - clk_sys => clk32, - - SPI_SCK => SPI_SCK, - CONF_DATA0 => CONF_DATA0, - SPI_SS2 => SPI_SS2, - SPI_DO => SPI_DO, - SPI_DI => SPI_DI, - - joystick_0 => joyA, - joystick_1 => joyB, - - conf_str => to_slv(CONF_STR), - - status => status, - buttons => buttons, - scandoubler_disable => tv15Khz_mode, - ypbpr => ypbpr, - - sd_lba => sd_lba, - sd_rd => sd_rd, - sd_wr => sd_wr, - sd_ack => sd_ack, - sd_ack_conf => sd_ack_conf, - sd_conf => sd_conf, - sd_sdhc => sd_sdhc, - sd_buff_addr => sd_buff_addr, - sd_buff_dout => sd_buff_dout, - sd_buff_din => sd_buff_din, - sd_buff_wr => sd_buff_wr, - img_mounted => sd_change, - ps2_kbd_clk => ps2_clk, - ps2_kbd_data => ps2_dat, - ioctl_download => ioctl_download, - ioctl_force_erase => ioctl_force_erase, - ioctl_erasing => ioctl_erasing, - ioctl_index => ioctl_index, - ioctl_wr => ioctl_wr, - ioctl_addr => ioctl_addr, - ioctl_dout => ioctl_data -); - - - cart_loading <= '1' when ioctl_download = '1' and ioctl_index = 3 else '0'; - - cart : cartridge - port map ( - romL => romL, - romH => romH, - UMAXromH => UMAXromH, - IOE => IOE, - IOF => IOF, - mem_write => not ram_we, - mem_ce => not ram_ce, - mem_ce_out => mem_ce, - - clk32 => clk32, - reset => reset_n, - reset_out => reset_crt, - - cart_id => cart_id, - cart_exrom => cart_exrom, - cart_game => cart_game, - - cart_bank_laddr => cart_bank_laddr, - cart_bank_size => cart_bank_size, - cart_bank_num => cart_bank_num, - cart_bank_type => cart_bank_type, - cart_bank_raddr => ioctl_load_addr, - cart_bank_wr => cart_hdr_wr, - - cart_attached => cart_attached, - cart_loading => cart_loading, - - c64_mem_address_in => c64_addr, - c64_data_out => c64_data_out, - - sdram_address_out => c64_addr_temp, - exrom => exrom, - game => game, - IOE_ena => ioE_rom, - IOF_ena => ioF_rom, - max_ram => max_ram, - freeze_key => freeze_key, - nmi => nmi, - nmi_ack => nmi_ack - ); - - -- rearrange joystick contacta for c64 - joyA_int <= joyA(6 downto 4) & joyA(0) & joyA(1) & joyA(2) & joyA(3); - joyB_int <= joyB(6 downto 4) & joyB(0) & joyB(1) & joyB(2) & joyB(3); - - -- swap joysticks if requested - joyA_c64 <= joyB_int when status(3)='1' else joyA_int; - joyB_c64 <= joyA_int when status(3)='1' else joyB_int; - - sdram_addr <= c64_addr_temp when iec_cycle='0' else ioctl_ram_addr; - sdram_data_out <= c64_data_out when iec_cycle='0' else ioctl_ram_data; - - -- ram_we and ce are active low - sdram_ce <= mem_ce when iec_cycle='0' else ioctl_iec_cycle_used; - sdram_we <= not ram_we when iec_cycle='0' else ioctl_iec_cycle_used; - - process(clk32) - begin - if falling_edge(clk32) then - - old_download <= ioctl_download; - iec_cycleD <= iec_cycle; - cart_hdr_wr <= '0'; - - if(iec_cycle='1' and iec_cycleD='0' and ioctl_ram_wr='1') then - ioctl_ram_wr <= '0'; - ioctl_iec_cycle_used <= '1'; - ioctl_ram_addr <= ioctl_load_addr; - ioctl_load_addr <= ioctl_load_addr + "1"; - if erasing = '1' then - ioctl_ram_data <= (others => '0'); - else - ioctl_ram_data <= ioctl_data; - end if; - else - if(iec_cycle='0') then - ioctl_iec_cycle_used <= '0'; - end if; - end if; - - if ioctl_wr='1' then - if ioctl_index = 2 then - if ioctl_addr = 0 then - ioctl_load_addr(7 downto 0) <= ioctl_data; - elsif(ioctl_addr = 1) then - ioctl_load_addr(15 downto 8) <= ioctl_data; - else - ioctl_ram_wr <= '1'; - end if; - end if; - - if ioctl_index = 3 then--CRT, e0(MAX) - if ioctl_addr = 0 then - ioctl_load_addr <= '0' & X"100000"; - cart_blk_len <= (others => '0'); - cart_hdr_cnt <= (others => '0'); - end if; - - if(ioctl_addr = X"16") then cart_id(15 downto 8) <= ioctl_data; end if; - if(ioctl_addr = X"17") then cart_id(7 downto 0) <= ioctl_data; end if; - if(ioctl_addr = X"18") then cart_exrom(7 downto 0)<= ioctl_data; end if; - if(ioctl_addr = X"19") then cart_game(7 downto 0) <= ioctl_data; end if; - - if(ioctl_addr >= X"40") then - if cart_blk_len = 0 and cart_hdr_cnt = 0 then - cart_hdr_cnt <= X"1"; - if ioctl_load_addr(12 downto 0) /= 0 then - -- align to 8KB boundary - ioctl_load_addr(12 downto 0) <= '0' & X"000"; - ioctl_load_addr(24 downto 13) <= ioctl_load_addr(24 downto 13) + "1"; - end if; - elsif cart_hdr_cnt /= 0 then - cart_hdr_cnt <= cart_hdr_cnt + "1"; - if(cart_hdr_cnt = 4) then cart_blk_len(31 downto 24) <= ioctl_data; end if; - if(cart_hdr_cnt = 5) then cart_blk_len(23 downto 16) <= ioctl_data; end if; - if(cart_hdr_cnt = 6) then cart_blk_len(15 downto 8) <= ioctl_data; end if; - if(cart_hdr_cnt = 7) then cart_blk_len(7 downto 0) <= ioctl_data; end if; - if(cart_hdr_cnt = 8) then cart_blk_len <= cart_blk_len - X"10"; end if; - if(cart_hdr_cnt = 9) then cart_bank_type <= ioctl_data; end if; - if(cart_hdr_cnt = 10) then cart_bank_num(15 downto 8) <= ioctl_data; end if; - if(cart_hdr_cnt = 11) then cart_bank_num(7 downto 0) <= ioctl_data; end if; - if(cart_hdr_cnt = 12) then cart_bank_laddr(15 downto 8)<= ioctl_data; end if; - if(cart_hdr_cnt = 13) then cart_bank_laddr(7 downto 0) <= ioctl_data; end if; - if(cart_hdr_cnt = 14) then cart_bank_size(15 downto 8) <= ioctl_data; end if; - if(cart_hdr_cnt = 15) then cart_bank_size(7 downto 0) <= ioctl_data; end if; - if(cart_hdr_cnt = 15) then cart_hdr_wr <= '1'; end if; - else - cart_blk_len <= cart_blk_len - "1"; - ioctl_ram_wr <= '1'; - end if; - end if; - end if; - end if; - - if old_download /= ioctl_download and ioctl_index = 3 then - cart_attached <= old_download; - erase_cram <= '1'; - end if; - - if status(5)='1' or buttons(1)='1' then - cart_attached <= '0'; - end if; - - if erasing='0' and force_erase = '1' then - erasing <='1'; - ioctl_load_addr <= (others => '0'); - end if; - - if erasing = '1' and ioctl_ram_wr = '0' then - erase_to <= erase_to + "1"; - if erase_to = "11111" then - if ioctl_load_addr < (erase_cram & X"FFFF") then - ioctl_ram_wr <= '1'; - else - erasing <= '0'; - erase_cram <= '0'; - end if; - end if; - end if; - end if; - end process; - - c64rom_wr <= ioctl_wr when (ioctl_index = 0) and (ioctl_addr(14) = '0') and (ioctl_download = '1') else '0'; - c1541rom_wr <= ioctl_wr when (ioctl_index = 0) and (ioctl_addr(14) = '1') and (ioctl_download = '1') else '0'; - - process(clk32) - begin - if rising_edge(clk32) then - clk16 <= not clk16; - clkdiv <= std_logic_vector(unsigned(clkdiv)+1); - if(clkdiv(1 downto 0) = "00") then - ce_8 <= '1'; - else - ce_8 <= '0'; - end if; - if(clkdiv(2 downto 0) = "000") then - ce_4 <= '1'; - else - ce_4 <= '0'; - end if; - end if; - end process; - - ntsc_init_mode <= status(2); - - -- second to generate 64mhz clock and phase shifted ram clock - pll : entity work.pll - port map( - inclk0 => CLOCK_27, - c0 => clk_ram, - c1 => SDRAM_CLK, - c2 => clk32, - locked => pll_locked - ); - - process(clk32) - begin - if rising_edge(clk32) then - -- Reset by: - -- Button at device, IO controller reboot, OSD or FPGA startup - if status(0)='1' or pll_locked = '0' then - reset_counter <= 1000000; - reset_n <= '0'; - elsif buttons(1)='1' or status(5)='1' or reset_key = '1' or reset_crt='1' or (ioctl_download='1' and ioctl_index = 3) then - reset_counter <= 255; - reset_n <= '0'; - elsif ioctl_download ='1' then - elsif erasing ='1' then - force_erase <= '0'; - else - if reset_counter = 0 then - reset_n <= '1'; - else - reset_counter <= reset_counter - 1; - if reset_counter = 100 then - force_erase <='1'; - end if; - end if; - end if; - end if; - end process; - - SDRAM_DQ(15 downto 8) <= (others => 'Z') when sdram_we='0' else (others => '0'); - SDRAM_DQ(7 downto 0) <= (others => 'Z') when sdram_we='0' else sdram_data_out; - - -- read from sdram - c64_data_in <= SDRAM_DQ(7 downto 0); - -- clock is always enabled and memory is never masked as we only - -- use one byte - SDRAM_CKE <= '1'; - SDRAM_DQML <= '0'; - SDRAM_DQMH <= '0'; - - sdr: sdram port map( - sd_addr => SDRAM_A, - sd_ba => SDRAM_BA, - sd_cs => SDRAM_nCS, - sd_we => SDRAM_nWE, - sd_ras => SDRAM_nRAS, - sd_cas => SDRAM_nCAS, - - clk => clk_ram, - addr => sdram_addr, - init => not pll_locked, - we => sdram_we, - refresh => idle, - ce => sdram_ce - ); - - - -- decode audio - dac_l : sigma_delta_dac - port map ( - CLK => clk32, - DACin => not audio_data(17) & audio_data(16 downto 3), - DACout => AUDIO_L, - RESET => '0' - ); - - dac_r : sigma_delta_dac - port map ( - CLK => clk32, - DACin => not audio_data(17) & audio_data(16 downto 3), - DACout => AUDIO_R, - RESET => '0' - ); - - fpga64 : entity work.fpga64_sid_iec - port map( - clk32 => clk32, - reset_n => reset_n, - c64gs => status(11), - kbd_clk => not ps2_clk, - kbd_dat => ps2_dat, - ramAddr => c64_addr_int, - ramDataOut => c64_data_out_int, - ramDataIn => c64_data_in_int, - ramCE => ram_ce, - ramWe => ram_we, - ntscInitMode => ntsc_init_mode, - hsync => hsync, - vsync => vsync, - r => r, - g => g, - b => b, - game => game, - exrom => exrom, - UMAXromH => UMAXromH, - CPU_hasbus => CPU_hasbus, - ioE_rom => ioE_rom, - ioF_rom => ioF_rom, - max_ram => max_ram, - irq_n => '1', - nmi_n => not nmi, - nmi_ack => nmi_ack, - freeze_key => freeze_key, - dma_n => '1', - romL => romL, - romH => romH, - IOE => IOE, - IOF => IOF, - ba => open, - joyA => unsigned(joyA_c64), - joyB => unsigned(joyB_c64), - serioclk => open, - ces => ces, - SIDclk => open, - still => open, - idle => idle, - audio_data => audio_data, - extfilter_en => not status(6), - iec_data_o => c64_iec_data_o, - iec_atn_o => c64_iec_atn_o, - iec_clk_o => c64_iec_clk_o, - iec_data_i => not c64_iec_data_i, - iec_clk_i => not c64_iec_clk_i, - iec_atn_i => not c64_iec_atn_i, - disk_num => open, - c64rom_addr => ioctl_addr(13 downto 0), - c64rom_data => ioctl_data, - c64rom_wr => c64rom_wr, - cart_detach_key => cart_detach_key, - reset_key => reset_key - ); - - - c64_iec_atn_i <= not ((not c64_iec_atn_o) and (not c1541_iec_atn_o) ); - c64_iec_data_i <= not ((not c64_iec_data_o) and (not c1541_iec_data_o)); - c64_iec_clk_i <= not ((not c64_iec_clk_o) and (not c1541_iec_clk_o) ); - - c1541_iec_atn_i <= c64_iec_atn_i; - c1541_iec_data_i <= c64_iec_data_i; - c1541_iec_clk_i <= c64_iec_clk_i; - - process(clk32, reset_n) - variable reset_cnt : integer range 0 to 32000000; - begin - if reset_n = '0' then - reset_cnt := 100000; - elsif rising_edge(clk32) then - if reset_cnt /= 0 then - reset_cnt := reset_cnt - 1; - end if; - end if; - - if reset_cnt = 0 then - c1541_reset <= '0'; - else - c1541_reset <= '1'; - end if; - end process; - - c1541_sd : entity work.c1541_sd - port map - ( - clk32 => clk32, - reset => c1541_reset, - - c1541rom_addr => ioctl_addr(13 downto 0), - c1541rom_data => ioctl_data, - c1541rom_wr => c1541rom_wr, - - disk_change => sd_change, - disk_readonly => disk_readonly, - - iec_atn_i => c1541_iec_atn_i, - iec_data_i => c1541_iec_data_i, - iec_clk_i => c1541_iec_clk_i, - - iec_atn_o => c1541_iec_atn_o, - iec_data_o => c1541_iec_data_o, - iec_clk_o => c1541_iec_clk_o, - - sd_lba => sd_lba, - sd_rd => sd_rd, - sd_wr => sd_wr, - sd_ack => sd_ack, - sd_ack_conf => sd_ack_conf, - sd_conf => sd_conf, - sd_sdhc => sd_sdhc, - sd_buff_addr => sd_buff_addr, - sd_buff_dout => sd_buff_dout, - sd_buff_din => sd_buff_din, - sd_buff_wr => sd_buff_wr, - - led => led_disk - ); - - comp_sync : entity work.composite_sync - port map( - clk32 => clk32, - hsync => hsync, - vsync => vsync, - ntsc => ntsc_init_mode, - hsync_out => hsync_out, - vsync_out => vsync_out, - blank => blank - ); - - c64_r <= (others => '0') when blank = '1' else std_logic_vector(r(7 downto 2)); - c64_g <= (others => '0') when blank = '1' else std_logic_vector(g(7 downto 2)); - c64_b <= (others => '0') when blank = '1' else std_logic_vector(b(7 downto 2)); - - scanlines <= status(10 downto 9); - hq2x <= status(9) xor status(8); - ce_pix_actual <= ce_4 when hq2x160='1' else ce_8; - - process(clk32) - begin - if rising_edge(clk32) then - if((old_vsync = '0') and (vsync_out = '1')) then - if(status(10 downto 8)="010") then - hq2x160 <= '1'; - else - hq2x160 <= '0'; - end if; - end if; - old_vsync <= vsync_out; - end if; - end process; - - vmixer : video_mixer - port map ( - clk_sys => clk_ram, - ce_pix => ce_8, - ce_pix_actual => ce_pix_actual, - - SPI_SCK => SPI_SCK, - SPI_SS3 => SPI_SS3, - SPI_DI => SPI_DI, - - scanlines => scanlines, - scandoubler_disable => tv15Khz_mode, - hq2x => hq2x, - ypbpr => ypbpr, - ypbpr_full => '1', - - R => c64_r, - G => c64_g, - B => c64_b, - HSync => hsync_out, - VSync => vsync_out, - line_start => '0', - mono => '0', - - VGA_R => VGA_R, - VGA_G => VGA_G, - VGA_B => VGA_B, - VGA_VS => VGA_VS, - VGA_HS => VGA_HS - ); - -end struct; diff --git a/cores/c64/rtl/m6522.vhd b/cores/c64/rtl/m6522.vhd deleted file mode 100644 index e9bd060..0000000 --- a/cores/c64/rtl/m6522.vhd +++ /dev/null @@ -1,919 +0,0 @@ - -- - -- A simulation model of VIC20 hardware - VIA implementation - -- Copyright (c) MikeJ - March 2003 - -- - -- All rights reserved - -- - -- Redistribution and use in source and synthezised forms, with or without - -- modification, are permitted provided that the following conditions are met: - -- - -- Redistributions of source code must retain the above copyright notice, - -- this list of conditions and the following disclaimer. - -- - -- Redistributions in synthesized form must reproduce the above copyright - -- notice, this list of conditions and the following disclaimer in the - -- documentation and/or other materials provided with the distribution. - -- - -- Neither the name of the author nor the names of other contributors may - -- be used to endorse or promote products derived from this software without - -- specific prior written permission. - -- - -- THIS CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - -- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - -- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - -- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE - -- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - -- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - -- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - -- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - -- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - -- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - -- POSSIBILITY OF SUCH DAMAGE. - -- - -- You are responsible for any legal issues arising from your use of this code. - -- - -- The latest version of this file can be found at: www.fpgaarcade.com - -- - -- Email vic20@fpgaarcade.com - -- - -- - -- Revision list - -- - -- version 004 fixes to PB7 T1 control and Mode 0 Shift Register operation - -- version 003 fix reset of T1/T2 IFR flags if T1/T2 is reload via reg5/reg9 from wolfgang (WoS) - -- Ported to numeric_std and simulation fix for signal initializations from arnim laeuger - -- version 002 fix from Mark McDougall, untested - -- version 001 initial release - -- not very sure about the shift register, documentation is a bit light. - - library ieee ; - use ieee.std_logic_1164.all ; - use ieee.numeric_std.all; - - entity M6522 is - port ( - - I_RS : in std_logic_vector(3 downto 0); - I_DATA : in std_logic_vector(7 downto 0); - O_DATA : out std_logic_vector(7 downto 0); - O_DATA_OE_L : out std_logic; - - I_RW_L : in std_logic; - I_CS1 : in std_logic; - I_CS2_L : in std_logic; - - O_IRQ_L : out std_logic; -- note, not open drain - -- port a - I_CA1 : in std_logic; - I_CA2 : in std_logic; - O_CA2 : out std_logic; - O_CA2_OE_L : out std_logic; - - I_PA : in std_logic_vector(7 downto 0); - O_PA : out std_logic_vector(7 downto 0); - O_PA_OE_L : out std_logic_vector(7 downto 0); - - -- port b - I_CB1 : in std_logic; - O_CB1 : out std_logic; - O_CB1_OE_L : out std_logic; - - I_CB2 : in std_logic; - O_CB2 : out std_logic; - O_CB2_OE_L : out std_logic; - - I_PB : in std_logic_vector(7 downto 0); - O_PB : out std_logic_vector(7 downto 0); - O_PB_OE_L : out std_logic_vector(7 downto 0); - - I_P2_H : in std_logic; -- high for phase 2 clock ____----__ - RESET_L : in std_logic; - ENA_4 : in std_logic; -- clk enable - CLK : in std_logic - ); - end; - - architecture RTL of M6522 is - - signal phase : std_logic_vector(1 downto 0):="00"; - signal p2_h_t1 : std_logic; - signal cs : std_logic; - - -- registers - signal r_ddra : std_logic_vector(7 downto 0); - signal r_ora : std_logic_vector(7 downto 0); - signal r_ira : std_logic_vector(7 downto 0); - - signal r_ddrb : std_logic_vector(7 downto 0); - signal r_orb : std_logic_vector(7 downto 0); - signal r_irb : std_logic_vector(7 downto 0); - - signal r_t1l_l : std_logic_vector(7 downto 0); - signal r_t1l_h : std_logic_vector(7 downto 0); - signal r_t2l_l : std_logic_vector(7 downto 0); - signal r_t2l_h : std_logic_vector(7 downto 0); -- not in real chip - signal r_sr : std_logic_vector(7 downto 0); - signal r_acr : std_logic_vector(7 downto 0); - signal r_pcr : std_logic_vector(7 downto 0); - signal r_ifr : std_logic_vector(7 downto 0); - signal r_ier : std_logic_vector(6 downto 0); - - signal sr_write_ena : boolean; - signal sr_read_ena : boolean; - signal ifr_write_ena : boolean; - signal ier_write_ena : boolean; - signal clear_irq : std_logic_vector(7 downto 0); - signal load_data : std_logic_vector(7 downto 0); - - -- timer 1 - signal t1c : std_logic_vector(15 downto 0) := (others => '1'); -- simulators may not catch up w/o init here... - signal t1c_active : boolean; - signal t1c_done : boolean; - signal t1_w_reset_int : boolean; - signal t1_r_reset_int : boolean; - signal t1_load_counter : boolean; - signal t1_reload_counter : boolean; - signal t1_toggle : std_logic; - signal t1_irq : std_logic := '0'; - - -- timer 2 - signal t2c : std_logic_vector(15 downto 0) := (others => '1'); -- simulators may not catch up w/o init here... - signal t2c_active : boolean; - signal t2c_done : boolean; - signal t2_pb6 : std_logic; - signal t2_pb6_t1 : std_logic; - signal t2_w_reset_int : boolean; - signal t2_r_reset_int : boolean; - signal t2_load_counter : boolean; - signal t2_reload_counter : boolean; - signal t2_irq : std_logic := '0'; - signal t2_sr_ena : boolean; - - -- shift reg - signal sr_cnt : std_logic_vector(3 downto 0); - signal sr_cb1_oe_l : std_logic; - signal sr_cb1_out : std_logic; - signal sr_drive_cb2 : std_logic; - signal sr_strobe : std_logic; - signal sr_strobe_t1 : std_logic; - signal sr_strobe_falling : boolean; - signal sr_strobe_rising : boolean; - signal sr_irq : std_logic; - signal sr_out : std_logic; - signal sr_off_delay : std_logic; - - -- io - signal w_orb_hs : std_logic; - signal w_ora_hs : std_logic; - signal r_irb_hs : std_logic; - signal r_ira_hs : std_logic; - - signal ca_hs_sr : std_logic; - signal ca_hs_pulse : std_logic; - signal cb_hs_sr : std_logic; - signal cb_hs_pulse : std_logic; - - signal cb1_in_mux : std_logic; - signal ca1_ip_reg : std_logic; - signal cb1_ip_reg : std_logic; - signal ca1_int : boolean; - signal cb1_int : boolean; - signal ca1_irq : std_logic; - signal cb1_irq : std_logic; - - signal ca2_ip_reg : std_logic; - signal cb2_ip_reg : std_logic; - signal ca2_int : boolean; - signal cb2_int : boolean; - signal ca2_irq : std_logic; - signal cb2_irq : std_logic; - - signal final_irq : std_logic; - begin - - p_phase : process - begin - -- internal clock phase - wait until rising_edge(CLK); - if (ENA_4 = '1') then - p2_h_t1 <= I_P2_H; - if (p2_h_t1 = '0') and (I_P2_H = '1') then - phase <= "11"; - else - phase <= std_logic_vector(unsigned(phase) + 1); - end if; - end if; - end process; - - p_cs : process(I_CS1, I_CS2_L, I_P2_H) - begin - cs <= '0'; - if (I_CS1 = '1') and (I_CS2_L = '0') and (I_P2_H = '1') then - cs <= '1'; - end if; - end process; - - -- peripheral control reg (pcr) - -- 0 ca1 interrupt control (0 +ve edge, 1 -ve edge) - -- 3..1 ca2 operation - -- 000 input -ve edge - -- 001 independend interrupt input -ve edge - -- 010 input +ve edge - -- 011 independend interrupt input +ve edge - -- 100 handshake output - -- 101 pulse output - -- 110 low output - -- 111 high output - -- 7..4 as 3..0 for cb1,cb2 - - -- auxiliary control reg (acr) - -- 0 input latch PA (0 disable, 1 enable) - -- 1 input latch PB (0 disable, 1 enable) - -- 4..2 shift reg control - -- 000 disable - -- 001 shift in using t2 - -- 010 shift in using o2 - -- 011 shift in using ext clk - -- 100 shift out free running t2 rate - -- 101 shift out using t2 - -- 101 shift out using o2 - -- 101 shift out using ext clk - -- 5 t2 timer control (0 timed interrupt, 1 count down with pulses on pb6) - -- 7..6 t1 timer control - -- 00 timed interrupt each time t1 is loaded pb7 disable - -- 01 continuous interrupts pb7 disable - -- 00 timed interrupt each time t1 is loaded pb7 one shot output - -- 01 continuous interrupts pb7 square wave output - -- - - p_write_reg_reset : process(RESET_L, CLK) - begin - if (RESET_L = '0') then - r_ora <= x"00"; r_orb <= x"00"; - r_ddra <= x"00"; r_ddrb <= x"00"; - r_acr <= x"00"; r_pcr <= x"00"; - - w_orb_hs <= '0'; - w_ora_hs <= '0'; - elsif rising_edge(CLK) then - if (ENA_4 = '1') then - w_orb_hs <= '0'; - w_ora_hs <= '0'; - if (cs = '1') and (I_RW_L = '0') then - case I_RS is - when x"0" => r_orb <= I_DATA; w_orb_hs <= '1'; - when x"1" => r_ora <= I_DATA; w_ora_hs <= '1'; - when x"2" => r_ddrb <= I_DATA; - when x"3" => r_ddra <= I_DATA; - - when x"B" => r_acr <= I_DATA; - when x"C" => r_pcr <= I_DATA; - when x"F" => r_ora <= I_DATA; - - when others => null; - end case; - end if; - - if r_acr(7) = '1' then - -- DMB: Forgetting to clear B7 broke Acornsoft Planetoid - if t1_load_counter then - r_orb(7) <= '0'; -- writing T1C-H resets bit 7 - elsif t1_toggle = '1' then - r_orb(7) <= not r_orb(7); -- toggle - end if; - end if; - end if; - end if; - end process; - - p_write_reg : process (RESET_L, CLK) is - begin - if (RESET_L = '0') then - -- The spec says, this is not reset. - -- Fact is that the 1541 VIA1 timer won't work, - -- as the firmware ONLY sets the r_t1l_h latch!!!! - r_t1l_l <= (others => '0'); - r_t1l_h <= (others => '0'); - r_t2l_l <= (others => '0'); - r_t2l_h <= (others => '0'); - elsif rising_edge(CLK) then - if (ENA_4 = '1') then - t1_w_reset_int <= false; - t1_load_counter <= false; - - t2_w_reset_int <= false; - t2_load_counter <= false; - - load_data <= x"00"; - sr_write_ena <= false; - ifr_write_ena <= false; - ier_write_ena <= false; - - if (cs = '1') and (I_RW_L = '0') then - load_data <= I_DATA; - case I_RS is - when x"4" => r_t1l_l <= I_DATA; - when x"5" => r_t1l_h <= I_DATA; t1_w_reset_int <= true; - t1_load_counter <= true; - - when x"6" => r_t1l_l <= I_DATA; - when x"7" => r_t1l_h <= I_DATA; t1_w_reset_int <= true; - - when x"8" => r_t2l_l <= I_DATA; - when x"9" => r_t2l_h <= I_DATA; t2_w_reset_int <= true; - t2_load_counter <= true; - - when x"A" => sr_write_ena <= true; - when x"D" => ifr_write_ena <= true; - when x"E" => ier_write_ena <= true; - - when others => null; - end case; - end if; - end if; - end if; - end process; - - p_oe : process(cs, I_RW_L) - begin - O_DATA_OE_L <= '1'; - if (cs = '1') and (I_RW_L = '1') then - O_DATA_OE_L <= '0'; - end if; - end process; - - p_read : process(cs, I_RW_L, I_RS, r_irb, r_ira, r_ddrb, r_ddra, t1c, r_t1l_l, - r_t1l_h, t2c, r_sr, r_acr, r_pcr, r_ifr, r_ier, r_orb) - begin - t1_r_reset_int <= false; - t2_r_reset_int <= false; - sr_read_ena <= false; - r_irb_hs <= '0'; - r_ira_hs <= '0'; - O_DATA <= x"00"; -- default - if (cs = '1') and (I_RW_L = '1') then - case I_RS is - --when x"0" => O_DATA <= r_irb; r_irb_hs <= '1'; - -- fix from Mark McDougall, untested - when x"0" => O_DATA <= (r_irb and not r_ddrb) or (r_orb and r_ddrb); r_irb_hs <= '1'; - when x"1" => O_DATA <= (r_ira and not r_ddra) or (r_ora and r_ddra); r_ira_hs <= '1'; - when x"2" => O_DATA <= r_ddrb; - when x"3" => O_DATA <= r_ddra; - when x"4" => O_DATA <= t1c( 7 downto 0); t1_r_reset_int <= true; - when x"5" => O_DATA <= t1c(15 downto 8); - when x"6" => O_DATA <= r_t1l_l; - when x"7" => O_DATA <= r_t1l_h; - when x"8" => O_DATA <= t2c( 7 downto 0); t2_r_reset_int <= true; - when x"9" => O_DATA <= t2c(15 downto 8); - when x"A" => O_DATA <= r_sr; sr_read_ena <= true; - when x"B" => O_DATA <= r_acr; - when x"C" => O_DATA <= r_pcr; - when x"D" => O_DATA <= r_ifr; - when x"E" => O_DATA <= ('0' & r_ier); - when x"F" => O_DATA <= r_ira; - when others => null; - end case; - end if; - - end process; - -- - -- IO - -- - p_ca1_cb1_sel : process(sr_cb1_oe_l, sr_cb1_out, I_CB1) - begin - -- if the shift register is enabled, cb1 may be an output - -- in this case, we should listen to the CB1_OUT for the interrupt - if (sr_cb1_oe_l = '1') then - cb1_in_mux <= I_CB1; - else - cb1_in_mux <= sr_cb1_out; - end if; - end process; - - p_ca1_cb1_int : process(r_pcr, ca1_ip_reg, I_CA1, cb1_ip_reg, cb1_in_mux) - begin - if (r_pcr(0) = '0') then -- ca1 control - -- negative edge - ca1_int <= (ca1_ip_reg = '1') and (I_CA1 = '0'); - else - -- positive edge - ca1_int <= (ca1_ip_reg = '0') and (I_CA1 = '1'); - end if; - - if (r_pcr(4) = '0') then -- cb1 control - -- negative edge - cb1_int <= (cb1_ip_reg = '1') and (cb1_in_mux = '0'); - else - -- positive edge - cb1_int <= (cb1_ip_reg = '0') and (cb1_in_mux = '1'); - end if; - end process; - - p_ca2_cb2_int : process(r_pcr, ca2_ip_reg, I_CA2, cb2_ip_reg, I_CB2) - begin - ca2_int <= false; - if (r_pcr(3) = '0') then -- ca2 input - if (r_pcr(2) = '0') then -- ca2 edge - -- negative edge - ca2_int <= (ca2_ip_reg = '1') and (I_CA2 = '0'); - else - -- positive edge - ca2_int <= (ca2_ip_reg = '0') and (I_CA2 = '1'); - end if; - end if; - - cb2_int <= false; - if (r_pcr(7) = '0') then -- cb2 input - if (r_pcr(6) = '0') then -- cb2 edge - -- negative edge - cb2_int <= (cb2_ip_reg = '1') and (I_CB2 = '0'); - else - -- positive edge - cb2_int <= (cb2_ip_reg = '0') and (I_CB2 = '1'); - end if; - end if; - end process; - - p_ca2_cb2 : process(RESET_L, CLK) - begin - if (RESET_L = '0') then - O_CA2 <= '0'; - O_CA2_OE_L <= '1'; - O_CB2 <= '0'; - O_CB2_OE_L <= '1'; - - ca_hs_sr <= '0'; - ca_hs_pulse <= '0'; - cb_hs_sr <= '0'; - cb_hs_pulse <= '0'; - elsif rising_edge(CLK) then - if (ENA_4 = '1') then - -- ca - if (phase = "00") and ((w_ora_hs = '1') or (r_ira_hs = '1')) then - ca_hs_sr <= '1'; - elsif ca1_int then - ca_hs_sr <= '0'; - end if; - - if (phase = "00") then - ca_hs_pulse <= w_ora_hs or r_ira_hs; - end if; - - O_CA2_OE_L <= not r_pcr(3); -- ca2 output - case r_pcr(3 downto 1) is - when "000" => O_CA2 <= '0'; -- input - when "001" => O_CA2 <= '0'; -- input - when "010" => O_CA2 <= '0'; -- input - when "011" => O_CA2 <= '0'; -- input - when "100" => O_CA2 <= not (ca_hs_sr); -- handshake - when "101" => O_CA2 <= not (ca_hs_pulse); -- pulse - when "110" => O_CA2 <= '0'; -- low - when "111" => O_CA2 <= '1'; -- high - when others => null; - end case; - - -- cb - if (phase = "00") and (w_orb_hs = '1') then - cb_hs_sr <= '1'; - elsif cb1_int then - cb_hs_sr <= '0'; - end if; - - if (phase = "00") then - cb_hs_pulse <= w_orb_hs; - end if; - - O_CB2_OE_L <= not (r_pcr(7) or sr_drive_cb2); -- cb2 output or serial - if (sr_drive_cb2 = '1') then -- serial output - O_CB2 <= sr_out; - else - case r_pcr(7 downto 5) is - when "000" => O_CB2 <= '0'; -- input - when "001" => O_CB2 <= '0'; -- input - when "010" => O_CB2 <= '0'; -- input - when "011" => O_CB2 <= '0'; -- input - when "100" => O_CB2 <= not (cb_hs_sr); -- handshake - when "101" => O_CB2 <= not (cb_hs_pulse); -- pulse - when "110" => O_CB2 <= '0'; -- low - when "111" => O_CB2 <= '1'; -- high - when others => null; - end case; - end if; - end if; - end if; - end process; - O_CB1 <= sr_cb1_out; - O_CB1_OE_L <= sr_cb1_oe_l; - - p_ca_cb_irq : process(RESET_L, CLK) - begin - if (RESET_L = '0') then - ca1_irq <= '0'; - ca2_irq <= '0'; - cb1_irq <= '0'; - cb2_irq <= '0'; - elsif rising_edge(CLK) then - if (ENA_4 = '1') then - -- not pretty - if ca1_int then - ca1_irq <= '1'; - elsif (r_ira_hs = '1') or (w_ora_hs = '1') or (clear_irq(1) = '1') then - ca1_irq <= '0'; - end if; - - if ca2_int then - ca2_irq <= '1'; - else - if (((r_ira_hs = '1') or (w_ora_hs = '1')) and (r_pcr(1) = '0')) or - (clear_irq(0) = '1') then - ca2_irq <= '0'; - end if; - end if; - - if cb1_int then - cb1_irq <= '1'; - elsif (r_irb_hs = '1') or (w_orb_hs = '1') or (clear_irq(4) = '1') then - cb1_irq <= '0'; - end if; - - if cb2_int then - cb2_irq <= '1'; - else - if (((r_irb_hs = '1') or (w_orb_hs = '1')) and (r_pcr(5) = '0')) or - (clear_irq(3) = '1') then - cb2_irq <= '0'; - end if; - end if; - end if; - end if; - end process; - - p_input_reg : process(RESET_L, CLK) - begin - if (RESET_L = '0') then - ca1_ip_reg <= '0'; - cb1_ip_reg <= '0'; - - ca2_ip_reg <= '0'; - cb2_ip_reg <= '0'; - - r_ira <= x"00"; - r_irb <= x"00"; - - elsif rising_edge(CLK) then - if (ENA_4 = '1') then - -- we have a fast clock, so we can have input registers - ca1_ip_reg <= I_CA1; - cb1_ip_reg <= cb1_in_mux; - - ca2_ip_reg <= I_CA2; - cb2_ip_reg <= I_CB2; - - if (r_acr(0) = '0') then - r_ira <= I_PA; - else -- enable latching - if ca1_int then - r_ira <= I_PA; - end if; - end if; - - if (r_acr(1) = '0') then - r_irb <= I_PB; - else -- enable latching - if cb1_int then - r_irb <= I_PB; - end if; - end if; - end if; - end if; - end process; - - - p_buffers : process(r_ddra, r_ora, r_ddrb, r_acr, r_orb) - begin - -- data direction reg (ddr) 0 = input, 1 = output - O_PA <= r_ora; - O_PA_OE_L <= not r_ddra; - - if (r_acr(7) = '1') then -- not clear if r_ddrb(7) must be 1 as well - O_PB_OE_L(7) <= '0'; -- an output if under t1 control - else - O_PB_OE_L(7) <= not (r_ddrb(7)); - end if; - - O_PB_OE_L(6 downto 0) <= not r_ddrb(6 downto 0); - O_PB(7 downto 0) <= r_orb(7 downto 0); - - end process; - -- - -- Timer 1 - -- - p_timer1_done : process - variable done : boolean; - begin - wait until rising_edge(CLK); - if (ENA_4 = '1') then - done := (t1c = x"0000"); - t1c_done <= done and (phase = "11"); - if (phase = "11") then - t1_reload_counter <= done and (r_acr(6) = '1'); - end if; - if t1_load_counter then -- done reset on load! - t1c_done <= false; - end if; - end if; - end process; - - p_timer1 : process - begin - wait until rising_edge(CLK); - if (ENA_4 = '1') then - if t1_load_counter or (t1_reload_counter and phase = "11") then - t1c( 7 downto 0) <= r_t1l_l; - t1c(15 downto 8) <= r_t1l_h; - elsif (phase="11") then - t1c <= std_logic_vector(unsigned(t1c) - 1); - end if; - - if t1_load_counter or t1_reload_counter then - t1c_active <= true; - elsif t1c_done then - t1c_active <= false; - end if; - - t1_toggle <= '0'; - if t1c_active and t1c_done then - t1_toggle <= '1'; - t1_irq <= '1'; - elsif t1_w_reset_int or t1_r_reset_int or (clear_irq(6) = '1') then - t1_irq <= '0'; - end if; - if t1_load_counter then -- irq reset on load! - t1_irq <= '0'; - end if; - end if; - end process; - -- - -- Timer2 - -- - p_timer2_pb6_input : process - begin - wait until rising_edge(CLK); - if (ENA_4 = '1') then - if (phase = "01") then -- leading edge p2_h - t2_pb6 <= I_PB(6); - t2_pb6_t1 <= t2_pb6; - end if; - end if; - end process; - - p_timer2_done : process - variable done : boolean; - begin - wait until rising_edge(CLK); - if (ENA_4 = '1') then - done := (t2c = x"0000"); - t2c_done <= done and (phase = "11"); - if (phase = "11") then - t2_reload_counter <= done; - end if; - if t2_load_counter then -- done reset on load! - t2c_done <= false; - end if; - end if; - end process; - - p_timer2 : process - variable ena : boolean; - begin - wait until rising_edge(CLK); - if (ENA_4 = '1') then - if (r_acr(5) = '0') then - ena := true; - else - ena := (t2_pb6_t1 = '1') and (t2_pb6 = '0'); -- falling edge - end if; - - if t2_load_counter or (t2_reload_counter and phase = "11") then - -- not sure if t2c_reload should be here. Does timer2 just continue to - -- count down, or is it reloaded ? Reloaded makes more sense if using - -- it to generate a clock for the shift register. - t2c( 7 downto 0) <= r_t2l_l; - t2c(15 downto 8) <= r_t2l_h; - else - if (phase="11") and ena then -- or count mode - t2c <= std_logic_vector(unsigned(t2c) - 1); - end if; - end if; - - t2_sr_ena <= (t2c(7 downto 0) = x"00") and (phase = "11"); - - if t2_load_counter then - t2c_active <= true; - elsif t2c_done then - t2c_active <= false; - end if; - - if t2c_active and t2c_done then - t2_irq <= '1'; - elsif t2_w_reset_int or t2_r_reset_int or (clear_irq(5) = '1') then - t2_irq <= '0'; - end if; - if t2_load_counter then -- irq reset on load! - t2_irq <= '0'; - end if; - end if; - end process; - -- - -- Shift Register - -- - p_sr : process(RESET_L, CLK) - variable dir_out : std_logic; - variable ena : std_logic; - variable cb1_op : std_logic; - variable cb1_ip : std_logic; - variable use_t2 : std_logic; - variable free_run : std_logic; - variable sr_count_ena : boolean; - begin - if (RESET_L = '0') then - r_sr <= x"00"; - sr_drive_cb2 <= '0'; - sr_cb1_oe_l <= '1'; - sr_cb1_out <= '0'; - sr_strobe <= '1'; - sr_cnt <= "0000"; - sr_irq <= '0'; - sr_out <= '1'; - sr_off_delay <= '0'; - elsif rising_edge(CLK) then - if (ENA_4 = '1') then - -- decode mode - dir_out := r_acr(4); -- output on cb2 - cb1_op := '0'; - cb1_ip := '0'; - use_t2 := '0'; - free_run := '0'; - - -- DMB: SR still runs even in disabled mode (on rising edge of CB1). - -- It just doesn't generate any interrupts. - -- Ref BBC micro advanced user guide p409 - - case r_acr(4 downto 2) is - -- DMB: in disabled mode, configure cb1 as an input - when "000" => ena := '0'; cb1_ip := '1'; - when "001" => ena := '1'; cb1_op := '1'; use_t2 := '1'; - when "010" => ena := '1'; cb1_op := '1'; - when "011" => ena := '1'; cb1_ip := '1'; - when "100" => ena := '1'; use_t2 := '1'; free_run := '1'; - when "101" => ena := '1'; cb1_op := '1'; use_t2 := '1'; - when "110" => ena := '1'; --free_run := '1'; -- hack - when "111" => ena := '1'; cb1_ip := '1'; - when others => null; - end case; - - -- clock select - -- DMB: in disabled mode, strobe from cb1 - if (cb1_ip = '1') then - sr_strobe <= I_CB1; - else - if (sr_cnt(3) = '0') and (free_run = '0') then - sr_strobe <= '1'; - else - if ((use_t2 = '1') and t2_sr_ena) or - ((use_t2 = '0') and (phase = "00")) then - sr_strobe <= not sr_strobe; - end if; - end if; - end if; - - -- latch on rising edge, shift on falling edge - if sr_write_ena then - r_sr <= load_data; - - else - -- DMB: allow shifting in all modes - if (dir_out = '0') then - -- input - if (sr_cnt(3) = '1') or (cb1_ip = '1') then - if sr_strobe_rising then - r_sr(0) <= I_CB2; - elsif sr_strobe_falling then - r_sr(7 downto 1) <= r_sr(6 downto 0); - end if; - end if; - sr_out <= '1'; - else - -- output - if (sr_cnt(3) = '1') or (sr_off_delay = '1') or (cb1_ip = '1') or (free_run = '1') then - if sr_strobe_falling then - r_sr(7 downto 1) <= r_sr(6 downto 0); - r_sr(0) <= r_sr(7); - sr_out <= r_sr(7); - end if; - else - sr_out <= '1'; - end if; - end if; - end if; - - sr_count_ena := sr_strobe_rising; - - -- DMB: reseting sr_count when not enabled cause the sr to - -- start running immediately it was enabled, which is incorrect - -- and broke the latest SmartSPI ROM on the BBC Micro - if ena = '1' and (sr_write_ena or sr_read_ena) then - -- some documentation says sr bit in IFR must be set as well ? - sr_cnt <= "1000"; - elsif sr_count_ena and (sr_cnt(3) = '1') then - sr_cnt <= std_logic_vector(unsigned(sr_cnt) + 1); - end if; - - if (phase = "00") then - sr_off_delay <= sr_cnt(3); -- give some hold time when shifting out - end if; - - if sr_count_ena and (sr_cnt = "1111") and (ena = '1') and (free_run = '0') then - sr_irq <= '1'; - elsif sr_write_ena or sr_read_ena or (clear_irq(2) = '1') then - sr_irq <= '0'; - end if; - - -- assign ops - sr_drive_cb2 <= dir_out; - sr_cb1_oe_l <= not cb1_op; - sr_cb1_out <= sr_strobe; - end if; - end if; - end process; - - p_sr_strobe_rise_fall : process - begin - wait until rising_edge(CLK); - if (ENA_4 = '1') then - sr_strobe_t1 <= sr_strobe; - sr_strobe_rising <= (sr_strobe_t1 = '0') and (sr_strobe = '1'); - sr_strobe_falling <= (sr_strobe_t1 = '1') and (sr_strobe = '0'); - end if; - end process; - -- - -- Interrupts - -- - p_ier : process(RESET_L, CLK) - begin - if (RESET_L = '0') then - r_ier <= "0000000"; - elsif rising_edge(CLK) then - if (ENA_4 = '1') then - if ier_write_ena then - if (load_data(7) = '1') then - -- set - r_ier <= r_ier or load_data(6 downto 0); - else - -- clear - r_ier <= r_ier and not load_data(6 downto 0); - end if; - end if; - end if; - end if; - end process; - - p_ifr : process(t1_irq, t2_irq, final_irq, ca1_irq, ca2_irq, sr_irq, - cb1_irq, cb2_irq) - begin - r_ifr(7) <= final_irq; - r_ifr(6) <= t1_irq; - r_ifr(5) <= t2_irq; - r_ifr(4) <= cb1_irq; - r_ifr(3) <= cb2_irq; - r_ifr(2) <= sr_irq; - r_ifr(1) <= ca1_irq; - r_ifr(0) <= ca2_irq; - - O_IRQ_L <= not final_irq; - end process; - - p_irq : process(RESET_L, CLK) - begin - if (RESET_L = '0') then - final_irq <= '0'; - elsif rising_edge(CLK) then - if (ENA_4 = '1') then - if ((r_ifr(6 downto 0) and r_ier(6 downto 0)) = "0000000") then - final_irq <= '0'; -- no interrupts - else - final_irq <= '1'; - end if; - end if; - end if; - end process; - - p_clear_irq : process(ifr_write_ena, load_data) - begin - clear_irq <= x"00"; - if ifr_write_ena then - clear_irq <= load_data; - end if; - end process; - - end architecture RTL; \ No newline at end of file diff --git a/cores/c64/rtl/sd_card.sv b/cores/c64/rtl/sd_card.sv deleted file mode 100644 index 41eafab..0000000 --- a/cores/c64/rtl/sd_card.sv +++ /dev/null @@ -1,142 +0,0 @@ -// -// sd_card.v -// -// Copyright (c) 2016 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the Lesser GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -// -///////////////////////////////////////////////////////////////////////// - -module sd_card -( - input clk, - input reset, - - output [31:0] sd_lba, - output reg sd_rd, - output reg sd_wr, - input sd_ack, - input sd_ack_conf, - output sd_conf, - output sd_sdhc, - - input [8:0] sd_buff_addr, - input [7:0] sd_buff_dout, - output [7:0] sd_buff_din, - input sd_buff_wr, - - input save_track, - input change, - input [5:0] track, - input [4:0] sector, - input [7:0] buff_addr, - output [7:0] buff_dout, - input [7:0] buff_din, - input buff_we, - output reg busy -); - -assign sd_lba = lba; -assign sd_conf = 0; -assign sd_sdhc = 1; - -trkbuf buffer -( - .clock(~clk), - - .address_a(sd_buff_base + base_fix + sd_buff_addr), - .data_a(sd_buff_dout), - .wren_a(sd_ack & sd_buff_wr), - .q_a(sd_buff_din), - - .address_b({sector, buff_addr}), - .data_b(buff_din), - .wren_b(buff_we), - .q_b(buff_dout) -); - -wire [9:0] start_sectors[41] = - '{ 0, 0, 21, 42, 63, 84,105,126,147,168,189,210,231,252,273,294,315,336,357,376,395, - 414,433,452,471,490,508,526,544,562,580,598,615,632,649,666,683,700,717,734,751}; - -reg [31:0] lba; -reg [12:0] base_fix; -reg [12:0] sd_buff_base; - -always @(posedge clk) begin - reg [5:0] ack; - reg [5:0] cur_track = 0; - reg old_change, ready = 0; - reg saving = 0; - - old_change <= change; - if(~old_change & change) ready <= 1; - - ack <= {ack[4:0], sd_ack}; - if(ack[5:4] == 2'b01) {sd_rd,sd_wr} <= 0; - - if(reset) begin - cur_track <= 'b111111; - busy <= 0; - sd_rd <= 0; - sd_wr <= 0; - saving<= 0; - end - - else - if(busy) begin - if(ack[5:4] == 2'b10) begin - if(sd_buff_base < 'h1800) begin - sd_buff_base <= sd_buff_base + 13'd512; - lba <= lba + 1'd1; - if(saving) sd_wr <= 1; - else sd_rd <= 1; - end - else - if(saving && (cur_track != track)) begin - saving <= 0; - cur_track <= track; - sd_buff_base <= 0; - base_fix <= start_sectors[track][0] ? 13'h1F00 : 13'h0000; - lba <= start_sectors[track][9:1]; - sd_rd <= 1; - end else begin - busy <= 0; - end - end - end - else - if(ready) begin - if(save_track && cur_track != 'b111111) begin - saving <= 1; - sd_buff_base <= 0; - lba <= start_sectors[cur_track][9:1]; - sd_wr <= 1; - busy <= 1; - end - else - if((cur_track != track) || (old_change && ~change)) begin - saving <= 0; - cur_track <= track; - sd_buff_base <= 0; - base_fix <= start_sectors[track][0] ? 13'h1F00 : 13'h0000; - lba <= start_sectors[track][9:1]; - sd_rd <= 1; - busy <= 1; - end - end -end - -endmodule