From 51da86634c3769b6eb8d0933efceb825816a2dd9 Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi Date: Thu, 23 Apr 2020 21:35:59 +0200 Subject: [PATCH] C64: [VIC2] fix VIC address out (phi1test.prg) --- cores/c64/rtl/fpga64_sid_iec.vhd | 2 +- cores/c64/rtl/video_vicII_656x_a.vhd | 19 ++++++++++++------- 2 files changed, 13 insertions(+), 8 deletions(-) diff --git a/cores/c64/rtl/fpga64_sid_iec.vhd b/cores/c64/rtl/fpga64_sid_iec.vhd index 52845bc..2dbb6e5 100644 --- a/cores/c64/rtl/fpga64_sid_iec.vhd +++ b/cores/c64/rtl/fpga64_sid_iec.vhd @@ -509,7 +509,7 @@ begin vic: entity work.video_vicii_656x generic map ( registeredAddress => false, - emulateRefresh => false, + emulateRefresh => true, emulateLightpen => true, emulateGraphics => true ) diff --git a/cores/c64/rtl/video_vicII_656x_a.vhd b/cores/c64/rtl/video_vicII_656x_a.vhd index 7acbd93..29194c8 100644 --- a/cores/c64/rtl/video_vicII_656x_a.vhd +++ b/cores/c64/rtl/video_vicII_656x_a.vhd @@ -379,9 +379,6 @@ vicStateMachine: process(clk) vicAddrLoc <= CB & nextChar(7 downto 0) & rowCounter; end if; end if; - if ECM = '1' then - vicAddrLoc(10 downto 9) <= "00"; - end if; case vicCycle is when cycleRefresh1 | cycleRefresh2 | cycleRefresh3 | cycleRefresh4 | cycleRefresh5 => @@ -393,19 +390,27 @@ vicStateMachine: process(clk) when cycleSpriteBa1 | cycleSpriteBa2 | cycleSpriteBa3 => vicAddrLoc <= (others => '1'); when cycleSpriteA => - vicAddrLoc <= VM & "1111111" & sprite; if phi = '1' then - vicAddrLoc <= MPtr & MCnt(to_integer(sprite)); + if MDMA_Next(to_integer(sprite)) then + vicAddrLoc <= MPtr & MCnt(to_integer(sprite)); + end if; + else + vicAddrLoc <= VM & "1111111" & sprite; end if; when cycleSpriteB => - vicAddrLoc <= MPtr & MCnt(to_integer(sprite)); + if MDMA_Next(to_integer(sprite)) then + vicAddrLoc <= MPtr & MCnt(to_integer(sprite)); + end if; when others => + if ECM = '1' then + vicAddrLoc(10 downto 9) <= "00"; + end if; if phi = '1' then vicAddrLoc <= VM & colCounter; end if; end case; end process; - + -- Registered address process(clk) begin