diff --git a/cores/c16/c16_mist.v b/cores/c16/c16_mist.v
index b436050..da927e8 100644
--- a/cores/c16/c16_mist.v
+++ b/cores/c16/c16_mist.v
@@ -143,9 +143,9 @@ wire mux_sdram_oe = clkref ? c16_sdram_oe : tap_sdram_oe;
 wire [15:0] sdram_din = { mux_sdram_data, mux_sdram_data };
 wire [14:0] sdram_addr_64k = mux_sdram_addr[15:1];   // 64k mapping
 wire [14:0] sdram_addr_16k = { 1'b0, mux_sdram_addr[13:7], 1'b0, mux_sdram_addr[6:1] };   // 16k
-wire [24:0] sdram_addr = (clkref | (~clkref & prg_download)) ?
+wire [23:0] sdram_addr = (clkref | (~clkref & prg_download)) ?
                          { 10'h00, memory_16k?sdram_addr_16k:sdram_addr_64k } :
-                         (tap_sdram_oe ? tap_play_addr : ioctl_sdram_addr);
+                         (tap_sdram_oe ? tap_play_addr[24:1] : ioctl_sdram_addr[24:1]);
 
 wire sdram_wr = mux_sdram_wr;
 wire sdram_oe = mux_sdram_oe;
@@ -171,12 +171,15 @@ end
 
 // latch/demultiplex dram address
 reg [7:0] c16_a_low;
-always @(negedge c16_ras)
-	c16_a_low <= c16_a;
-
 reg [7:0] c16_a_hi;
-always @(negedge c16_cas)
-	c16_a_hi <= c16_a;
+
+always @(posedge clk28) begin
+	reg c16_rasD, c16_casD;
+	c16_rasD <= c16_ras;
+	c16_casD <= c16_cas;
+	if (c16_rasD & ~c16_ras) c16_a_low <= c16_a;
+	if (c16_casD & ~c16_cas) c16_a_hi  <= c16_a;
+end
 
 sdram sdram (
    // interface to the MT48LC16M16 chip
diff --git a/cores/c16/sdram.v b/cores/c16/sdram.v
index 2575d19..e32e095 100644
--- a/cores/c16/sdram.v
+++ b/cores/c16/sdram.v
@@ -39,7 +39,7 @@ module sdram (
 	
 	input [15:0]  		din,		// data input from chipset/cpu
 	output reg [15:0]	dout,		// data output to chipset/cpu
-	input [24:0]   		addr,       // 25 bit word address
+	input [23:0]   		addr,       // 24 bit word address
 	input [1:0] 		ds,         // data strobe for hi/low byte
 	input 		 		oe,         // cpu/chipset requests read
 	input 		 		we          // cpu/chipset requests write
@@ -129,11 +129,11 @@ always @(posedge clk) begin
 		end
 	end else begin
 		if(q <= STATE_CMD_START) begin	
-			sd_addr <= addr[20:8];
+			sd_addr <= { addr[20:15], addr[6:0] };
 			sd_ba <= addr[22:21];
 			sd_dqm <= { !ds[1], !ds[0] };
 		end else
-			sd_addr <= { 4'b0010, addr[23], addr[7:0]};
+			sd_addr <= { 4'b0010, addr[23], addr[14:7]};
 	
 		if(q == STATE_IDLE) begin
 			if(we || oe) sd_cmd <= CMD_ACTIVE;