diff --git a/tests/tg68k/TG68K_ALU.vhd b/tests/tg68k/TG68K_ALU.vhd
index cb1851f..0f588d6 100644
--- a/tests/tg68k/TG68K_ALU.vhd
+++ b/tests/tg68k/TG68K_ALU.vhd
@@ -164,7 +164,7 @@ architecture logic of TG68K_ALU IS
   signal copymux0     : std_logic_vector(39 downto 0);
   signal copymux1     : std_logic_vector(39 downto 0);
   signal copymux2     : std_logic_vector(39 downto 0);
-  signal copymux3     : std_logic_vector(31 downto 0);
+  signal copymux3     : std_logic_vector(39 downto 0);
   signal bf_set2      : std_logic_vector(31 downto 0);
   signal shift        : std_logic_vector(39 downto 0);
   signal copy         : std_logic_vector(39 downto 0);
@@ -509,38 +509,36 @@ process (clk, mux, mask, bitnr, bf_ins, bf_bchg, bf_bset, bf_exts, bf_shift, inm
 	  bf_set2(31 downto 0) <= inmux3;
 	end if;
 
+        -- shift 16 bits left if required while expanding sign from 32 bits to 40 bits
+        --TH: Check if it's possible to shift 1 bits in from lsb instead of wrapping
 	if bf_loffset(4) = '1' then
-	  copymux3 <= sign(15 downto 0) & sign(31 downto 16);
+	  copymux3 <= sign(23 downto 0) & "11111111" & sign(31 downto 24);
 	else
-	  copymux3 <= sign;
+	  copymux3 <= "11111111" & sign;
 	end if;
+        
+        -- shift 8 bits left if required
 	if bf_loffset(3) = '1' then
-	  copymux2(31 downto 0) <= copymux3(23 downto 0) & copymux3(31 downto 24);
+	  copymux2 <= copymux3(31 downto 0) & copymux3(39 downto 32);
 	else
-	  copymux2(31 downto 0) <= copymux3;
+	  copymux2 <= copymux3;
 	end if;
-        
-        --TH: Is the following really useful/needed here? I had to add some more
-        -- processing later to make this really work. But i assume this
-        -- code here should then not be needed anymore.
-        -- But tests say it is :-( Need to understand why!
-	if bf_d32 = '1' then
-	  copymux2(39 downto 32) <= copymux3(7 downto 0);
-	else
-	  copymux2(39 downto 32) <= "11111111";
-	end if;
-        
+
+        -- shift 4 bits left if required
 	if bf_loffset(2) = '1' then
 	  copymux1 <= copymux2(35 downto 0) & copymux2(39 downto 36);
 	else
 	  copymux1 <= copymux2;
 	end if;
+        
+        -- shift 2 bits left if required
 	if bf_loffset(1) = '1' then
 	  copymux0 <= copymux1(37 downto 0) & copymux1(39 downto 38);
 	else
 	  copymux0 <= copymux1;
 	end if;
 
+        -- shift 1 bit left if required
         if bf_loffset(0) = '1' then
           copymuxd32 <= copymux0(38 downto 0) & copymux0(39);
 	else
diff --git a/tests/tg68k/TG68KdotC_Kernel.vhd b/tests/tg68k/TG68KdotC_Kernel.vhd
index a7851b7..d068a2f 100644
--- a/tests/tg68k/TG68KdotC_Kernel.vhd
+++ b/tests/tg68k/TG68KdotC_Kernel.vhd
@@ -114,7 +114,6 @@ architecture logic of TG68KdotC_Kernel is
   signal sndOPC                 : std_logic_vector(15 downto 0);
 
   signal last_opc_read          : std_logic_vector(15 downto 0);
-  signal registerin             : std_logic_vector(31 downto 0);
   signal reg_QA                 : std_logic_vector(31 downto 0);
   signal reg_QB                 : std_logic_vector(31 downto 0);
   signal Wwrena                 : bit;
@@ -1753,7 +1752,7 @@ PROCESS (clk, IPL, setstate, state, exec_write_back, set_direct_data, next_micro
 				  ea_build_now <= '1';
 				  set_exec(opcMOVESR) <= '1';
 				  datatype <= "01";
-				  write_back <= '1'; -- im 68000 wird auch erst gelesen
+				  write_back <= '1'; -- 68000 also reads first
 				  if cpu(0) = '1' and state = "10" then
 					skipFetch <= '1';
 				  end if;
@@ -1785,7 +1784,7 @@ PROCESS (clk, IPL, setstate, state, exec_write_back, set_direct_data, next_micro
 				  set_exec(opcMOVECCR) <= '1';
 				  --datatype <= "00"; -- WRONG, should be WORD zero extended.
 				  datatype <= "01"; -- WRONG, should be WORD zero extended.
-				  write_back <= '1'; -- im 68000 wird auch erst gelesen
+				  write_back <= '1'; -- 68000 also reads first
 				  if opcode(5 downto 4) = "00" then
 					set_exec(Regwrena) <= '1';
 				  end if;
@@ -2556,7 +2555,11 @@ PROCESS (clk, IPL, setstate, state, exec_write_back, set_direct_data, next_micro
 			  end if;
 														-- register destination
 			  if opcode(4 downto 3) = "00" then
-				set_exec(Regwrena) <= '1';
+                                -- bftst doesn't write
+                                if opcode(10 downto 8) /= "000" then
+                                  set_exec(Regwrena) <= '1';
+                                end if;
+                            
 				if exec(ea_build) = '1' then
 				  dest_2ndHbits <= '1';
 				  source_2ndLbits <= '1';
diff --git a/tests/tg68k/tests/bfxxx.s b/tests/tg68k/tests/bfxxx.s
index ac2fc4f..b214abf 100644
--- a/tests/tg68k/tests/bfxxx.s
+++ b/tests/tg68k/tests/bfxxx.s
@@ -2,12 +2,13 @@
 	; http://oldwww.nvg.ntnu.no/amiga/MC680x0_Sections/bfset.HTML
 	; http://oldwww.nvg.ntnu.no/amiga/MC680x0_Sections/bfchg.HTML
 	; http://oldwww.nvg.ntnu.no/amiga/MC680x0_Sections/bfclr.HTML
-
+	; http://68k.hax.com/BFSET
+	
 	;; test register wrapping
 	;; this test failed in tg68 since the target register always
 	;; was d0
 	move.l  #$11223344,d2
-	bfset	d2{24:16}
+	bfset	d2{24:15}
 	bmi	fail			; msb ($44) was not set
 	cmp.l 	#$ff2233ff,d2
 	bne	fail
@@ -25,6 +26,15 @@
   	cmp.l 	#$fff67bcd,testword1+4
  	bne     fail
 
+;	move.l  #$abc00000,testword1
+;	move.l  #$00067bcd,testword1+4
+;	move.l  #testword1,a0
+;	bfset	(a0){12:32}
+;	cmp.l 	#$abcfffff,testword1
+;   	bne     fail
+;  	cmp.l 	#$fff67bcd,testword1+4
+; 	bne     fail
+
  	move.l  #$a0010bcd,testword1
  	bfset	testword1{4:16}
  	beq	fail			; one bit wasn't 0
@@ -119,6 +129,19 @@
 	cmp	#1,d3
 	bne	fail
 	
+	;; mikej report 16.1.16
+	moveq	#-1,d0
+	bftst	d0{0:18}
+	cmp.l	#-1,d0
+	bne.s	fail 			; tk68k modified the register
+	
+	;; mikej report 16.1.16
+	moveq	#-1,d0
+	moveq	#-1,d1
+	bfchg	d0{0:18}
+	cmp.l	#$3fff,d0
+	bne.s	fail 
+
 	;; test some of the 68020 addressing modes
 	move.l  #$12345678,testword3
  	move.l  #$89abcdef,testword3+4