From 5b7de4ea7ccc0f661f562b8423af6558320843cd Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi Date: Sun, 2 Sep 2018 02:46:18 +0200 Subject: [PATCH] C16: upgradeable BASIC and 1541 ROMs 1541 + kernal + basic --- cores/c16/basic_rom.v | 8 +++- cores/c16/c1541/c1541_logic.vhd | 26 +++++++---- cores/c16/c1541/c1541_sd.vhd | 12 ++++- cores/c16/c1541/gen_rom.vhd | 65 ++++++++++++++++++++++++++++ cores/c16/c1541/sprom.vhd | 77 --------------------------------- cores/c16/c16.v | 15 ++++--- cores/c16/c16_mist.qsf | 9 ++-- cores/c16/c16_mist.v | 37 +++++++++------- 8 files changed, 135 insertions(+), 114 deletions(-) create mode 100644 cores/c16/c1541/gen_rom.vhd delete mode 100644 cores/c16/c1541/sprom.vhd diff --git a/cores/c16/basic_rom.v b/cores/c16/basic_rom.v index f319ae9..f5825d5 100644 --- a/cores/c16/basic_rom.v +++ b/cores/c16/basic_rom.v @@ -37,6 +37,8 @@ module basic_rom( input wire clk, input wire [13:0] address_in, output wire [7:0] data_out, + input wire [7:0] data_in, + input wire wr, input wire cs ); @@ -46,9 +48,13 @@ reg [7:0] data; reg cs_prev=1'b1; wire enable; -always@(posedge clk) +always@(posedge clk) begin + if (wr) + basic[address_in] <= data_in; + if(enable) data<=basic[address_in]; +end always@(posedge clk) cs_prev<=cs; diff --git a/cores/c16/c1541/c1541_logic.vhd b/cores/c16/c1541/c1541_logic.vhd index 0d90fda..6abcd74 100644 --- a/cores/c16/c1541/c1541_logic.vhd +++ b/cores/c16/c1541/c1541_logic.vhd @@ -40,6 +40,11 @@ entity c1541_logic is wps_n : in std_logic; -- write-protect sense tr00_sense_n : in std_logic; -- track 0 sense (unused?) act : out std_logic; -- activity LED + + c1541rom_clk : in std_logic; + c1541rom_addr : in std_logic_vector(13 downto 0); + c1541rom_data : in std_logic_vector(7 downto 0); + c1541rom_wr : in std_logic; dbg_adr_fetch : out std_logic_vector(15 downto 0); -- dbg DAR dbg_cpu_irq : out std_logic -- dbg DAR @@ -126,7 +131,7 @@ begin count := std_logic_vector(unsigned(count) + 1); end if; - if count = "00000" then clk_1M_pulse <= '1'; else clk_1M_pulse <='0' ; end if; + if count = "10000" then clk_1M_pulse <= '1'; else clk_1M_pulse <='0' ; end if; if count = "00000" then p2_h_r <= '1'; else p2_h_r <='0' ; end if; if count = "10000" then p2_h_f <= '1'; else p2_h_f <='0' ; end if; end process; @@ -226,24 +231,29 @@ begin data_out => cpu_do ); - rom_inst : entity work.sprom + rom_inst : entity work.gen_rom generic map ( -- init_file => "../roms/JiffyDOS_C1541.hex", -- DAR tested OK -- init_file => "../roms/25196802.hex", -- init_file => "../roms/25196801.hex", - init_file => "../roms/325302-1_901229-03.hex", + INIT_FILE => "../roms/325302-1_901229-03.hex", -- init_file => "../roms/1541_c000_01_and_e000_06aa.hex", -- DAR tested OK - numwords_a => 16384, - widthad_a => 14 + DATA_WIDTH => 8, + ADDR_WIDTH => 14 ) port map ( - clock => clk_32M, - address => cpu_a(13 downto 0), - q => rom_do + rdclock => clk_32M, + rdaddress => cpu_a(13 downto 0), + q => rom_do, + + wrclock => c1541rom_clk, + wraddress => c1541rom_addr, + wren => c1541rom_wr, + data => c1541rom_data ); ram_inst : entity work.spram diff --git a/cores/c16/c1541/c1541_sd.vhd b/cores/c16/c1541/c1541_sd.vhd index 676f499..86a954b 100644 --- a/cores/c16/c1541/c1541_sd.vhd +++ b/cores/c16/c1541/c1541_sd.vhd @@ -56,6 +56,11 @@ port( led : out std_logic; + c1541rom_clk : in std_logic; + c1541rom_addr : in std_logic_vector(13 downto 0); + c1541rom_data : in std_logic_vector(7 downto 0); + c1541rom_wr : in std_logic; + dbg_track_num_dbl : out std_logic_vector(6 downto 0); dbg_sd_busy : out std_logic; dbg_sd_state : out std_logic_vector(7 downto 0); @@ -171,7 +176,12 @@ begin wps_n => '1', -- write-protect sense (0 = protected) tr00_sense_n => '1', -- track 0 sense (unused?) act => act, -- activity LED - + + c1541rom_clk => c1541rom_clk, + c1541rom_addr => c1541rom_addr, + c1541rom_data => c1541rom_data, + c1541rom_wr => c1541rom_wr, + dbg_adr_fetch => dbg_adr_fetch, dbg_cpu_irq => open ); diff --git a/cores/c16/c1541/gen_rom.vhd b/cores/c16/c1541/gen_rom.vhd new file mode 100644 index 0000000..b254f67 --- /dev/null +++ b/cores/c16/c1541/gen_rom.vhd @@ -0,0 +1,65 @@ +-- altera message_off 10306 + +library ieee; +use IEEE.std_logic_1164.all; +use IEEE.std_logic_unsigned.ALL; +use IEEE.numeric_std.all; + +entity gen_rom is + + generic + ( + INIT_FILE : string := ""; + ADDR_WIDTH : natural := 14; + DATA_WIDTH : natural := 8 + ); + + port + ( + wrclock : in std_logic; + wraddress : in std_logic_vector((ADDR_WIDTH - 1) downto 0) := (others => '0'); + data : in std_logic_vector((DATA_WIDTH - 1) downto 0) := (others => '0'); + wren : in std_logic := '0'; + + rdclock : in std_logic; + rdaddress : in std_logic_vector((ADDR_WIDTH - 1) downto 0); + q : out std_logic_vector((DATA_WIDTH - 1) downto 0); + cs : in std_logic := '1' + ); + +end gen_rom; + +architecture rtl of gen_rom is + + subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0); + type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t; + + shared variable ram : memory_t; + + attribute ram_init_file : string; + attribute ram_init_file of ram : variable is INIT_FILE; + + signal q0 : std_logic_vector((DATA_WIDTH - 1) downto 0); + + +begin + + q<= q0 when cs = '1' else (others => '1'); + + -- WR Port + process(wrclock) begin + if(rising_edge(wrclock)) then + if(wren = '1') then + ram(to_integer(unsigned(wraddress))) := data; + end if; + end if; + end process; + + -- RD Port + process(rdclock) begin + if(rising_edge(rdclock)) then + q0 <= ram(to_integer(unsigned(rdaddress))); + end if; + end process; + +end rtl; diff --git a/cores/c16/c1541/sprom.vhd b/cores/c16/c1541/sprom.vhd deleted file mode 100644 index 2b1ae58..0000000 --- a/cores/c16/c1541/sprom.vhd +++ /dev/null @@ -1,77 +0,0 @@ -LIBRARY ieee; -USE ieee.std_logic_1164.all; - -LIBRARY altera_mf; -USE altera_mf.all; - -ENTITY sprom IS - GENERIC - ( - init_file : string := ""; - numwords_a : natural := 0; -- not used any more - widthad_a : natural; - width_a : natural := 8; - outdata_reg_a : string := "UNREGISTERED" - ); - PORT - ( - address : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - clock : IN STD_LOGIC ; - q : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); -END sprom; - - -ARCHITECTURE SYN OF sprom IS - - SIGNAL sub_wire0 : STD_LOGIC_VECTOR (width_a-1 DOWNTO 0); - - COMPONENT altsyncram - GENERIC ( - clock_enable_input_a : STRING; - clock_enable_output_a : STRING; - init_file : STRING; - intended_device_family : STRING; - lpm_hint : STRING; - lpm_type : STRING; - numwords_a : NATURAL; - operation_mode : STRING; - outdata_aclr_a : STRING; - outdata_reg_a : STRING; - widthad_a : NATURAL; - width_a : NATURAL; - width_byteena_a : NATURAL - ); - PORT ( - clock0 : IN STD_LOGIC ; - address_a : IN STD_LOGIC_VECTOR (widthad_a-1 DOWNTO 0); - q_a : OUT STD_LOGIC_VECTOR (width_a-1 DOWNTO 0) - ); - END COMPONENT; - -BEGIN - q <= sub_wire0(width_a-1 DOWNTO 0); - - altsyncram_component : altsyncram - GENERIC MAP ( - clock_enable_input_a => "BYPASS", - clock_enable_output_a => "BYPASS", - init_file => init_file, - intended_device_family => "Cyclone II", - lpm_hint => "ENABLE_RUNTIME_MOD=NO", - lpm_type => "altsyncram", - numwords_a => 2**widthad_a, - operation_mode => "ROM", - outdata_aclr_a => "NONE", - outdata_reg_a => outdata_reg_a, - widthad_a => widthad_a, - width_a => width_a, - width_byteena_a => 1 - ) - PORT MAP ( - clock0 => clock, - address_a => address, - q_a => sub_wire0 - ); - -END SYN; diff --git a/cores/c16/c16.v b/cores/c16/c16.v index 542d74e..7410dd6 100644 --- a/cores/c16/c16.v +++ b/cores/c16/c16.v @@ -65,10 +65,11 @@ module C16 #(parameter MODE_PAL = 1)( output AUDIO_L, output AUDIO_R, - - input [13:0] kernal_dl_addr, - input [7:0] kernal_dl_data, + + input [13:0] dl_addr, + input [7:0] dl_data, input kernal_dl_write, + input basic_dl_write, output PAL, @@ -152,9 +153,9 @@ ted mos8360( kernal_rom #(.MODE_PAL(MODE_PAL)) kernal( .clk(CLK28), - .address_in(sreset?kernal_dl_addr:c16_addr[13:0]), + .address_in(kernal_dl_write?dl_addr:c16_addr[13:0]), .data_out(kernal_data), - .data_in(kernal_dl_data), + .data_in(dl_data), .wr(kernal_dl_write), .cs(cs1) ); @@ -163,8 +164,10 @@ ted mos8360( basic_rom basic( .clk(CLK28), - .address_in(c16_addr[13:0]), + .address_in(basic_dl_write?dl_addr:c16_addr[13:0]), .data_out(basic_data), + .data_in(dl_data), + .wr(basic_dl_write), .cs(cs0) ); diff --git a/cores/c16/c16_mist.qsf b/cores/c16/c16_mist.qsf index 48f3a83..b409066 100644 --- a/cores/c16/c16_mist.qsf +++ b/cores/c16/c16_mist.qsf @@ -167,7 +167,7 @@ set_global_assignment -name USE_CONFIGURATION_DEVICE OFF # SignalTap II Assignments # ======================== set_global_assignment -name ENABLE_SIGNALTAP OFF -set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp2.stp +set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp # Power Estimation Assignments # ============================ @@ -341,11 +341,9 @@ set_global_assignment -name VERILOG_FILE c16_mist.v set_global_assignment -name VERILOG_FILE c16_keymatrix.v set_global_assignment -name VERILOG_FILE c16.v set_global_assignment -name VERILOG_FILE basic_rom.v -set_global_assignment -name SIGNALTAP_FILE stp1.stp -set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp set_global_assignment -name VHDL_FILE c1541/gcr_floppy.vhd set_global_assignment -name VHDL_FILE c1541/spram.vhd -set_global_assignment -name VHDL_FILE c1541/sprom.vhd +set_global_assignment -name VHDL_FILE c1541/gen_rom.vhd set_global_assignment -name VHDL_FILE c1541/c1541_sd.vhd set_global_assignment -name VHDL_FILE c1541/c1541_logic.vhd set_global_assignment -name VHDL_FILE c1541/via6522.vhd @@ -366,5 +364,4 @@ set_global_assignment -name VHDL_FILE 1541ultimate2cpu/alu.vhd set_global_assignment -name VHDL_FILE t65/T65_Pack.vhd set_global_assignment -name VHDL_FILE t65/T65_MCode.vhd set_global_assignment -name VHDL_FILE t65/T65_ALU.vhd -set_global_assignment -name VHDL_FILE t65/T65.vhd -set_global_assignment -name SIGNALTAP_FILE output_files/stp2.stp \ No newline at end of file +set_global_assignment -name VHDL_FILE t65/T65.vhd \ No newline at end of file diff --git a/cores/c16/c16_mist.v b/cores/c16/c16_mist.v index 886077c..dead4c0 100644 --- a/cores/c16/c16_mist.v +++ b/cores/c16/c16_mist.v @@ -487,21 +487,23 @@ wire c16_rw; wire [7:0] c16_a; wire [7:0] c16_dout; -reg kernal_dl_wr; -reg [7:0] kernal_dl_data; -reg [13:0] kernal_dl_addr; +reg kernal_dl_wr, basic_dl_wr, c1541_dl_wr; +reg [7:0] rom_dl_data; +reg [13:0] rom_dl_addr; -wire ioctl_kernal_wr = rom_download && ioctl_wr; +wire ioctl_rom_wr = rom_download && ioctl_wr; -reg last_ioctl_wr; always @(negedge clk28) begin - last_ioctl_wr <= ioctl_kernal_wr; - if(ioctl_kernal_wr && !last_ioctl_wr) begin - kernal_dl_data <= ioctl_data; - kernal_dl_addr <= ioctl_addr[13:0]; - kernal_dl_wr <= 1'b1; + reg last_ioctl_rom_wr; + last_ioctl_rom_wr <= ioctl_rom_wr; + if(ioctl_rom_wr && !last_ioctl_rom_wr) begin + rom_dl_data <= ioctl_data; + rom_dl_addr <= ioctl_addr[13:0]; + c1541_dl_wr <= !ioctl_addr[15:14]; + kernal_dl_wr <= ioctl_addr[15:14] == 2'd1; + basic_dl_wr <= ioctl_addr[15:14] == 2'd2; end else - kernal_dl_wr <= 1'b0; + { kernal_dl_wr, basic_dl_wr, c1541_dl_wr } <= 0; end // include the c16 itself @@ -529,9 +531,10 @@ C16 #(.MODE_PAL(MODE_PAL)) c16 ( .PS2DAT ( ps2_kbd_data ), .PS2CLK ( ps2_kbd_clk ), - .kernal_dl_addr ( kernal_dl_addr ), - .kernal_dl_data ( kernal_dl_data ), - .kernal_dl_write ( kernal_dl_wr), + .dl_addr ( rom_dl_addr ), + .dl_data ( rom_dl_data ), + .kernal_dl_write ( kernal_dl_wr ), + .basic_dl_write ( basic_dl_wr ), .IEC_DATAOUT ( c16_iec_data_o ), .IEC_DATAIN ( !c16_iec_data_i ), @@ -635,8 +638,12 @@ c1541_sd c1541_sd ( .sd_buff_dout ( sd_dout ), .sd_buff_wr ( sd_dout_strobe ), .sd_buff_addr ( sd_buff_addr ), + .led ( led_disk ), - .led ( led_disk ) + .c1541rom_clk ( clk28 ), + .c1541rom_addr ( rom_dl_addr ), + .c1541rom_data ( rom_dl_data ), + .c1541rom_wr ( c1541_dl_wr ) ); endmodule