From 6334cfd2c1079a44445f4dff2988ca9bec79abbc Mon Sep 17 00:00:00 2001
From: harbaum <till.harbaum@1und1.de>
Date: Mon, 10 Sep 2018 10:42:29 +0200
Subject: [PATCH] Add YPbPr tutorial

---
 tutorials/soc/lesson12/image.hex     | 502 +++++++++++++++++++++++++++
 tutorials/soc/lesson12/image.png     | Bin 0 -> 34560 bytes
 tutorials/soc/lesson12/image.qip     |   3 +
 tutorials/soc/lesson12/image.v       | 164 +++++++++
 tutorials/soc/lesson12/img2hex.sh    |   4 +
 tutorials/soc/lesson12/osd.v         | 182 ++++++++++
 tutorials/soc/lesson12/rgb2ypbpr.sv  |  55 +++
 tutorials/soc/lesson12/scandoubler.v | 147 ++++++++
 tutorials/soc/lesson12/soc.qpf       |  30 ++
 tutorials/soc/lesson12/soc.qsf       | 165 +++++++++
 tutorials/soc/lesson12/soc.rbf       | Bin 0 -> 241782 bytes
 tutorials/soc/lesson12/soc.v         | 194 +++++++++++
 tutorials/soc/lesson12/user_io.v     | 417 ++++++++++++++++++++++
 tutorials/soc/lesson12/video.v       | 124 +++++++
 tutorials/soc/readme.md              |  34 ++
 15 files changed, 2021 insertions(+)
 create mode 100644 tutorials/soc/lesson12/image.hex
 create mode 100644 tutorials/soc/lesson12/image.png
 create mode 100644 tutorials/soc/lesson12/image.qip
 create mode 100644 tutorials/soc/lesson12/image.v
 create mode 100755 tutorials/soc/lesson12/img2hex.sh
 create mode 100644 tutorials/soc/lesson12/osd.v
 create mode 100644 tutorials/soc/lesson12/rgb2ypbpr.sv
 create mode 100644 tutorials/soc/lesson12/scandoubler.v
 create mode 100644 tutorials/soc/lesson12/soc.qpf
 create mode 100644 tutorials/soc/lesson12/soc.qsf
 create mode 100644 tutorials/soc/lesson12/soc.rbf
 create mode 100644 tutorials/soc/lesson12/soc.v
 create mode 100644 tutorials/soc/lesson12/user_io.v
 create mode 100644 tutorials/soc/lesson12/video.v

diff --git a/tutorials/soc/lesson12/image.hex b/tutorials/soc/lesson12/image.hex
new file mode 100644
index 0000000..63ed88f
--- /dev/null
+++ b/tutorials/soc/lesson12/image.hex
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diff --git a/tutorials/soc/lesson12/image.qip b/tutorials/soc/lesson12/image.qip
new file mode 100644
index 0000000..2693b8e
--- /dev/null
+++ b/tutorials/soc/lesson12/image.qip
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "image.v"]
diff --git a/tutorials/soc/lesson12/image.v b/tutorials/soc/lesson12/image.v
new file mode 100644
index 0000000..5a4b7ea
--- /dev/null
+++ b/tutorials/soc/lesson12/image.v
@@ -0,0 +1,164 @@
+// megafunction wizard: %ROM: 1-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: image.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.4 Build 182 03/12/2014 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2014 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module image (
+	address,
+	clock,
+	q);
+
+	input	[13:0]  address;
+	input	  clock;
+	output	[7:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [7:0] sub_wire0;
+	wire [7:0] q = sub_wire0[7:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (address),
+				.clock0 (clock),
+				.q_a (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.address_b (1'b1),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_a ({8{1'b1}}),
+				.data_b (1'b1),
+				.eccstatus (),
+				.q_b (),
+				.rden_a (1'b1),
+				.rden_b (1'b1),
+				.wren_a (1'b0),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_a = "NONE",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+`ifdef NO_PLI
+		altsyncram_component.init_file = "image.rif"
+`else
+		altsyncram_component.init_file = "image.hex"
+`endif
+,
+		altsyncram_component.intended_device_family = "Cyclone III",
+		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 16384,
+		altsyncram_component.operation_mode = "ROM",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_reg_a = "UNREGISTERED",
+		altsyncram_component.widthad_a = 14,
+		altsyncram_component.width_a = 8,
+		altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clken NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING "image.hex"
+// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "16384"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+// Retrieval info: PRIVATE: WidthAddr NUMERIC "14"
+// Retrieval info: PRIVATE: WidthData NUMERIC "8"
+// Retrieval info: PRIVATE: rden NUMERIC "0"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: INIT_FILE STRING "image.hex"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: address 0 0 14 0 INPUT NODEFVAL "address[13..0]"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
+// Retrieval info: CONNECT: @address_a 0 0 14 0 address 0 0 14 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 8 0 @q_a 0 0 8 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL image.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL image.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL image.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL image.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL image_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL image_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/tutorials/soc/lesson12/img2hex.sh b/tutorials/soc/lesson12/img2hex.sh
new file mode 100755
index 0000000..d1af36f
--- /dev/null
+++ b/tutorials/soc/lesson12/img2hex.sh
@@ -0,0 +1,4 @@
+#!/bin/bash
+avconv -vcodec png -i image.png -vcodec rawvideo -f rawvideo -pix_fmt rgb8 image.raw
+srec_cat image.raw -binary -o image.hex -intel
+
diff --git a/tutorials/soc/lesson12/osd.v b/tutorials/soc/lesson12/osd.v
new file mode 100644
index 0000000..a654b40
--- /dev/null
+++ b/tutorials/soc/lesson12/osd.v
@@ -0,0 +1,182 @@
+// A simple OSD implementation. Can be hooked up between a cores
+// VGA output and the physical VGA pins
+
+module osd (
+	// OSDs pixel clock, should be synchronous to cores pixel clock to
+	// avoid jitter.
+	input 			pclk,
+
+	// SPI interface
+	input         sck,
+	input         ss,
+	input         sdi,
+
+	// VGA signals coming from core
+	input [5:0]  	red_in,
+	input [5:0]  	green_in,
+	input [5:0]  	blue_in,
+	input				hs_in,
+	input				vs_in,
+	
+	// VGA signals going to video connector
+	output [5:0]  	red_out,
+	output [5:0]  	green_out,
+	output [5:0]  	blue_out,
+	output			hs_out,
+	output			vs_out
+);
+
+parameter OSD_X_OFFSET = 10'd0;
+parameter OSD_Y_OFFSET = 10'd0;
+parameter OSD_COLOR    = 3'd0;
+
+localparam OSD_WIDTH  = 10'd256;
+localparam OSD_HEIGHT = 10'd128;
+
+// *********************************************************************************
+// spi client
+// *********************************************************************************
+
+// this core supports only the display related OSD commands
+// of the minimig
+reg [7:0]      sbuf;
+reg [7:0]      cmd;
+reg [4:0]      cnt;
+reg [10:0]     bcnt;
+reg    			osd_enable;
+
+reg [7:0] osd_buffer [2047:0];  // the OSD buffer itself
+
+// the OSD has its own SPI interface to the io controller
+always@(posedge sck, posedge ss) begin
+  if(ss == 1'b1) begin
+      cnt <= 5'd0;
+      bcnt <= 11'd0;
+  end else begin
+    sbuf <= { sbuf[6:0], sdi};
+
+    // 0:7 is command, rest payload
+    if(cnt < 15)
+      cnt <= cnt + 4'd1;
+    else
+      cnt <= 4'd8;
+
+      if(cnt == 7) begin
+       cmd <= {sbuf[6:0], sdi};
+      
+      // lower three command bits are line address
+      bcnt <= { sbuf[1:0], sdi, 8'h00};
+
+      // command 0x40: OSDCMDENABLE, OSDCMDDISABLE
+      if(sbuf[6:3] == 4'b0100)
+        osd_enable <= sdi;
+    end
+
+    // command 0x20: OSDCMDWRITE
+    if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
+      osd_buffer[bcnt] <= {sbuf[6:0], sdi};
+      bcnt <= bcnt + 11'd1;
+    end
+  end
+end
+
+// *********************************************************************************
+// video timing and sync polarity anaylsis
+// *********************************************************************************
+
+// horizontal counter
+reg [9:0] h_cnt;
+reg hsD, hsD2;
+reg [9:0] hs_low, hs_high;
+wire hs_pol = hs_high < hs_low;
+wire [9:0] h_dsp_width = hs_pol?hs_low:hs_high;
+wire [9:0] h_dsp_ctr = { 1'b0, h_dsp_width[9:1] };
+
+always @(posedge pclk) begin
+	// bring hsync into local clock domain
+	hsD <= hs_in;
+	hsD2 <= hsD;
+
+	// falling edge of hs_in
+	if(!hsD && hsD2) begin	
+		h_cnt <= 10'd0;
+		hs_high <= h_cnt;
+	end
+
+	// rising edge of hs_in
+	else if(hsD && !hsD2) begin	
+		h_cnt <= 10'd0;
+		hs_low <= h_cnt;
+	end 
+	
+	else
+		h_cnt <= h_cnt + 10'd1;
+end
+
+// vertical counter
+reg [9:0] v_cnt;
+reg vsD, vsD2;
+reg [9:0] vs_low, vs_high;
+wire vs_pol = vs_high < vs_low;
+wire [9:0] v_dsp_width = vs_pol?vs_low:vs_high;
+wire [9:0] v_dsp_ctr = { 1'b0, v_dsp_width[9:1] };
+
+always @(posedge hs_in) begin
+	// bring vsync into local clock domain
+	vsD <= vs_in;
+	vsD2 <= vsD;
+
+	// falling edge of vs_in
+	if(!vsD && vsD2) begin	
+		v_cnt <= 10'd0;
+		vs_high <= v_cnt;
+	end
+
+	// rising edge of vs_in
+	else if(vsD && !vsD2) begin	
+		v_cnt <= 10'd0;
+		vs_low <= v_cnt;
+	end 
+	
+	else
+		v_cnt <= v_cnt + 10'd1;
+end
+
+// area in which OSD is being displayed
+wire [9:0] h_osd_start = h_dsp_ctr + OSD_X_OFFSET - (OSD_WIDTH >> 1);
+wire [9:0] h_osd_end   = h_dsp_ctr + OSD_X_OFFSET + (OSD_WIDTH >> 1) - 1;
+wire [9:0] v_osd_start = v_dsp_ctr + OSD_Y_OFFSET - (OSD_HEIGHT >> 1);
+wire [9:0] v_osd_end   = v_dsp_ctr + OSD_Y_OFFSET + (OSD_HEIGHT >> 1) - 1;
+
+reg h_osd_active, v_osd_active;
+always @(posedge pclk) begin
+	if(hs_in != hs_pol) begin
+		if(h_cnt == h_osd_start) h_osd_active <= 1'b1;
+		if(h_cnt == h_osd_end)   h_osd_active <= 1'b0;
+	end
+	if(vs_in != vs_pol) begin
+		if(v_cnt == v_osd_start) v_osd_active <= 1'b1;
+		if(v_cnt == v_osd_end)   v_osd_active <= 1'b0;
+	end
+end
+
+wire osd_de = osd_enable && h_osd_active && v_osd_active;
+
+wire [7:0] osd_hcnt = h_cnt - h_osd_start + 7'd1;  // one pixel offset for osd_byte register
+wire [6:0] osd_vcnt = v_cnt - v_osd_start;
+
+wire osd_pixel = osd_byte[osd_vcnt[3:1]];
+
+reg [7:0] osd_byte; 
+always @(posedge pclk)
+  osd_byte <= osd_buffer[{osd_vcnt[6:4], osd_hcnt}];
+
+wire [2:0] osd_color = OSD_COLOR;
+assign red_out   = !osd_de?red_in:  {osd_pixel, osd_pixel, osd_color[2], red_in[5:3]  };
+assign green_out = !osd_de?green_in:{osd_pixel, osd_pixel, osd_color[1], green_in[5:3]};
+assign blue_out  = !osd_de?blue_in: {osd_pixel, osd_pixel, osd_color[0], blue_in[5:3] };
+
+assign hs_out = hs_in;
+assign vs_out = vs_in;
+
+endmodule
\ No newline at end of file
diff --git a/tutorials/soc/lesson12/rgb2ypbpr.sv b/tutorials/soc/lesson12/rgb2ypbpr.sv
new file mode 100644
index 0000000..1e1662e
--- /dev/null
+++ b/tutorials/soc/lesson12/rgb2ypbpr.sv
@@ -0,0 +1,55 @@
+module rgb2ypbpr (
+	input [5:0]     red,
+	input [5:0]     green,
+	input [5:0]     blue,
+
+	output [5:0]    y,
+	output [5:0]    pb,
+	output [5:0]    pr
+);	
+	
+wire [5:0] yuv_full[225] = '{
+  6'd0,   6'd0,  6'd0,  6'd0,  6'd1,  6'd1,  6'd1,  6'd1,
+  6'd2,   6'd2,  6'd2,  6'd3,  6'd3,  6'd3,  6'd3,  6'd4,
+  6'd4,   6'd4,  6'd5,  6'd5,  6'd5,  6'd5,  6'd6,  6'd6,
+  6'd6,   6'd7,  6'd7,  6'd7,  6'd7,  6'd8,  6'd8,  6'd8,
+  6'd9,   6'd9,  6'd9,  6'd9, 6'd10, 6'd10, 6'd10, 6'd11,
+  6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13,
+  6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15,
+  6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17,
+  6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20,
+  6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22,
+  6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24,
+  6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27,
+  6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29,
+  6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31,
+  6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33,
+  6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36,
+  6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38,
+  6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40,
+  6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42,
+  6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45,
+  6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47,
+  6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49,
+  6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52,
+  6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54,
+  6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56,
+  6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58,
+  6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61,
+  6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63,
+  6'd63
+};
+
+wire [18:0]  y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0});
+wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0});
+wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0});
+
+wire [7:0] y_i  = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 :  y_8[15:8];
+wire [7:0] pb_i = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8];
+wire [7:0] pr_i = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8];
+
+assign pr = yuv_full[pr_i - 8'd16];
+assign y  = yuv_full[y_i  - 8'd16];
+assign pb = yuv_full[pb_i - 8'd16];
+
+endmodule
diff --git a/tutorials/soc/lesson12/scandoubler.v b/tutorials/soc/lesson12/scandoubler.v
new file mode 100644
index 0000000..6edcc8d
--- /dev/null
+++ b/tutorials/soc/lesson12/scandoubler.v
@@ -0,0 +1,147 @@
+//
+// scandoubler.v
+// 
+// Copyright (c) 2015 Till Harbaum <till@harbaum.org> 
+// 
+// This source file is free software: you can redistribute it and/or modify 
+// it under the terms of the GNU General Public License as published 
+// by the Free Software Foundation, either version 3 of the License, or 
+// (at your option) any later version. 
+// 
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of 
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the 
+// GNU General Public License for more details.
+// 
+// You should have received a copy of the GNU General Public License 
+// along with this program.  If not, see <http://www.gnu.org/licenses/>. 
+
+module scandoubler (
+  // system interface
+  input        clk_in,
+  input 	      clk_out,
+  
+  input        scanlines,
+  
+  // shifter video interface
+  input 	   hs_in,
+  input 	   vs_in,
+  input [5:0] 	r_in,
+  input [5:0] 	g_in,
+  input [5:0] 	b_in,
+
+  // output interface
+  output reg [5:0] r_out,
+  output reg [5:0] g_out,
+  output reg [5:0] b_out,
+  output reg vs_out,
+  output reg hs_out
+);
+
+// scan doubler output register
+reg [17:0]  sd_out;
+
+// --------------------- create output signals -----------------
+// latch everything once more to make it glitch free and apply scanline effect
+reg scanline;
+
+always @(posedge clk_out) begin
+	vs_out <= vs_in;
+	hs_out <= hs_sd;
+
+   // reset scanlines at every new screen
+   if(vs_out != vs_in)
+     scanline <= 1'b0;
+   
+    // toggle scanlines at begin of every hsync
+    if(hs_out && !hs_sd)
+         scanline <= !scanline;
+
+    // if no scanlines or not a scanline
+	 if(!scanlines || !scanline) begin
+		r_out <= { sd_out[17:12] };
+		g_out <= { sd_out[11:6] };
+		b_out <= { sd_out[5:0] };
+	end else begin
+		r_out <= { 1'b0, sd_out[17:13] };
+		g_out <= { 1'b0, sd_out[11:7] };
+		b_out <= { 1'b0, sd_out[5:1] };
+	end
+end
+   
+
+   
+// ==================================================================
+// ======================== the line buffers ========================
+// ==================================================================
+
+// 2 lines of 1024 pixels 3*6 bit RGB
+reg [17:0] sd_buffer [2047:0];
+
+// use alternating sd_buffers when storing/reading data   
+reg vsD;
+reg line_toggle;
+always @(negedge clk_in) begin
+	vsD <= vs_in;
+
+   if(vsD != vs_in) 
+     line_toggle <= 1'b0;
+
+   // begin of incoming hsync
+   if(hsD && !hs_in) 
+     line_toggle <= !line_toggle;
+end
+   
+always @(negedge clk_in) begin 
+	sd_buffer[{line_toggle, hcnt}] <= { r_in, g_in, b_in };
+end
+   
+// ==================================================================
+// =================== horizontal timing analysis ===================
+// ==================================================================
+
+// total hsync time (in 16MHz cycles), hs_total reaches 1024
+reg [9:0] hs_max;
+reg [9:0] hs_rise;
+reg [9:0] hcnt;
+reg hsD;
+   
+always @(negedge clk_in) begin
+	hsD <= hs_in;
+
+	// falling edge of hsync indicates start of line
+	if(hsD && !hs_in) begin
+		hs_max <= hcnt;
+		hcnt <= 10'd0;
+	end else
+		hcnt <= hcnt + 10'd1;
+
+	// save position of rising edge
+	if(!hsD && hs_in)
+		hs_rise <= hcnt;
+end
+   
+// ==================================================================
+// ==================== output timing generation ====================
+// ==================================================================
+
+reg [9:0] sd_hcnt;
+reg hs_sd;
+
+// timing generation runs 32 MHz (twice the input signal analysis speed)
+always @(posedge clk_out) begin
+
+   // output counter synchronous to input and at twice the rate
+   sd_hcnt <= sd_hcnt + 10'd1;
+   if(hsD && !hs_in)     sd_hcnt <= hs_max;
+   if(sd_hcnt == hs_max) sd_hcnt <= 10'd0;
+
+   // replicate horizontal sync at twice the speed
+   if(sd_hcnt == hs_max)  hs_sd <= 1'b0;
+   if(sd_hcnt == hs_rise) hs_sd <= 1'b1;
+
+   // read data from line sd_buffer
+   sd_out <= sd_buffer[{~line_toggle, sd_hcnt}];
+end
+   
+endmodule
diff --git a/tutorials/soc/lesson12/soc.qpf b/tutorials/soc/lesson12/soc.qpf
new file mode 100644
index 0000000..a057227
--- /dev/null
+++ b/tutorials/soc/lesson12/soc.qpf
@@ -0,0 +1,30 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2010 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 10.1 Build 153 11/29/2010 SJ Full Version
+# Date created = 11:11:11  June 13, 2011
+#
+# -------------------------------------------------------------------------- #
+
+QUARTUS_VERSION = "10.1"
+DATE = "11:11:11  June 13, 2011"
+
+# Revisions
+
+PROJECT_REVISION = "soc"
diff --git a/tutorials/soc/lesson12/soc.qsf b/tutorials/soc/lesson12/soc.qsf
new file mode 100644
index 0000000..979792e
--- /dev/null
+++ b/tutorials/soc/lesson12/soc.qsf
@@ -0,0 +1,165 @@
+# -------------------------------------------------------------------------- #
+#
+# Copyright (C) 1991-2011 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+#
+# -------------------------------------------------------------------------- #
+#
+# Quartus II
+# Version 11.0 Build 157 04/27/2011 SJ Full Version
+# Date created = 17:14:01  April 10, 2012
+#
+# -------------------------------------------------------------------------- #
+#
+# Notes:
+#
+# 1) The default values for assignments are stored in the file:
+#		led_assignment_defaults.qdf
+#    If this file doesn't exist, see file:
+#		assignment_defaults.qdf
+#
+# 2) Altera recommends that you do not modify this file. This
+#    file is updated automatically by the Quartus II software
+#    and any changes you make may be lost or overwritten.
+#
+# -------------------------------------------------------------------------- #
+
+
+set_global_assignment -name FAMILY "Cyclone III"
+set_global_assignment -name DEVICE EP3C25E144C8
+set_global_assignment -name TOP_LEVEL_ENTITY soc
+set_global_assignment -name ORIGINAL_QUARTUS_VERSION 11.0
+set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:14:01  APRIL 10, 2012"
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
+set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
+set_global_assignment -name DEVICE_FILTER_PACKAGE "ANY QFP"
+set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 8
+set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1
+set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
+set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
+set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF
+set_global_assignment -name RESERVE_ALL_UNUSED_PINS_WEAK_PULLUP "AS INPUT TRI-STATED"
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise
+set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall
+set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
+set_global_assignment -name GENERATE_RBF_FILE ON
+set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
+set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
+
+set_location_assignment PIN_7 -to LED
+set_location_assignment PIN_22 -to CLOCK_50[0]
+set_location_assignment PIN_23 -to CLOCK_50[1]
+set_location_assignment PIN_128 -to CLOCK_32[0]
+set_location_assignment PIN_129 -to CLOCK_32[1]
+set_location_assignment PIN_54 -to CLOCK_27[0]
+set_location_assignment PIN_55 -to CLOCK_27[1]
+set_location_assignment PIN_144 -to VGA_R[5]
+set_location_assignment PIN_143 -to VGA_R[4]
+set_location_assignment PIN_142 -to VGA_R[3]
+set_location_assignment PIN_141 -to VGA_R[2]
+set_location_assignment PIN_137 -to VGA_R[1]
+set_location_assignment PIN_135 -to VGA_R[0]
+set_location_assignment PIN_133 -to VGA_B[5]
+set_location_assignment PIN_132 -to VGA_B[4]
+set_location_assignment PIN_125 -to VGA_B[3]
+set_location_assignment PIN_121 -to VGA_B[2]
+set_location_assignment PIN_120 -to VGA_B[1]
+set_location_assignment PIN_115 -to VGA_B[0]
+set_location_assignment PIN_114 -to VGA_G[5]
+set_location_assignment PIN_113 -to VGA_G[4]
+set_location_assignment PIN_112 -to VGA_G[3]
+set_location_assignment PIN_111 -to VGA_G[2]
+set_location_assignment PIN_110 -to VGA_G[1]
+set_location_assignment PIN_106 -to VGA_G[0]
+set_location_assignment PIN_136 -to VGA_VS
+set_location_assignment PIN_119 -to VGA_HS
+set_location_assignment PIN_65 -to AUDIO_L
+set_location_assignment PIN_80 -to AUDIO_R
+set_location_assignment PIN_46 -to UART_TX
+set_location_assignment PIN_31 -to UART_RX
+set_location_assignment PIN_105 -to SPI_DO
+set_location_assignment PIN_88 -to SPI_DI
+set_location_assignment PIN_126 -to SPI_SCK
+set_location_assignment PIN_127 -to SPI_SS2
+set_location_assignment PIN_91 -to SPI_SS3
+set_location_assignment PIN_90 -to SPI_SS4
+set_location_assignment PIN_13 -to CONF_DATA0
+
+set_location_assignment PIN_49 -to SDRAM_A[0]
+set_location_assignment PIN_44 -to SDRAM_A[1]
+set_location_assignment PIN_42 -to SDRAM_A[2]
+set_location_assignment PIN_39 -to SDRAM_A[3]
+set_location_assignment PIN_4 -to SDRAM_A[4]
+set_location_assignment PIN_6 -to SDRAM_A[5]
+set_location_assignment PIN_8 -to SDRAM_A[6]
+set_location_assignment PIN_10 -to SDRAM_A[7]
+set_location_assignment PIN_11 -to SDRAM_A[8]
+set_location_assignment PIN_28 -to SDRAM_A[9]
+set_location_assignment PIN_50 -to SDRAM_A[10]
+set_location_assignment PIN_30 -to SDRAM_A[11]
+set_location_assignment PIN_32 -to SDRAM_A[12]
+set_location_assignment PIN_83 -to SDRAM_DQ[0]
+set_location_assignment PIN_79 -to SDRAM_DQ[1]
+set_location_assignment PIN_77 -to SDRAM_DQ[2]
+set_location_assignment PIN_76 -to SDRAM_DQ[3]
+set_location_assignment PIN_72 -to SDRAM_DQ[4]
+set_location_assignment PIN_71 -to SDRAM_DQ[5]
+set_location_assignment PIN_69 -to SDRAM_DQ[6]
+set_location_assignment PIN_68 -to SDRAM_DQ[7]
+set_location_assignment PIN_86 -to SDRAM_DQ[8]
+set_location_assignment PIN_87 -to SDRAM_DQ[9]
+set_location_assignment PIN_98 -to SDRAM_DQ[10]
+set_location_assignment PIN_99 -to SDRAM_DQ[11]
+set_location_assignment PIN_100 -to SDRAM_DQ[12]
+set_location_assignment PIN_101 -to SDRAM_DQ[13]
+set_location_assignment PIN_103 -to SDRAM_DQ[14]
+set_location_assignment PIN_104 -to SDRAM_DQ[15]
+set_location_assignment PIN_58 -to SDRAM_BA[0]
+set_location_assignment PIN_51 -to SDRAM_BA[1]
+set_location_assignment PIN_85 -to SDRAM_DQMH
+set_location_assignment PIN_67 -to SDRAM_DQML
+set_location_assignment PIN_60 -to SDRAM_nRAS
+set_location_assignment PIN_64 -to SDRAM_nCAS
+set_location_assignment PIN_66 -to SDRAM_nWE
+set_location_assignment PIN_59 -to SDRAM_nCS
+set_location_assignment PIN_33 -to SDRAM_CKE
+set_location_assignment PIN_43 -to SDRAM_CLK
+
+
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
+set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
+set_global_assignment -name FITTER_EFFORT "FAST FIT"
+set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "23 MM HEAT SINK WITH 200 LFPM AIRFLOW"
+set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
+set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_*
+set_global_assignment -name SYSTEMVERILOG_FILE rgb2ypbpr.sv
+set_global_assignment -name VERILOG_FILE video.v
+set_global_assignment -name VERILOG_FILE scandoubler.v
+set_global_assignment -name VERILOG_FILE user_io.v
+set_global_assignment -name VERILOG_FILE osd.v
+set_global_assignment -name VERILOG_FILE soc.v
+set_global_assignment -name QIP_FILE image.qip
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/tutorials/soc/lesson12/soc.rbf b/tutorials/soc/lesson12/soc.rbf
new file mode 100644
index 0000000000000000000000000000000000000000..076f0410f34743dda300f6c9f13d814d3140cbf3
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diff --git a/tutorials/soc/lesson12/soc.v b/tutorials/soc/lesson12/soc.v
new file mode 100644
index 0000000..4e29e78
--- /dev/null
+++ b/tutorials/soc/lesson12/soc.v
@@ -0,0 +1,194 @@
+// A simple system-on-a-chip (SoC) for the MiST
+// (c) 2015 Till Harbaum
+									  
+module soc (
+   input [1:0] CLOCK_27,
+   output 		SDRAM_nCS,
+	
+   // SPI interface to arm io controller
+   output      SPI_DO,
+   input       SPI_DI,
+   input       SPI_SCK,
+   input       SPI_SS2,
+   input       SPI_SS3,
+   input       SPI_SS4,
+   input       CONF_DATA0, 
+
+	output 		VGA_HS,
+   output 	 	VGA_VS,
+   output [5:0] VGA_R,
+   output [5:0] VGA_G,
+   output [5:0] VGA_B
+);
+
+// de-activate unused SDRAM
+assign SDRAM_nCS = 1;
+
+// the configuration string is returned to the io controller to allow
+// it to control the menu on the OSD 
+parameter CONF_STR = {
+        "VID_TEST;;",
+        "O1,Scanlines,On,Off;",
+        "O2,Video Mode,NTSC,PAL"
+};
+
+wire scanlines_ena = !status[1];
+wire pal_ena       =  status[2];
+
+parameter CONF_STR_LEN = 10+20+22;
+
+// the status register is controlled by the on screen display (OSD)
+wire scandoubler_disable;
+wire ypbpr;
+wire [7:0] status;
+
+// include user_io module for arm controller communication
+user_io #(.STRLEN(CONF_STR_LEN)) user_io ( 
+      .conf_str   ( CONF_STR   ),
+      .SPI_CLK    ( SPI_SCK    ),
+      .SPI_SS_IO  ( CONF_DATA0 ),
+      .SPI_MISO   ( SPI_DO     ),
+      .SPI_MOSI   ( SPI_DI     ),
+      .scandoubler_disable    ( scandoubler_disable ),
+      .ypbpr      ( ypbpr      ),
+      .status     ( status     )
+);
+
+wire [5:0] video_r, video_g, video_b;
+wire video_hs, video_vs;
+
+// include VGA controller
+video video (
+	.pclk  	 ( pixel_clock			),
+	 
+	.cpu_clk  ( pixel_clock      	),
+	.cpu_wr   ( copy_in_progress 	),
+	.cpu_addr ( addr - 14'd1     	),
+	.cpu_data ( data             	),
+	.pal      ( pal_ena           ),
+	
+	.hs       ( video_hs 			),
+	.vs       ( video_vs 			),
+	.r        ( video_r  			),
+	.g        ( video_g  			),
+	.b        ( video_b  			)
+);
+
+wire [5:0] sd_r, sd_g, sd_b;
+wire sd_hs, sd_vs;
+
+scandoubler scandoubler (
+	.clk_in        ( pixel_clock   ),
+	.clk_out       ( vga_clock     ),
+   .scanlines     ( scanlines_ena ),
+  
+	// 
+	.hs_in          ( video_hs     ),
+	.vs_in          ( video_vs     ),
+	.r_in           ( video_r      ),
+	.g_in           ( video_g      ),
+	.b_in           ( video_b      ),
+
+	.hs_out         ( sd_hs        ),
+	.vs_out         ( sd_vs        ),
+	.r_out          ( sd_r         ),
+	.g_out          ( sd_g         ),
+	.b_out          ( sd_b         )
+);
+
+// In TV (15khz) mode the composite sync signal required by TVs is output on
+// the VGA_HS output. The VGA_VS is driven to high and can be used e.g. to switch
+// a scart tv into RGBS mode. See https://github.com/mist-devel/mist-board/wiki/ScartCable
+assign VGA_HS = (scandoubler_disable || ypbpr)?!(video_hs^video_vs):sd_hs;
+assign VGA_VS = (scandoubler_disable || ypbpr)?1'b1:sd_vs;
+assign VGA_R  = ypbpr?pr:out_r;
+assign VGA_G  = ypbpr? y:out_g;
+assign VGA_B  = ypbpr?pb:out_b;
+
+wire [5:0] y, pb, pr;
+
+// include the rgb to ypbpr colorspace converter
+rgb2ypbpr rgb2ypbpr (
+	.red   ( out_r ),
+	.green ( out_g ),
+	.blue  ( out_b ),
+
+	.y     ( y     ),
+	.pb    ( pb    ),
+	.pr    ( pr    )
+);
+
+wire [5:0] out_r, out_g, out_b;
+
+// Make sure OSD scales horizontally to double size on TV as it also scales
+// vertically since the scandoubler is disabled and thus only half the number of lines
+// is being displayed making every line twice as high
+wire osd_clk = scandoubler_disable?pixel_clock:vga_clock;
+
+// Feed scnadoubled or normal signal into OSD
+wire osd_hs = scandoubler_disable?video_hs:sd_hs;
+wire osd_vs = scandoubler_disable?video_vs:sd_vs;
+wire [5:0] osd_r = scandoubler_disable?video_r:sd_r;
+wire [5:0] osd_g = scandoubler_disable?video_g:sd_g;
+wire [5:0] osd_b = scandoubler_disable?video_b:sd_b;
+
+// include the on screen display
+osd #(10,0,4) osd (
+   .pclk       ( osd_clk      ),
+
+   // spi for OSD
+   .sdi        ( SPI_DI       ),
+   .sck        ( SPI_SCK      ),
+   .ss         ( SPI_SS3      ),
+
+   .red_in     ( osd_r        ),
+   .green_in   ( osd_g        ),
+   .blue_in    ( osd_b        ),
+   .hs_in      ( osd_hs       ),
+   .vs_in      ( osd_vs       ),
+
+   .red_out    ( out_r        ),
+   .green_out  ( out_g        ),
+   .blue_out   ( out_b        )
+);
+
+// include ROM containing the demo image
+image image (
+	.clock   ( pixel_clock ),
+	.address ( addr ),
+	.q       ( data )
+);
+
+reg reset = 1'b1;
+reg [13:0] addr;
+wire [7:0] data;
+reg copy_in_progress;
+
+// A small state machine which copies image data from ROM into VRAM
+// of the video controller. The state machines runs directly after power
+// on and works on the falling clock edge since ROM and VRAM operate
+// in the rising edge. The VRAM address is dereased by 1 since the ROM
+// delivers it's data with one clock delay due to its internal registers.
+always @(negedge pixel_clock) begin
+	if(reset) begin
+		reset <= 1'b0;
+		addr <= 14'd0;
+		copy_in_progress <= 1'b1;
+	end else begin
+		if(copy_in_progress) begin
+			addr <= addr + 14'd1;
+			if(addr == 15999)
+				copy_in_progress <= 1'b0;
+		end
+	end
+end
+	
+reg pixel_clock;
+always @(posedge vga_clock)
+	pixel_clock <= !pixel_clock;
+	
+// The pixel clock we use for our TV video modes is 13.5 Mhz. Thus the VGA pixel
+// clock is exactly the 27 Mhz MIST board clock. No pll needed ...
+wire vga_clock = CLOCK_27[0];
+
+endmodule
diff --git a/tutorials/soc/lesson12/user_io.v b/tutorials/soc/lesson12/user_io.v
new file mode 100644
index 0000000..5cecc55
--- /dev/null
+++ b/tutorials/soc/lesson12/user_io.v
@@ -0,0 +1,417 @@
+//
+// user_io.v
+//
+// user_io for the MiST board
+// http://code.google.com/p/mist-board/
+//
+// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
+//
+// This source file is free software: you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published
+// by the Free Software Foundation, either version 3 of the License, or
+// (at your option) any later version.
+//
+// This source file is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program.  If not, see <http://www.gnu.org/licenses/>.
+//
+
+// parameter STRLEN and the actual length of conf_str have to match
+ 
+module user_io #(parameter STRLEN=0) (
+	input [(8*STRLEN)-1:0] conf_str,
+
+	input      		SPI_CLK,
+	input      		SPI_SS_IO,
+	output     		reg SPI_MISO,
+	input      		SPI_MOSI,
+	
+	output reg [7:0] 	joystick_0,
+	output reg [7:0] 	joystick_1,
+	output reg [15:0] joystick_analog_0,
+	output reg [15:0] joystick_analog_1,
+	output [1:0] 		buttons,
+	output [1:0] 		switches,
+   output            scandoubler_disable,
+   output            ypbpr,
+
+	output reg [7:0]   status,
+
+	// connection to sd card emulation
+	input [31:0]  sd_lba,
+	input         sd_rd,
+	input         sd_wr,
+	output reg	  sd_ack,
+	input         sd_conf,
+	input         sd_sdhc,
+	output [7:0]  sd_dout,  // valid on rising edge of sd_dout_strobe
+	output reg	  sd_dout_strobe,
+	input [7:0]   sd_din,
+	output reg 	  sd_din_strobe,
+	
+
+	// ps2 keyboard emulation
+	input 	  		ps2_clk,				// 12-16khz provided by core
+	output	 		ps2_kbd_clk,
+	output reg 		ps2_kbd_data,
+	output	 		ps2_mouse_clk,
+	output reg 		ps2_mouse_data,
+
+	// serial com port 
+	input [7:0]		serial_data,
+	input				serial_strobe
+);
+
+reg [6:0]         sbuf;
+reg [7:0]         cmd;
+reg [2:0] 	      bit_cnt;    // counts bits 0-7 0-7 ...
+reg [7:0]         byte_cnt;   // counts bytes
+reg [5:0]         joystick0;
+reg [5:0]         joystick1;
+reg [5:0] 	      but_sw;
+reg [2:0]         stick_idx;
+
+assign buttons = but_sw[1:0];
+assign switches = but_sw[3:2];
+assign scandoubler_disable = but_sw[4];
+assign ypbpr = but_sw[5];
+
+assign sd_dout = { sbuf, SPI_MOSI};
+
+// this variant of user_io is for 8 bit cores (type == a4) only
+wire [7:0] core_type = 8'ha4;
+
+// command byte read by the io controller
+wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
+
+// filter spi clock. the 8 bit gate delay is ~2.5ns in total
+wire [7:0] spi_sck_D = { spi_sck_D[6:0], SPI_CLK } /* synthesis keep */;
+wire spi_sck = (spi_sck && spi_sck_D != 8'h00) || (!spi_sck && spi_sck_D == 8'hff);
+
+// drive MISO only when transmitting core id
+always@(negedge spi_sck or posedge SPI_SS_IO) begin
+	if(SPI_SS_IO == 1) begin
+	   SPI_MISO <= 1'bZ;
+	end else begin
+
+		// first byte returned is always core type, further bytes are 
+		// command dependent
+      if(byte_cnt == 0) begin
+		  SPI_MISO <= core_type[~bit_cnt];
+
+		end else begin
+			// reading serial fifo
+		   if(cmd == 8'h1b) begin
+				// send alternating flag byte and data
+				if(byte_cnt[0]) 	SPI_MISO <= serial_out_status[~bit_cnt];
+				else					SPI_MISO <= serial_out_byte[~bit_cnt];
+			end
+			
+			// reading config string
+		   else if(cmd == 8'h14) begin
+				// returning a byte from string
+				if(byte_cnt < STRLEN + 1)
+					SPI_MISO <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
+				else
+					SPI_MISO <= 1'b0;
+			end
+			
+			// reading sd card status
+		   else if(cmd == 8'h16) begin
+				if(byte_cnt == 1)
+					SPI_MISO <= sd_cmd[~bit_cnt];
+				else if((byte_cnt >= 2) && (byte_cnt < 6))
+					SPI_MISO <= sd_lba[{5-byte_cnt, ~bit_cnt}];
+				else
+					SPI_MISO <= 1'b0;
+			end
+			
+			// reading sd card write data
+		   else if(cmd == 8'h18)
+				SPI_MISO <= sd_din[~bit_cnt];
+				
+			else
+				SPI_MISO <= 1'b0;
+		end
+   end
+end
+
+// ---------------- PS2 ---------------------
+
+// 8 byte fifos to store ps2 bytes
+localparam PS2_FIFO_BITS = 3;
+
+// keyboard
+reg [7:0] ps2_kbd_fifo [(2**PS2_FIFO_BITS)-1:0];
+reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
+reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
+
+// ps2 transmitter state machine
+reg [3:0] ps2_kbd_tx_state;
+reg [7:0] ps2_kbd_tx_byte;
+reg ps2_kbd_parity;
+
+assign ps2_kbd_clk = ps2_clk || (ps2_kbd_tx_state == 0);
+
+// ps2 transmitter
+// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
+reg ps2_kbd_r_inc;
+always@(posedge ps2_clk) begin
+	ps2_kbd_r_inc <= 1'b0;
+	
+	if(ps2_kbd_r_inc)
+		ps2_kbd_rptr <= ps2_kbd_rptr + 1;
+
+	// transmitter is idle?
+	if(ps2_kbd_tx_state == 0) begin
+		// data in fifo present?
+		if(ps2_kbd_wptr != ps2_kbd_rptr) begin
+			// load tx register from fifo
+			ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
+			ps2_kbd_r_inc <= 1'b1;
+			
+			// reset parity
+			ps2_kbd_parity <= 1'b1;
+			
+			// start transmitter
+			ps2_kbd_tx_state <= 4'd1;
+
+			// put start bit on data line
+			ps2_kbd_data <= 1'b0;			// start bit is 0
+		end
+	end else begin
+	
+		// transmission of 8 data bits
+		if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
+			ps2_kbd_data <= ps2_kbd_tx_byte[0];			  // data bits
+			ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
+			if(ps2_kbd_tx_byte[0]) 
+				ps2_kbd_parity <= !ps2_kbd_parity;
+		end
+
+		// transmission of parity
+		if(ps2_kbd_tx_state == 9)
+			ps2_kbd_data <= ps2_kbd_parity;
+			
+		// transmission of stop bit
+		if(ps2_kbd_tx_state == 10)
+			ps2_kbd_data <= 1'b1;			// stop bit is 1
+
+		// advance state machine
+		if(ps2_kbd_tx_state < 11)
+			ps2_kbd_tx_state <= ps2_kbd_tx_state + 4'd1;
+		else	
+			ps2_kbd_tx_state <= 4'd0;
+	
+	end
+end
+  
+// mouse
+reg [7:0] ps2_mouse_fifo [(2**PS2_FIFO_BITS)-1:0];
+reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
+reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
+
+// ps2 transmitter state machine
+reg [3:0] ps2_mouse_tx_state;
+reg [7:0] ps2_mouse_tx_byte;
+reg ps2_mouse_parity;
+
+assign ps2_mouse_clk = ps2_clk || (ps2_mouse_tx_state == 0);
+
+// ps2 transmitter
+// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
+reg ps2_mouse_r_inc;
+always@(posedge ps2_clk) begin
+	ps2_mouse_r_inc <= 1'b0;
+	
+	if(ps2_mouse_r_inc)
+		ps2_mouse_rptr <= ps2_mouse_rptr + 1;
+
+	// transmitter is idle?
+	if(ps2_mouse_tx_state == 0) begin
+		// data in fifo present?
+		if(ps2_mouse_wptr != ps2_mouse_rptr) begin
+			// load tx register from fifo
+			ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
+			ps2_mouse_r_inc <= 1'b1;
+			
+			// reset parity
+			ps2_mouse_parity <= 1'b1;
+			
+			// start transmitter
+			ps2_mouse_tx_state <= 4'd1;
+
+			// put start bit on data line
+			ps2_mouse_data <= 1'b0;			// start bit is 0
+		end
+	end else begin
+	
+		// transmission of 8 data bits
+		if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
+			ps2_mouse_data <= ps2_mouse_tx_byte[0];			  // data bits
+			ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
+			if(ps2_mouse_tx_byte[0]) 
+				ps2_mouse_parity <= !ps2_mouse_parity;
+		end
+
+		// transmission of parity
+		if(ps2_mouse_tx_state == 9)
+			ps2_mouse_data <= ps2_mouse_parity;
+			
+		// transmission of stop bit
+		if(ps2_mouse_tx_state == 10)
+			ps2_mouse_data <= 1'b1;			// stop bit is 1
+
+		// advance state machine
+		if(ps2_mouse_tx_state < 11)
+			ps2_mouse_tx_state <= ps2_mouse_tx_state + 4'd1;
+		else	
+			ps2_mouse_tx_state <= 4'd0;
+	
+	end
+end
+
+// fifo to receive serial data from core to be forwarded to io controller
+
+// 16 byte fifo to store serial bytes
+localparam SERIAL_OUT_FIFO_BITS = 6;
+reg [7:0] serial_out_fifo [(2**SERIAL_OUT_FIFO_BITS)-1:0];
+reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_wptr;
+reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_rptr;
+ 
+wire serial_out_data_available = serial_out_wptr != serial_out_rptr;
+wire [7:0] serial_out_byte = serial_out_fifo[serial_out_rptr] /* synthesis keep */;
+wire [7:0] serial_out_status = { 7'b1000000, serial_out_data_available};
+
+// status[0] is reset signal from io controller and is thus used to flush
+// the fifo
+always @(posedge serial_strobe or posedge status[0]) begin
+	if(status[0] == 1) begin
+		serial_out_wptr <= 0;
+	end else begin 
+		serial_out_fifo[serial_out_wptr] <= serial_data;
+		serial_out_wptr <= serial_out_wptr + 1;
+	end
+end 
+
+always@(negedge spi_sck or posedge status[0]) begin
+	if(status[0] == 1) begin
+		serial_out_rptr <= 0;
+	end else begin
+		if((byte_cnt != 0) && (cmd == 8'h1b)) begin
+			// read last bit -> advance read pointer
+			if((bit_cnt == 7) && !byte_cnt[0] && serial_out_data_available)
+				serial_out_rptr <= serial_out_rptr + 1;
+		end
+	end
+end
+
+// SPI receiver
+always@(posedge spi_sck or posedge SPI_SS_IO) begin
+
+	if(SPI_SS_IO == 1) begin
+	   bit_cnt <= 3'd0;
+	   byte_cnt <= 8'd0;
+		sd_ack <= 1'b0;
+		sd_dout_strobe <= 1'b0;
+		sd_din_strobe <= 1'b0;
+	end else begin
+		sd_dout_strobe <= 1'b0;
+		sd_din_strobe <= 1'b0;
+		
+		if(bit_cnt != 7)
+			sbuf[6:0] <= { sbuf[5:0], SPI_MOSI };
+			
+		bit_cnt <= bit_cnt + 3'd1;
+		if((bit_cnt == 7)&&(byte_cnt != 8'd255)) 
+			byte_cnt <= byte_cnt + 8'd1;
+
+		// finished reading command byte
+      if(bit_cnt == 7) begin
+			if(byte_cnt == 0) begin
+				cmd <= { sbuf, SPI_MOSI};
+			
+				// fetch first byte when sectore FPGA->IO command has been seen
+				if({ sbuf, SPI_MOSI} == 8'h18)
+					sd_din_strobe <= 1'b1;
+					
+				if(({ sbuf, SPI_MOSI} == 8'h17) || ({ sbuf, SPI_MOSI} == 8'h18))
+					sd_ack <= 1'b1;
+					
+			end else begin
+			
+				// buttons and switches
+				if(cmd == 8'h01)
+					but_sw <= { sbuf[4:0], SPI_MOSI }; 
+
+				if(cmd == 8'h02)
+					joystick_0 <= { sbuf, SPI_MOSI };
+				 
+				if(cmd == 8'h03)
+					joystick_1 <= { sbuf, SPI_MOSI };
+				 
+				if(cmd == 8'h04) begin
+					// store incoming ps2 mouse bytes 
+					ps2_mouse_fifo[ps2_mouse_wptr] <= { sbuf, SPI_MOSI }; 
+					ps2_mouse_wptr <= ps2_mouse_wptr + 1;
+				end
+
+				if(cmd == 8'h05) begin
+					// store incoming ps2 keyboard bytes 
+					ps2_kbd_fifo[ps2_kbd_wptr] <= { sbuf, SPI_MOSI }; 
+					ps2_kbd_wptr <= ps2_kbd_wptr + 1;
+				end
+				
+				if(cmd == 8'h15)
+					status <= { sbuf[6:0], SPI_MOSI };
+				
+				// send sector IO -> FPGA
+				if(cmd == 8'h17) begin
+					// flag that download begins
+//					sd_dout <= { sbuf, SPI_MOSI};
+					sd_dout_strobe <= 1'b1;
+				end
+				
+				// send sector FPGA -> IO
+				if(cmd == 8'h18)
+					sd_din_strobe <= 1'b1;
+				
+				// send SD config IO -> FPGA
+				if(cmd == 8'h19) begin
+					// flag that download begins
+//					sd_dout <= { sbuf, SPI_MOSI};
+					// sd card knows data is config if sd_dout_strobe is asserted
+					// with sd_ack still being inactive (low)
+					sd_dout_strobe <= 1'b1;
+				end
+				
+				// joystick analog
+				if(cmd == 8'h1a) begin
+					// first byte is joystick indes
+					if(byte_cnt == 1)
+						stick_idx <= { sbuf[1:0], SPI_MOSI };
+					else if(byte_cnt == 2) begin
+						// second byte is x axis
+						if(stick_idx == 0)
+							joystick_analog_0[15:8] <= { sbuf, SPI_MOSI };
+						else if(stick_idx == 1)
+							joystick_analog_1[15:8] <= { sbuf, SPI_MOSI };
+					end else if(byte_cnt == 3) begin
+						// third byte is y axis
+						if(stick_idx == 0)
+							joystick_analog_0[7:0] <= { sbuf, SPI_MOSI };
+						else if(stick_idx == 1)
+							joystick_analog_1[7:0] <= { sbuf, SPI_MOSI };
+					end
+				end
+
+			end
+		end
+	end
+end
+   
+endmodule
diff --git a/tutorials/soc/lesson12/video.v b/tutorials/soc/lesson12/video.v
new file mode 100644
index 0000000..c18a0a5
--- /dev/null
+++ b/tutorials/soc/lesson12/video.v
@@ -0,0 +1,124 @@
+// A simple system-on-a-chip (SoC) for the MiST
+// (c) 2016 Till Harbaum
+
+// video controller generating 160x100 pixles. The video mode is based
+// upon a non-interlaced PAL or NTSC TV mode.
+
+
+module video (
+   // pixel clock
+   input  pclk,
+	
+	// config input
+	input  pal,
+	
+	// CPU interface (write only!)	
+	input  cpu_clk,
+	input  cpu_wr,
+	input [13:0] cpu_addr,
+	input [7:0] cpu_data,
+
+	// output to VGA screen
+   output reg	hs,
+   output reg 	vs,
+   output [5:0] r,
+   output [5:0] g,
+   output [5:0] b
+);
+
+// PAL timing: 
+// 864 pixel total horizontal @ 13.5 Mhz = 15.625 kHz
+// 312 lines vertically @ 15.625 kHz = 50.08 Hz
+
+// NTSC timing: 
+// 858 pixel total horizontal @ 13.5 Mhz = 15.735 kHz
+// 262 lines vertically @ 15.735 kHz = 60.05 Hz
+
+parameter H   = 640;         // width of visible area
+wire [9:0] hfp = pal?51:56;  // unused time before hsync
+wire [9:0] hsw = pal?63:63;  // width of hsync
+wire [9:0] hbp = pal?110:99; // unused time after hsync
+
+parameter V   = 200;         // height of visible area
+wire [9:0] vfp = pal?46:23;  // unused time before vsync
+wire [9:0] vsw = pal?2:3;    // width of vsync
+wire [9:0] vbp = pal?64:36;  // unused time after vsync
+
+reg[9:0]  h_cnt;        // horizontal pixel counter
+reg[9:0]  v_cnt;        // vertical pixel counter
+
+// horizontal pixel counter
+always@(posedge pclk) begin
+	if(h_cnt==H+hfp+hsw+hbp-1)  h_cnt <= 10'd0;
+	else                        h_cnt <= h_cnt + 10'd1;
+
+        // generate negative hsync signal
+	if(h_cnt == H+hfp)     hs <= 1'b0;
+	if(h_cnt == H+hfp+hsw) hs <= 1'b1;
+end
+
+// veritical pixel counter
+always@(posedge pclk) begin
+        // the vertical counter is processed at the begin of each hsync
+	if(h_cnt == H+hfp) begin
+		if(v_cnt==vsw+vbp+V+vfp-1) v_cnt <= 10'd0; 
+		else								v_cnt <= v_cnt + 10'd1;
+
+               // generate negative vsync signal
+ 		if(v_cnt == V+vfp)     vs <= 1'b0;
+		if(v_cnt == V+vfp+vsw) vs <= 1'b1;
+	end
+end
+
+// 16000 bytes of internal video memory for 160x100 pixel at 8 Bit (RGB 332)
+reg [7:0] vmem [160*100-1:0];
+
+reg [13:0] video_counter;
+reg [7:0] pixel;
+
+// write VRAM via CPU interface
+always @(posedge cpu_clk)
+	if(cpu_wr) 
+		vmem[cpu_addr] <= cpu_data;
+
+// read VRAM for video generation
+always@(posedge pclk) begin
+       // The video counter is being reset at the begin of each vsync.
+        // Otherwise it's increased every fourth pixel in the visible area.
+        // At the end of the first three of four lines the counter is
+        // decreased by the total line length to display the same contents
+        // for four lines so 100 different lines are displayed on the 400
+        // VGA lines.
+
+        // visible area?
+	if((v_cnt < V) && (h_cnt < H)) begin
+		// increase video counter after each pixel
+		if(h_cnt[1:0] == 2'd3)
+			video_counter <= video_counter + 14'd1;
+		
+		pixel <= vmem[video_counter];               // read VRAM
+	end else begin
+	        // video counter is manipulated at the end of a line outside
+	        // the visible area
+		if(h_cnt == H+hfp) begin
+				// the video counter is reset at the begin of the vsync
+		      // at the end of every second line it's decremented
+		      // one line to repeat the same pixels over two display
+		      // lines
+			if(v_cnt == V+vfp)
+				video_counter <= 14'd0;
+			else if((v_cnt < V) && (v_cnt[0] != 2'd1))
+				video_counter <= video_counter - 14'd160;
+		end
+			
+		pixel <= 8'h00;   // color outside visible area: black
+	end
+end
+
+// split the 8 rgb bits into the three base colors. Every second line is
+// darker to give some scanlines effect
+assign r = { pixel[7:5],  3'b000 };
+assign g = { pixel[4:2],  3'b000 };
+assign b = { pixel[1:0], 4'b0000 };
+
+endmodule
diff --git a/tutorials/soc/readme.md b/tutorials/soc/readme.md
index 97a84e7..cbe8ecd 100644
--- a/tutorials/soc/readme.md
+++ b/tutorials/soc/readme.md
@@ -721,4 +721,38 @@ Links:
 
 Files required on SD card:
  - [`soc.rbf`](https://github.com/mist-devel/mist-board/raw/master/tutorials/soc/lesson11/soc.rbf) renamed to `core.rbf`
+
+[Lesson 12](https://github.com/mist-devel/mist-board/tree/master/tutorials/soc/lesson12): YPbPr component video
+-------------------------------
+
+SCART is a nice way to send a true "retro" video signal to a TV.
+Unfortunately SCART or any other kind of RGBs input isn't available
+on most modern TVs anymore.
+
+What many TVs still have is a so-called YPbPr component input. This
+type of input uses three connections Y, Pb and Pr. Y carries a
+geyscale signal together with a composite sync signal. Thus only
+connecting the Y signal may already result in a grayscale image
+on many TVs. The other two signal Pb and Pr carry color difference
+signals. Together with the Y signal they allow the TV to reconstruct
+the color. 
+
+For YPbPr a special adaptor is need for the MIST as described in the
+[MIST wiki](https://github.com/mist-devel/mist-board/wiki/YPbPr_Cable).
+
+Many TVs support various common video modes on their component inputs.
+It is thus often possible to use the YPbPr with or without
+scandoubler.  With scandoubler enabled the resulting 720p modes may
+even use scanline effects.
+
+This makes a YPbPr connection a very nice choice when connecting the
+MIST to many modern TVs.
+
+Links:
+ - [MIST YpbPr adapter](https://github.com/mist-devel/mist-board/wiki/YPbPr_Cable)
+ - [Enabling YPbPr in the MIST .ini file](https://github.com/mist-devel/mist-board/wiki/DocIni#ypbpr)
+ - [Buy a cable](http://lotharek.pl/product.php?pid=168)
+
+Files required on SD card:
+ - [`soc.rbf`](https://github.com/mist-devel/mist-board/raw/master/tutorials/soc/lesson12/soc.rbf) renamed to `core.rbf`
   
\ No newline at end of file