mirror of
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ghdl based TG68K simulation and development setup
This commit is contained in:
harbaum
parent
bc547280ab
commit
653b61d9d9
55
tests/tg68k/Makefile
Normal file
55
tests/tg68k/Makefile
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@ -0,0 +1,55 @@
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CODE = testcode
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SRCS = TG68K_ALU.vhd TG68K_Pack.vhd TG68KdotC_Kernel.vhd $(CODE)_defs_pack.vhd $(CODE)_pack.vhd tg68k_tb.vhd
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OBJS = $(SRCS:.vhd=.o)
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ROOT = tg68k_tb
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VCD = $(ROOT).vcd
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GHW = $(ROOT).ghw
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TOOLS=../../../tools
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PATCH = tg68k_pack_unpk.patch
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ZIP = tg68k_pack_unpk.zip
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all: $(GHW)
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TG68KdotC_Kernel.o: TG68K_Pack.o
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TG68K_ALU.o: TG68K_Pack.o
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tg68k_tb.o: $(CODE)_pack.o
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$(CODE)_pack.o: $(CODE)_defs_pack.o
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%.o: %.vhd # work-obj93.cf
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ghdl -a $<
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work-obj93.cf: $(SRCS)
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ghdl -i $(SRCS)
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$(ROOT): $(OBJS)
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ghdl -e $@
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clean::
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rm -f work-obj93.cf *.o $(CODE).bin $(CODE)_pack.vhd *~ *.lst *.ghw $(ROOT)
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$(VCD): $(ROOT) Makefile
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ghdl -r $< --ieee-asserts=disable --stop-time=10000ns --vcd=$@
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$(GHW): $(ROOT) Makefile
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ghdl -r $< --ieee-asserts=disable --stop-time=10000ns --wave=$@
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#view: $(VCD)
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# gtkwave $< $(ROOT).sav
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view: $(GHW)
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gtkwave $< $(ROOT).sav
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%.bin: %.s
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$(TOOLS)/vasm/vasmm68k_mot -m68020 -Fbin -o $@ -L $(CODE).lst -nosym $<
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hexdump -C $@
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%_pack.vhd: %.bin
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srec_cat $< -binary -o $@ --VHdl 2 testcode
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zip::
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make clean
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make patch
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zip -r $(ZIP) *.vhd $(CODE)* Makefile *.sav orig
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patch::
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for i in orig/*.vhd ; do diff -Nbaur $$i `basename $$i`; done >$(PATCH) | true
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934
tests/tg68k/TG68K_ALU.vhd
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934
tests/tg68k/TG68K_ALU.vhd
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@ -0,0 +1,934 @@
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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-- --
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-- Copyright (c) 2009-2011 Tobias Gubener --
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-- Subdesign fAMpIGA by TobiFlex --
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-- --
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-- This source file is free software: you can redistribute it and/or modify --
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-- it under the terms of the GNU General Public License as published --
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-- by the Free Software Foundation, either version 3 of the License, or --
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-- (at your option) any later version. --
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-- --
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-- This source file is distributed in the hope that it will be useful, --
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
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-- GNU General Public License for more details. --
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-- --
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-- You should have received a copy of the GNU General Public License --
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-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
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-- --
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------------------------------------------------------------------------------
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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-- use ieee.std_logic_unsigned.all;
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use IEEE.numeric_std.all;
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use work.TG68K_Pack.all;
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entity TG68K_ALU is
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generic(
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MUL_Mode : integer := 0; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
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DIV_Mode : integer := 0 --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
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);
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port(clk : in std_logic;
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Reset : in std_logic;
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clkena_lw : in std_logic:='1';
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execOPC : in bit;
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exe_condition : in std_logic;
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exec_tas : in std_logic;
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long_start : in bit;
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movem_presub : in bit;
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set_stop : in bit;
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Z_error : in bit;
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rot_bits : in std_logic_vector(1 downto 0);
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exec : in bit_vector(lastOpcBit downto 0);
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OP1out : in std_logic_vector(31 downto 0);
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OP2out : in std_logic_vector(31 downto 0);
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reg_QA : in std_logic_vector(31 downto 0);
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reg_QB : in std_logic_vector(31 downto 0);
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opcode : in std_logic_vector(15 downto 0);
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datatype : in std_logic_vector(1 downto 0);
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exe_opcode : in std_logic_vector(15 downto 0);
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exe_datatype : in std_logic_vector(1 downto 0);
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sndOPC : in std_logic_vector(15 downto 0);
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last_data_read : in std_logic_vector(15 downto 0);
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data_read : in std_logic_vector(15 downto 0);
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FlagsSR : in std_logic_vector(7 downto 0);
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micro_state : in micro_states;
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bf_ext_in : in std_logic_vector(7 downto 0);
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bf_ext_out : out std_logic_vector(7 downto 0);
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bf_shift : in std_logic_vector(5 downto 0);
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bf_width : in std_logic_vector(5 downto 0);
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bf_loffset : in std_logic_vector(4 downto 0);
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set_V_Flag : buffer bit;
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Flags : buffer std_logic_vector(7 downto 0);
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c_out : buffer std_logic_vector(2 downto 0);
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addsub_q : buffer std_logic_vector(31 downto 0);
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ALUout : out std_logic_vector(31 downto 0)
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);
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end TG68K_ALU;
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architecture logic of TG68K_ALU is
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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-- ALU and more
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-----------------------------------------------------------------------------
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-----------------------------------------------------------------------------
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signal OP1in : std_logic_vector(31 downto 0);
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signal addsub_a : std_logic_vector(31 downto 0);
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signal addsub_b : std_logic_vector(31 downto 0);
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signal notaddsub_b : std_logic_vector(33 downto 0);
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signal add_result : std_logic_vector(33 downto 0);
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signal addsub_ofl : std_logic_vector(2 downto 0);
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signal opaddsub : bit;
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signal c_in : std_logic_vector(3 downto 0);
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signal flag_z : std_logic_vector(2 downto 0);
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signal set_Flags : std_logic_vector(3 downto 0); --NZVC
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signal CCRin : std_logic_vector(7 downto 0);
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signal niba_l : std_logic_vector(5 downto 0);
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signal niba_h : std_logic_vector(5 downto 0);
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signal niba_lc : std_logic;
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signal niba_hc : std_logic;
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signal bcda_lc : std_logic;
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signal bcda_hc : std_logic;
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signal nibs_l : std_logic_vector(5 downto 0);
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signal nibs_h : std_logic_vector(5 downto 0);
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signal nibs_lc : std_logic;
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signal nibs_hc : std_logic;
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signal bcd_a : std_logic_vector(8 downto 0);
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signal bcd_s : std_logic_vector(8 downto 0);
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signal pack_out : std_logic_vector(15 downto 0);
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signal pack_a : std_logic_vector(15 downto 0);
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signal result_mulu : std_logic_vector(63 downto 0);
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signal result_div : std_logic_vector(63 downto 0);
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signal set_mV_Flag : std_logic;
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signal V_Flag : bit;
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signal rot_rot : std_logic;
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signal rot_lsb : std_logic;
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signal rot_msb : std_logic;
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signal rot_X : std_logic;
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signal rot_C : std_logic;
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signal rot_out : std_logic_vector(31 downto 0);
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signal asl_VFlag : std_logic;
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signal bit_bits : std_logic_vector(1 downto 0);
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signal bit_number : std_logic_vector(4 downto 0);
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signal bits_out : std_logic_vector(31 downto 0);
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signal one_bit_in : std_logic;
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signal bchg : std_logic;
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signal bset : std_logic;
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signal mulu_sign : std_logic;
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signal mulu_signext : std_logic_vector(16 downto 0);
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signal muls_msb : std_logic;
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signal mulu_reg : std_logic_vector(63 downto 0);
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signal FAsign : std_logic;
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signal faktorA : std_logic_vector(31 downto 0);
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signal faktorB : std_logic_vector(31 downto 0);
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signal div_reg : std_logic_vector(63 downto 0);
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signal div_quot : std_logic_vector(63 downto 0);
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signal div_ovl : std_logic;
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signal div_neg : std_logic;
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signal div_bit : std_logic;
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signal div_sub : std_logic_vector(32 downto 0);
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signal div_over : std_logic_vector(32 downto 0);
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signal nozero : std_logic;
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signal div_qsign : std_logic;
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signal divisor : std_logic_vector(63 downto 0);
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signal divs : std_logic;
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signal signedOP : std_logic;
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signal OP1_sign : std_logic;
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signal OP2_sign : std_logic;
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signal OP2outext : std_logic_vector(15 downto 0);
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signal in_offset : std_logic_vector(5 downto 0);
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-- signal in_width : std_logic_vector(5 downto 0);
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signal datareg : std_logic_vector(31 downto 0);
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signal insert : std_logic_vector(31 downto 0);
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-- signal bf_result : std_logic_vector(31 downto 0);
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-- signal bf_offset : std_logic_vector(5 downto 0);
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-- signal bf_width : std_logic_vector(5 downto 0);
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-- signal bf_firstbit : std_logic_vector(5 downto 0);
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signal bf_datareg : std_logic_vector(31 downto 0);
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-- signal bf_out : std_logic_vector(31 downto 0);
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signal result : std_logic_vector(39 downto 0);
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signal result_tmp : std_logic_vector(39 downto 0);
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signal sign : std_logic_vector(31 downto 0);
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signal bf_set1 : std_logic_vector(39 downto 0);
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signal inmux0 : std_logic_vector(39 downto 0);
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signal inmux1 : std_logic_vector(39 downto 0);
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signal inmux2 : std_logic_vector(39 downto 0);
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signal inmux3 : std_logic_vector(31 downto 0);
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signal copymux0 : std_logic_vector(39 downto 0);
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signal copymux1 : std_logic_vector(39 downto 0);
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signal copymux2 : std_logic_vector(39 downto 0);
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signal copymux3 : std_logic_vector(31 downto 0);
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signal bf_set2 : std_logic_vector(31 downto 0);
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-- signal bf_set3 : std_logic_vector(31 downto 0);
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signal shift : std_logic_vector(39 downto 0);
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signal copy : std_logic_vector(39 downto 0);
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-- signal offset : std_logic_vector(5 downto 0);
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-- signal width : std_logic_vector(5 downto 0);
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signal bf_firstbit : std_logic_vector(5 downto 0);
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signal mux : std_logic_vector(3 downto 0);
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signal bitnr : std_logic_vector(4 downto 0);
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signal mask : std_logic_vector(31 downto 0);
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signal bf_bset : std_logic;
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signal bf_NFlag : std_logic;
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signal bf_bchg : std_logic;
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signal bf_ins : std_logic;
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signal bf_exts : std_logic;
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signal bf_fffo : std_logic;
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signal bf_d32 : std_logic;
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signal bf_s32 : std_logic;
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signal index : std_logic_vector(4 downto 0);
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-- signal i : integer range 0 to 31;
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-- signal i : integer range 0 to 31;
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-- signal i : std_logic_vector(5 downto 0);
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BEGIN
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-----------------------------------------------------------------------------
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-- set OP1in
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-----------------------------------------------------------------------------
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PROCESS (OP2out, reg_QB, opcode, OP1out, OP1in, exe_datatype, addsub_q, execOPC, exec,
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pack_out, bcd_a, bcd_s, result_mulu, result_div, exe_condition, bf_shift,
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Flags, FlagsSR, bits_out, exec_tas, rot_out, exe_opcode, result, bf_fffo, bf_firstbit, bf_datareg)
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BEGIN
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ALUout <= OP1in;
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ALUout(7) <= OP1in(7) OR exec_tas;
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IF exec(opcBFwb)='1' THEN
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ALUout <= result(31 downto 0);
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IF bf_fffo='1' THEN
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ALUout <= (OTHERS =>'0');
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ALUout(5 downto 0) <= std_logic_vector(unsigned(bf_firstbit) + unsigned(bf_shift));
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END IF;
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END IF;
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OP1in <= addsub_q;
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IF exec(opcABCD)='1' THEN
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OP1in(7 downto 0) <= bcd_a(7 downto 0);
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ELSIF exec(opcSBCD)='1' THEN
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OP1in(7 downto 0) <= bcd_s(7 downto 0);
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ELSIF exec(opcMULU)='1' AND MUL_Mode/=3 THEN
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IF exec(write_lowlong)='1' AND (MUL_Mode=1 OR MUL_Mode=2) THEN
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OP1in <= result_mulu(31 downto 0);
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ELSE
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OP1in <= result_mulu(63 downto 32);
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END IF;
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ELSIF exec(opcDIVU)='1' AND DIV_Mode/=3 THEN
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IF exe_opcode(15)='1' OR DIV_Mode=0 THEN
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-- IF exe_opcode(15)='1' THEN
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OP1in <= result_div(47 downto 32)&result_div(15 downto 0);
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ELSE --64bit
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IF exec(write_reminder)='1' THEN
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OP1in <= result_div(63 downto 32);
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ELSE
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OP1in <= result_div(31 downto 0);
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END IF;
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END IF;
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ELSIF exec(opcOR)='1' THEN
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OP1in <= OP2out OR OP1out;
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ELSIF exec(opcAND)='1' THEN
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OP1in <= OP2out AND OP1out;
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ELSIF exec(opcScc)='1' THEN
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OP1in(7 downto 0) <= (others=>exe_condition);
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ELSIF exec(opcEOR)='1' THEN
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OP1in <= OP2out XOR OP1out;
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ELSIF exec(opcMOVE)='1' OR exec(exg)='1' THEN
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-- OP1in <= OP2out(31 downto 8)&(OP2out(7)OR exec_tas)&OP2out(6 downto 0);
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OP1in <= OP2out;
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ELSIF exec(opcROT)='1' THEN
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OP1in <= rot_out;
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ELSIF exec(opcSWAP)='1' THEN
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OP1in <= OP1out(15 downto 0)& OP1out(31 downto 16);
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ELSIF exec(opcBITS)='1' THEN
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OP1in <= bits_out;
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ELSIF exec(opcBF)='1' THEN
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OP1in <= bf_datareg;
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ELSIF exec(opcMOVESR)='1' THEN
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OP1in(7 downto 0) <= Flags;
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IF exe_datatype="00" THEN
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OP1in(15 downto 8) <= "00000000";
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ELSE
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OP1in(15 downto 8) <= FlagsSR;
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END IF;
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ELSIF exec(opcPACK)='1' THEN
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OP1in(15 downto 0) <= pack_out;
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END IF;
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END PROCESS;
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-----------------------------------------------------------------------------
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-- addsub
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-----------------------------------------------------------------------------
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PROCESS (OP1out, OP2out, execOPC, datatype, Flags, long_start, movem_presub, exe_datatype, exec, addsub_a, addsub_b, opaddsub,
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notaddsub_b, add_result, c_in, sndOPC)
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BEGIN
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addsub_a <= OP1out;
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IF exec(get_bfoffset)='1' THEN
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IF sndOPC(11)='1' THEN
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addsub_a <= OP1out(31)&OP1out(31)&OP1out(31)&OP1out(31 downto 3);
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ELSE
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addsub_a <= "000000000000000000000000000000"&sndOPC(10 downto 9);
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END IF;
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END IF;
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IF exec(subidx)='1' THEN
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opaddsub <= '1';
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ELSE
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opaddsub <= '0';
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END IF;
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c_in(0) <='0';
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addsub_b <= OP2out;
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IF execOPC='0' AND exec(OP2out_one)='0' AND exec(get_bfoffset)='0'THEN
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IF long_start='0' AND datatype="00" AND exec(use_SP)='0' THEN
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addsub_b <= "00000000000000000000000000000001";
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ELSIF long_start='0' AND exe_datatype="10" AND (exec(presub) OR exec(postadd) OR movem_presub)='1' THEN
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IF exec(movem_action)='1' THEN
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addsub_b <= "00000000000000000000000000000110";
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ELSE
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addsub_b <= "00000000000000000000000000000100";
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END IF;
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ELSE
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addsub_b <= "00000000000000000000000000000010";
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END IF;
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ELSE
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IF (exec(use_XZFlag)='1' AND Flags(4)='1') OR exec(opcCHK)='1' THEN
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c_in(0) <= '1';
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END IF;
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opaddsub <= exec(addsub);
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END IF;
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IF opaddsub='0' OR long_start='1' THEN --ADD
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notaddsub_b <= '0'&addsub_b&c_in(0);
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ELSE --SUB
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notaddsub_b <= NOT ('0'&addsub_b&c_in(0));
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END IF;
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add_result <= std_logic_vector( unsigned('0'&addsub_a¬addsub_b(0)) + unsigned(notaddsub_b));
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c_in(1) <= add_result(9) XOR addsub_a(8) XOR addsub_b(8);
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c_in(2) <= add_result(17) XOR addsub_a(16) XOR addsub_b(16);
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c_in(3) <= add_result(33);
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addsub_q <= add_result(32 downto 1);
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addsub_ofl(0) <= (c_in(1) XOR add_result(8) XOR addsub_a(7) XOR addsub_b(7)); --V Byte
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addsub_ofl(1) <= (c_in(2) XOR add_result(16) XOR addsub_a(15) XOR addsub_b(15)); --V Word
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addsub_ofl(2) <= (c_in(3) XOR add_result(32) XOR addsub_a(31) XOR addsub_b(31)); --V Long
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c_out <= c_in(3 downto 1);
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END PROCESS;
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------------------------------------------------------------------------------
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--ALU
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------------------------------------------------------------------------------
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PROCESS (OP1out, OP2out, pack_a, niba_hc, niba_h, niba_l, niba_lc, nibs_hc, nibs_h, nibs_l, nibs_lc, Flags)
|
||||
BEGIN
|
||||
IF exe_opcode(7 downto 6) = "01" THEN
|
||||
-- PACK
|
||||
pack_a <= std_logic_vector(unsigned(OP1out(15 downto 0))+unsigned(OP2out(15 downto 0)));
|
||||
pack_out <= "00000000" & pack_a(11 downto 8) & pack_a(3 downto 0);
|
||||
ELSE
|
||||
-- UNPK
|
||||
pack_a <= "0000" & OP2out(7 downto 4) & "0000" & OP2out(3 downto 0);
|
||||
pack_out <= std_logic_vector(unsigned(OP1out(15 downto 0))+unsigned(pack_a));
|
||||
END IF;
|
||||
|
||||
--BCD_ARITH-------------------------------------------------------------------
|
||||
--ADC
|
||||
bcd_a <= niba_hc & std_logic_vector(unsigned(niba_h(4 downto 1)) + ('0',niba_hc,niba_hc,'0')) &
|
||||
std_logic_vector(unsigned(niba_l(4 downto 1)) + ('0',niba_lc,niba_lc,'0'));
|
||||
niba_l <= std_logic_vector(unsigned('0'&OP1out(3 downto 0)&'1') + unsigned('0'&OP2out(3 downto 0)&Flags(4)));
|
||||
niba_lc <= niba_l(5) OR (niba_l(4) AND niba_l(3)) OR (niba_l(4) AND niba_l(2));
|
||||
|
||||
niba_h <= std_logic_vector(unsigned('0'&OP1out(7 downto 4)&'1') + unsigned('0'&OP2out(7 downto 4)&niba_lc));
|
||||
niba_hc <= niba_h(5) OR (niba_h(4) AND niba_h(3)) OR (niba_h(4) AND niba_h(2));
|
||||
--SBC
|
||||
bcd_s <= nibs_hc & std_logic_vector(unsigned(nibs_h(4 downto 1)) - ('0',nibs_hc,nibs_hc,'0')) &
|
||||
std_logic_vector(unsigned(nibs_l(4 downto 1)) - ('0',nibs_lc,nibs_lc,'0'));
|
||||
nibs_l <= std_logic_vector(unsigned('0'&OP1out(3 downto 0)&'0') - unsigned('0'&OP2out(3 downto 0)&Flags(4)));
|
||||
nibs_lc <= nibs_l(5);
|
||||
|
||||
nibs_h <= std_logic_vector(unsigned('0'&OP1out(7 downto 4)&'0') - unsigned('0'&OP2out(7 downto 4)&nibs_lc));
|
||||
nibs_hc <= nibs_h(5);
|
||||
END PROCESS;
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Bits
|
||||
-----------------------------------------------------------------------------
|
||||
PROCESS (clk, exe_opcode, OP1out, OP2out, one_bit_in, bchg, bset, bit_Number, sndOPC)
|
||||
BEGIN
|
||||
IF rising_edge(clk) THEN
|
||||
IF clkena_lw = '1' THEN
|
||||
bchg <= '0';
|
||||
bset <= '0';
|
||||
CASE opcode(7 downto 6) IS
|
||||
WHEN "01" => --bchg
|
||||
bchg <= '1';
|
||||
WHEN "11" => --bset
|
||||
bset <= '1';
|
||||
WHEN OTHERS => NULL;
|
||||
END CASE;
|
||||
END IF;
|
||||
END IF;
|
||||
|
||||
IF exe_opcode(8)='0' THEN
|
||||
IF exe_opcode(5 downto 4)="00" THEN
|
||||
bit_number <= sndOPC(4 downto 0);
|
||||
ELSE
|
||||
bit_number <= "00"&sndOPC(2 downto 0);
|
||||
END IF;
|
||||
ELSE
|
||||
IF exe_opcode(5 downto 4)="00" THEN
|
||||
bit_number <= reg_QB(4 downto 0);
|
||||
ELSE
|
||||
bit_number <= "00"®_QB(2 downto 0);
|
||||
END IF;
|
||||
END IF;
|
||||
|
||||
one_bit_in <= OP1out(to_integer(unsigned(bit_Number)));
|
||||
bits_out <= OP1out;
|
||||
bits_out(to_integer(unsigned(bit_Number))) <= (bchg AND NOT one_bit_in) OR bset ;
|
||||
END PROCESS;
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Bit Field
|
||||
-----------------------------------------------------------------------------
|
||||
PROCESS (clk, mux, mask, bitnr, bf_ins, bf_bchg, bf_bset, bf_exts, bf_shift, inmux0, inmux1, inmux2, inmux3, bf_set2, OP1out, OP2out, result_tmp, bf_ext_in,
|
||||
shift, datareg, bf_NFlag, result, reg_QB, sign, bf_d32, bf_s32, copy, bf_loffset, copymux0, copymux1, copymux2, copymux3, bf_width)
|
||||
BEGIN
|
||||
IF rising_edge(clk) THEN
|
||||
IF clkena_lw = '1' THEN
|
||||
bf_bset <= '0';
|
||||
bf_bchg <= '0';
|
||||
bf_ins <= '0';
|
||||
bf_exts <= '0';
|
||||
bf_fffo <= '0';
|
||||
bf_d32 <= '0';
|
||||
bf_s32 <= '0';
|
||||
CASE opcode(10 downto 8) IS
|
||||
WHEN "010" => bf_bchg <= '1'; --BFCHG
|
||||
WHEN "011" => bf_exts <= '1'; --BFEXTS
|
||||
-- WHEN "100" => insert <= (OTHERS =>'0'); --BFCLR
|
||||
WHEN "101" => bf_fffo <= '1'; --BFFFO
|
||||
WHEN "110" => bf_bset <= '1'; --BFSET
|
||||
WHEN "111" => bf_ins <= '1'; --BFINS
|
||||
bf_s32 <= '1';
|
||||
WHEN OTHERS => NULL;
|
||||
END CASE;
|
||||
IF opcode(4 downto 3)="00" THEN
|
||||
bf_d32 <= '1';
|
||||
END IF;
|
||||
bf_ext_out <= result(39 downto 32);
|
||||
END IF;
|
||||
END IF;
|
||||
shift <= bf_ext_in&OP2out;
|
||||
IF bf_s32='1' THEN
|
||||
shift(39 downto 32) <= OP2out(7 downto 0);
|
||||
END IF;
|
||||
|
||||
IF bf_shift(0)='1' THEN
|
||||
inmux0 <= shift(0)&shift(39 downto 1);
|
||||
ELSE
|
||||
inmux0 <= shift;
|
||||
END IF;
|
||||
IF bf_shift(1)='1' THEN
|
||||
inmux1 <= inmux0(1 downto 0)&inmux0(39 downto 2);
|
||||
ELSE
|
||||
inmux1 <= inmux0;
|
||||
END IF;
|
||||
IF bf_shift(2)='1' THEN
|
||||
inmux2 <= inmux1(3 downto 0)&inmux1(39 downto 4);
|
||||
ELSE
|
||||
inmux2 <= inmux1;
|
||||
END IF;
|
||||
IF bf_shift(3)='1' THEN
|
||||
inmux3 <= inmux2(7 downto 0)&inmux2(31 downto 8);
|
||||
ELSE
|
||||
inmux3 <= inmux2(31 downto 0);
|
||||
END IF;
|
||||
IF bf_shift(4)='1' THEN
|
||||
bf_set2(31 downto 0) <= inmux3(15 downto 0)&inmux3(31 downto 16);
|
||||
ELSE
|
||||
bf_set2(31 downto 0) <= inmux3;
|
||||
END IF;
|
||||
|
||||
IF bf_loffset(4)='1' THEN
|
||||
copymux3 <= sign(15 downto 0)&sign(31 downto 16);
|
||||
ELSE
|
||||
copymux3 <= sign;
|
||||
END IF;
|
||||
IF bf_loffset(3)='1' THEN
|
||||
copymux2(31 downto 0) <= copymux3(23 downto 0)©mux3(31 downto 24);
|
||||
ELSE
|
||||
copymux2(31 downto 0) <= copymux3;
|
||||
END IF;
|
||||
IF bf_d32='1' THEN
|
||||
copymux2(39 downto 32) <= copymux3(7 downto 0);
|
||||
ELSE
|
||||
copymux2(39 downto 32) <= "11111111";
|
||||
END IF;
|
||||
IF bf_loffset(2)='1' THEN
|
||||
copymux1 <= copymux2(35 downto 0)©mux2(39 downto 36);
|
||||
ELSE
|
||||
copymux1 <= copymux2;
|
||||
END IF;
|
||||
IF bf_loffset(1)='1' THEN
|
||||
copymux0 <= copymux1(37 downto 0)©mux1(39 downto 38);
|
||||
ELSE
|
||||
copymux0 <= copymux1;
|
||||
END IF;
|
||||
IF bf_loffset(0)='1' THEN
|
||||
copy <= copymux0(38 downto 0)©mux0(39);
|
||||
ELSE
|
||||
copy <= copymux0;
|
||||
END IF;
|
||||
|
||||
result_tmp <= bf_ext_in&OP1out;
|
||||
IF bf_ins='1' THEN
|
||||
datareg <= reg_QB;
|
||||
ELSE
|
||||
datareg <= bf_set2;
|
||||
END IF;
|
||||
IF bf_ins='1' THEN
|
||||
result(31 downto 0) <= bf_set2;
|
||||
result(39 downto 32) <= bf_set2(7 downto 0);
|
||||
ELSIF bf_bchg='1' THEN
|
||||
result(31 downto 0) <= NOT OP1out;
|
||||
result(39 downto 32) <= NOT bf_ext_in;
|
||||
ELSE
|
||||
result <= (OTHERS => '0');
|
||||
END IF;
|
||||
IF bf_bset='1' THEN
|
||||
result <= (OTHERS => '1');
|
||||
END IF;
|
||||
|
||||
sign <= (OTHERS => '0');
|
||||
bf_NFlag <= datareg(to_integer(unsigned(bf_width)));
|
||||
FOR i in 0 to 31 LOOP
|
||||
IF i > unsigned(bf_width(4 downto 0)) THEN
|
||||
datareg(i) <= '0';
|
||||
sign(i) <= '1';
|
||||
END IF;
|
||||
END LOOP;
|
||||
|
||||
FOR i in 0 to 39 LOOP
|
||||
IF copy(i)='1' THEN
|
||||
result(i) <= result_tmp(i);
|
||||
END IF;
|
||||
END LOOP;
|
||||
|
||||
IF bf_exts='1' AND bf_NFlag='1' THEN
|
||||
bf_datareg <= datareg OR sign;
|
||||
ELSE
|
||||
bf_datareg <= datareg;
|
||||
END IF;
|
||||
-- bf_datareg <= copy(31 downto 0);
|
||||
-- result(31 downto 0)<=datareg;
|
||||
--BFFFO
|
||||
mask <= datareg;
|
||||
bf_firstbit <= '0'&bitnr;
|
||||
bitnr <= "11111";
|
||||
IF mask(31 downto 28)="0000" THEN
|
||||
IF mask(27 downto 24)="0000" THEN
|
||||
IF mask(23 downto 20)="0000" THEN
|
||||
IF mask(19 downto 16)="0000" THEN
|
||||
bitnr(4) <= '0';
|
||||
IF mask(15 downto 12)="0000" THEN
|
||||
IF mask(11 downto 8)="0000" THEN
|
||||
bitnr(3) <= '0';
|
||||
IF mask(7 downto 4)="0000" THEN
|
||||
bitnr(2) <= '0';
|
||||
mux <= mask(3 downto 0);
|
||||
ELSE
|
||||
mux <= mask(7 downto 4);
|
||||
END IF;
|
||||
ELSE
|
||||
mux <= mask(11 downto 8);
|
||||
bitnr(2) <= '0';
|
||||
END IF;
|
||||
ELSE
|
||||
mux <= mask(15 downto 12);
|
||||
END IF;
|
||||
ELSE
|
||||
mux <= mask(19 downto 16);
|
||||
bitnr(3) <= '0';
|
||||
bitnr(2) <= '0';
|
||||
END IF;
|
||||
ELSE
|
||||
mux <= mask(23 downto 20);
|
||||
bitnr(3) <= '0';
|
||||
END IF;
|
||||
ELSE
|
||||
mux <= mask(27 downto 24);
|
||||
bitnr(2) <= '0';
|
||||
END IF;
|
||||
ELSE
|
||||
mux <= mask(31 downto 28);
|
||||
END IF;
|
||||
|
||||
IF mux(3 downto 2)="00" THEN
|
||||
bitnr(1) <= '0';
|
||||
IF mux(1)='0' THEN
|
||||
bitnr(0) <= '0';
|
||||
END IF;
|
||||
ELSE
|
||||
IF mux(3)='0' THEN
|
||||
bitnr(0) <= '0';
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Rotation
|
||||
-----------------------------------------------------------------------------
|
||||
PROCESS (exe_opcode, OP1out, Flags, rot_bits, rot_msb, rot_lsb, rot_rot, exec)
|
||||
BEGIN
|
||||
CASE exe_opcode(7 downto 6) IS
|
||||
WHEN "00" => --Byte
|
||||
rot_rot <= OP1out(7);
|
||||
WHEN "01"|"11" => --Word
|
||||
rot_rot <= OP1out(15);
|
||||
WHEN "10" => --Long
|
||||
rot_rot <= OP1out(31);
|
||||
WHEN OTHERS => NULL;
|
||||
END CASE;
|
||||
|
||||
CASE rot_bits IS
|
||||
WHEN "00" => --ASL, ASR
|
||||
rot_lsb <= '0';
|
||||
rot_msb <= rot_rot;
|
||||
WHEN "01" => --LSL, LSR
|
||||
rot_lsb <= '0';
|
||||
rot_msb <= '0';
|
||||
WHEN "10" => --ROXL, ROXR
|
||||
rot_lsb <= Flags(4);
|
||||
rot_msb <= Flags(4);
|
||||
WHEN "11" => --ROL, ROR
|
||||
rot_lsb <= rot_rot;
|
||||
rot_msb <= OP1out(0);
|
||||
WHEN OTHERS => NULL;
|
||||
END CASE;
|
||||
|
||||
IF exec(rot_nop)='1' THEN
|
||||
rot_out <= OP1out;
|
||||
rot_X <= Flags(4);
|
||||
IF rot_bits="10" THEN --ROXL, ROXR
|
||||
rot_C <= Flags(4);
|
||||
ELSE
|
||||
rot_C <= '0';
|
||||
END IF;
|
||||
ELSE
|
||||
IF exe_opcode(8)='1' THEN --left
|
||||
rot_out <= OP1out(30 downto 0)&rot_lsb;
|
||||
rot_X <= rot_rot;
|
||||
rot_C <= rot_rot;
|
||||
ELSE --right
|
||||
rot_X <= OP1out(0);
|
||||
rot_C <= OP1out(0);
|
||||
rot_out <= rot_msb&OP1out(31 downto 1);
|
||||
CASE exe_opcode(7 downto 6) IS
|
||||
WHEN "00" => --Byte
|
||||
rot_out(7) <= rot_msb;
|
||||
WHEN "01"|"11" => --Word
|
||||
rot_out(15) <= rot_msb;
|
||||
WHEN OTHERS => NULL;
|
||||
END CASE;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
--CCR op
|
||||
------------------------------------------------------------------------------
|
||||
PROCESS (clk, Reset, exe_opcode, exe_datatype, Flags, last_data_read, OP2out, flag_z, OP1IN, c_out, addsub_ofl,
|
||||
bcd_s, bcd_a, exec)
|
||||
BEGIN
|
||||
IF exec(andiSR)='1' THEN
|
||||
CCRin <= Flags AND last_data_read(7 downto 0);
|
||||
ELSIF exec(eoriSR)='1' THEN
|
||||
CCRin <= Flags XOR last_data_read(7 downto 0);
|
||||
ELSIF exec(oriSR)='1' THEN
|
||||
CCRin <= Flags OR last_data_read(7 downto 0);
|
||||
ELSE
|
||||
CCRin <= OP2out(7 downto 0);
|
||||
END IF;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
--Flags
|
||||
------------------------------------------------------------------------------
|
||||
flag_z <= "000";
|
||||
IF exec(use_XZFlag)='1' AND flags(2)='0' THEN
|
||||
flag_z <= "000";
|
||||
ELSIF OP1in(7 downto 0)="00000000" THEN
|
||||
flag_z(0) <= '1';
|
||||
IF OP1in(15 downto 8)="00000000" THEN
|
||||
flag_z(1) <= '1';
|
||||
IF OP1in(31 downto 16)="0000000000000000" THEN
|
||||
flag_z(2) <= '1';
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
|
||||
-- --Flags NZVC
|
||||
IF exe_datatype="00" THEN --Byte
|
||||
set_flags <= OP1IN(7)&flag_z(0)&addsub_ofl(0)&c_out(0);
|
||||
IF exec(opcABCD)='1' THEN
|
||||
set_flags(0) <= bcd_a(8);
|
||||
ELSIF exec(opcSBCD)='1' THEN
|
||||
set_flags(0) <= bcd_s(8);
|
||||
END IF;
|
||||
ELSIF exe_datatype="10" OR exec(opcCPMAW)='1' THEN --Long
|
||||
set_flags <= OP1IN(31)&flag_z(2)&addsub_ofl(2)&c_out(2);
|
||||
ELSE --Word
|
||||
set_flags <= OP1IN(15)&flag_z(1)&addsub_ofl(1)&c_out(1);
|
||||
END IF;
|
||||
|
||||
IF rising_edge(clk) THEN
|
||||
IF clkena_lw = '1' THEN
|
||||
IF exec(directSR)='1' OR set_stop='1' THEN
|
||||
Flags(7 downto 0) <= data_read(7 downto 0);
|
||||
END IF;
|
||||
IF exec(directCCR)='1' THEN
|
||||
Flags(7 downto 0) <= data_read(7 downto 0);
|
||||
END IF;
|
||||
|
||||
IF exec(opcROT)='1' THEN
|
||||
asl_VFlag <= ((set_flags(3) XOR rot_rot) OR asl_VFlag);
|
||||
ELSE
|
||||
asl_VFlag <= '0';
|
||||
END IF;
|
||||
IF exec(to_CCR)='1' THEN
|
||||
Flags(7 downto 0) <= CCRin(7 downto 0); --CCR
|
||||
ELSIF Z_error='1' THEN
|
||||
IF exe_opcode(8)='0' THEN
|
||||
Flags(3 downto 0) <= reg_QA(31)&"000";
|
||||
ELSE
|
||||
Flags(3 downto 0) <= "0100";
|
||||
END IF;
|
||||
ELSIF exec(no_Flags)='0' THEN
|
||||
IF exec(opcADD)='1' THEN
|
||||
Flags(4) <= set_flags(0);
|
||||
ELSIF exec(opcROT)='1' AND rot_bits/="11" AND exec(rot_nop)='0' THEN
|
||||
Flags(4) <= rot_X;
|
||||
END IF;
|
||||
|
||||
IF (exec(opcADD) OR exec(opcCMP))='1' THEN
|
||||
Flags(3 downto 0) <= set_flags;
|
||||
ELSIF exec(opcDIVU)='1' AND DIV_Mode/=3 THEN
|
||||
IF V_Flag='1' THEN
|
||||
Flags(3 downto 0) <= "1010";
|
||||
ELSE
|
||||
Flags(3 downto 0) <= OP1IN(15)&flag_z(1)&"00";
|
||||
END IF;
|
||||
ELSIF exec(write_reminder)='1' AND MUL_Mode/=3 THEN -- z-flag MULU.l
|
||||
Flags(3) <= set_flags(3);
|
||||
Flags(2) <= set_flags(2) AND Flags(2);
|
||||
Flags(1) <= '0';
|
||||
Flags(0) <= '0';
|
||||
ELSIF exec(write_lowlong)='1' AND (MUL_Mode=1 OR MUL_Mode=2) THEN -- flag MULU.l
|
||||
Flags(3) <= set_flags(3);
|
||||
Flags(2) <= set_flags(2);
|
||||
Flags(1) <= set_mV_Flag; --V
|
||||
Flags(0) <= '0';
|
||||
ELSIF exec(opcOR)='1' OR exec(opcAND)='1' OR exec(opcEOR)='1' OR exec(opcMOVE)='1' OR exec(opcMOVEQ)='1' OR exec(opcSWAP)='1' OR exec(opcBF)='1' OR (exec(opcMULU)='1' AND MUL_Mode/=3) THEN
|
||||
Flags(1 downto 0) <= "00";
|
||||
Flags(3 downto 2) <= set_flags(3 downto 2);
|
||||
IF exec(opcBF)='1' THEN
|
||||
Flags(3) <= bf_NFlag;
|
||||
END IF;
|
||||
ELSIF exec(opcROT)='1' THEN
|
||||
Flags(3 downto 2) <= set_flags(3 downto 2);
|
||||
Flags(0) <= rot_C;
|
||||
IF rot_bits="00" AND ((set_flags(3) XOR rot_rot) OR asl_VFlag)='1' THEN --ASL/ASR
|
||||
Flags(1) <= '1';
|
||||
ELSE
|
||||
Flags(1) <= '0';
|
||||
END IF;
|
||||
ELSIF exec(opcBITS)='1' THEN
|
||||
Flags(2) <= NOT one_bit_in;
|
||||
ELSIF exec(opcCHK)='1' THEN
|
||||
IF exe_datatype="01" THEN --Word
|
||||
Flags(3) <= OP1out(15);
|
||||
ELSE
|
||||
Flags(3) <= OP1out(31);
|
||||
END IF;
|
||||
IF OP1out(15 downto 0)=X"0000" AND (exe_datatype="01" OR OP1out(31 downto 16)=X"0000") THEN
|
||||
Flags(2) <='1';
|
||||
ELSE
|
||||
Flags(2) <='0';
|
||||
END IF;
|
||||
Flags(1 downto 0) <= "00";
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
Flags(7 downto 5) <= "000";
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
---- MULU/MULS
|
||||
-------------------------------------------------------------------------------
|
||||
PROCESS (exe_opcode, OP2out, muls_msb, mulu_reg, FAsign, mulu_sign, reg_QA, faktorB, result_mulu, signedOP)
|
||||
BEGIN
|
||||
IF (signedOP='1' AND faktorB(31)='1') OR FAsign='1' THEN
|
||||
muls_msb <= mulu_reg(63);
|
||||
ELSE
|
||||
muls_msb <= '0';
|
||||
END IF;
|
||||
|
||||
IF signedOP='1' AND faktorB(31)='1' THEN
|
||||
mulu_sign <= '1';
|
||||
ELSE
|
||||
mulu_sign <= '0';
|
||||
END IF;
|
||||
|
||||
IF MUL_Mode=0 THEN -- 16 Bit
|
||||
result_mulu(63 downto 32) <= muls_msb&mulu_reg(63 downto 33);
|
||||
result_mulu(15 downto 0) <= 'X'&mulu_reg(15 downto 1);
|
||||
IF mulu_reg(0)='1' THEN
|
||||
IF FAsign='1' THEN
|
||||
result_mulu(63 downto 47) <= std_logic_vector(muls_msb & unsigned(mulu_reg(63 downto 48)) - unsigned(mulu_sign&faktorB(31 downto 16)) );
|
||||
ELSE
|
||||
result_mulu(63 downto 47) <= std_logic_vector(muls_msb & unsigned(mulu_reg(63 downto 48)) + unsigned(mulu_sign&faktorB(31 downto 16)) );
|
||||
END IF;
|
||||
END IF;
|
||||
ELSE -- 32 Bit
|
||||
result_mulu <= muls_msb&mulu_reg(63 downto 1);
|
||||
IF mulu_reg(0)='1' THEN
|
||||
IF FAsign='1' THEN
|
||||
result_mulu(63 downto 31) <= std_logic_vector(muls_msb & unsigned(mulu_reg(63 downto 32))-unsigned(mulu_sign&faktorB));
|
||||
ELSE
|
||||
result_mulu(63 downto 31) <= std_logic_vector(muls_msb & unsigned(mulu_reg(63 downto 32))+unsigned(mulu_sign&faktorB));
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
IF exe_opcode(15)='1' OR MUL_Mode=0 THEN
|
||||
faktorB(31 downto 16) <= OP2out(15 downto 0);
|
||||
faktorB(15 downto 0) <= (OTHERS=>'0');
|
||||
ELSE
|
||||
faktorB <= OP2out;
|
||||
END IF;
|
||||
IF (result_mulu(63 downto 32)=X"00000000" AND (signedOP='0' OR result_mulu(31)='0')) OR
|
||||
(result_mulu(63 downto 32)=X"FFFFFFFF" AND signedOP='1' AND result_mulu(31)='1') THEN
|
||||
set_mV_Flag <= '0';
|
||||
ELSE
|
||||
set_mV_Flag <= '1';
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (clk)
|
||||
BEGIN
|
||||
IF rising_edge(clk) THEN
|
||||
IF clkena_lw='1' THEN
|
||||
IF micro_state=mul1 THEN
|
||||
mulu_reg(63 downto 32) <= (OTHERS=>'0');
|
||||
IF divs='1' AND ((exe_opcode(15)='1' AND reg_QA(15)='1') OR (exe_opcode(15)='0' AND reg_QA(31)='1')) THEN --MULS Neg faktor
|
||||
FAsign <= '1';
|
||||
mulu_reg(31 downto 0) <= std_logic_vector(0-unsigned(reg_QA));
|
||||
ELSE
|
||||
FAsign <= '0';
|
||||
mulu_reg(31 downto 0) <= reg_QA;
|
||||
END IF;
|
||||
ELSIF exec(opcMULU)='0' THEN
|
||||
mulu_reg <= result_mulu;
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
---- DIVU/DIVS
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
PROCESS (execOPC, OP1out, OP2out, div_reg, div_neg, div_bit, div_sub, div_quot, OP1_sign, div_over, result_div, reg_QA, opcode, sndOPC, divs, exe_opcode, reg_QB,
|
||||
signedOP, nozero, div_qsign, OP2outext)
|
||||
BEGIN
|
||||
divs <= (opcode(15) AND opcode(8)) OR (NOT opcode(15) AND sndOPC(11));
|
||||
divisor(15 downto 0) <= (OTHERS=> '0');
|
||||
divisor(63 downto 32) <= (OTHERS=> divs AND reg_QA(31));
|
||||
IF exe_opcode(15)='1' OR DIV_Mode=0 THEN
|
||||
divisor(47 downto 16) <= reg_QA;
|
||||
ELSE
|
||||
divisor(31 downto 0) <= reg_QA;
|
||||
IF exe_opcode(14)='1' AND sndOPC(10)='1' THEN
|
||||
divisor(63 downto 32) <= reg_QB;
|
||||
END IF;
|
||||
END IF;
|
||||
IF signedOP='1' OR opcode(15)='0' THEN
|
||||
OP2outext <= OP2out(31 downto 16);
|
||||
ELSE
|
||||
OP2outext <= (OTHERS=> '0');
|
||||
END IF;
|
||||
IF signedOP='1' AND OP2out(31) ='1' THEN
|
||||
div_sub <= std_logic_vector(unsigned(div_reg(63 downto 31)) + unsigned('1'&OP2out(31 downto 0)));
|
||||
ELSE
|
||||
div_sub <= std_logic_vector(unsigned(div_reg(63 downto 31))-unsigned('0'&OP2outext(15 downto 0)&OP2out(15 downto 0)));
|
||||
END IF;
|
||||
IF DIV_Mode=0 THEN
|
||||
div_bit <= div_sub(16);
|
||||
ELSE
|
||||
div_bit <= div_sub(32);
|
||||
END IF;
|
||||
IF div_bit='1' THEN
|
||||
div_quot(63 downto 32) <= div_reg(62 downto 31);
|
||||
ELSE
|
||||
div_quot(63 downto 32) <= div_sub(31 downto 0);
|
||||
END IF;
|
||||
div_quot(31 downto 0) <= div_reg(30 downto 0)&NOT div_bit;
|
||||
|
||||
|
||||
IF ((nozero='1' AND signedOP='1' AND (OP2out(31) XOR OP1_sign XOR div_neg XOR div_qsign)='1' ) --Overflow DIVS
|
||||
OR (signedOP='0' AND div_over(32)='0')) AND DIV_Mode/=3 THEN --Overflow DIVU
|
||||
set_V_Flag <= '1';
|
||||
ELSE
|
||||
set_V_Flag <= '0';
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (clk)
|
||||
BEGIN
|
||||
IF rising_edge(clk) THEN
|
||||
IF clkena_lw='1' THEN
|
||||
V_Flag <= set_V_Flag;
|
||||
signedOP <= divs;
|
||||
IF micro_state=div1 THEN
|
||||
nozero <= '0';
|
||||
IF divs='1' AND divisor(63)='1' THEN -- Neg divisor
|
||||
OP1_sign <= '1';
|
||||
div_reg <= std_logic_vector(0-unsigned(divisor));
|
||||
ELSE
|
||||
OP1_sign <= '0';
|
||||
div_reg <= divisor;
|
||||
END IF;
|
||||
ELSE
|
||||
div_reg <= div_quot;
|
||||
nozero <= NOT div_bit OR nozero;
|
||||
END IF;
|
||||
IF micro_state=div2 THEN
|
||||
div_qsign <= NOT div_bit;
|
||||
div_neg <= signedOP AND (OP2out(31) XOR OP1_sign);
|
||||
IF DIV_Mode=0 THEN
|
||||
div_over(32 downto 16) <= std_logic_vector(unsigned('0'&div_reg(47 downto 32))-unsigned('0'&OP2out(15 downto 0)));
|
||||
ELSE
|
||||
div_over <= std_logic_vector(unsigned('0'&div_reg(63 downto 32))-unsigned('0'&OP2out));
|
||||
END IF;
|
||||
END IF;
|
||||
IF exec(write_reminder)='0' THEN
|
||||
-- IF exec_DIVU='0' THEN
|
||||
IF div_neg='1' THEN
|
||||
result_div(31 downto 0) <= std_logic_vector(0-unsigned(div_quot(31 downto 0)));
|
||||
ELSE
|
||||
result_div(31 downto 0) <= div_quot(31 downto 0);
|
||||
END IF;
|
||||
|
||||
IF OP1_sign='1' THEN
|
||||
result_div(63 downto 32) <= std_logic_vector(0-unsigned(div_quot(63 downto 32)));
|
||||
ELSE
|
||||
result_div(63 downto 32) <= div_quot(63 downto 32);
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
END;
|
||||
166
tests/tg68k/TG68K_Pack.vhd
Normal file
166
tests/tg68k/TG68K_Pack.vhd
Normal file
@ -0,0 +1,166 @@
|
||||
------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------
|
||||
-- --
|
||||
-- Copyright (c) 2009-2013 Tobias Gubener --
|
||||
-- Subdesign fAMpIGA by TobiFlex --
|
||||
-- --
|
||||
-- This source file is free software: you can redistribute it and/or modify --
|
||||
-- it under the terms of the GNU General Public License as published --
|
||||
-- by the Free Software Foundation, either version 3 of the License, or --
|
||||
-- (at your option) any later version. --
|
||||
-- --
|
||||
-- This source file is distributed in the hope that it will be useful, --
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
|
||||
-- GNU General Public License for more details. --
|
||||
-- --
|
||||
-- You should have received a copy of the GNU General Public License --
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
|
||||
-- --
|
||||
------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
|
||||
package TG68K_Pack is
|
||||
|
||||
type micro_states is (idle, nop, ld_nn, st_nn, ld_dAn1, ld_AnXn1, ld_AnXn2, st_dAn1, ld_AnXnbd1, ld_AnXnbd2, ld_AnXnbd3,
|
||||
ld_229_1, ld_229_2, ld_229_3, ld_229_4, st_229_1, st_229_2, st_229_3, st_229_4,
|
||||
st_AnXn1, st_AnXn2, bra1, bsr1, bsr2, nopnop, dbcc1, movem1, movem2, movem3,
|
||||
andi, op_AxAy, cmpm, link1, link2, unlink1, unlink2, int1, int2, int3, int4, rte1, rte2, rte3, trap0, trap1, trap2, trap3,
|
||||
trap4, trap5, trap6, movec1, movep1, movep2, movep3, movep4, movep5, rota1, bf1,
|
||||
mul1, mul2, mul_end1, mul_end2, div1, div2, div3, div4, div_end1, div_end2, pack1, pack2, pack3);
|
||||
|
||||
constant opcMOVE : integer := 0; --
|
||||
constant opcMOVEQ : integer := 1; --
|
||||
constant opcMOVESR : integer := 2; --
|
||||
constant opcADD : integer := 3; --
|
||||
constant opcADDQ : integer := 4; --
|
||||
constant opcOR : integer := 5; --
|
||||
constant opcAND : integer := 6; --
|
||||
constant opcEOR : integer := 7; --
|
||||
constant opcCMP : integer := 8; --
|
||||
constant opcROT : integer := 9; --
|
||||
constant opcCPMAW : integer := 10;
|
||||
constant opcEXT : integer := 11; --
|
||||
constant opcABCD : integer := 12; --
|
||||
constant opcSBCD : integer := 13; --
|
||||
constant opcBITS : integer := 14; --
|
||||
constant opcSWAP : integer := 15; --
|
||||
constant opcScc : integer := 16; --
|
||||
constant andiSR : integer := 17; --
|
||||
constant eoriSR : integer := 18; --
|
||||
constant oriSR : integer := 19; --
|
||||
constant opcMULU : integer := 20; --
|
||||
constant opcDIVU : integer := 21; --
|
||||
constant dispouter : integer := 22; --
|
||||
constant rot_nop : integer := 23; --
|
||||
constant ld_rot_cnt : integer := 24; --
|
||||
constant writePC_add : integer := 25; --
|
||||
constant ea_data_OP1 : integer := 26; --
|
||||
constant ea_data_OP2 : integer := 27; --
|
||||
constant use_XZFlag : integer := 28; --
|
||||
constant get_bfoffset : integer := 29; --
|
||||
constant save_memaddr : integer := 30; --
|
||||
constant opcCHK : integer := 31; --
|
||||
constant movec_rd : integer := 32; --
|
||||
constant movec_wr : integer := 33; --
|
||||
constant Regwrena : integer := 34; --
|
||||
constant update_FC : integer := 35; --
|
||||
constant linksp : integer := 36; --
|
||||
constant movepl : integer := 37; --
|
||||
constant update_ld : integer := 38; --
|
||||
constant OP1addr : integer := 39; --
|
||||
constant write_reg : integer := 40; --
|
||||
constant changeMode : integer := 41; --
|
||||
constant ea_build : integer := 42; --
|
||||
constant trap_chk : integer := 43; --
|
||||
constant store_ea_data : integer := 44; --
|
||||
constant addrlong : integer := 45; --
|
||||
constant postadd : integer := 46; --
|
||||
constant presub : integer := 47; --
|
||||
constant subidx : integer := 48; --
|
||||
constant no_Flags : integer := 49; --
|
||||
constant use_SP : integer := 50; --
|
||||
constant to_CCR : integer := 51; --
|
||||
constant to_SR : integer := 52; --
|
||||
constant OP2out_one : integer := 53; --
|
||||
constant OP1out_zero : integer := 54; --
|
||||
constant mem_addsub : integer := 55; --
|
||||
constant addsub : integer := 56; --
|
||||
constant directPC : integer := 57; --
|
||||
constant direct_delta : integer := 58; --
|
||||
constant directSR : integer := 59; --
|
||||
constant directCCR : integer := 60; --
|
||||
constant exg : integer := 61; --
|
||||
constant get_ea_now : integer := 62; --
|
||||
constant ea_to_pc : integer := 63; --
|
||||
constant hold_dwr : integer := 64; --
|
||||
constant to_USP : integer := 65; --
|
||||
constant from_USP : integer := 66; --
|
||||
constant write_lowlong : integer := 67; --
|
||||
constant write_reminder : integer := 68; --
|
||||
constant movem_action : integer := 69; --
|
||||
constant briefext : integer := 70; --
|
||||
constant get_2ndOPC : integer := 71; --
|
||||
constant mem_byte : integer := 72; --
|
||||
constant longaktion : integer := 73; --
|
||||
constant opcRESET : integer := 74; --
|
||||
constant opcBF : integer := 75; --
|
||||
constant opcBFwb : integer := 76; --
|
||||
constant opcPACK : integer := 77; --
|
||||
-- constant s2nd_hbits : integer := 77; --
|
||||
-- constant : integer := 75; --
|
||||
-- constant : integer := 76; --
|
||||
-- constant : integer := 7; --
|
||||
-- constant : integer := 7; --
|
||||
-- constant : integer := 7; --
|
||||
|
||||
constant lastOpcBit : integer := 77;
|
||||
|
||||
component TG68K_ALU
|
||||
generic(
|
||||
MUL_Mode : integer := 0; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
|
||||
DIV_Mode : integer := 0 --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
|
||||
);
|
||||
port(
|
||||
clk : in std_logic;
|
||||
Reset : in std_logic;
|
||||
clkena_lw : in std_logic:='1';
|
||||
execOPC : in bit;
|
||||
exe_condition : in std_logic;
|
||||
exec_tas : in std_logic;
|
||||
long_start : in bit;
|
||||
movem_presub : in bit;
|
||||
set_stop : in bit;
|
||||
Z_error : in bit;
|
||||
rot_bits : in std_logic_vector(1 downto 0);
|
||||
exec : in bit_vector(lastOpcBit downto 0);
|
||||
OP1out : in std_logic_vector(31 downto 0);
|
||||
OP2out : in std_logic_vector(31 downto 0);
|
||||
reg_QA : in std_logic_vector(31 downto 0);
|
||||
reg_QB : in std_logic_vector(31 downto 0);
|
||||
opcode : in std_logic_vector(15 downto 0);
|
||||
datatype : in std_logic_vector(1 downto 0);
|
||||
exe_opcode : in std_logic_vector(15 downto 0);
|
||||
exe_datatype : in std_logic_vector(1 downto 0);
|
||||
sndOPC : in std_logic_vector(15 downto 0);
|
||||
last_data_read : in std_logic_vector(15 downto 0);
|
||||
data_read : in std_logic_vector(15 downto 0);
|
||||
FlagsSR : in std_logic_vector(7 downto 0);
|
||||
micro_state : in micro_states;
|
||||
bf_ext_in : in std_logic_vector(7 downto 0);
|
||||
bf_ext_out : out std_logic_vector(7 downto 0);
|
||||
bf_shift : in std_logic_vector(5 downto 0);
|
||||
bf_width : in std_logic_vector(5 downto 0);
|
||||
bf_loffset : in std_logic_vector(4 downto 0);
|
||||
|
||||
set_V_Flag : buffer bit;
|
||||
Flags : buffer std_logic_vector(7 downto 0);
|
||||
c_out : buffer std_logic_vector(2 downto 0);
|
||||
addsub_q : buffer std_logic_vector(31 downto 0);
|
||||
ALUout : out std_logic_vector(31 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
end;
|
||||
3312
tests/tg68k/TG68KdotC_Kernel.vhd
Normal file
3312
tests/tg68k/TG68KdotC_Kernel.vhd
Normal file
File diff suppressed because it is too large
Load Diff
920
tests/tg68k/orig/TG68K_ALU.vhd
Normal file
920
tests/tg68k/orig/TG68K_ALU.vhd
Normal file
@ -0,0 +1,920 @@
|
||||
------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------
|
||||
-- --
|
||||
-- Copyright (c) 2009-2011 Tobias Gubener --
|
||||
-- Subdesign fAMpIGA by TobiFlex --
|
||||
-- --
|
||||
-- This source file is free software: you can redistribute it and/or modify --
|
||||
-- it under the terms of the GNU General Public License as published --
|
||||
-- by the Free Software Foundation, either version 3 of the License, or --
|
||||
-- (at your option) any later version. --
|
||||
-- --
|
||||
-- This source file is distributed in the hope that it will be useful, --
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
|
||||
-- GNU General Public License for more details. --
|
||||
-- --
|
||||
-- You should have received a copy of the GNU General Public License --
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
|
||||
-- --
|
||||
------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
-- use ieee.std_logic_unsigned.all;
|
||||
use IEEE.numeric_std.all;
|
||||
use work.TG68K_Pack.all;
|
||||
|
||||
entity TG68K_ALU is
|
||||
generic(
|
||||
MUL_Mode : integer := 0; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
|
||||
DIV_Mode : integer := 0 --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
|
||||
);
|
||||
port(clk : in std_logic;
|
||||
Reset : in std_logic;
|
||||
clkena_lw : in std_logic:='1';
|
||||
execOPC : in bit;
|
||||
exe_condition : in std_logic;
|
||||
exec_tas : in std_logic;
|
||||
long_start : in bit;
|
||||
movem_presub : in bit;
|
||||
set_stop : in bit;
|
||||
Z_error : in bit;
|
||||
rot_bits : in std_logic_vector(1 downto 0);
|
||||
exec : in bit_vector(lastOpcBit downto 0);
|
||||
OP1out : in std_logic_vector(31 downto 0);
|
||||
OP2out : in std_logic_vector(31 downto 0);
|
||||
reg_QA : in std_logic_vector(31 downto 0);
|
||||
reg_QB : in std_logic_vector(31 downto 0);
|
||||
opcode : in std_logic_vector(15 downto 0);
|
||||
datatype : in std_logic_vector(1 downto 0);
|
||||
exe_opcode : in std_logic_vector(15 downto 0);
|
||||
exe_datatype : in std_logic_vector(1 downto 0);
|
||||
sndOPC : in std_logic_vector(15 downto 0);
|
||||
last_data_read : in std_logic_vector(15 downto 0);
|
||||
data_read : in std_logic_vector(15 downto 0);
|
||||
FlagsSR : in std_logic_vector(7 downto 0);
|
||||
micro_state : in micro_states;
|
||||
bf_ext_in : in std_logic_vector(7 downto 0);
|
||||
bf_ext_out : out std_logic_vector(7 downto 0);
|
||||
bf_shift : in std_logic_vector(5 downto 0);
|
||||
bf_width : in std_logic_vector(5 downto 0);
|
||||
bf_loffset : in std_logic_vector(4 downto 0);
|
||||
|
||||
set_V_Flag : buffer bit;
|
||||
Flags : buffer std_logic_vector(7 downto 0);
|
||||
c_out : buffer std_logic_vector(2 downto 0);
|
||||
addsub_q : buffer std_logic_vector(31 downto 0);
|
||||
ALUout : out std_logic_vector(31 downto 0)
|
||||
);
|
||||
end TG68K_ALU;
|
||||
|
||||
architecture logic of TG68K_ALU is
|
||||
-----------------------------------------------------------------------------
|
||||
-----------------------------------------------------------------------------
|
||||
-- ALU and more
|
||||
-----------------------------------------------------------------------------
|
||||
-----------------------------------------------------------------------------
|
||||
signal OP1in : std_logic_vector(31 downto 0);
|
||||
signal addsub_a : std_logic_vector(31 downto 0);
|
||||
signal addsub_b : std_logic_vector(31 downto 0);
|
||||
signal notaddsub_b : std_logic_vector(33 downto 0);
|
||||
signal add_result : std_logic_vector(33 downto 0);
|
||||
signal addsub_ofl : std_logic_vector(2 downto 0);
|
||||
signal opaddsub : bit;
|
||||
signal c_in : std_logic_vector(3 downto 0);
|
||||
signal flag_z : std_logic_vector(2 downto 0);
|
||||
signal set_Flags : std_logic_vector(3 downto 0); --NZVC
|
||||
signal CCRin : std_logic_vector(7 downto 0);
|
||||
|
||||
signal niba_l : std_logic_vector(5 downto 0);
|
||||
signal niba_h : std_logic_vector(5 downto 0);
|
||||
signal niba_lc : std_logic;
|
||||
signal niba_hc : std_logic;
|
||||
signal bcda_lc : std_logic;
|
||||
signal bcda_hc : std_logic;
|
||||
signal nibs_l : std_logic_vector(5 downto 0);
|
||||
signal nibs_h : std_logic_vector(5 downto 0);
|
||||
signal nibs_lc : std_logic;
|
||||
signal nibs_hc : std_logic;
|
||||
|
||||
signal bcd_a : std_logic_vector(8 downto 0);
|
||||
signal bcd_s : std_logic_vector(8 downto 0);
|
||||
signal result_mulu : std_logic_vector(63 downto 0);
|
||||
signal result_div : std_logic_vector(63 downto 0);
|
||||
signal set_mV_Flag : std_logic;
|
||||
signal V_Flag : bit;
|
||||
|
||||
signal rot_rot : std_logic;
|
||||
signal rot_lsb : std_logic;
|
||||
signal rot_msb : std_logic;
|
||||
signal rot_X : std_logic;
|
||||
signal rot_C : std_logic;
|
||||
signal rot_out : std_logic_vector(31 downto 0);
|
||||
signal asl_VFlag : std_logic;
|
||||
signal bit_bits : std_logic_vector(1 downto 0);
|
||||
signal bit_number : std_logic_vector(4 downto 0);
|
||||
signal bits_out : std_logic_vector(31 downto 0);
|
||||
signal one_bit_in : std_logic;
|
||||
signal bchg : std_logic;
|
||||
signal bset : std_logic;
|
||||
|
||||
signal mulu_sign : std_logic;
|
||||
signal mulu_signext : std_logic_vector(16 downto 0);
|
||||
signal muls_msb : std_logic;
|
||||
signal mulu_reg : std_logic_vector(63 downto 0);
|
||||
signal FAsign : std_logic;
|
||||
signal faktorA : std_logic_vector(31 downto 0);
|
||||
signal faktorB : std_logic_vector(31 downto 0);
|
||||
|
||||
signal div_reg : std_logic_vector(63 downto 0);
|
||||
signal div_quot : std_logic_vector(63 downto 0);
|
||||
signal div_ovl : std_logic;
|
||||
signal div_neg : std_logic;
|
||||
signal div_bit : std_logic;
|
||||
signal div_sub : std_logic_vector(32 downto 0);
|
||||
signal div_over : std_logic_vector(32 downto 0);
|
||||
signal nozero : std_logic;
|
||||
signal div_qsign : std_logic;
|
||||
signal divisor : std_logic_vector(63 downto 0);
|
||||
signal divs : std_logic;
|
||||
signal signedOP : std_logic;
|
||||
signal OP1_sign : std_logic;
|
||||
signal OP2_sign : std_logic;
|
||||
signal OP2outext : std_logic_vector(15 downto 0);
|
||||
|
||||
signal in_offset : std_logic_vector(5 downto 0);
|
||||
-- signal in_width : std_logic_vector(5 downto 0);
|
||||
signal datareg : std_logic_vector(31 downto 0);
|
||||
signal insert : std_logic_vector(31 downto 0);
|
||||
-- signal bf_result : std_logic_vector(31 downto 0);
|
||||
-- signal bf_offset : std_logic_vector(5 downto 0);
|
||||
-- signal bf_width : std_logic_vector(5 downto 0);
|
||||
-- signal bf_firstbit : std_logic_vector(5 downto 0);
|
||||
signal bf_datareg : std_logic_vector(31 downto 0);
|
||||
-- signal bf_out : std_logic_vector(31 downto 0);
|
||||
signal result : std_logic_vector(39 downto 0);
|
||||
signal result_tmp : std_logic_vector(39 downto 0);
|
||||
signal sign : std_logic_vector(31 downto 0);
|
||||
signal bf_set1 : std_logic_vector(39 downto 0);
|
||||
signal inmux0 : std_logic_vector(39 downto 0);
|
||||
signal inmux1 : std_logic_vector(39 downto 0);
|
||||
signal inmux2 : std_logic_vector(39 downto 0);
|
||||
signal inmux3 : std_logic_vector(31 downto 0);
|
||||
signal copymux0 : std_logic_vector(39 downto 0);
|
||||
signal copymux1 : std_logic_vector(39 downto 0);
|
||||
signal copymux2 : std_logic_vector(39 downto 0);
|
||||
signal copymux3 : std_logic_vector(31 downto 0);
|
||||
signal bf_set2 : std_logic_vector(31 downto 0);
|
||||
-- signal bf_set3 : std_logic_vector(31 downto 0);
|
||||
signal shift : std_logic_vector(39 downto 0);
|
||||
signal copy : std_logic_vector(39 downto 0);
|
||||
-- signal offset : std_logic_vector(5 downto 0);
|
||||
-- signal width : std_logic_vector(5 downto 0);
|
||||
signal bf_firstbit : std_logic_vector(5 downto 0);
|
||||
signal mux : std_logic_vector(3 downto 0);
|
||||
signal bitnr : std_logic_vector(4 downto 0);
|
||||
signal mask : std_logic_vector(31 downto 0);
|
||||
signal bf_bset : std_logic;
|
||||
signal bf_NFlag : std_logic;
|
||||
signal bf_bchg : std_logic;
|
||||
signal bf_ins : std_logic;
|
||||
signal bf_exts : std_logic;
|
||||
signal bf_fffo : std_logic;
|
||||
signal bf_d32 : std_logic;
|
||||
signal bf_s32 : std_logic;
|
||||
signal index : std_logic_vector(4 downto 0);
|
||||
-- signal i : integer range 0 to 31;
|
||||
-- signal i : integer range 0 to 31;
|
||||
-- signal i : std_logic_vector(5 downto 0);
|
||||
BEGIN
|
||||
-----------------------------------------------------------------------------
|
||||
-- set OP1in
|
||||
-----------------------------------------------------------------------------
|
||||
PROCESS (OP2out, reg_QB, opcode, OP1out, OP1in, exe_datatype, addsub_q, execOPC, exec,
|
||||
bcd_a, bcd_s, result_mulu, result_div, exe_condition, bf_shift,
|
||||
Flags, FlagsSR, bits_out, exec_tas, rot_out, exe_opcode, result, bf_fffo, bf_firstbit, bf_datareg)
|
||||
BEGIN
|
||||
ALUout <= OP1in;
|
||||
ALUout(7) <= OP1in(7) OR exec_tas;
|
||||
IF exec(opcBFwb)='1' THEN
|
||||
ALUout <= result(31 downto 0);
|
||||
IF bf_fffo='1' THEN
|
||||
ALUout <= (OTHERS =>'0');
|
||||
ALUout(5 downto 0) <= std_logic_vector(unsigned(bf_firstbit) + unsigned(bf_shift));
|
||||
END IF;
|
||||
END IF;
|
||||
|
||||
OP1in <= addsub_q;
|
||||
IF exec(opcABCD)='1' THEN
|
||||
OP1in(7 downto 0) <= bcd_a(7 downto 0);
|
||||
ELSIF exec(opcSBCD)='1' THEN
|
||||
OP1in(7 downto 0) <= bcd_s(7 downto 0);
|
||||
ELSIF exec(opcMULU)='1' AND MUL_Mode/=3 THEN
|
||||
IF exec(write_lowlong)='1' AND (MUL_Mode=1 OR MUL_Mode=2) THEN
|
||||
OP1in <= result_mulu(31 downto 0);
|
||||
ELSE
|
||||
OP1in <= result_mulu(63 downto 32);
|
||||
END IF;
|
||||
ELSIF exec(opcDIVU)='1' AND DIV_Mode/=3 THEN
|
||||
IF exe_opcode(15)='1' OR DIV_Mode=0 THEN
|
||||
-- IF exe_opcode(15)='1' THEN
|
||||
OP1in <= result_div(47 downto 32)&result_div(15 downto 0);
|
||||
ELSE --64bit
|
||||
IF exec(write_reminder)='1' THEN
|
||||
OP1in <= result_div(63 downto 32);
|
||||
ELSE
|
||||
OP1in <= result_div(31 downto 0);
|
||||
END IF;
|
||||
END IF;
|
||||
ELSIF exec(opcOR)='1' THEN
|
||||
OP1in <= OP2out OR OP1out;
|
||||
ELSIF exec(opcAND)='1' THEN
|
||||
OP1in <= OP2out AND OP1out;
|
||||
ELSIF exec(opcScc)='1' THEN
|
||||
OP1in(7 downto 0) <= (others=>exe_condition);
|
||||
ELSIF exec(opcEOR)='1' THEN
|
||||
OP1in <= OP2out XOR OP1out;
|
||||
ELSIF exec(opcMOVE)='1' OR exec(exg)='1' THEN
|
||||
-- OP1in <= OP2out(31 downto 8)&(OP2out(7)OR exec_tas)&OP2out(6 downto 0);
|
||||
OP1in <= OP2out;
|
||||
ELSIF exec(opcROT)='1' THEN
|
||||
OP1in <= rot_out;
|
||||
ELSIF exec(opcSWAP)='1' THEN
|
||||
OP1in <= OP1out(15 downto 0)& OP1out(31 downto 16);
|
||||
ELSIF exec(opcBITS)='1' THEN
|
||||
OP1in <= bits_out;
|
||||
ELSIF exec(opcBF)='1' THEN
|
||||
OP1in <= bf_datareg;
|
||||
ELSIF exec(opcMOVESR)='1' THEN
|
||||
OP1in(7 downto 0) <= Flags;
|
||||
IF exe_datatype="00" THEN
|
||||
OP1in(15 downto 8) <= "00000000";
|
||||
ELSE
|
||||
OP1in(15 downto 8) <= FlagsSR;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- addsub
|
||||
-----------------------------------------------------------------------------
|
||||
PROCESS (OP1out, OP2out, execOPC, datatype, Flags, long_start, movem_presub, exe_datatype, exec, addsub_a, addsub_b, opaddsub,
|
||||
notaddsub_b, add_result, c_in, sndOPC)
|
||||
BEGIN
|
||||
addsub_a <= OP1out;
|
||||
IF exec(get_bfoffset)='1' THEN
|
||||
IF sndOPC(11)='1' THEN
|
||||
addsub_a <= OP1out(31)&OP1out(31)&OP1out(31)&OP1out(31 downto 3);
|
||||
ELSE
|
||||
addsub_a <= "000000000000000000000000000000"&sndOPC(10 downto 9);
|
||||
END IF;
|
||||
END IF;
|
||||
|
||||
IF exec(subidx)='1' THEN
|
||||
opaddsub <= '1';
|
||||
ELSE
|
||||
opaddsub <= '0';
|
||||
END IF;
|
||||
|
||||
c_in(0) <='0';
|
||||
addsub_b <= OP2out;
|
||||
IF execOPC='0' AND exec(OP2out_one)='0' AND exec(get_bfoffset)='0'THEN
|
||||
IF long_start='0' AND datatype="00" AND exec(use_SP)='0' THEN
|
||||
addsub_b <= "00000000000000000000000000000001";
|
||||
ELSIF long_start='0' AND exe_datatype="10" AND (exec(presub) OR exec(postadd) OR movem_presub)='1' THEN
|
||||
IF exec(movem_action)='1' THEN
|
||||
addsub_b <= "00000000000000000000000000000110";
|
||||
ELSE
|
||||
addsub_b <= "00000000000000000000000000000100";
|
||||
END IF;
|
||||
ELSE
|
||||
addsub_b <= "00000000000000000000000000000010";
|
||||
END IF;
|
||||
ELSE
|
||||
IF (exec(use_XZFlag)='1' AND Flags(4)='1') OR exec(opcCHK)='1' THEN
|
||||
c_in(0) <= '1';
|
||||
END IF;
|
||||
opaddsub <= exec(addsub);
|
||||
END IF;
|
||||
|
||||
IF opaddsub='0' OR long_start='1' THEN --ADD
|
||||
notaddsub_b <= '0'&addsub_b&c_in(0);
|
||||
ELSE --SUB
|
||||
notaddsub_b <= NOT ('0'&addsub_b&c_in(0));
|
||||
END IF;
|
||||
add_result <= std_logic_vector( unsigned('0'&addsub_a¬addsub_b(0)) + unsigned(notaddsub_b));
|
||||
c_in(1) <= add_result(9) XOR addsub_a(8) XOR addsub_b(8);
|
||||
c_in(2) <= add_result(17) XOR addsub_a(16) XOR addsub_b(16);
|
||||
c_in(3) <= add_result(33);
|
||||
addsub_q <= add_result(32 downto 1);
|
||||
addsub_ofl(0) <= (c_in(1) XOR add_result(8) XOR addsub_a(7) XOR addsub_b(7)); --V Byte
|
||||
addsub_ofl(1) <= (c_in(2) XOR add_result(16) XOR addsub_a(15) XOR addsub_b(15)); --V Word
|
||||
addsub_ofl(2) <= (c_in(3) XOR add_result(32) XOR addsub_a(31) XOR addsub_b(31)); --V Long
|
||||
c_out <= c_in(3 downto 1);
|
||||
END PROCESS;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
--ALU
|
||||
------------------------------------------------------------------------------
|
||||
PROCESS (OP1out, OP2out, niba_hc, niba_h, niba_l, niba_lc, nibs_hc, nibs_h, nibs_l, nibs_lc, Flags)
|
||||
BEGIN
|
||||
--BCD_ARITH-------------------------------------------------------------------
|
||||
--ADC
|
||||
bcd_a <= niba_hc & std_logic_vector(unsigned(niba_h(4 downto 1)) + ('0',niba_hc,niba_hc,'0')) &
|
||||
std_logic_vector(unsigned(niba_l(4 downto 1)) + ('0',niba_lc,niba_lc,'0'));
|
||||
niba_l <= std_logic_vector(unsigned('0'&OP1out(3 downto 0)&'1') + unsigned('0'&OP2out(3 downto 0)&Flags(4)));
|
||||
niba_lc <= niba_l(5) OR (niba_l(4) AND niba_l(3)) OR (niba_l(4) AND niba_l(2));
|
||||
|
||||
niba_h <= std_logic_vector(unsigned('0'&OP1out(7 downto 4)&'1') + unsigned('0'&OP2out(7 downto 4)&niba_lc));
|
||||
niba_hc <= niba_h(5) OR (niba_h(4) AND niba_h(3)) OR (niba_h(4) AND niba_h(2));
|
||||
--SBC
|
||||
bcd_s <= nibs_hc & std_logic_vector(unsigned(nibs_h(4 downto 1)) - ('0',nibs_hc,nibs_hc,'0')) &
|
||||
std_logic_vector(unsigned(nibs_l(4 downto 1)) - ('0',nibs_lc,nibs_lc,'0'));
|
||||
nibs_l <= std_logic_vector(unsigned('0'&OP1out(3 downto 0)&'0') - unsigned('0'&OP2out(3 downto 0)&Flags(4)));
|
||||
nibs_lc <= nibs_l(5);
|
||||
|
||||
nibs_h <= std_logic_vector(unsigned('0'&OP1out(7 downto 4)&'0') - unsigned('0'&OP2out(7 downto 4)&nibs_lc));
|
||||
nibs_hc <= nibs_h(5);
|
||||
END PROCESS;
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Bits
|
||||
-----------------------------------------------------------------------------
|
||||
PROCESS (clk, exe_opcode, OP1out, OP2out, one_bit_in, bchg, bset, bit_Number, sndOPC)
|
||||
BEGIN
|
||||
IF rising_edge(clk) THEN
|
||||
IF clkena_lw = '1' THEN
|
||||
bchg <= '0';
|
||||
bset <= '0';
|
||||
CASE opcode(7 downto 6) IS
|
||||
WHEN "01" => --bchg
|
||||
bchg <= '1';
|
||||
WHEN "11" => --bset
|
||||
bset <= '1';
|
||||
WHEN OTHERS => NULL;
|
||||
END CASE;
|
||||
END IF;
|
||||
END IF;
|
||||
|
||||
IF exe_opcode(8)='0' THEN
|
||||
IF exe_opcode(5 downto 4)="00" THEN
|
||||
bit_number <= sndOPC(4 downto 0);
|
||||
ELSE
|
||||
bit_number <= "00"&sndOPC(2 downto 0);
|
||||
END IF;
|
||||
ELSE
|
||||
IF exe_opcode(5 downto 4)="00" THEN
|
||||
bit_number <= reg_QB(4 downto 0);
|
||||
ELSE
|
||||
bit_number <= "00"®_QB(2 downto 0);
|
||||
END IF;
|
||||
END IF;
|
||||
|
||||
one_bit_in <= OP1out(to_integer(unsigned(bit_Number)));
|
||||
bits_out <= OP1out;
|
||||
bits_out(to_integer(unsigned(bit_Number))) <= (bchg AND NOT one_bit_in) OR bset ;
|
||||
END PROCESS;
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Bit Field
|
||||
-----------------------------------------------------------------------------
|
||||
PROCESS (clk, mux, mask, bitnr, bf_ins, bf_bchg, bf_bset, bf_exts, bf_shift, inmux0, inmux1, inmux2, inmux3, bf_set2, OP1out, OP2out, result_tmp, bf_ext_in,
|
||||
shift, datareg, bf_NFlag, result, reg_QB, sign, bf_d32, bf_s32, copy, bf_loffset, copymux0, copymux1, copymux2, copymux3, bf_width)
|
||||
BEGIN
|
||||
IF rising_edge(clk) THEN
|
||||
IF clkena_lw = '1' THEN
|
||||
bf_bset <= '0';
|
||||
bf_bchg <= '0';
|
||||
bf_ins <= '0';
|
||||
bf_exts <= '0';
|
||||
bf_fffo <= '0';
|
||||
bf_d32 <= '0';
|
||||
bf_s32 <= '0';
|
||||
CASE opcode(10 downto 8) IS
|
||||
WHEN "010" => bf_bchg <= '1'; --BFCHG
|
||||
WHEN "011" => bf_exts <= '1'; --BFEXTS
|
||||
-- WHEN "100" => insert <= (OTHERS =>'0'); --BFCLR
|
||||
WHEN "101" => bf_fffo <= '1'; --BFFFO
|
||||
WHEN "110" => bf_bset <= '1'; --BFSET
|
||||
WHEN "111" => bf_ins <= '1'; --BFINS
|
||||
bf_s32 <= '1';
|
||||
WHEN OTHERS => NULL;
|
||||
END CASE;
|
||||
IF opcode(4 downto 3)="00" THEN
|
||||
bf_d32 <= '1';
|
||||
END IF;
|
||||
bf_ext_out <= result(39 downto 32);
|
||||
END IF;
|
||||
END IF;
|
||||
shift <= bf_ext_in&OP2out;
|
||||
IF bf_s32='1' THEN
|
||||
shift(39 downto 32) <= OP2out(7 downto 0);
|
||||
END IF;
|
||||
|
||||
IF bf_shift(0)='1' THEN
|
||||
inmux0 <= shift(0)&shift(39 downto 1);
|
||||
ELSE
|
||||
inmux0 <= shift;
|
||||
END IF;
|
||||
IF bf_shift(1)='1' THEN
|
||||
inmux1 <= inmux0(1 downto 0)&inmux0(39 downto 2);
|
||||
ELSE
|
||||
inmux1 <= inmux0;
|
||||
END IF;
|
||||
IF bf_shift(2)='1' THEN
|
||||
inmux2 <= inmux1(3 downto 0)&inmux1(39 downto 4);
|
||||
ELSE
|
||||
inmux2 <= inmux1;
|
||||
END IF;
|
||||
IF bf_shift(3)='1' THEN
|
||||
inmux3 <= inmux2(7 downto 0)&inmux2(31 downto 8);
|
||||
ELSE
|
||||
inmux3 <= inmux2(31 downto 0);
|
||||
END IF;
|
||||
IF bf_shift(4)='1' THEN
|
||||
bf_set2(31 downto 0) <= inmux3(15 downto 0)&inmux3(31 downto 16);
|
||||
ELSE
|
||||
bf_set2(31 downto 0) <= inmux3;
|
||||
END IF;
|
||||
|
||||
IF bf_loffset(4)='1' THEN
|
||||
copymux3 <= sign(15 downto 0)&sign(31 downto 16);
|
||||
ELSE
|
||||
copymux3 <= sign;
|
||||
END IF;
|
||||
IF bf_loffset(3)='1' THEN
|
||||
copymux2(31 downto 0) <= copymux3(23 downto 0)©mux3(31 downto 24);
|
||||
ELSE
|
||||
copymux2(31 downto 0) <= copymux3;
|
||||
END IF;
|
||||
IF bf_d32='1' THEN
|
||||
copymux2(39 downto 32) <= copymux3(7 downto 0);
|
||||
ELSE
|
||||
copymux2(39 downto 32) <= "11111111";
|
||||
END IF;
|
||||
IF bf_loffset(2)='1' THEN
|
||||
copymux1 <= copymux2(35 downto 0)©mux2(39 downto 36);
|
||||
ELSE
|
||||
copymux1 <= copymux2;
|
||||
END IF;
|
||||
IF bf_loffset(1)='1' THEN
|
||||
copymux0 <= copymux1(37 downto 0)©mux1(39 downto 38);
|
||||
ELSE
|
||||
copymux0 <= copymux1;
|
||||
END IF;
|
||||
IF bf_loffset(0)='1' THEN
|
||||
copy <= copymux0(38 downto 0)©mux0(39);
|
||||
ELSE
|
||||
copy <= copymux0;
|
||||
END IF;
|
||||
|
||||
result_tmp <= bf_ext_in&OP1out;
|
||||
IF bf_ins='1' THEN
|
||||
datareg <= reg_QB;
|
||||
ELSE
|
||||
datareg <= bf_set2;
|
||||
END IF;
|
||||
IF bf_ins='1' THEN
|
||||
result(31 downto 0) <= bf_set2;
|
||||
result(39 downto 32) <= bf_set2(7 downto 0);
|
||||
ELSIF bf_bchg='1' THEN
|
||||
result(31 downto 0) <= NOT OP1out;
|
||||
result(39 downto 32) <= NOT bf_ext_in;
|
||||
ELSE
|
||||
result <= (OTHERS => '0');
|
||||
END IF;
|
||||
IF bf_bset='1' THEN
|
||||
result <= (OTHERS => '1');
|
||||
END IF;
|
||||
|
||||
sign <= (OTHERS => '0');
|
||||
bf_NFlag <= datareg(to_integer(unsigned(bf_width)));
|
||||
FOR i in 0 to 31 LOOP
|
||||
IF i > unsigned(bf_width(4 downto 0)) THEN
|
||||
datareg(i) <= '0';
|
||||
sign(i) <= '1';
|
||||
END IF;
|
||||
END LOOP;
|
||||
|
||||
FOR i in 0 to 39 LOOP
|
||||
IF copy(i)='1' THEN
|
||||
result(i) <= result_tmp(i);
|
||||
END IF;
|
||||
END LOOP;
|
||||
|
||||
IF bf_exts='1' AND bf_NFlag='1' THEN
|
||||
bf_datareg <= datareg OR sign;
|
||||
ELSE
|
||||
bf_datareg <= datareg;
|
||||
END IF;
|
||||
-- bf_datareg <= copy(31 downto 0);
|
||||
-- result(31 downto 0)<=datareg;
|
||||
--BFFFO
|
||||
mask <= datareg;
|
||||
bf_firstbit <= '0'&bitnr;
|
||||
bitnr <= "11111";
|
||||
IF mask(31 downto 28)="0000" THEN
|
||||
IF mask(27 downto 24)="0000" THEN
|
||||
IF mask(23 downto 20)="0000" THEN
|
||||
IF mask(19 downto 16)="0000" THEN
|
||||
bitnr(4) <= '0';
|
||||
IF mask(15 downto 12)="0000" THEN
|
||||
IF mask(11 downto 8)="0000" THEN
|
||||
bitnr(3) <= '0';
|
||||
IF mask(7 downto 4)="0000" THEN
|
||||
bitnr(2) <= '0';
|
||||
mux <= mask(3 downto 0);
|
||||
ELSE
|
||||
mux <= mask(7 downto 4);
|
||||
END IF;
|
||||
ELSE
|
||||
mux <= mask(11 downto 8);
|
||||
bitnr(2) <= '0';
|
||||
END IF;
|
||||
ELSE
|
||||
mux <= mask(15 downto 12);
|
||||
END IF;
|
||||
ELSE
|
||||
mux <= mask(19 downto 16);
|
||||
bitnr(3) <= '0';
|
||||
bitnr(2) <= '0';
|
||||
END IF;
|
||||
ELSE
|
||||
mux <= mask(23 downto 20);
|
||||
bitnr(3) <= '0';
|
||||
END IF;
|
||||
ELSE
|
||||
mux <= mask(27 downto 24);
|
||||
bitnr(2) <= '0';
|
||||
END IF;
|
||||
ELSE
|
||||
mux <= mask(31 downto 28);
|
||||
END IF;
|
||||
|
||||
IF mux(3 downto 2)="00" THEN
|
||||
bitnr(1) <= '0';
|
||||
IF mux(1)='0' THEN
|
||||
bitnr(0) <= '0';
|
||||
END IF;
|
||||
ELSE
|
||||
IF mux(3)='0' THEN
|
||||
bitnr(0) <= '0';
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
-----------------------------------------------------------------------------
|
||||
-- Rotation
|
||||
-----------------------------------------------------------------------------
|
||||
PROCESS (exe_opcode, OP1out, Flags, rot_bits, rot_msb, rot_lsb, rot_rot, exec)
|
||||
BEGIN
|
||||
CASE exe_opcode(7 downto 6) IS
|
||||
WHEN "00" => --Byte
|
||||
rot_rot <= OP1out(7);
|
||||
WHEN "01"|"11" => --Word
|
||||
rot_rot <= OP1out(15);
|
||||
WHEN "10" => --Long
|
||||
rot_rot <= OP1out(31);
|
||||
WHEN OTHERS => NULL;
|
||||
END CASE;
|
||||
|
||||
CASE rot_bits IS
|
||||
WHEN "00" => --ASL, ASR
|
||||
rot_lsb <= '0';
|
||||
rot_msb <= rot_rot;
|
||||
WHEN "01" => --LSL, LSR
|
||||
rot_lsb <= '0';
|
||||
rot_msb <= '0';
|
||||
WHEN "10" => --ROXL, ROXR
|
||||
rot_lsb <= Flags(4);
|
||||
rot_msb <= Flags(4);
|
||||
WHEN "11" => --ROL, ROR
|
||||
rot_lsb <= rot_rot;
|
||||
rot_msb <= OP1out(0);
|
||||
WHEN OTHERS => NULL;
|
||||
END CASE;
|
||||
|
||||
IF exec(rot_nop)='1' THEN
|
||||
rot_out <= OP1out;
|
||||
rot_X <= Flags(4);
|
||||
IF rot_bits="10" THEN --ROXL, ROXR
|
||||
rot_C <= Flags(4);
|
||||
ELSE
|
||||
rot_C <= '0';
|
||||
END IF;
|
||||
ELSE
|
||||
IF exe_opcode(8)='1' THEN --left
|
||||
rot_out <= OP1out(30 downto 0)&rot_lsb;
|
||||
rot_X <= rot_rot;
|
||||
rot_C <= rot_rot;
|
||||
ELSE --right
|
||||
rot_X <= OP1out(0);
|
||||
rot_C <= OP1out(0);
|
||||
rot_out <= rot_msb&OP1out(31 downto 1);
|
||||
CASE exe_opcode(7 downto 6) IS
|
||||
WHEN "00" => --Byte
|
||||
rot_out(7) <= rot_msb;
|
||||
WHEN "01"|"11" => --Word
|
||||
rot_out(15) <= rot_msb;
|
||||
WHEN OTHERS => NULL;
|
||||
END CASE;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
--CCR op
|
||||
------------------------------------------------------------------------------
|
||||
PROCESS (clk, Reset, exe_opcode, exe_datatype, Flags, last_data_read, OP2out, flag_z, OP1IN, c_out, addsub_ofl,
|
||||
bcd_s, bcd_a, exec)
|
||||
BEGIN
|
||||
IF exec(andiSR)='1' THEN
|
||||
CCRin <= Flags AND last_data_read(7 downto 0);
|
||||
ELSIF exec(eoriSR)='1' THEN
|
||||
CCRin <= Flags XOR last_data_read(7 downto 0);
|
||||
ELSIF exec(oriSR)='1' THEN
|
||||
CCRin <= Flags OR last_data_read(7 downto 0);
|
||||
ELSE
|
||||
CCRin <= OP2out(7 downto 0);
|
||||
END IF;
|
||||
|
||||
------------------------------------------------------------------------------
|
||||
--Flags
|
||||
------------------------------------------------------------------------------
|
||||
flag_z <= "000";
|
||||
IF exec(use_XZFlag)='1' AND flags(2)='0' THEN
|
||||
flag_z <= "000";
|
||||
ELSIF OP1in(7 downto 0)="00000000" THEN
|
||||
flag_z(0) <= '1';
|
||||
IF OP1in(15 downto 8)="00000000" THEN
|
||||
flag_z(1) <= '1';
|
||||
IF OP1in(31 downto 16)="0000000000000000" THEN
|
||||
flag_z(2) <= '1';
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
|
||||
-- --Flags NZVC
|
||||
IF exe_datatype="00" THEN --Byte
|
||||
set_flags <= OP1IN(7)&flag_z(0)&addsub_ofl(0)&c_out(0);
|
||||
IF exec(opcABCD)='1' THEN
|
||||
set_flags(0) <= bcd_a(8);
|
||||
ELSIF exec(opcSBCD)='1' THEN
|
||||
set_flags(0) <= bcd_s(8);
|
||||
END IF;
|
||||
ELSIF exe_datatype="10" OR exec(opcCPMAW)='1' THEN --Long
|
||||
set_flags <= OP1IN(31)&flag_z(2)&addsub_ofl(2)&c_out(2);
|
||||
ELSE --Word
|
||||
set_flags <= OP1IN(15)&flag_z(1)&addsub_ofl(1)&c_out(1);
|
||||
END IF;
|
||||
|
||||
IF rising_edge(clk) THEN
|
||||
IF clkena_lw = '1' THEN
|
||||
IF exec(directSR)='1' OR set_stop='1' THEN
|
||||
Flags(7 downto 0) <= data_read(7 downto 0);
|
||||
END IF;
|
||||
IF exec(directCCR)='1' THEN
|
||||
Flags(7 downto 0) <= data_read(7 downto 0);
|
||||
END IF;
|
||||
|
||||
IF exec(opcROT)='1' THEN
|
||||
asl_VFlag <= ((set_flags(3) XOR rot_rot) OR asl_VFlag);
|
||||
ELSE
|
||||
asl_VFlag <= '0';
|
||||
END IF;
|
||||
IF exec(to_CCR)='1' THEN
|
||||
Flags(7 downto 0) <= CCRin(7 downto 0); --CCR
|
||||
ELSIF Z_error='1' THEN
|
||||
IF exe_opcode(8)='0' THEN
|
||||
Flags(3 downto 0) <= reg_QA(31)&"000";
|
||||
ELSE
|
||||
Flags(3 downto 0) <= "0100";
|
||||
END IF;
|
||||
ELSIF exec(no_Flags)='0' THEN
|
||||
IF exec(opcADD)='1' THEN
|
||||
Flags(4) <= set_flags(0);
|
||||
ELSIF exec(opcROT)='1' AND rot_bits/="11" AND exec(rot_nop)='0' THEN
|
||||
Flags(4) <= rot_X;
|
||||
END IF;
|
||||
|
||||
IF (exec(opcADD) OR exec(opcCMP))='1' THEN
|
||||
Flags(3 downto 0) <= set_flags;
|
||||
ELSIF exec(opcDIVU)='1' AND DIV_Mode/=3 THEN
|
||||
IF V_Flag='1' THEN
|
||||
Flags(3 downto 0) <= "1010";
|
||||
ELSE
|
||||
Flags(3 downto 0) <= OP1IN(15)&flag_z(1)&"00";
|
||||
END IF;
|
||||
ELSIF exec(write_reminder)='1' AND MUL_Mode/=3 THEN -- z-flag MULU.l
|
||||
Flags(3) <= set_flags(3);
|
||||
Flags(2) <= set_flags(2) AND Flags(2);
|
||||
Flags(1) <= '0';
|
||||
Flags(0) <= '0';
|
||||
ELSIF exec(write_lowlong)='1' AND (MUL_Mode=1 OR MUL_Mode=2) THEN -- flag MULU.l
|
||||
Flags(3) <= set_flags(3);
|
||||
Flags(2) <= set_flags(2);
|
||||
Flags(1) <= set_mV_Flag; --V
|
||||
Flags(0) <= '0';
|
||||
ELSIF exec(opcOR)='1' OR exec(opcAND)='1' OR exec(opcEOR)='1' OR exec(opcMOVE)='1' OR exec(opcMOVEQ)='1' OR exec(opcSWAP)='1' OR exec(opcBF)='1' OR (exec(opcMULU)='1' AND MUL_Mode/=3) THEN
|
||||
Flags(1 downto 0) <= "00";
|
||||
Flags(3 downto 2) <= set_flags(3 downto 2);
|
||||
IF exec(opcBF)='1' THEN
|
||||
Flags(3) <= bf_NFlag;
|
||||
END IF;
|
||||
ELSIF exec(opcROT)='1' THEN
|
||||
Flags(3 downto 2) <= set_flags(3 downto 2);
|
||||
Flags(0) <= rot_C;
|
||||
IF rot_bits="00" AND ((set_flags(3) XOR rot_rot) OR asl_VFlag)='1' THEN --ASL/ASR
|
||||
Flags(1) <= '1';
|
||||
ELSE
|
||||
Flags(1) <= '0';
|
||||
END IF;
|
||||
ELSIF exec(opcBITS)='1' THEN
|
||||
Flags(2) <= NOT one_bit_in;
|
||||
ELSIF exec(opcCHK)='1' THEN
|
||||
IF exe_datatype="01" THEN --Word
|
||||
Flags(3) <= OP1out(15);
|
||||
ELSE
|
||||
Flags(3) <= OP1out(31);
|
||||
END IF;
|
||||
IF OP1out(15 downto 0)=X"0000" AND (exe_datatype="01" OR OP1out(31 downto 16)=X"0000") THEN
|
||||
Flags(2) <='1';
|
||||
ELSE
|
||||
Flags(2) <='0';
|
||||
END IF;
|
||||
Flags(1 downto 0) <= "00";
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
Flags(7 downto 5) <= "000";
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
---- MULU/MULS
|
||||
-------------------------------------------------------------------------------
|
||||
PROCESS (exe_opcode, OP2out, muls_msb, mulu_reg, FAsign, mulu_sign, reg_QA, faktorB, result_mulu, signedOP)
|
||||
BEGIN
|
||||
IF (signedOP='1' AND faktorB(31)='1') OR FAsign='1' THEN
|
||||
muls_msb <= mulu_reg(63);
|
||||
ELSE
|
||||
muls_msb <= '0';
|
||||
END IF;
|
||||
|
||||
IF signedOP='1' AND faktorB(31)='1' THEN
|
||||
mulu_sign <= '1';
|
||||
ELSE
|
||||
mulu_sign <= '0';
|
||||
END IF;
|
||||
|
||||
IF MUL_Mode=0 THEN -- 16 Bit
|
||||
result_mulu(63 downto 32) <= muls_msb&mulu_reg(63 downto 33);
|
||||
result_mulu(15 downto 0) <= 'X'&mulu_reg(15 downto 1);
|
||||
IF mulu_reg(0)='1' THEN
|
||||
IF FAsign='1' THEN
|
||||
result_mulu(63 downto 47) <= std_logic_vector(muls_msb & unsigned(mulu_reg(63 downto 48)) - unsigned(mulu_sign&faktorB(31 downto 16)) );
|
||||
ELSE
|
||||
result_mulu(63 downto 47) <= std_logic_vector(muls_msb & unsigned(mulu_reg(63 downto 48)) + unsigned(mulu_sign&faktorB(31 downto 16)) );
|
||||
END IF;
|
||||
END IF;
|
||||
ELSE -- 32 Bit
|
||||
result_mulu <= muls_msb&mulu_reg(63 downto 1);
|
||||
IF mulu_reg(0)='1' THEN
|
||||
IF FAsign='1' THEN
|
||||
result_mulu(63 downto 31) <= std_logic_vector(muls_msb & unsigned(mulu_reg(63 downto 32))-unsigned(mulu_sign&faktorB));
|
||||
ELSE
|
||||
result_mulu(63 downto 31) <= std_logic_vector(muls_msb & unsigned(mulu_reg(63 downto 32))+unsigned(mulu_sign&faktorB));
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
IF exe_opcode(15)='1' OR MUL_Mode=0 THEN
|
||||
faktorB(31 downto 16) <= OP2out(15 downto 0);
|
||||
faktorB(15 downto 0) <= (OTHERS=>'0');
|
||||
ELSE
|
||||
faktorB <= OP2out;
|
||||
END IF;
|
||||
IF (result_mulu(63 downto 32)=X"00000000" AND (signedOP='0' OR result_mulu(31)='0')) OR
|
||||
(result_mulu(63 downto 32)=X"FFFFFFFF" AND signedOP='1' AND result_mulu(31)='1') THEN
|
||||
set_mV_Flag <= '0';
|
||||
ELSE
|
||||
set_mV_Flag <= '1';
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (clk)
|
||||
BEGIN
|
||||
IF rising_edge(clk) THEN
|
||||
IF clkena_lw='1' THEN
|
||||
IF micro_state=mul1 THEN
|
||||
mulu_reg(63 downto 32) <= (OTHERS=>'0');
|
||||
IF divs='1' AND ((exe_opcode(15)='1' AND reg_QA(15)='1') OR (exe_opcode(15)='0' AND reg_QA(31)='1')) THEN --MULS Neg faktor
|
||||
FAsign <= '1';
|
||||
mulu_reg(31 downto 0) <= std_logic_vector(0-unsigned(reg_QA));
|
||||
ELSE
|
||||
FAsign <= '0';
|
||||
mulu_reg(31 downto 0) <= reg_QA;
|
||||
END IF;
|
||||
ELSIF exec(opcMULU)='0' THEN
|
||||
mulu_reg <= result_mulu;
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
-------------------------------------------------------------------------------
|
||||
---- DIVU/DIVS
|
||||
-------------------------------------------------------------------------------
|
||||
|
||||
PROCESS (execOPC, OP1out, OP2out, div_reg, div_neg, div_bit, div_sub, div_quot, OP1_sign, div_over, result_div, reg_QA, opcode, sndOPC, divs, exe_opcode, reg_QB,
|
||||
signedOP, nozero, div_qsign, OP2outext)
|
||||
BEGIN
|
||||
divs <= (opcode(15) AND opcode(8)) OR (NOT opcode(15) AND sndOPC(11));
|
||||
divisor(15 downto 0) <= (OTHERS=> '0');
|
||||
divisor(63 downto 32) <= (OTHERS=> divs AND reg_QA(31));
|
||||
IF exe_opcode(15)='1' OR DIV_Mode=0 THEN
|
||||
divisor(47 downto 16) <= reg_QA;
|
||||
ELSE
|
||||
divisor(31 downto 0) <= reg_QA;
|
||||
IF exe_opcode(14)='1' AND sndOPC(10)='1' THEN
|
||||
divisor(63 downto 32) <= reg_QB;
|
||||
END IF;
|
||||
END IF;
|
||||
IF signedOP='1' OR opcode(15)='0' THEN
|
||||
OP2outext <= OP2out(31 downto 16);
|
||||
ELSE
|
||||
OP2outext <= (OTHERS=> '0');
|
||||
END IF;
|
||||
IF signedOP='1' AND OP2out(31) ='1' THEN
|
||||
div_sub <= std_logic_vector(unsigned(div_reg(63 downto 31)) + unsigned('1'&OP2out(31 downto 0)));
|
||||
ELSE
|
||||
div_sub <= std_logic_vector(unsigned(div_reg(63 downto 31))-unsigned('0'&OP2outext(15 downto 0)&OP2out(15 downto 0)));
|
||||
END IF;
|
||||
IF DIV_Mode=0 THEN
|
||||
div_bit <= div_sub(16);
|
||||
ELSE
|
||||
div_bit <= div_sub(32);
|
||||
END IF;
|
||||
IF div_bit='1' THEN
|
||||
div_quot(63 downto 32) <= div_reg(62 downto 31);
|
||||
ELSE
|
||||
div_quot(63 downto 32) <= div_sub(31 downto 0);
|
||||
END IF;
|
||||
div_quot(31 downto 0) <= div_reg(30 downto 0)&NOT div_bit;
|
||||
|
||||
|
||||
IF ((nozero='1' AND signedOP='1' AND (OP2out(31) XOR OP1_sign XOR div_neg XOR div_qsign)='1' ) --Overflow DIVS
|
||||
OR (signedOP='0' AND div_over(32)='0')) AND DIV_Mode/=3 THEN --Overflow DIVU
|
||||
set_V_Flag <= '1';
|
||||
ELSE
|
||||
set_V_Flag <= '0';
|
||||
END IF;
|
||||
END PROCESS;
|
||||
|
||||
PROCESS (clk)
|
||||
BEGIN
|
||||
IF rising_edge(clk) THEN
|
||||
IF clkena_lw='1' THEN
|
||||
V_Flag <= set_V_Flag;
|
||||
signedOP <= divs;
|
||||
IF micro_state=div1 THEN
|
||||
nozero <= '0';
|
||||
IF divs='1' AND divisor(63)='1' THEN -- Neg divisor
|
||||
OP1_sign <= '1';
|
||||
div_reg <= std_logic_vector(0-unsigned(divisor));
|
||||
ELSE
|
||||
OP1_sign <= '0';
|
||||
div_reg <= divisor;
|
||||
END IF;
|
||||
ELSE
|
||||
div_reg <= div_quot;
|
||||
nozero <= NOT div_bit OR nozero;
|
||||
END IF;
|
||||
IF micro_state=div2 THEN
|
||||
div_qsign <= NOT div_bit;
|
||||
div_neg <= signedOP AND (OP2out(31) XOR OP1_sign);
|
||||
IF DIV_Mode=0 THEN
|
||||
div_over(32 downto 16) <= std_logic_vector(unsigned('0'&div_reg(47 downto 32))-unsigned('0'&OP2out(15 downto 0)));
|
||||
ELSE
|
||||
div_over <= std_logic_vector(unsigned('0'&div_reg(63 downto 32))-unsigned('0'&OP2out));
|
||||
END IF;
|
||||
END IF;
|
||||
IF exec(write_reminder)='0' THEN
|
||||
-- IF exec_DIVU='0' THEN
|
||||
IF div_neg='1' THEN
|
||||
result_div(31 downto 0) <= std_logic_vector(0-unsigned(div_quot(31 downto 0)));
|
||||
ELSE
|
||||
result_div(31 downto 0) <= div_quot(31 downto 0);
|
||||
END IF;
|
||||
|
||||
IF OP1_sign='1' THEN
|
||||
result_div(63 downto 32) <= std_logic_vector(0-unsigned(div_quot(63 downto 32)));
|
||||
ELSE
|
||||
result_div(63 downto 32) <= div_quot(63 downto 32);
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END IF;
|
||||
END PROCESS;
|
||||
END;
|
||||
165
tests/tg68k/orig/TG68K_Pack.vhd
Normal file
165
tests/tg68k/orig/TG68K_Pack.vhd
Normal file
@ -0,0 +1,165 @@
|
||||
------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------
|
||||
-- --
|
||||
-- Copyright (c) 2009-2013 Tobias Gubener --
|
||||
-- Subdesign fAMpIGA by TobiFlex --
|
||||
-- --
|
||||
-- This source file is free software: you can redistribute it and/or modify --
|
||||
-- it under the terms of the GNU General Public License as published --
|
||||
-- by the Free Software Foundation, either version 3 of the License, or --
|
||||
-- (at your option) any later version. --
|
||||
-- --
|
||||
-- This source file is distributed in the hope that it will be useful, --
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
|
||||
-- GNU General Public License for more details. --
|
||||
-- --
|
||||
-- You should have received a copy of the GNU General Public License --
|
||||
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
|
||||
-- --
|
||||
------------------------------------------------------------------------------
|
||||
------------------------------------------------------------------------------
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
|
||||
package TG68K_Pack is
|
||||
|
||||
type micro_states is (idle, nop, ld_nn, st_nn, ld_dAn1, ld_AnXn1, ld_AnXn2, st_dAn1, ld_AnXnbd1, ld_AnXnbd2, ld_AnXnbd3,
|
||||
ld_229_1, ld_229_2, ld_229_3, ld_229_4, st_229_1, st_229_2, st_229_3, st_229_4,
|
||||
st_AnXn1, st_AnXn2, bra1, bsr1, bsr2, nopnop, dbcc1, movem1, movem2, movem3,
|
||||
andi, op_AxAy, cmpm, link1, link2, unlink1, unlink2, int1, int2, int3, int4, rte1, rte2, rte3, trap0, trap1, trap2, trap3,
|
||||
trap4, trap5, trap6, movec1, movep1, movep2, movep3, movep4, movep5, rota1, bf1,
|
||||
mul1, mul2, mul_end1, mul_end2, div1, div2, div3, div4, div_end1, div_end2);
|
||||
|
||||
constant opcMOVE : integer := 0; --
|
||||
constant opcMOVEQ : integer := 1; --
|
||||
constant opcMOVESR : integer := 2; --
|
||||
constant opcADD : integer := 3; --
|
||||
constant opcADDQ : integer := 4; --
|
||||
constant opcOR : integer := 5; --
|
||||
constant opcAND : integer := 6; --
|
||||
constant opcEOR : integer := 7; --
|
||||
constant opcCMP : integer := 8; --
|
||||
constant opcROT : integer := 9; --
|
||||
constant opcCPMAW : integer := 10;
|
||||
constant opcEXT : integer := 11; --
|
||||
constant opcABCD : integer := 12; --
|
||||
constant opcSBCD : integer := 13; --
|
||||
constant opcBITS : integer := 14; --
|
||||
constant opcSWAP : integer := 15; --
|
||||
constant opcScc : integer := 16; --
|
||||
constant andiSR : integer := 17; --
|
||||
constant eoriSR : integer := 18; --
|
||||
constant oriSR : integer := 19; --
|
||||
constant opcMULU : integer := 20; --
|
||||
constant opcDIVU : integer := 21; --
|
||||
constant dispouter : integer := 22; --
|
||||
constant rot_nop : integer := 23; --
|
||||
constant ld_rot_cnt : integer := 24; --
|
||||
constant writePC_add : integer := 25; --
|
||||
constant ea_data_OP1 : integer := 26; --
|
||||
constant ea_data_OP2 : integer := 27; --
|
||||
constant use_XZFlag : integer := 28; --
|
||||
constant get_bfoffset : integer := 29; --
|
||||
constant save_memaddr : integer := 30; --
|
||||
constant opcCHK : integer := 31; --
|
||||
constant movec_rd : integer := 32; --
|
||||
constant movec_wr : integer := 33; --
|
||||
constant Regwrena : integer := 34; --
|
||||
constant update_FC : integer := 35; --
|
||||
constant linksp : integer := 36; --
|
||||
constant movepl : integer := 37; --
|
||||
constant update_ld : integer := 38; --
|
||||
constant OP1addr : integer := 39; --
|
||||
constant write_reg : integer := 40; --
|
||||
constant changeMode : integer := 41; --
|
||||
constant ea_build : integer := 42; --
|
||||
constant trap_chk : integer := 43; --
|
||||
constant store_ea_data : integer := 44; --
|
||||
constant addrlong : integer := 45; --
|
||||
constant postadd : integer := 46; --
|
||||
constant presub : integer := 47; --
|
||||
constant subidx : integer := 48; --
|
||||
constant no_Flags : integer := 49; --
|
||||
constant use_SP : integer := 50; --
|
||||
constant to_CCR : integer := 51; --
|
||||
constant to_SR : integer := 52; --
|
||||
constant OP2out_one : integer := 53; --
|
||||
constant OP1out_zero : integer := 54; --
|
||||
constant mem_addsub : integer := 55; --
|
||||
constant addsub : integer := 56; --
|
||||
constant directPC : integer := 57; --
|
||||
constant direct_delta : integer := 58; --
|
||||
constant directSR : integer := 59; --
|
||||
constant directCCR : integer := 60; --
|
||||
constant exg : integer := 61; --
|
||||
constant get_ea_now : integer := 62; --
|
||||
constant ea_to_pc : integer := 63; --
|
||||
constant hold_dwr : integer := 64; --
|
||||
constant to_USP : integer := 65; --
|
||||
constant from_USP : integer := 66; --
|
||||
constant write_lowlong : integer := 67; --
|
||||
constant write_reminder : integer := 68; --
|
||||
constant movem_action : integer := 69; --
|
||||
constant briefext : integer := 70; --
|
||||
constant get_2ndOPC : integer := 71; --
|
||||
constant mem_byte : integer := 72; --
|
||||
constant longaktion : integer := 73; --
|
||||
constant opcRESET : integer := 74; --
|
||||
constant opcBF : integer := 75; --
|
||||
constant opcBFwb : integer := 76; --
|
||||
constant s2nd_hbits : integer := 77; --
|
||||
-- constant : integer := 75; --
|
||||
-- constant : integer := 76; --
|
||||
-- constant : integer := 7; --
|
||||
-- constant : integer := 7; --
|
||||
-- constant : integer := 7; --
|
||||
|
||||
constant lastOpcBit : integer := 77;
|
||||
|
||||
component TG68K_ALU
|
||||
generic(
|
||||
MUL_Mode : integer := 0; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
|
||||
DIV_Mode : integer := 0 --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
|
||||
);
|
||||
port(
|
||||
clk : in std_logic;
|
||||
Reset : in std_logic;
|
||||
clkena_lw : in std_logic:='1';
|
||||
execOPC : in bit;
|
||||
exe_condition : in std_logic;
|
||||
exec_tas : in std_logic;
|
||||
long_start : in bit;
|
||||
movem_presub : in bit;
|
||||
set_stop : in bit;
|
||||
Z_error : in bit;
|
||||
rot_bits : in std_logic_vector(1 downto 0);
|
||||
exec : in bit_vector(lastOpcBit downto 0);
|
||||
OP1out : in std_logic_vector(31 downto 0);
|
||||
OP2out : in std_logic_vector(31 downto 0);
|
||||
reg_QA : in std_logic_vector(31 downto 0);
|
||||
reg_QB : in std_logic_vector(31 downto 0);
|
||||
opcode : in std_logic_vector(15 downto 0);
|
||||
datatype : in std_logic_vector(1 downto 0);
|
||||
exe_opcode : in std_logic_vector(15 downto 0);
|
||||
exe_datatype : in std_logic_vector(1 downto 0);
|
||||
sndOPC : in std_logic_vector(15 downto 0);
|
||||
last_data_read : in std_logic_vector(15 downto 0);
|
||||
data_read : in std_logic_vector(15 downto 0);
|
||||
FlagsSR : in std_logic_vector(7 downto 0);
|
||||
micro_state : in micro_states;
|
||||
bf_ext_in : in std_logic_vector(7 downto 0);
|
||||
bf_ext_out : out std_logic_vector(7 downto 0);
|
||||
bf_shift : in std_logic_vector(5 downto 0);
|
||||
bf_width : in std_logic_vector(5 downto 0);
|
||||
bf_loffset : in std_logic_vector(4 downto 0);
|
||||
|
||||
set_V_Flag : buffer bit;
|
||||
Flags : buffer std_logic_vector(7 downto 0);
|
||||
c_out : buffer std_logic_vector(2 downto 0);
|
||||
addsub_q : buffer std_logic_vector(31 downto 0);
|
||||
ALUout : out std_logic_vector(31 downto 0)
|
||||
);
|
||||
end component;
|
||||
|
||||
end;
|
||||
3232
tests/tg68k/orig/TG68KdotC_Kernel.vhd
Normal file
3232
tests/tg68k/orig/TG68KdotC_Kernel.vhd
Normal file
File diff suppressed because it is too large
Load Diff
35
tests/tg68k/testcode.s
Normal file
35
tests/tg68k/testcode.s
Normal file
@ -0,0 +1,35 @@
|
||||
org $fc0000 ;
|
||||
|
||||
start:
|
||||
; jsr sub
|
||||
move #$a700,sr ; Enter trace mode
|
||||
; nop ;
|
||||
lsr #5,d0
|
||||
|
||||
; move.l #$3237,d0
|
||||
; pack d0,d5,#$0123 ; d5 = $3a
|
||||
; unpk d5,d6,#$4040 ; d6 = $434a
|
||||
; move.l #testdata1,a0
|
||||
; move.l #testdata2,a1
|
||||
; pack -(a0),-(a1),#$1122
|
||||
; pack -(a0),-(a1),#$f0f0
|
||||
; unpk -(a0),-(a1),#$1122
|
||||
; unpk -(a0),-(a1),#$f0f0
|
||||
loop: move d0,d0
|
||||
bra.s loop
|
||||
|
||||
sub: rts
|
||||
|
||||
dc.l 0,0,0,0
|
||||
|
||||
dc.l $12345678
|
||||
testdata1:
|
||||
dc.l $aaaaaaaa
|
||||
|
||||
dc.l $c0ffee12
|
||||
testdata2:
|
||||
dc.l $55555555
|
||||
|
||||
org $fc0100 ;
|
||||
trace: rte
|
||||
|
||||
44
tests/tg68k/testcode_defs_pack.vhd
Normal file
44
tests/tg68k/testcode_defs_pack.vhd
Normal file
@ -0,0 +1,44 @@
|
||||
--
|
||||
-- Example ROM definitions pack for type-independent srecord output
|
||||
-- Copyright (C) 2000 Hendrik De Vloed - hendrik.devloed@rug.ac.be
|
||||
-- Copyright (C) 2007 Peter Miller
|
||||
--
|
||||
-- This program is free software; you can redistribute it and/or modify
|
||||
-- it under the terms of the GNU General Public License as published by
|
||||
-- the Free Software Foundation; either version 3 of the License, or
|
||||
-- (at your option) any later version.
|
||||
--
|
||||
-- This program is distributed in the hope that it will be useful,
|
||||
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
-- GNU General Public License for more details.
|
||||
--
|
||||
-- You should have received a copy of the GNU General Public License
|
||||
-- along with this program. If not, see
|
||||
-- <http://www.gnu.org/licenses/>.
|
||||
--
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
package testcode_defs_pack is
|
||||
-- The basic type of the data word stored in the ROM. Define
|
||||
-- your ROM's width here.
|
||||
subtype testcode_rom_entry is std_logic_vector(15 downto 0);
|
||||
-- The type used to represent the ROM. Define your range
|
||||
-- here.
|
||||
type testcode_rom_array is array(0 to 511) of testcode_rom_entry;
|
||||
-- The "Don't Care" value used to fill unused parts of the ROM.
|
||||
constant testcode_dont_care : testcode_rom_entry := (others=>'-');
|
||||
-- The conversion function used to make srecord's output
|
||||
-- independent of the actual rom_entry type and # of bits.
|
||||
function testcode_entry(data:natural) return testcode_rom_entry;
|
||||
end package;
|
||||
|
||||
library IEEE;
|
||||
use IEEE.numeric_std.all;
|
||||
package body testcode_defs_pack is
|
||||
function testcode_entry(data:natural) return testcode_rom_entry is
|
||||
begin
|
||||
return std_logic_vector(to_unsigned(data,testcode_rom_entry'length));
|
||||
end testcode_entry;
|
||||
end package body;
|
||||
86
tests/tg68k/tg68k_tb.sav
Normal file
86
tests/tg68k/tg68k_tb.sav
Normal file
@ -0,0 +1,86 @@
|
||||
[*]
|
||||
[*] GTKWave Analyzer v3.3.58 (w)1999-2014 BSI
|
||||
[*] Wed Jun 3 09:28:41 2015
|
||||
[*]
|
||||
[dumpfile] "/home/tharbaum/tmp/mist/hdl/tests/tg68k/tg68k_tb.ghw"
|
||||
[dumpfile_mtime] "Wed Jun 3 09:27:59 2015"
|
||||
[dumpfile_size] 199850
|
||||
[savefile] "/home/tharbaum/tmp/mist/hdl/tests/tg68k/tg68k_tb.sav"
|
||||
[timestart] 1181500000
|
||||
[size] 1240 816
|
||||
[pos] 11 123
|
||||
*-27.000000 2190000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
|
||||
[treeopen] top.
|
||||
[treeopen] top.tg68k_tb.
|
||||
[treeopen] top.tg68k_tb.tg68k.
|
||||
[sst_width] 202
|
||||
[signals_width] 257
|
||||
[sst_expanded] 1
|
||||
[sst_vpaned_height] 434
|
||||
@28
|
||||
top.tg68k_tb.clk
|
||||
@22
|
||||
#{top.tg68k_tb.addr[31:0]} top.tg68k_tb.addr[31] top.tg68k_tb.addr[30] top.tg68k_tb.addr[29] top.tg68k_tb.addr[28] top.tg68k_tb.addr[27] top.tg68k_tb.addr[26] top.tg68k_tb.addr[25] top.tg68k_tb.addr[24] top.tg68k_tb.addr[23] top.tg68k_tb.addr[22] top.tg68k_tb.addr[21] top.tg68k_tb.addr[20] top.tg68k_tb.addr[19] top.tg68k_tb.addr[18] top.tg68k_tb.addr[17] top.tg68k_tb.addr[16] top.tg68k_tb.addr[15] top.tg68k_tb.addr[14] top.tg68k_tb.addr[13] top.tg68k_tb.addr[12] top.tg68k_tb.addr[11] top.tg68k_tb.addr[10] top.tg68k_tb.addr[9] top.tg68k_tb.addr[8] top.tg68k_tb.addr[7] top.tg68k_tb.addr[6] top.tg68k_tb.addr[5] top.tg68k_tb.addr[4] top.tg68k_tb.addr[3] top.tg68k_tb.addr[2] top.tg68k_tb.addr[1] top.tg68k_tb.addr[0]
|
||||
@28
|
||||
#{top.tg68k_tb.tg68k.busstate[1:0]} top.tg68k_tb.tg68k.busstate[1] top.tg68k_tb.tg68k.busstate[0]
|
||||
@22
|
||||
#{top.tg68k_tb.din[15:0]} top.tg68k_tb.din[15] top.tg68k_tb.din[14] top.tg68k_tb.din[13] top.tg68k_tb.din[12] top.tg68k_tb.din[11] top.tg68k_tb.din[10] top.tg68k_tb.din[9] top.tg68k_tb.din[8] top.tg68k_tb.din[7] top.tg68k_tb.din[6] top.tg68k_tb.din[5] top.tg68k_tb.din[4] top.tg68k_tb.din[3] top.tg68k_tb.din[2] top.tg68k_tb.din[1] top.tg68k_tb.din[0]
|
||||
#{top.tg68k_tb.tg68k.data_write[15:0]} top.tg68k_tb.tg68k.data_write[15] top.tg68k_tb.tg68k.data_write[14] top.tg68k_tb.tg68k.data_write[13] top.tg68k_tb.tg68k.data_write[12] top.tg68k_tb.tg68k.data_write[11] top.tg68k_tb.tg68k.data_write[10] top.tg68k_tb.tg68k.data_write[9] top.tg68k_tb.tg68k.data_write[8] top.tg68k_tb.tg68k.data_write[7] top.tg68k_tb.tg68k.data_write[6] top.tg68k_tb.tg68k.data_write[5] top.tg68k_tb.tg68k.data_write[4] top.tg68k_tb.tg68k.data_write[3] top.tg68k_tb.tg68k.data_write[2] top.tg68k_tb.tg68k.data_write[1] top.tg68k_tb.tg68k.data_write[0]
|
||||
#{top.tg68k_tb.tg68k.exe_opcode[15:0]} top.tg68k_tb.tg68k.exe_opcode[15] top.tg68k_tb.tg68k.exe_opcode[14] top.tg68k_tb.tg68k.exe_opcode[13] top.tg68k_tb.tg68k.exe_opcode[12] top.tg68k_tb.tg68k.exe_opcode[11] top.tg68k_tb.tg68k.exe_opcode[10] top.tg68k_tb.tg68k.exe_opcode[9] top.tg68k_tb.tg68k.exe_opcode[8] top.tg68k_tb.tg68k.exe_opcode[7] top.tg68k_tb.tg68k.exe_opcode[6] top.tg68k_tb.tg68k.exe_opcode[5] top.tg68k_tb.tg68k.exe_opcode[4] top.tg68k_tb.tg68k.exe_opcode[3] top.tg68k_tb.tg68k.exe_opcode[2] top.tg68k_tb.tg68k.exe_opcode[1] top.tg68k_tb.tg68k.exe_opcode[0]
|
||||
@28
|
||||
top.tg68k_tb.tg68k.rdindex_a
|
||||
@22
|
||||
#{top.tg68k_tb.tg68k.reg_qa[31:0]} top.tg68k_tb.tg68k.reg_qa[31] top.tg68k_tb.tg68k.reg_qa[30] top.tg68k_tb.tg68k.reg_qa[29] top.tg68k_tb.tg68k.reg_qa[28] top.tg68k_tb.tg68k.reg_qa[27] top.tg68k_tb.tg68k.reg_qa[26] top.tg68k_tb.tg68k.reg_qa[25] top.tg68k_tb.tg68k.reg_qa[24] top.tg68k_tb.tg68k.reg_qa[23] top.tg68k_tb.tg68k.reg_qa[22] top.tg68k_tb.tg68k.reg_qa[21] top.tg68k_tb.tg68k.reg_qa[20] top.tg68k_tb.tg68k.reg_qa[19] top.tg68k_tb.tg68k.reg_qa[18] top.tg68k_tb.tg68k.reg_qa[17] top.tg68k_tb.tg68k.reg_qa[16] top.tg68k_tb.tg68k.reg_qa[15] top.tg68k_tb.tg68k.reg_qa[14] top.tg68k_tb.tg68k.reg_qa[13] top.tg68k_tb.tg68k.reg_qa[12] top.tg68k_tb.tg68k.reg_qa[11] top.tg68k_tb.tg68k.reg_qa[10] top.tg68k_tb.tg68k.reg_qa[9] top.tg68k_tb.tg68k.reg_qa[8] top.tg68k_tb.tg68k.reg_qa[7] top.tg68k_tb.tg68k.reg_qa[6] top.tg68k_tb.tg68k.reg_qa[5] top.tg68k_tb.tg68k.reg_qa[4] top.tg68k_tb.tg68k.reg_qa[3] top.tg68k_tb.tg68k.reg_qa[2] top.tg68k_tb.tg68k.reg_qa[1] top.tg68k_tb.tg68k.reg_qa[0]
|
||||
@28
|
||||
top.tg68k_tb.tg68k.rdindex_b
|
||||
@22
|
||||
#{top.tg68k_tb.tg68k.reg_qb[31:0]} top.tg68k_tb.tg68k.reg_qb[31] top.tg68k_tb.tg68k.reg_qb[30] top.tg68k_tb.tg68k.reg_qb[29] top.tg68k_tb.tg68k.reg_qb[28] top.tg68k_tb.tg68k.reg_qb[27] top.tg68k_tb.tg68k.reg_qb[26] top.tg68k_tb.tg68k.reg_qb[25] top.tg68k_tb.tg68k.reg_qb[24] top.tg68k_tb.tg68k.reg_qb[23] top.tg68k_tb.tg68k.reg_qb[22] top.tg68k_tb.tg68k.reg_qb[21] top.tg68k_tb.tg68k.reg_qb[20] top.tg68k_tb.tg68k.reg_qb[19] top.tg68k_tb.tg68k.reg_qb[18] top.tg68k_tb.tg68k.reg_qb[17] top.tg68k_tb.tg68k.reg_qb[16] top.tg68k_tb.tg68k.reg_qb[15] top.tg68k_tb.tg68k.reg_qb[14] top.tg68k_tb.tg68k.reg_qb[13] top.tg68k_tb.tg68k.reg_qb[12] top.tg68k_tb.tg68k.reg_qb[11] top.tg68k_tb.tg68k.reg_qb[10] top.tg68k_tb.tg68k.reg_qb[9] top.tg68k_tb.tg68k.reg_qb[8] top.tg68k_tb.tg68k.reg_qb[7] top.tg68k_tb.tg68k.reg_qb[6] top.tg68k_tb.tg68k.reg_qb[5] top.tg68k_tb.tg68k.reg_qb[4] top.tg68k_tb.tg68k.reg_qb[3] top.tg68k_tb.tg68k.reg_qb[2] top.tg68k_tb.tg68k.reg_qb[1] top.tg68k_tb.tg68k.reg_qb[0]
|
||||
@28
|
||||
top.tg68k_tb.tg68k.bwrena
|
||||
@22
|
||||
#{top.tg68k_tb.tg68k.regfile[0][31:0]} top.tg68k_tb.tg68k.regfile[0][31] top.tg68k_tb.tg68k.regfile[0][30] top.tg68k_tb.tg68k.regfile[0][29] top.tg68k_tb.tg68k.regfile[0][28] top.tg68k_tb.tg68k.regfile[0][27] top.tg68k_tb.tg68k.regfile[0][26] top.tg68k_tb.tg68k.regfile[0][25] top.tg68k_tb.tg68k.regfile[0][24] top.tg68k_tb.tg68k.regfile[0][23] top.tg68k_tb.tg68k.regfile[0][22] top.tg68k_tb.tg68k.regfile[0][21] top.tg68k_tb.tg68k.regfile[0][20] top.tg68k_tb.tg68k.regfile[0][19] top.tg68k_tb.tg68k.regfile[0][18] top.tg68k_tb.tg68k.regfile[0][17] top.tg68k_tb.tg68k.regfile[0][16] top.tg68k_tb.tg68k.regfile[0][15] top.tg68k_tb.tg68k.regfile[0][14] top.tg68k_tb.tg68k.regfile[0][13] top.tg68k_tb.tg68k.regfile[0][12] top.tg68k_tb.tg68k.regfile[0][11] top.tg68k_tb.tg68k.regfile[0][10] top.tg68k_tb.tg68k.regfile[0][9] top.tg68k_tb.tg68k.regfile[0][8] top.tg68k_tb.tg68k.regfile[0][7] top.tg68k_tb.tg68k.regfile[0][6] top.tg68k_tb.tg68k.regfile[0][5] top.tg68k_tb.tg68k.regfile[0][4] top.tg68k_tb.tg68k.regfile[0][3] top.tg68k_tb.tg68k.regfile[0][2] top.tg68k_tb.tg68k.regfile[0][1] top.tg68k_tb.tg68k.regfile[0][0]
|
||||
#{top.tg68k_tb.tg68k.regfile[5][31:0]} top.tg68k_tb.tg68k.regfile[5][31] top.tg68k_tb.tg68k.regfile[5][30] top.tg68k_tb.tg68k.regfile[5][29] top.tg68k_tb.tg68k.regfile[5][28] top.tg68k_tb.tg68k.regfile[5][27] top.tg68k_tb.tg68k.regfile[5][26] top.tg68k_tb.tg68k.regfile[5][25] top.tg68k_tb.tg68k.regfile[5][24] top.tg68k_tb.tg68k.regfile[5][23] top.tg68k_tb.tg68k.regfile[5][22] top.tg68k_tb.tg68k.regfile[5][21] top.tg68k_tb.tg68k.regfile[5][20] top.tg68k_tb.tg68k.regfile[5][19] top.tg68k_tb.tg68k.regfile[5][18] top.tg68k_tb.tg68k.regfile[5][17] top.tg68k_tb.tg68k.regfile[5][16] top.tg68k_tb.tg68k.regfile[5][15] top.tg68k_tb.tg68k.regfile[5][14] top.tg68k_tb.tg68k.regfile[5][13] top.tg68k_tb.tg68k.regfile[5][12] top.tg68k_tb.tg68k.regfile[5][11] top.tg68k_tb.tg68k.regfile[5][10] top.tg68k_tb.tg68k.regfile[5][9] top.tg68k_tb.tg68k.regfile[5][8] top.tg68k_tb.tg68k.regfile[5][7] top.tg68k_tb.tg68k.regfile[5][6] top.tg68k_tb.tg68k.regfile[5][5] top.tg68k_tb.tg68k.regfile[5][4] top.tg68k_tb.tg68k.regfile[5][3] top.tg68k_tb.tg68k.regfile[5][2] top.tg68k_tb.tg68k.regfile[5][1] top.tg68k_tb.tg68k.regfile[5][0]
|
||||
#{top.tg68k_tb.tg68k.regfile[6][31:0]} top.tg68k_tb.tg68k.regfile[6][31] top.tg68k_tb.tg68k.regfile[6][30] top.tg68k_tb.tg68k.regfile[6][29] top.tg68k_tb.tg68k.regfile[6][28] top.tg68k_tb.tg68k.regfile[6][27] top.tg68k_tb.tg68k.regfile[6][26] top.tg68k_tb.tg68k.regfile[6][25] top.tg68k_tb.tg68k.regfile[6][24] top.tg68k_tb.tg68k.regfile[6][23] top.tg68k_tb.tg68k.regfile[6][22] top.tg68k_tb.tg68k.regfile[6][21] top.tg68k_tb.tg68k.regfile[6][20] top.tg68k_tb.tg68k.regfile[6][19] top.tg68k_tb.tg68k.regfile[6][18] top.tg68k_tb.tg68k.regfile[6][17] top.tg68k_tb.tg68k.regfile[6][16] top.tg68k_tb.tg68k.regfile[6][15] top.tg68k_tb.tg68k.regfile[6][14] top.tg68k_tb.tg68k.regfile[6][13] top.tg68k_tb.tg68k.regfile[6][12] top.tg68k_tb.tg68k.regfile[6][11] top.tg68k_tb.tg68k.regfile[6][10] top.tg68k_tb.tg68k.regfile[6][9] top.tg68k_tb.tg68k.regfile[6][8] top.tg68k_tb.tg68k.regfile[6][7] top.tg68k_tb.tg68k.regfile[6][6] top.tg68k_tb.tg68k.regfile[6][5] top.tg68k_tb.tg68k.regfile[6][4] top.tg68k_tb.tg68k.regfile[6][3] top.tg68k_tb.tg68k.regfile[6][2] top.tg68k_tb.tg68k.regfile[6][1] top.tg68k_tb.tg68k.regfile[6][0]
|
||||
#{top.tg68k_tb.tg68k.alu.aluout[31:0]} top.tg68k_tb.tg68k.alu.aluout[31] top.tg68k_tb.tg68k.alu.aluout[30] top.tg68k_tb.tg68k.alu.aluout[29] top.tg68k_tb.tg68k.alu.aluout[28] top.tg68k_tb.tg68k.alu.aluout[27] top.tg68k_tb.tg68k.alu.aluout[26] top.tg68k_tb.tg68k.alu.aluout[25] top.tg68k_tb.tg68k.alu.aluout[24] top.tg68k_tb.tg68k.alu.aluout[23] top.tg68k_tb.tg68k.alu.aluout[22] top.tg68k_tb.tg68k.alu.aluout[21] top.tg68k_tb.tg68k.alu.aluout[20] top.tg68k_tb.tg68k.alu.aluout[19] top.tg68k_tb.tg68k.alu.aluout[18] top.tg68k_tb.tg68k.alu.aluout[17] top.tg68k_tb.tg68k.alu.aluout[16] top.tg68k_tb.tg68k.alu.aluout[15] top.tg68k_tb.tg68k.alu.aluout[14] top.tg68k_tb.tg68k.alu.aluout[13] top.tg68k_tb.tg68k.alu.aluout[12] top.tg68k_tb.tg68k.alu.aluout[11] top.tg68k_tb.tg68k.alu.aluout[10] top.tg68k_tb.tg68k.alu.aluout[9] top.tg68k_tb.tg68k.alu.aluout[8] top.tg68k_tb.tg68k.alu.aluout[7] top.tg68k_tb.tg68k.alu.aluout[6] top.tg68k_tb.tg68k.alu.aluout[5] top.tg68k_tb.tg68k.alu.aluout[4] top.tg68k_tb.tg68k.alu.aluout[3] top.tg68k_tb.tg68k.alu.aluout[2] top.tg68k_tb.tg68k.alu.aluout[1] top.tg68k_tb.tg68k.alu.aluout[0]
|
||||
#{top.tg68k_tb.tg68k.alu.op1out[31:0]} top.tg68k_tb.tg68k.alu.op1out[31] top.tg68k_tb.tg68k.alu.op1out[30] top.tg68k_tb.tg68k.alu.op1out[29] top.tg68k_tb.tg68k.alu.op1out[28] top.tg68k_tb.tg68k.alu.op1out[27] top.tg68k_tb.tg68k.alu.op1out[26] top.tg68k_tb.tg68k.alu.op1out[25] top.tg68k_tb.tg68k.alu.op1out[24] top.tg68k_tb.tg68k.alu.op1out[23] top.tg68k_tb.tg68k.alu.op1out[22] top.tg68k_tb.tg68k.alu.op1out[21] top.tg68k_tb.tg68k.alu.op1out[20] top.tg68k_tb.tg68k.alu.op1out[19] top.tg68k_tb.tg68k.alu.op1out[18] top.tg68k_tb.tg68k.alu.op1out[17] top.tg68k_tb.tg68k.alu.op1out[16] top.tg68k_tb.tg68k.alu.op1out[15] top.tg68k_tb.tg68k.alu.op1out[14] top.tg68k_tb.tg68k.alu.op1out[13] top.tg68k_tb.tg68k.alu.op1out[12] top.tg68k_tb.tg68k.alu.op1out[11] top.tg68k_tb.tg68k.alu.op1out[10] top.tg68k_tb.tg68k.alu.op1out[9] top.tg68k_tb.tg68k.alu.op1out[8] top.tg68k_tb.tg68k.alu.op1out[7] top.tg68k_tb.tg68k.alu.op1out[6] top.tg68k_tb.tg68k.alu.op1out[5] top.tg68k_tb.tg68k.alu.op1out[4] top.tg68k_tb.tg68k.alu.op1out[3] top.tg68k_tb.tg68k.alu.op1out[2] top.tg68k_tb.tg68k.alu.op1out[1] top.tg68k_tb.tg68k.alu.op1out[0]
|
||||
#{top.tg68k_tb.tg68k.alu.op2out[31:0]} top.tg68k_tb.tg68k.alu.op2out[31] top.tg68k_tb.tg68k.alu.op2out[30] top.tg68k_tb.tg68k.alu.op2out[29] top.tg68k_tb.tg68k.alu.op2out[28] top.tg68k_tb.tg68k.alu.op2out[27] top.tg68k_tb.tg68k.alu.op2out[26] top.tg68k_tb.tg68k.alu.op2out[25] top.tg68k_tb.tg68k.alu.op2out[24] top.tg68k_tb.tg68k.alu.op2out[23] top.tg68k_tb.tg68k.alu.op2out[22] top.tg68k_tb.tg68k.alu.op2out[21] top.tg68k_tb.tg68k.alu.op2out[20] top.tg68k_tb.tg68k.alu.op2out[19] top.tg68k_tb.tg68k.alu.op2out[18] top.tg68k_tb.tg68k.alu.op2out[17] top.tg68k_tb.tg68k.alu.op2out[16] top.tg68k_tb.tg68k.alu.op2out[15] top.tg68k_tb.tg68k.alu.op2out[14] top.tg68k_tb.tg68k.alu.op2out[13] top.tg68k_tb.tg68k.alu.op2out[12] top.tg68k_tb.tg68k.alu.op2out[11] top.tg68k_tb.tg68k.alu.op2out[10] top.tg68k_tb.tg68k.alu.op2out[9] top.tg68k_tb.tg68k.alu.op2out[8] top.tg68k_tb.tg68k.alu.op2out[7] top.tg68k_tb.tg68k.alu.op2out[6] top.tg68k_tb.tg68k.alu.op2out[5] top.tg68k_tb.tg68k.alu.op2out[4] top.tg68k_tb.tg68k.alu.op2out[3] top.tg68k_tb.tg68k.alu.op2out[2] top.tg68k_tb.tg68k.alu.op2out[1] top.tg68k_tb.tg68k.alu.op2out[0]
|
||||
#{top.tg68k_tb.tg68k.regfile[8][31:0]} top.tg68k_tb.tg68k.regfile[8][31] top.tg68k_tb.tg68k.regfile[8][30] top.tg68k_tb.tg68k.regfile[8][29] top.tg68k_tb.tg68k.regfile[8][28] top.tg68k_tb.tg68k.regfile[8][27] top.tg68k_tb.tg68k.regfile[8][26] top.tg68k_tb.tg68k.regfile[8][25] top.tg68k_tb.tg68k.regfile[8][24] top.tg68k_tb.tg68k.regfile[8][23] top.tg68k_tb.tg68k.regfile[8][22] top.tg68k_tb.tg68k.regfile[8][21] top.tg68k_tb.tg68k.regfile[8][20] top.tg68k_tb.tg68k.regfile[8][19] top.tg68k_tb.tg68k.regfile[8][18] top.tg68k_tb.tg68k.regfile[8][17] top.tg68k_tb.tg68k.regfile[8][16] top.tg68k_tb.tg68k.regfile[8][15] top.tg68k_tb.tg68k.regfile[8][14] top.tg68k_tb.tg68k.regfile[8][13] top.tg68k_tb.tg68k.regfile[8][12] top.tg68k_tb.tg68k.regfile[8][11] top.tg68k_tb.tg68k.regfile[8][10] top.tg68k_tb.tg68k.regfile[8][9] top.tg68k_tb.tg68k.regfile[8][8] top.tg68k_tb.tg68k.regfile[8][7] top.tg68k_tb.tg68k.regfile[8][6] top.tg68k_tb.tg68k.regfile[8][5] top.tg68k_tb.tg68k.regfile[8][4] top.tg68k_tb.tg68k.regfile[8][3] top.tg68k_tb.tg68k.regfile[8][2] top.tg68k_tb.tg68k.regfile[8][1] top.tg68k_tb.tg68k.regfile[8][0]
|
||||
#{top.tg68k_tb.tg68k.regfile[9][31:0]} top.tg68k_tb.tg68k.regfile[9][31] top.tg68k_tb.tg68k.regfile[9][30] top.tg68k_tb.tg68k.regfile[9][29] top.tg68k_tb.tg68k.regfile[9][28] top.tg68k_tb.tg68k.regfile[9][27] top.tg68k_tb.tg68k.regfile[9][26] top.tg68k_tb.tg68k.regfile[9][25] top.tg68k_tb.tg68k.regfile[9][24] top.tg68k_tb.tg68k.regfile[9][23] top.tg68k_tb.tg68k.regfile[9][22] top.tg68k_tb.tg68k.regfile[9][21] top.tg68k_tb.tg68k.regfile[9][20] top.tg68k_tb.tg68k.regfile[9][19] top.tg68k_tb.tg68k.regfile[9][18] top.tg68k_tb.tg68k.regfile[9][17] top.tg68k_tb.tg68k.regfile[9][16] top.tg68k_tb.tg68k.regfile[9][15] top.tg68k_tb.tg68k.regfile[9][14] top.tg68k_tb.tg68k.regfile[9][13] top.tg68k_tb.tg68k.regfile[9][12] top.tg68k_tb.tg68k.regfile[9][11] top.tg68k_tb.tg68k.regfile[9][10] top.tg68k_tb.tg68k.regfile[9][9] top.tg68k_tb.tg68k.regfile[9][8] top.tg68k_tb.tg68k.regfile[9][7] top.tg68k_tb.tg68k.regfile[9][6] top.tg68k_tb.tg68k.regfile[9][5] top.tg68k_tb.tg68k.regfile[9][4] top.tg68k_tb.tg68k.regfile[9][3] top.tg68k_tb.tg68k.regfile[9][2] top.tg68k_tb.tg68k.regfile[9][1] top.tg68k_tb.tg68k.regfile[9][0]
|
||||
@28
|
||||
top.tg68k_tb.tg68k.decodeopc
|
||||
top.tg68k_tb.tg68k.next_micro_state
|
||||
top.tg68k_tb.tg68k.micro_state
|
||||
@22
|
||||
#{top.tg68k_tb.tg68k.data_write_tmp[31:0]} top.tg68k_tb.tg68k.data_write_tmp[31] top.tg68k_tb.tg68k.data_write_tmp[30] top.tg68k_tb.tg68k.data_write_tmp[29] top.tg68k_tb.tg68k.data_write_tmp[28] top.tg68k_tb.tg68k.data_write_tmp[27] top.tg68k_tb.tg68k.data_write_tmp[26] top.tg68k_tb.tg68k.data_write_tmp[25] top.tg68k_tb.tg68k.data_write_tmp[24] top.tg68k_tb.tg68k.data_write_tmp[23] top.tg68k_tb.tg68k.data_write_tmp[22] top.tg68k_tb.tg68k.data_write_tmp[21] top.tg68k_tb.tg68k.data_write_tmp[20] top.tg68k_tb.tg68k.data_write_tmp[19] top.tg68k_tb.tg68k.data_write_tmp[18] top.tg68k_tb.tg68k.data_write_tmp[17] top.tg68k_tb.tg68k.data_write_tmp[16] top.tg68k_tb.tg68k.data_write_tmp[15] top.tg68k_tb.tg68k.data_write_tmp[14] top.tg68k_tb.tg68k.data_write_tmp[13] top.tg68k_tb.tg68k.data_write_tmp[12] top.tg68k_tb.tg68k.data_write_tmp[11] top.tg68k_tb.tg68k.data_write_tmp[10] top.tg68k_tb.tg68k.data_write_tmp[9] top.tg68k_tb.tg68k.data_write_tmp[8] top.tg68k_tb.tg68k.data_write_tmp[7] top.tg68k_tb.tg68k.data_write_tmp[6] top.tg68k_tb.tg68k.data_write_tmp[5] top.tg68k_tb.tg68k.data_write_tmp[4] top.tg68k_tb.tg68k.data_write_tmp[3] top.tg68k_tb.tg68k.data_write_tmp[2] top.tg68k_tb.tg68k.data_write_tmp[1] top.tg68k_tb.tg68k.data_write_tmp[0]
|
||||
#{top.tg68k_tb.tg68k.data_read[31:0]} top.tg68k_tb.tg68k.data_read[31] top.tg68k_tb.tg68k.data_read[30] top.tg68k_tb.tg68k.data_read[29] top.tg68k_tb.tg68k.data_read[28] top.tg68k_tb.tg68k.data_read[27] top.tg68k_tb.tg68k.data_read[26] top.tg68k_tb.tg68k.data_read[25] top.tg68k_tb.tg68k.data_read[24] top.tg68k_tb.tg68k.data_read[23] top.tg68k_tb.tg68k.data_read[22] top.tg68k_tb.tg68k.data_read[21] top.tg68k_tb.tg68k.data_read[20] top.tg68k_tb.tg68k.data_read[19] top.tg68k_tb.tg68k.data_read[18] top.tg68k_tb.tg68k.data_read[17] top.tg68k_tb.tg68k.data_read[16] top.tg68k_tb.tg68k.data_read[15] top.tg68k_tb.tg68k.data_read[14] top.tg68k_tb.tg68k.data_read[13] top.tg68k_tb.tg68k.data_read[12] top.tg68k_tb.tg68k.data_read[11] top.tg68k_tb.tg68k.data_read[10] top.tg68k_tb.tg68k.data_read[9] top.tg68k_tb.tg68k.data_read[8] top.tg68k_tb.tg68k.data_read[7] top.tg68k_tb.tg68k.data_read[6] top.tg68k_tb.tg68k.data_read[5] top.tg68k_tb.tg68k.data_read[4] top.tg68k_tb.tg68k.data_read[3] top.tg68k_tb.tg68k.data_read[2] top.tg68k_tb.tg68k.data_read[1] top.tg68k_tb.tg68k.data_read[0]
|
||||
#{top.tg68k_tb.tg68k.last_data_read[31:0]} top.tg68k_tb.tg68k.last_data_read[31] top.tg68k_tb.tg68k.last_data_read[30] top.tg68k_tb.tg68k.last_data_read[29] top.tg68k_tb.tg68k.last_data_read[28] top.tg68k_tb.tg68k.last_data_read[27] top.tg68k_tb.tg68k.last_data_read[26] top.tg68k_tb.tg68k.last_data_read[25] top.tg68k_tb.tg68k.last_data_read[24] top.tg68k_tb.tg68k.last_data_read[23] top.tg68k_tb.tg68k.last_data_read[22] top.tg68k_tb.tg68k.last_data_read[21] top.tg68k_tb.tg68k.last_data_read[20] top.tg68k_tb.tg68k.last_data_read[19] top.tg68k_tb.tg68k.last_data_read[18] top.tg68k_tb.tg68k.last_data_read[17] top.tg68k_tb.tg68k.last_data_read[16] top.tg68k_tb.tg68k.last_data_read[15] top.tg68k_tb.tg68k.last_data_read[14] top.tg68k_tb.tg68k.last_data_read[13] top.tg68k_tb.tg68k.last_data_read[12] top.tg68k_tb.tg68k.last_data_read[11] top.tg68k_tb.tg68k.last_data_read[10] top.tg68k_tb.tg68k.last_data_read[9] top.tg68k_tb.tg68k.last_data_read[8] top.tg68k_tb.tg68k.last_data_read[7] top.tg68k_tb.tg68k.last_data_read[6] top.tg68k_tb.tg68k.last_data_read[5] top.tg68k_tb.tg68k.last_data_read[4] top.tg68k_tb.tg68k.last_data_read[3] top.tg68k_tb.tg68k.last_data_read[2] top.tg68k_tb.tg68k.last_data_read[1] top.tg68k_tb.tg68k.last_data_read[0]
|
||||
@28
|
||||
#{top.tg68k_tb.tg68k.datatype[1:0]} top.tg68k_tb.tg68k.datatype[1] top.tg68k_tb.tg68k.datatype[0]
|
||||
@c00022
|
||||
#{top.tg68k_tb.tg68k.flagssr[7:0]} top.tg68k_tb.tg68k.flagssr[7] top.tg68k_tb.tg68k.flagssr[6] top.tg68k_tb.tg68k.flagssr[5] top.tg68k_tb.tg68k.flagssr[4] top.tg68k_tb.tg68k.flagssr[3] top.tg68k_tb.tg68k.flagssr[2] top.tg68k_tb.tg68k.flagssr[1] top.tg68k_tb.tg68k.flagssr[0]
|
||||
@28
|
||||
top.tg68k_tb.tg68k.flagssr[7]
|
||||
top.tg68k_tb.tg68k.flagssr[6]
|
||||
top.tg68k_tb.tg68k.flagssr[5]
|
||||
top.tg68k_tb.tg68k.flagssr[4]
|
||||
top.tg68k_tb.tg68k.flagssr[3]
|
||||
top.tg68k_tb.tg68k.flagssr[2]
|
||||
top.tg68k_tb.tg68k.flagssr[1]
|
||||
top.tg68k_tb.tg68k.flagssr[0]
|
||||
@1401200
|
||||
-group_end
|
||||
@c00023
|
||||
#{top.tg68k_tb.tg68k.flags[7:0]} top.tg68k_tb.tg68k.flags[7] top.tg68k_tb.tg68k.flags[6] top.tg68k_tb.tg68k.flags[5] top.tg68k_tb.tg68k.flags[4] top.tg68k_tb.tg68k.flags[3] top.tg68k_tb.tg68k.flags[2] top.tg68k_tb.tg68k.flags[1] top.tg68k_tb.tg68k.flags[0]
|
||||
@29
|
||||
top.tg68k_tb.tg68k.flags[7]
|
||||
top.tg68k_tb.tg68k.flags[6]
|
||||
top.tg68k_tb.tg68k.flags[5]
|
||||
top.tg68k_tb.tg68k.flags[4]
|
||||
top.tg68k_tb.tg68k.flags[3]
|
||||
top.tg68k_tb.tg68k.flags[2]
|
||||
top.tg68k_tb.tg68k.flags[1]
|
||||
top.tg68k_tb.tg68k.flags[0]
|
||||
@1401201
|
||||
-group_end
|
||||
[pattern_trace] 1
|
||||
[pattern_trace] 0
|
||||
129
tests/tg68k/tg68k_tb.vhd
Normal file
129
tests/tg68k/tg68k_tb.vhd
Normal file
@ -0,0 +1,129 @@
|
||||
-- https://raw.githubusercontent.com/rkrajnc/minimig-de1/master/bench/cpu_cache_sdram/cpu_cache_sdram_tb.v
|
||||
-- http://www.asic-world.com/vhdl/first1.html
|
||||
|
||||
library ieee;
|
||||
use ieee.std_logic_1164.all;
|
||||
use IEEE.numeric_std.all;
|
||||
use std.textio.all;
|
||||
use work.testcode_pack.all;
|
||||
|
||||
-- `timescale 1us/1ns
|
||||
|
||||
entity tg68k_tb is
|
||||
end;
|
||||
|
||||
architecture tg68k_tb of tg68k_tb is
|
||||
|
||||
-- include tg68k
|
||||
component TG68KdotC_Kernel
|
||||
generic(
|
||||
SR_Read : integer:= 2; --0=>user, 1=>privileged, 2=>switchable with CPU(0)
|
||||
VBR_Stackframe : integer:= 2; --0=>no, 1=>yes/extended, 2=>switchable with CPU(0)
|
||||
extAddr_Mode : integer:= 2; --0=>no, 1=>yes, 2=>switchable with CPU(1)
|
||||
MUL_Mode : integer := 2; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no MUL,
|
||||
DIV_Mode : integer := 2; --0=>16Bit, 1=>32Bit, 2=>switchable with CPU(1), 3=>no DIV,
|
||||
BitField : integer := 2 --0=>no, 1=>yes, 2=>switchable with CPU(1)
|
||||
);
|
||||
port (clk : in std_logic;
|
||||
nReset : in std_logic; --low active
|
||||
clkena_in : in std_logic;
|
||||
data_in : in std_logic_vector(15 downto 0);
|
||||
IPL : in std_logic_vector(2 downto 0):="111";
|
||||
IPL_autovector : in std_logic;
|
||||
berr : in std_logic; -- only 68000 sp dummy
|
||||
CPU : in std_logic_vector(1 downto 0);
|
||||
addr : buffer std_logic_vector(31 downto 0);
|
||||
data_write : out std_logic_vector(15 downto 0);
|
||||
nWr : out std_logic;
|
||||
nUDS, nLDS : out std_logic;
|
||||
busstate : out std_logic_vector(1 downto 0);
|
||||
nResetOut : out std_logic;
|
||||
FC : out std_logic_vector(2 downto 0);
|
||||
clr_berr : out std_logic;
|
||||
-- for debug
|
||||
db_OP1out : out std_logic_vector(31 downto 0);
|
||||
db_OP2out : out std_logic_vector(31 downto 0);
|
||||
skipFetch : out std_logic;
|
||||
regin : buffer std_logic_vector(31 downto 0)
|
||||
);
|
||||
end component ;
|
||||
|
||||
signal clk : std_logic := '0';
|
||||
signal reset_n : std_logic := '1';
|
||||
signal din : std_logic_vector(15 downto 0);
|
||||
signal dout : std_logic_vector(15 downto 0);
|
||||
signal addr : std_logic_vector(31 downto 0);
|
||||
signal busstate : std_logic_vector(1 downto 0);
|
||||
|
||||
type ram_t is array(0 to 255) of std_logic_vector(15 downto 0);
|
||||
signal ram : ram_t;
|
||||
|
||||
begin
|
||||
|
||||
-- wire up cpu
|
||||
tg68k : TG68KdotC_Kernel
|
||||
port map (
|
||||
clk => clk,
|
||||
nReset => reset_n,
|
||||
clkena_in => '1',
|
||||
data_in => din,
|
||||
data_write => dout,
|
||||
IPL => "111",
|
||||
IPL_autovector => '0',
|
||||
berr => '0',
|
||||
CPU => "11", -- 00=68000, 11=68020
|
||||
addr => addr,
|
||||
busstate => busstate
|
||||
);
|
||||
|
||||
-- generate a 32mhz clock
|
||||
clock : process
|
||||
begin
|
||||
wait for 30 ns; clk <= not clk;
|
||||
end process clock;
|
||||
|
||||
stimulus : process
|
||||
begin
|
||||
report "start";
|
||||
|
||||
reset_n <= '0';
|
||||
wait for 125 ns; reset_n <= '1';
|
||||
|
||||
assert false report "tg68k out of reset"
|
||||
severity note;
|
||||
|
||||
wait;
|
||||
end process stimulus;
|
||||
|
||||
memory : process (clk)
|
||||
variable c_str : line;
|
||||
begin
|
||||
if (clk = '0' and clk'event) then
|
||||
if(busstate = "11") then
|
||||
if(unsigned(addr) >= x"55aa0000" and unsigned(addr) < (x"55aa0000"+512)) then
|
||||
ram(to_integer((unsigned(addr) - x"55aa0000"))/2) <= dout;
|
||||
end if;
|
||||
elsif(busstate = "00" or busstate = "10") then
|
||||
if (unsigned(addr) < 256) then
|
||||
case addr is
|
||||
when x"00000000" => din <= x"55aa"; -- stack at 55aa0100
|
||||
when x"00000002" => din <= x"0100";
|
||||
when x"00000004" => din <= x"00fc"; -- tos rom base -> fc0000
|
||||
when x"00000006" => din <= x"0000";
|
||||
when x"00000024" => din <= x"00fc"; -- trace vector -> fc0100
|
||||
when x"00000026" => din <= x"0100";
|
||||
when others => din <= x"0000";
|
||||
end case;
|
||||
elsif(unsigned(addr) >= x"00fc0000" and unsigned(addr) < (x"00fc0000"+512)) then
|
||||
din <= testcode_rom(to_integer((unsigned(addr) - x"00fc0000"))/2);
|
||||
elsif(unsigned(addr) >= x"55aa0000" and unsigned(addr) < (x"55aa0000"+512)) then
|
||||
din <= ram(to_integer((unsigned(addr) - x"55aa0000"))/2);
|
||||
else
|
||||
din <= (others=>'-');
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process memory;
|
||||
|
||||
end tg68k_tb;
|
||||
|
||||
19
tests/tg68k/todo.txt
Normal file
19
tests/tg68k/todo.txt
Normal file
@ -0,0 +1,19 @@
|
||||
PACK Dx,Dy,#
|
||||
|
||||
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
|
||||
1 0 0 0 <Dy/Ay> 1 0 1 0 0 RM <Dx/Ax>
|
||||
|
||||
RM=0->Dx/y RM=1->-(Ax/y)
|
||||
|
||||
UNPK Dx,Dy,#
|
||||
|
||||
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
|
||||
1 0 0 0 <Dy/Ay> 1 1 0 0 0 RM <Dx/Ax>
|
||||
|
||||
trace
|
||||
|
||||
t0 (bit14): trace on change of flow.
|
||||
|
||||
all trace happens after the instruction!
|
||||
|
||||
nop is also a change of flow
|
||||
Loading…
x
Reference in New Issue
Block a user