diff --git a/cores/archie/fpga/mist/archimedes_mist_top.v b/cores/archie/fpga/mist/archimedes_mist_top.v index 1f389ea..56abe6a 100644 --- a/cores/archie/fpga/mist/archimedes_mist_top.v +++ b/cores/archie/fpga/mist/archimedes_mist_top.v @@ -84,7 +84,7 @@ wire core_hs, core_vs; wire [15:0] coreaud_l, coreaud_r; // data loading -wire downloading; +wire downloading, uploading; wire loader_active = downloading && (dio_index == 1 || dio_index == 2); wire [7:0] dio_index; wire loader_we /* synthesis keep */ ; @@ -92,7 +92,8 @@ reg loader_stb = 1'b0 /* synthesis keep */ ; reg rom_ready = 0; (*KEEP="TRUE"*)wire [3:0] loader_sel /* synthesis keep */ ; (*KEEP="TRUE"*)wire [23:0] loader_addr /* synthesis keep */ ; -(*KEEP="TRUE"*)wire [31:0] loader_data /* synthesis keep */ ; +(*KEEP="TRUE"*)wire [31:0] loader_dout /* synthesis keep */ ; +wire [7:0] loader_din; // user io @@ -408,7 +409,8 @@ DATA_IO ( .ide_data_rd ( ide_data_rd ), .ide_data_we ( ide_data_we ), - .downloading ( downloading ), + .downloading ( downloading ), + .uploading ( uploading ), .index ( dio_index ), // ram interface @@ -416,7 +418,8 @@ DATA_IO ( .wr ( loader_we ), .a ( loader_addr ), .sel ( loader_sel ), - .d ( loader_data ) + .dout ( loader_dout ), + .din ( loader_din ) ); wire core_ack_in /* synthesis keep */ ; @@ -568,8 +571,10 @@ i2cSlaveTop CMOS ( .sdaOut ( i2c_dout ), .scl ( i2c_clock ), .we ( downloading && dio_index == 3 && loader_we ), + .rd ( uploading && dio_index == 3), .addr ( loader_addr[7:0] ), - .data ( loader_data[7:0] ) + .din ( loader_dout[7:0] ), + .dout ( loader_din ) ); audio AUDIO ( @@ -603,7 +608,7 @@ assign ram_sel = loader_active ? loader_sel : core_sel_o; assign ram_address = loader_active ? {loader_addr[23:2],2'b00} : {core_address_out[23:2],2'b00}; assign ram_stb = loader_active ? loader_stb : core_stb_out; assign ram_cyc = loader_active ? loader_stb : core_stb_out; -assign ram_data_in = loader_active ? loader_data : core_data_out; +assign ram_data_in = loader_active ? loader_dout : core_data_out; assign core_ack_in = loader_active ? 1'b0 : ram_ack; endmodule // archimedes_mist_top diff --git a/cores/archie/fpga/mist/data_io.v b/cores/archie/fpga/mist/data_io.v index d1c651a..1dfee6d 100644 --- a/cores/archie/fpga/mist/data_io.v +++ b/cores/archie/fpga/mist/data_io.v @@ -5,7 +5,7 @@ // Providing ROM and IDE data up- and download via the MISTs // own arm7 cpu. // -// http://code.google.com/p/mist-board/ +// https://github.com/mist-devel/mist-board // // Copyright (c) 2014-2015 Till Harbaum // @@ -48,6 +48,7 @@ module data_io #(parameter ADDR_WIDTH=24, START_ADDR = 0) ( output reg ide_data_we, output reg downloading, // signal indicating an active download + output reg uploading, // signal indicating an active upload (CMOS RAM) output [ADDR_WIDTH-1:0] size, // number of bytes in input buffer output reg [7:0] index, // menu index @@ -56,14 +57,15 @@ module data_io #(parameter ADDR_WIDTH=24, START_ADDR = 0) ( output reg wr, output reg [ADDR_WIDTH-1:0] a, output [3:0] sel, - output [31:0] d + output [31:0] dout, + input [7:0] din ); (*KEEP="TRUE"*)assign sel = a[1:0] == 2'b00 ? 4'b0001 : a[1:0] == 2'b01 ? 4'b0010 : a[1:0] == 2'b10 ? 4'b0100 : 4'b1000; -assign d = {data,data,data,data}; +assign dout = {data,data,data,data}; assign size = addr - START_ADDR; // ********************************************************************************* @@ -81,9 +83,12 @@ reg [2:0] bit_cnt_sd; reg [ADDR_WIDTH-1:0] addr; -localparam UIO_FILE_TX = 8'h53; -localparam UIO_FILE_TX_DAT = 8'h54; -localparam UIO_FILE_INDEX = 8'h55; +localparam DIO_FILE_TX = 8'h53; +localparam DIO_FILE_TX_DAT = 8'h54; +localparam DIO_FILE_INDEX = 8'h55; +localparam DIO_FILE_INFO = 8'h56; +localparam DIO_FILE_RX = 8'h57; +localparam DIO_FILE_RX_DAT = 8'h58; localparam CMD_IDECMD = 8'h04; localparam CMD_IDEDAT = 8'h08; @@ -155,6 +160,8 @@ always@(negedge sck or posedge ss) begin CMD_IDE_DATA_RD: dout_r <= ide_data_i; + DIO_FILE_RX_DAT: dout_r <= din; + default: dout_r <= cmdcode; endcase @@ -290,7 +297,7 @@ always @(posedge clk) begin if (abyte_cnt > 4) ide_data_rd <= 1; // file transfer commands - UIO_FILE_TX: + DIO_FILE_TX: begin // prepare if(spi_byte_in) begin @@ -303,7 +310,7 @@ always @(posedge clk) begin end // transfer - UIO_FILE_TX_DAT: + DIO_FILE_TX_DAT: begin a <= addr; addr <= addr + 1'd1; @@ -312,7 +319,25 @@ always @(posedge clk) begin end // index - UIO_FILE_INDEX: index <= spi_byte_in; + DIO_FILE_INDEX: index <= spi_byte_in; + + // start/stop receive + DIO_FILE_RX: + begin + // prepare + if(spi_byte_in) begin + a <= START_ADDR; + uploading <= 1; + end else begin + uploading <= 0; + end + end + + DIO_FILE_RX_DAT: + begin + a <= a + 1'd1; + end + endcase; end end diff --git a/cores/archie/rtl/i2cslave/i2cSlave.v b/cores/archie/rtl/i2cslave/i2cSlave.v index 7e8c83a..65b1cb1 100644 --- a/cores/archie/rtl/i2cslave/i2cSlave.v +++ b/cores/archie/rtl/i2cslave/i2cSlave.v @@ -50,13 +50,17 @@ module i2cSlave ( input sdaIn, output sdaOut, input scl, - - // parallel write + + // parallel read/write input we, + input rd, input [7:0] addr, - input [7:0] data + input [7:0] din, + output [7:0] dout ); +assign dout = dataFromRegIF; + // local wires and regs reg sdaDeb; reg sclDeb; @@ -152,8 +156,8 @@ end registerInterface u_registerInterface( .clk(clk), - .addr(we ? addr : regAddr), - .dataIn(we ? data : dataToRegIF), + .addr((we | rd) ? addr : regAddr), + .dataIn(we ? din : dataToRegIF), .writeEn(writeEn | we), .dataOut(dataFromRegIF) ); diff --git a/cores/archie/rtl/i2cslave/i2cSlaveTop.v b/cores/archie/rtl/i2cslave/i2cSlaveTop.v index 1396a1c..1287cae 100644 --- a/cores/archie/rtl/i2cslave/i2cSlaveTop.v +++ b/cores/archie/rtl/i2cslave/i2cSlaveTop.v @@ -52,10 +52,12 @@ module i2cSlaveTop ( output sdaOut, input scl, - // parallel write + // parallel read/write input we, + input rd, input [7:0] addr, - input [7:0] data + input [7:0] din, + output [7:0] dout ); i2cSlave u_i2cSlave( @@ -64,9 +66,11 @@ i2cSlave u_i2cSlave( .sdaIn(sdaIn), .sdaOut(sdaOut), .scl(scl), + .rd(rd), .we(we), .addr(addr), - .data(data) + .din(din), + .dout(dout) ); endmodule