diff --git a/cores/mist/data_io.v b/cores/mist/data_io.v
index a3759cc..6ff5e72 100644
--- a/cores/mist/data_io.v
+++ b/cores/mist/data_io.v
@@ -16,8 +16,9 @@ module data_io (
 	output [4:0] dma_idx,
 	input [7:0] dma_data,
 	output reg dma_ack,
-	output reg dma_nak,
 
+	output reg br,
+	
 	// ram interface
 	output reg [2:0] state, // state bits required to drive the sdram host
 	output [22:0] addr,
@@ -39,7 +40,7 @@ reg writeD2;     // synchronized write delayed by one 8Mhz clock
 reg read;        // read request received via SPI
 reg readD;       // read synchonized to 8Mhz clock
 reg readD2;      // synchronized read delayed by one 8Mhz clock
-   
+	
 // during write the address needs to be decremented by one as the
 // address auto increment takes place at the beginning of each transfer
 assign addr = addrR[22:0] - ((cmd == 2)?23'b1:23'b0);
@@ -93,10 +94,8 @@ always@(posedge sck, posedge ss) begin
 		write <= 1'b0;
 		read <= 1'b0;
 		dma_ack <= 1'b0;
-		dma_nak <= 1'b0;
 	end else begin
 		dma_ack <= 1'b0;
-		dma_nak <= 1'b0;
 		sbuf <= { sbuf[13:0], sdi};
 
 		// 0:7 is command, 8:15 and 16:23 is payload bytes
@@ -116,9 +115,13 @@ always@(posedge sck, posedge ss) begin
 			if({sbuf[6:0], sdi } == 8'd6)
 				dma_ack <= 1'b1;
 
-			// send nak
+			// request bus
 			if({sbuf[6:0], sdi } == 8'd7)
-				dma_nak <= 1'b1;
+				br <= 1'b1;
+
+			// release bus
+			if({sbuf[6:0], sdi } == 8'd8)
+				br <= 1'b0;
 
 			// if we can see a read coming initiate sdram read transfer asap
 			if({sbuf[6:0], sdi } == 8'd3)
diff --git a/cores/mist/dma.v b/cores/mist/dma.v
index bc1204e..e6c7c7b 100644
--- a/cores/mist/dma.v
+++ b/cores/mist/dma.v
@@ -12,7 +12,6 @@ module dma (
 
 	// output to mfp
 	output irq,
-	output reg br,
 	
 	// input from system config
 	input fdc_wr_prot,
@@ -22,7 +21,6 @@ module dma (
 	input [4:0] dio_idx,
 	output reg [7:0] dio_data,
 	input dio_ack,
-	input dio_nak,
 	
 	// input from psg
 	input drv_side,
@@ -153,14 +151,12 @@ reg [7:0] acsi_cmd_parms [4:0];
 reg acsi_busy;
 reg acsi_irq;
 
-// acsi status register is read (clears interrupt)
-wire acsi_status_read = sel && rw && (mode[4:3] == 2'b01);
+// acsi status register is access (clears interrupt)
+wire acsi_status_read = sel && (addr == 3'h2) && (mode[4:3] == 2'b01);
 
 reg dio_ackD, dio_ackD2;
-reg dio_nakD, dio_nakD2;
 always @(posedge clk) begin
 	dio_ackD <= dio_ack;
-	dio_nakD <= dio_nak;
 end
 	
 always @(negedge clk) begin
@@ -179,17 +175,10 @@ always @(negedge clk) begin
 		acsi_cmd <= 5'd0;
 		acsi_irq <= 1'b0;
 		acsi_busy <= 1'b0;
-		br <= 1'b0;
    end else begin
-		// acknowledge comes from io controller
-		// rising edge on ack -> clear busy flag
-		dio_nakD2 <= dio_nakD;
-		if(dio_nakD && !dio_nakD2)
-			br <= 1'b0;        // release bus
 		
 		dio_ackD2 <= dio_ackD;
 		if(dio_ackD && !dio_ackD2) begin
-			br <= 1'b0;        // release bus
 			scnt <= 8'h00;     // all sectors transmitted
 		
 			// fdc_busy == 3 -> fdc waiting for io controller
@@ -211,7 +200,7 @@ always @(negedge clk) begin
 		if(fdc_status_read)
 			fdc_irq <= 1'b0;
 
-		// cpu is reading status register -> clear fdc irq
+		// cpu is reading status register -> clear acsi irq
 		if(acsi_status_read)
 			acsi_irq <= 1'b0;
 
@@ -265,13 +254,11 @@ always @(negedge clk) begin
 
 						// ------------- TYPE II commands -------------
 						if(din[7:5] == 3'b100) begin         // read sector
-							br <= 1'b1;         // request bus
 							fdc_busy <= 2'd3;
 						end
 							
 						if(din[7:5] == 3'b101)         // write sector
 							if(!fdc_wr_prot) begin
-							   br <= 1'b1;         // request bus
 								fdc_busy <= 2'd3;
 							end
 
@@ -320,7 +307,6 @@ always @(negedge clk) begin
 							if(acsi_byte_counter < 4)
 								acsi_irq <= 1'b1;
 							else begin
-								br <= 1'b1;         // request bus
 								acsi_busy <= 1'b1;  // request io cntroller
 							end
 						end
diff --git a/cores/mist/mist_top.v b/cores/mist/mist_top.v
index 69df83e..d0cfce8 100644
--- a/cores/mist/mist_top.v
+++ b/cores/mist/mist_top.v
@@ -114,11 +114,8 @@ end
 		
 // no tristate busses exist inside the FPGA. so bus request doesn't do
 // much more than halting the cpu by suppressing dtack
-wire br = dma_br && (tg68_cpustate[1:0] == 2'b00) ;   // dma is only other bus master (yet)
-wire dma_br;
-
-// dma_br may come at any time. Make sure the real br comes not before the end 
-// of the instruction
+wire br = data_io_br; //  && (tg68_cpustate[1:0] == 2'b00) ;   // dma is only other bus master (yet)
+wire data_io_br;
 
 // request interrupt ack from mfp for IPL == 6
 wire mfp_iack = cpu_cycle && cpu2iack && address_strobe && (tg68_adr[3:1] == 3'b110);
@@ -330,7 +327,7 @@ YM2149 ym2149 (
 	.CLK                	( sclk[1]  					)	// 2 MHz
 );
   
-wire dma_dio_ack, dma_dio_nak;
+wire dma_dio_ack;
 wire [4:0] dma_dio_idx;
 wire [7:0] dma_dio_data;
 
@@ -350,7 +347,6 @@ dma dma (
 	.dout     (dma_data_out),
 	
 	.irq      (dma_irq     ),
-	.br       (dma_br      ),
 
 	// system control interface
 	.fdc_wr_prot (wr_prot),
@@ -360,7 +356,6 @@ dma dma (
 	.dio_idx  (dma_dio_idx ),
 	.dio_data (dma_dio_data),
 	.dio_ack  (dma_dio_ack ),
-	.dio_nak  (dma_dio_nak ),
 
 	// floppy interface
 	.drv_sel  (floppy_sel  ),
@@ -714,11 +709,12 @@ data_io data_io (
 		.ss    		(SPI_SS2			),
 		.sdo			(data_io_sdo	),
 
+		.br         (data_io_br    ),
+		
 		// dma status interface
 		.dma_idx    (dma_dio_idx   ),
 		.dma_data   (dma_dio_data  ),
 		.dma_ack    (dma_dio_ack   ),
-		.dma_nak    (dma_dio_nak   ),
 
 		// ram interface
 		.state 	 	(host_state		),