From 7122e993fc996ebc15ac39b1b451c91d7197255b Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi Date: Fri, 18 Oct 2019 19:54:49 +0200 Subject: [PATCH] Archie: reduce clock to 40MHz --- cores/archie/fpga/mist/clockgen.v | 38 +++++++++++++++---------------- cores/archie/rtl/archimedes_top.v | 2 +- cores/archie/rtl/ioc.v | 4 ++-- 3 files changed, 22 insertions(+), 22 deletions(-) diff --git a/cores/archie/fpga/mist/clockgen.v b/cores/archie/fpga/mist/clockgen.v index 9bf424b..4e80651 100644 --- a/cores/archie/fpga/mist/clockgen.v +++ b/cores/archie/fpga/mist/clockgen.v @@ -14,7 +14,7 @@ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 13.1.4 Build 182 03/12/2014 SJ Web Edition +// 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition // ************************************************************ @@ -111,17 +111,17 @@ module clockgen ( .vcounderrange ()); defparam altpll_component.bandwidth_type = "AUTO", - altpll_component.clk0_divide_by = 9, + altpll_component.clk0_divide_by = 27, altpll_component.clk0_duty_cycle = 50, - altpll_component.clk0_multiply_by = 14, + altpll_component.clk0_multiply_by = 40, altpll_component.clk0_phase_shift = "0", - altpll_component.clk1_divide_by = 3, + altpll_component.clk1_divide_by = 9, altpll_component.clk1_duty_cycle = 50, - altpll_component.clk1_multiply_by = 14, + altpll_component.clk1_multiply_by = 40, altpll_component.clk1_phase_shift = "0", - altpll_component.clk3_divide_by = 3, + altpll_component.clk3_divide_by = 9, altpll_component.clk3_duty_cycle = 50, - altpll_component.clk3_multiply_by = 14, + altpll_component.clk3_multiply_by = 40, altpll_component.clk3_phase_shift = "-1845", altpll_component.compensate_clock = "CLK0", altpll_component.inclk0_input_frequency = 37037, @@ -202,9 +202,9 @@ endmodule // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "42.000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "126.000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "126.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "40.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "120.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "120.000000" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -235,9 +235,9 @@ endmodule // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" // Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "42.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "126.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "126.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "40.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "120.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "120.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1" @@ -290,17 +290,17 @@ endmodule // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" -// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "14" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "40" // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9" // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "14" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "40" // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "3" +// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "9" // Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "14" +// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "40" // Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "-1845" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" diff --git a/cores/archie/rtl/archimedes_top.v b/cores/archie/rtl/archimedes_top.v index d16a653..f2173ff 100644 --- a/cores/archie/rtl/archimedes_top.v +++ b/cores/archie/rtl/archimedes_top.v @@ -319,7 +319,7 @@ wire floppy_reset; wire fdc_sel = cpu_stb & cpu_cyc & floppy_en; -fdc1772 #(.CLK(42000000)) FDC1772 ( +fdc1772 #(.CLK(40000000)) FDC1772 ( .clkcpu ( CLKCPU_I ), .clk8m_en ( ioc_clk8m_en ), diff --git a/cores/archie/rtl/ioc.v b/cores/archie/rtl/ioc.v index 33d01c0..322b597 100644 --- a/cores/archie/rtl/ioc.v +++ b/cores/archie/rtl/ioc.v @@ -249,9 +249,9 @@ always @(posedge clkcpu) begin end - // increment the clock counter. 42 MHz clkcpu assumed. + // increment the clock counter. 40 MHz clkcpu assumed. clken_counter <= clken_counter + 1'd1; - if (clken_counter == 20) clken_counter <= 0; + if (clken_counter == 19) clken_counter <= 0; if (write_request & ctrl_selected) begin