diff --git a/cores/c16/c1530.vhd b/cores/c16/c1530.vhd new file mode 100644 index 0000000..fb2c897 --- /dev/null +++ b/cores/c16/c1530.vhd @@ -0,0 +1,237 @@ +--------------------------------------------------------------------------------- +-- Commodore 1530 to SD card host (read only) by Dar (darfpga@aol.fr) 25-Mars-2019 +-- http://darfpga.blogspot.fr +-- also darfpga on sourceforge +-- +-- tap/wav player +-- Converted to 8 bit FIFO - Slingshot +--------------------------------------------------------------------------------- + +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_unsigned.all; +use ieee.numeric_std.all; + +entity c1530 is +port( + clk32 : in std_logic; + restart_tape : in std_logic; -- keep to 1 to long enough to clear fifo + -- reset tap header bytes skip counter + + wav_mode : in std_logic; -- 1 for wav mode, 0 for tap mode + tap_version : in std_logic_vector(1 downto 0); -- tap file version (0-2) + + host_tap_in : in std_logic_vector(7 downto 0); -- 8bits fifo input + host_tap_wrreq : in std_logic; -- set to 1 for 1 clk32 to write 1 word + tap_fifo_wrfull : out std_logic; -- do not write when fifo tap_fifo_full = 1 + tap_fifo_error : out std_logic; -- fifo fall empty (unrecoverable error) + + osd_play_stop_toggle : in std_logic; -- PLAY/STOP toggle button from OSD + + cass_sense : out std_logic; -- 0 = PLAY/REW/FF/REC button is pressed + cass_read : buffer std_logic; -- tape read signal + cass_write : in std_logic; -- signal to write on tape (not used) + cass_motor : in std_logic; -- 0 = tape motor is powered + + ear_input : in std_logic -- tape input from EAR port +); +end c1530; + +architecture struct of c1530 is + +signal tap_player_tick_cnt : std_logic_vector( 5 downto 0); +signal wav_player_tick_cnt : std_logic_vector(11 downto 0); +signal tap_dword : std_logic_vector(31 downto 0); +signal wave_cnt : std_logic_vector(23 downto 0); +signal wave_len : std_logic_vector(23 downto 0); + +signal tap_fifo_do : std_logic_vector(7 downto 0); +signal tap_fifo_rdreq : std_logic; +signal tap_fifo_empty : std_logic; +signal get_24bits_len : std_logic; +signal start_bytes : std_logic_vector(7 downto 0); +signal skip_bytes : std_logic; +signal playing : std_logic; -- 1 = tap or wav file is playing + +signal osd_play_stop_toggleD : std_logic; -- for detecting change in the OSD toggle button +signal sense : std_logic; -- status of the PLAY/STOP tape button + +signal ear_inputD : std_logic; -- for detecting input from EAR port +signal ear_input_detected : std_logic; -- 1=input from EAR port was detected +signal ear_autostop_counter : std_logic_vector(28 downto 0); -- counter for stopping after a delay when ear is no longer detected + +constant autostop_time: std_logic_vector(28 downto 0) := std_logic_vector(to_unsigned(32000000 * 5, ear_autostop_counter'length)); -- about 5 seconds + +begin + +-- for wav mode use large depth fifo (eg 512 x 32bits) +-- for tap mode fifo may be smaller (eg 16 x 32bits) +tap_fifo_inst : entity work.tap_fifo +port map( + aclr => restart_tape, + data => host_tap_in, + clock => clk32, + rdreq => tap_fifo_rdreq, + wrreq => host_tap_wrreq, + q => tap_fifo_do, + empty => tap_fifo_empty, + full => tap_fifo_wrfull +); + +process(clk32, restart_tape) +begin + + if restart_tape = '1' then + + start_bytes <= X"00"; + skip_bytes <= '1'; + tap_player_tick_cnt <= (others => '0'); + wav_player_tick_cnt <= (others => '0'); + wave_len <= (others => '0'); + wave_cnt <= (others => '0'); + get_24bits_len <= '0'; + + tap_fifo_rdreq <='0'; + tap_fifo_error <='0'; -- run out of data + + sense <= '1'; -- STOP tape + + elsif rising_edge(clk32) then + + -- detect OSD PLAY/STOP button press + osd_play_stop_toggleD <= osd_play_stop_toggle; + if osd_play_stop_toggleD = '0' and osd_play_stop_toggle = '1' then + sense <= not sense; + end if; + + -- detect EAR input + ear_inputD <= ear_input; + if ear_inputD /= ear_input then + ear_input_detected <= '1'; + ear_autostop_counter <= autostop_time; + end if; + + -- EAR input + if ear_input_detected='1' then + sense <= '0'; -- automatically press PLAY + cass_read <= not ear_input; + + -- autostop + if ear_autostop_counter = 0 then + ear_input_detected <= '0'; + sense <= '1'; -- automatically press STOP + else + ear_autostop_counter <= ear_autostop_counter - "1"; + end if; + end if; + + playing <= (not cass_motor) and (not sense) and (not ear_input_detected); -- cass_motor and sense are low active + + if playing = '0' and ear_input_detected = '0' then + cass_read <= '1'; + end if; + + tap_fifo_rdreq <= '0'; + + if (playing = '1') and (wav_mode = '1') then + + -- Wav player required a large depth fifo to give chance + -- fifo not falling empty while host go reading next sd card sector + -- (fifo is read every ~22µs, host have to be faster than 11ms to read sd sector) + + wav_player_tick_cnt <= wav_player_tick_cnt + '1'; + + if wav_player_tick_cnt = x"2F0" then -- ~33MHz/44.1KHz + + wav_player_tick_cnt <= (others => '0'); + + -- check for empty fifo (unrecoverable error) + if tap_fifo_empty = '1' then + tap_fifo_error <= '1'; + else + tap_fifo_rdreq <= '1'; + end if; + + end if; + cass_read <= not tap_fifo_do(7); -- only use msb (wav data is either xFF or x00/x01) + + end if; -- play wav mode + + -- tap player + + if (playing = '1') and (wav_mode = '0') then + + tap_player_tick_cnt <= tap_player_tick_cnt + '1'; + +-- if ((tap_player_tick_cnt = "100000") and (skip_bytes = '0')) then -- divide by 33 + if ((tap_player_tick_cnt = "011111") and (skip_bytes = '0')) then -- divide by 32 + + -- square wave period (1/2 duty cycle not mandatory, only falling edge matter) + if tap_version(1) = '0' then + if wave_cnt > '0' & wave_len(10 downto 1) then + cass_read <= '1'; + else + cass_read <= '0'; + end if; + end if; + + tap_player_tick_cnt <= "000000"; + wave_cnt <= wave_cnt + 1; + + if wave_cnt >= wave_len then + wave_cnt <= (others => '0'); + if tap_version = 2 then + cass_read <= not cass_read; + end if; + if tap_fifo_empty = '1' then + tap_fifo_error <= '1'; + else + tap_fifo_rdreq <= '1'; + if tap_fifo_do = x"00" then + wave_len <= x"000100"; -- interpret data x00 for tap version 0 + get_24bits_len <= tap_version(0) or tap_version(1); + else + wave_len <= '0'&x"000" & tap_fifo_do & "000"; + end if; + end if; + end if; + end if; -- tap_player_tick_cnt = "100000" + + -- catch 24bits wave_len for data x00 in tap version 1,2 + if (get_24bits_len = '1' ) and (skip_bytes = '0') and (tap_player_tick_cnt(0) = '1') then + + if tap_player_tick_cnt = "000101" then + get_24bits_len <= '0'; + end if; + + if tap_fifo_empty = '1' then + tap_fifo_error <= '1'; + else + tap_fifo_rdreq <= '1'; + wave_len <= tap_fifo_do & wave_len(23 downto 8); + end if; + + if tap_version(1) = '0' then + cass_read <= '1'; + end if; + end if; + + -- skip tap header bytes + if (skip_bytes = '1' and tap_fifo_empty = '0') then + tap_fifo_rdreq <= '1'; + cass_read <= '1'; + if start_bytes < X"14" then + start_bytes <= start_bytes + X"01"; + else + skip_bytes <= '0'; + end if; + end if; + + end if; -- play tap + + end if; -- clk32 +end process; + +cass_sense <= sense; + +end struct; diff --git a/cores/c16/c16.v b/cores/c16/c16.v index 7410dd6..1bda274 100644 --- a/cores/c16/c16.v +++ b/cores/c16/c16.v @@ -63,6 +63,11 @@ module C16 #(parameter MODE_PAL = 1)( //input IEC_ATNIN, output IEC_RESET, + input CASS_READ, + output CASS_WRITE, + input CASS_SENSE, + output CASS_MOTOR, + output AUDIO_L, output AUDIO_R, @@ -238,7 +243,7 @@ always @(posedge CLK28) // reset tries to emulate the length of a real reset // assign VSYNC=1'b1; // set scart mode to RGB for TV assign c16_addr=(~mux)?c16_addrlatch:cpu_addr&ted_addr; // C16 address bus -assign c16_data=(mux)?c16_datalatch:cpu_data&ted_data&ram_data&kernal_data&basic_data&keyport_data; // C16 data bus +assign c16_data=(mux)?c16_datalatch:cpu_data&ted_data&ram_data&kernal_data&basic_data&keyport_data&cass_data; // C16 data bus always @(posedge CLK28) // addres and data bus latching emulates dynamic memory behaviour of these buses begin @@ -263,4 +268,10 @@ assign IEC_ATNOUT=port_out[2]; //assign ATN=IEC_ATNIN; assign IEC_RESET=sreset; +assign CASS_MOTOR = port_out[3]; +assign port_in[4] = CASS_READ; +wire cass_sel = cpu_addr[15:4] == 12'hFD1; +wire [7:0] cass_data = { 5'b11111, cass_sel ? CASS_SENSE : 1'b1, 2'b11 }; +assign CASS_WRITE = port_out[6]; + endmodule diff --git a/cores/c16/c16_mist.qsf b/cores/c16/c16_mist.qsf index f8f9a2d..31ba997 100644 --- a/cores/c16/c16_mist.qsf +++ b/cores/c16/c16_mist.qsf @@ -118,6 +118,7 @@ set_location_assignment PIN_66 -to SDRAM_nWE set_location_assignment PIN_59 -to SDRAM_nCS set_location_assignment PIN_33 -to SDRAM_CKE set_location_assignment PIN_43 -to SDRAM_CLK +set_location_assignment PIN_31 -to UART_RX # Classic Timing Assignments # ========================== @@ -338,6 +339,10 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SPI_DO set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CONF_DATA0 set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001 set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF +set_global_assignment -name ENABLE_DRC_SETTINGS OFF +set_location_assignment PLL_1 -to pll_c16|altpll_component|auto_generated|pll1 +set_global_assignment -name VHDL_FILE tap_fifo.vhd +set_global_assignment -name VHDL_FILE c1530.vhd set_global_assignment -name VHDL_FILE gen_ram.vhd set_global_assignment -name VERILOG_FILE data_io.v set_global_assignment -name VERILOG_FILE sdram.v @@ -371,7 +376,5 @@ set_global_assignment -name QIP_FILE pll_c16.qip set_global_assignment -name QIP_FILE rom_reconfig_pal.qip set_global_assignment -name QIP_FILE rom_reconfig_ntsc.qip set_global_assignment -name QIP_FILE pll_reconfig.qip -set_global_assignment -name ENABLE_DRC_SETTINGS ON set_global_assignment -name SIGNALTAP_FILE output_files/ioctl.stp -set_location_assignment PLL_1 -to pll_c16|altpll_component|auto_generated|pll1 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/cores/c16/c16_mist.v b/cores/c16/c16_mist.v index 2c19dc1..373347c 100644 --- a/cores/c16/c16_mist.v +++ b/cores/c16/c16_mist.v @@ -54,7 +54,9 @@ module c16_mist ( output VGA_VS, output [5:0] VGA_R, output [5:0] VGA_G, - output [5:0] VGA_B + output [5:0] VGA_B, + + input UART_RX ); // ------------------------------------------------------------------------- @@ -70,18 +72,29 @@ module c16_mist ( // it to control the menu on the OSD parameter CONF_STR = { "C16;PRGTAP;", - "S,D64,Mount Disk;", + "S,D64,Mount Disk;", "F,ROM,Load Kernal;", + "T6,Play/Stop tape;", + "O7,Tape sound,Off,On;", "O2,Scanlines,Off,On;", "O3,Joysticks,Normal,Swapped;", - "O4,Memory,64k,16k;", + "O4,Memory,64k,16k;", "T5,Reset;" }; -parameter CONF_STR_LEN = 11+17+18+20+28+18+9; +parameter CONF_STR_LEN = 11+17+18+18+21+20+28+18+9; localparam TAP_MEM_START = 22'h20000; +reg uart_rxD; +reg uart_rxD2; + +// UART_RX synchronizer +always @(posedge clk28) begin + uart_rxD <= UART_RX; + uart_rxD2 <= uart_rxD; +end + // the status register is controlled by the on screen display (OSD) wire [7:0] status; wire tv15khz; @@ -90,6 +103,8 @@ wire scanlines = status[2]; wire joystick_swap = status[3]; wire memory_16k = status[4]; wire osd_reset = status[5]; +wire tap_play = status[6]; +wire tap_sound = status[7]; wire [1:0] buttons; wire [7:0] js0, js1; @@ -118,21 +133,22 @@ wire c16_sdram_oe = !c16_cas && c16_rw; // ioctl_sdram_data // multiplex c16 and ioctl signals -wire [15:0] mux_sdram_addr = clkref ? c16_sdram_addr : ioctl_sdram_addr[15:0]; +wire [24:0] mux_sdram_addr = clkref ? c16_sdram_addr : (tap_sdram_oe ? tap_play_addr : ioctl_sdram_addr); wire [ 7:0] mux_sdram_data = clkref ? c16_sdram_data : ioctl_sdram_data; wire mux_sdram_wr = clkref ? c16_sdram_wr : ioctl_sdram_write; -wire mux_sdram_oe = clkref ? c16_sdram_oe : 0; +wire mux_sdram_oe = clkref ? c16_sdram_oe : tap_sdram_oe; wire [15:0] sdram_din = { mux_sdram_data, mux_sdram_data }; wire [14:0] sdram_addr_64k = mux_sdram_addr[15:1]; // 64k mapping wire [14:0] sdram_addr_16k = { 1'b0, mux_sdram_addr[13:7], 1'b0, mux_sdram_addr[6:1] }; // 16k -wire [24:0] sdram_addr = (clkref | (~clkref & prg_download)) ? { 10'h00, memory_16k?sdram_addr_16k:sdram_addr_64k } : ioctl_sdram_addr; +wire [24:0] sdram_addr = (clkref | (~clkref & prg_download)) ? + { 10'h00, memory_16k?sdram_addr_16k:sdram_addr_64k } : + (tap_sdram_oe ? tap_play_addr : ioctl_sdram_addr); wire sdram_wr = mux_sdram_wr; wire sdram_oe = mux_sdram_oe; wire [1:0] sdram_ds = { mux_sdram_addr[0], !mux_sdram_addr[0] }; -// only c16 reads from sdram wire [15:0] sdram_dout; wire [7:0] c16_din = zp_overwrite?zp_ovl_dout: (c16_a_low[0]?sdram_dout[15:8]:sdram_dout[7:0]); @@ -335,10 +351,10 @@ always @(posedge clk28) begin // registers are automatically adjusted at the end of the // download/injection // the registers to be set have been taken from the vice emulator - reg_2d <= ioctl_sdram_addr + 16'd1; - reg_2f <= ioctl_sdram_addr + 16'd1; - reg_31 <= ioctl_sdram_addr + 16'd1; - reg_9d <= ioctl_sdram_addr + 16'd1; + reg_2d <= ioctl_sdram_addr[15:0] + 16'd1; + reg_2f <= ioctl_sdram_addr[15:0] + 16'd1; + reg_31 <= ioctl_sdram_addr[15:0] + 16'd1; + reg_9d <= ioctl_sdram_addr[15:0] + 16'd1; end else if(zp_sel && !c16_rw) begin // cpu writes registers if(zp_2d_sel) reg_2d[ 7:0] <= c16_dout; @@ -401,7 +417,70 @@ always @(posedge clk28) begin end end -reg tap_version; +// --------------------------------------------------------------------------------- +// -------------------------------- TAP playback ----------------------------------- +// --------------------------------------------------------------------------------- + +reg [24:0] tap_play_addr; +reg [24:0] tap_last_addr; +reg [7:0] tap_data_in; +reg tap_reset; +reg tap_wrreq; +reg tap_wrfull; +reg [1:0] tap_version; +reg tap_sdram_oe; +wire cass_read; +wire cass_write; +wire cass_motor; +wire cass_sense; + +always @(posedge clk28) begin + reg clkref_D; + + if (reset) begin + tap_play_addr <= TAP_MEM_START; + tap_last_addr <= TAP_MEM_START; + tap_sdram_oe <= 0; + tap_reset <= 1; + end else begin + tap_reset <= 0; + if (tap_download) begin + tap_play_addr <= TAP_MEM_START; + tap_last_addr <= ioctl_sdram_addr; + tap_reset <= 1; + if (ioctl_sdram_addr == (TAP_MEM_START + 25'h0C) && ioctl_wr) begin + tap_version <= ioctl_data[1:0]; + end + end + clkref_D <= clkref; + tap_wrreq <= 0; + if (clkref_D && !clkref && !ioctl_downloading && tap_play_addr != tap_last_addr && !tap_wrfull) tap_sdram_oe <= 1; + if (clkref && !clkref_D && tap_sdram_oe) begin + tap_wrreq <= 1; + tap_data_in <= tap_play_addr[0] ? sdram_dout[15:8]:sdram_dout[7:0]; + tap_sdram_oe <= 0; + tap_play_addr <= tap_play_addr + 1'd1; + end + end +end + +c1530 c1530 +( + .clk32(clk28), + .restart_tape(tap_reset), + .wav_mode(0), + .tap_version(tap_version), + .host_tap_in(tap_data_in), + .host_tap_wrreq(tap_wrreq), + .tap_fifo_wrfull(tap_wrfull), + .tap_fifo_error(), + .cass_read(cass_read), + .cass_write(cass_write), + .cass_motor(cass_motor), + .cass_sense(cass_sense), + .osd_play_stop_toggle(tap_play), + .ear_input(uart_rxD2) +); // --------------------------------------------------------------------------------- // ------------------------------ the on screen display ---------------------------- @@ -526,6 +605,10 @@ always @(negedge clk28) begin { kernal_dl_wr, basic_dl_wr, c1541_dl_wr } <= 0; end +wire audio_l_out, audio_r_out; +assign AUDIO_L = audio_l_out | (tap_sound & ~cass_read); +assign AUDIO_R = audio_r_out | (tap_sound & ~cass_read); + // include the c16 itself C16 c16 ( .CLK28 ( clk28 ), @@ -563,8 +646,13 @@ C16 c16 ( .IEC_ATNOUT ( c16_iec_atn_o ), .IEC_RESET ( ), - .AUDIO_L ( AUDIO_L ), - .AUDIO_R ( AUDIO_R ), + .CASS_READ ( cass_read ), + .CASS_WRITE ( cass_write ), + .CASS_MOTOR ( cass_motor ), + .CASS_SENSE ( cass_sense ), + + .AUDIO_L ( audio_l_out ), + .AUDIO_R ( audio_r_out ), .PAL ( c16_pal ), @@ -722,7 +810,7 @@ end // --------------------------------------------------------------------------------- wire led_disk; -assign LED = !led_disk; +assign LED = !led_disk && cass_motor; wire c16_iec_atn_o; wire c16_iec_data_o; diff --git a/cores/c16/tap_fifo.vhd b/cores/c16/tap_fifo.vhd new file mode 100644 index 0000000..4ea7fe1 --- /dev/null +++ b/cores/c16/tap_fifo.vhd @@ -0,0 +1,190 @@ +-- megafunction wizard: %FIFO% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: scfifo + +-- ============================================================ +-- File Name: tap_fifo.vhd +-- Megafunction Name(s): +-- scfifo +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 13.1.4 Build 182 03/12/2014 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2014 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY tap_fifo IS + PORT + ( + aclr : IN STD_LOGIC ; + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rdreq : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + empty : OUT STD_LOGIC ; + full : OUT STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0) + ); +END tap_fifo; + + +ARCHITECTURE SYN OF tap_fifo IS + + SIGNAL sub_wire0 : STD_LOGIC ; + SIGNAL sub_wire1 : STD_LOGIC ; + SIGNAL sub_wire2 : STD_LOGIC_VECTOR (7 DOWNTO 0); + + + + COMPONENT scfifo + GENERIC ( + add_ram_output_register : STRING; + intended_device_family : STRING; + lpm_numwords : NATURAL; + lpm_showahead : STRING; + lpm_type : STRING; + lpm_width : NATURAL; + lpm_widthu : NATURAL; + overflow_checking : STRING; + underflow_checking : STRING; + use_eab : STRING + ); + PORT ( + aclr : IN STD_LOGIC ; + clock : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); + rdreq : IN STD_LOGIC ; + empty : OUT STD_LOGIC ; + full : OUT STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + wrreq : IN STD_LOGIC + ); + END COMPONENT; + +BEGIN + empty <= sub_wire0; + full <= sub_wire1; + q <= sub_wire2(7 DOWNTO 0); + + scfifo_component : scfifo + GENERIC MAP ( + add_ram_output_register => "OFF", + intended_device_family => "Cyclone III", + lpm_numwords => 64, + lpm_showahead => "OFF", + lpm_type => "scfifo", + lpm_width => 8, + lpm_widthu => 6, + overflow_checking => "ON", + underflow_checking => "ON", + use_eab => "ON" + ) + PORT MAP ( + aclr => aclr, + clock => clock, + data => data, + rdreq => rdreq, + wrreq => wrreq, + empty => sub_wire0, + full => sub_wire1, + q => sub_wire2 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "0" +-- Retrieval info: PRIVATE: Depth NUMERIC "64" +-- Retrieval info: PRIVATE: Empty NUMERIC "1" +-- Retrieval info: PRIVATE: Full NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: Optimize NUMERIC "0" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: UsedW NUMERIC "0" +-- Retrieval info: PRIVATE: Width NUMERIC "8" +-- Retrieval info: PRIVATE: dc_aclr NUMERIC "0" +-- Retrieval info: PRIVATE: diff_widths NUMERIC "0" +-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +-- Retrieval info: PRIVATE: output_width NUMERIC "8" +-- Retrieval info: PRIVATE: rsEmpty NUMERIC "1" +-- Retrieval info: PRIVATE: rsFull NUMERIC "0" +-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +-- Retrieval info: PRIVATE: sc_aclr NUMERIC "1" +-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: wsFull NUMERIC "1" +-- Retrieval info: PRIVATE: wsUsedW NUMERIC "0" +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "64" +-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8" +-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "6" +-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: USE_EAB STRING "ON" +-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL "aclr" +-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock" +-- Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]" +-- Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty" +-- Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full" +-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]" +-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq" +-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq" +-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0 +-- Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0 +-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +-- Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0 +-- Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0 +-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0 +-- Retrieval info: GEN_FILE: TYPE_NORMAL tap_fifo.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL tap_fifo.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL tap_fifo.cmp FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL tap_fifo.bsf FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL tap_fifo_inst.vhd FALSE +-- Retrieval info: LIB_FILE: altera_mf