diff --git a/cores/c64/rtl/c1541/c1541_sd.vhd b/cores/c64/rtl/c1541/c1541_sd.vhd
index 6f29f65..1fe44ae 100644
--- a/cores/c64/rtl/c1541/c1541_sd.vhd
+++ b/cores/c64/rtl/c1541/c1541_sd.vhd
@@ -110,6 +110,9 @@ signal track_modified   : std_logic;
 signal sector_offset    : std_logic;
 signal save_track_stage : std_logic_vector(3 downto 0);
 
+signal wps_flag : std_logic;
+signal change_timer : integer;
+
 signal dbg_sector : std_logic_vector(4 downto 0); 
 signal dbg_adr_fetch : std_logic_vector(15 downto 0); 
 
@@ -172,7 +175,7 @@ begin
     freq            => freq,     -- motor frequency
     sync_n          => sync_n,   -- reading SYNC bytes
     byte_n          => byte_n,   -- byte ready
-    wps_n           => not disk_readonly,      -- write-protect sense (0 = protected)
+    wps_n           => not wps_flag,      -- write-protect sense (0 = protected)
     tr00_sense_n    => '1',      -- track 0 sense (unused?)
     act             => act,      -- activity LED
 
@@ -266,7 +269,22 @@ port map
 --
 --	dbg_state => dbg_sd_state
 --);
-	
+
+wps_flag <= disk_readonly when change_timer = 0 else not disk_readonly;
+
+process (clk32,reset)
+begin
+	if reset = '1' then
+		change_timer <= 0;
+	elsif rising_edge(clk32) then
+		if disk_change = '1' then
+			change_timer <= 1000000;
+		elsif change_timer /= 0 then
+			change_timer <= change_timer - 1;
+		end if;
+	end if;
+end process;
+
 process (clk32)
 begin
 	if rising_edge(clk32) then