mirror of
https://github.com/mist-devel/mist-board.git
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STEroids fixed and accelerated
This commit is contained in:
harbaum
parent
707c606173
commit
7edbc00f3c
@ -26,10 +26,11 @@ module cache (
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input reset,
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input flush,
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input strobe,
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input [22:0] addr, // cpu word address
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input [1:0] ds, // upper (0) and lower (1) data strobe
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output reg [15:0] dout,
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output [15:0] dout,
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output hit,
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// interface to store entire cache lines when read from ram
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@ -64,7 +65,7 @@ localparam ALLZERO = 64'd0; // 2 ** BITS zero bits
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// L = cache line
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// W = 16 bit word select
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wire [21-BITS-1:0] tag = addr[22:2+BITS];
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reg [BITS-1:0] line;
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wire [BITS-1:0] line = addr[2+BITS-1:2];
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/* ------------------------------------------------------------------------------ */
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/* --------------------------------- cache memory ------------------------------- */
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@ -78,7 +79,7 @@ reg [31:24] data_latch_3 [ENTRIES-1:0];
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reg [23:16] data_latch_2 [ENTRIES-1:0];
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reg [15: 8] data_latch_1 [ENTRIES-1:0];
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reg [ 7: 0] data_latch_0 [ENTRIES-1:0];
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reg [21-BITS-1:0] tag_latch [ENTRIES-1:0];
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reg [ENTRIES-1:0] valid;
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@ -89,60 +90,72 @@ reg [21-BITS-1:0] current_tag;
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// assign hit = valid[line] && (tag_latch[line] == tag);
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assign hit = valid[line] && (current_tag == tag);
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reg [15:0] dout_latch_0;
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reg [15:0] dout_latch_1;
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reg [15:0] dout_latch_2;
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reg [15:0] dout_latch_3;
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// permanently output data according to current line
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// de-multiplex 64 bit data into word requested by cpu
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assign dout = (addr[1:0] == 0)?dout_latch_0:
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(addr[1:0] == 1)?dout_latch_1:
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(addr[1:0] == 2)?dout_latch_2:
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dout_latch_3;
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always @(posedge clk_128) begin
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dout <= (addr[1:0] == 2'd0)?{data_latch_1[line], data_latch_0[line]}:
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(addr[1:0] == 2'd1)?{data_latch_3[line], data_latch_2[line]}:
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(addr[1:0] == 2'd2)?{data_latch_5[line], data_latch_4[line]}:
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{data_latch_7[line], data_latch_6[line]};
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dout_latch_0 <= {data_latch_1[line], data_latch_0[line]};
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dout_latch_1 <= {data_latch_3[line], data_latch_2[line]};
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dout_latch_2 <= {data_latch_5[line], data_latch_4[line]};
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dout_latch_3 <= {data_latch_7[line], data_latch_6[line]};
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current_tag <= tag_latch[line];
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end
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always @(negedge clk_128)
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line <= addr[2+BITS-1:2];
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always @(posedge clk_128) begin
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if(reset || flush) begin
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valid <= ALLZERO;
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end else begin
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// store indicates that a whole cache line is to be stored
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if(store) begin
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data_latch_7[line] <= din64[63:56];
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data_latch_6[line] <= din64[55:48];
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data_latch_5[line] <= din64[47:40];
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data_latch_4[line] <= din64[39:32];
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data_latch_3[line] <= din64[31:24];
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data_latch_2[line] <= din64[23:16];
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data_latch_1[line] <= din64[15: 8];
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data_latch_0[line] <= din64[ 7: 0];
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// the store and update signals are valid in the last cycle only. The cpu runs
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// at 32MHz and is valid if t=14,15,0,1
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if(t==15) begin
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// store indicates that a whole cache line is to be stored
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if(store) begin
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data_latch_7[line] <= din64[63:56];
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data_latch_6[line] <= din64[55:48];
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data_latch_5[line] <= din64[47:40];
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data_latch_4[line] <= din64[39:32];
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data_latch_3[line] <= din64[31:24];
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data_latch_2[line] <= din64[23:16];
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data_latch_1[line] <= din64[15: 8];
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data_latch_0[line] <= din64[ 7: 0];
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tag_latch[line] <= tag;
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valid[line] <= 1'b1;
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end
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tag_latch[line] <= tag;
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valid[line] <= 1'b1;
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end
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// cpu (or other bus master!) writes to ram, so update cache contents if necessary
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else if(update && hit) begin
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// no need to care for "tag_latch" or "valid" as they simply stay the same
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// cpu (or other bus master!) writes to ram, so update cache contents if necessary
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else if(update && hit) begin
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// no need to care for "tag_latch" or "valid" as they simply stay the same
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if(addr[1:0] == 2'd0) begin
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if(ds[1]) data_latch_0[line] <= din16[7:0];
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if(ds[0]) data_latch_1[line] <= din16[15:8];
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end
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if(addr[1:0] == 2'd0) begin
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if(ds[1]) data_latch_0[line] <= din16[7:0];
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if(ds[0]) data_latch_1[line] <= din16[15:8];
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end
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if(addr[1:0] == 2'd1) begin
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if(ds[1]) data_latch_2[line] <= din16[7:0];
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if(ds[0]) data_latch_3[line] <= din16[15:8];
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end
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if(addr[1:0] == 2'd1) begin
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if(ds[1]) data_latch_2[line] <= din16[7:0];
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if(ds[0]) data_latch_3[line] <= din16[15:8];
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end
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if(addr[1:0] == 2'd2) begin
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if(ds[1]) data_latch_4[line] <= din16[7:0];
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if(ds[0]) data_latch_5[line] <= din16[15:8];
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end
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if(addr[1:0] == 2'd2) begin
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if(ds[1]) data_latch_4[line] <= din16[7:0];
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if(ds[0]) data_latch_5[line] <= din16[15:8];
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end
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if(addr[1:0] == 2'd3) begin
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if(ds[1]) data_latch_6[line] <= din16[7:0];
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if(ds[0]) data_latch_7[line] <= din16[15:8];
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if(addr[1:0] == 2'd3) begin
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if(ds[1]) data_latch_6[line] <= din16[7:0];
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if(ds[0]) data_latch_7[line] <= din16[15:8];
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end
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end
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end
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end
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@ -14,11 +14,11 @@
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 13.1.0 Build 162 10/23/2013 SJ Web Edition
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// 13.1.4 Build 182 03/12/2014 SJ Web Edition
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// ************************************************************
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//Copyright (C) 1991-2013 Altera Corporation
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//Copyright (C) 1991-2014 Altera Corporation
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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@ -126,10 +126,10 @@ module clock (
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altpll_component.clk2_divide_by = 18,
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altpll_component.clk2_duty_cycle = 50,
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altpll_component.clk2_multiply_by = 85,
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altpll_component.clk2_phase_shift = "-1500",
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altpll_component.clk3_divide_by = 5625,
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altpll_component.clk2_phase_shift = "-2500",
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altpll_component.clk3_divide_by = 27000000,
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altpll_component.clk3_duty_cycle = 50,
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altpll_component.clk3_multiply_by = 512,
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altpll_component.clk3_multiply_by = 2457599,
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altpll_component.clk3_phase_shift = "0",
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altpll_component.compensate_clock = "CLK0",
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altpll_component.inclk0_input_frequency = 37037,
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@ -265,7 +265,7 @@ endmodule
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// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
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// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
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// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
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// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-1500.00000000"
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// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-2500.00000000"
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// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
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// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
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// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
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@ -323,10 +323,10 @@ endmodule
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// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "18"
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// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
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// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "85"
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// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-1500"
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// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "5625"
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// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-2500"
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// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "27000000"
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// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
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// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "512"
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// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2457599"
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// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0"
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// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
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// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
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@ -14,10 +14,10 @@
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 13.1.0 Build 162 10/23/2013 SJ Web Edition
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// 13.1.4 Build 182 03/12/2014 SJ Web Edition
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// ************************************************************
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//Copyright (C) 1991-2013 Altera Corporation
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//Copyright (C) 1991-2014 Altera Corporation
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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@ -137,7 +137,7 @@ endmodule
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// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
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// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
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// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
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// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-1000.00000000"
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// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-2500.00000000"
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// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000"
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// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
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// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
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@ -195,7 +195,7 @@ endmodule
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// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "18"
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// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
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// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "85"
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// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-1000"
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// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-2500"
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// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "27000000"
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// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
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// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "2457599"
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@ -77,7 +77,7 @@ wire tg68_berr = (dtack_timeout == 4'd15);
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reg [3:0] berr_cnt_out /* synthesis noprune */;
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reg [3:0] berr_cnt;
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reg berrD;
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always @(posedge clk_8) begin
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always @(negedge clk_8) begin
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berrD <= tg68_berr;
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if(reset) begin
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@ -94,14 +94,23 @@ end
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reg bus_ok, cpu_cycle_L;
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always @(negedge clk_8) begin
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// bus error if cpu owns bus, but no dtack, nor ram access,
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// nor fast cpu cycle
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bus_ok <= tg68_dtack || br || cpu2mem || cpu_fast_cycle;
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// nor fast cpu cycle nor cpu does internsal processing
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bus_ok <= tg68_dtack || br || cpu2mem || cpu_fast_cycle || (tg68_busstate == 2'b01);
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cpu_cycle_L <= cpu_cycle;
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end
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reg berr_reset;
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always @(negedge clk_32) begin
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if(reset)
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berr_reset <= 1'b1;
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else if(clkenaD)
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berr_reset <= tg68_clr_berr;
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end
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reg [3:0] dtack_timeout;
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always @(posedge clk_8) begin
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if(reset || tg68_clr_berr) begin
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always @(posedge clk_32 or posedge berr_reset) begin
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// if(reset || tg68_clr_berr) begin
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if(berr_reset) begin
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dtack_timeout <= 4'd0;
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end else begin
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if(cpu_cycle_L) begin
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@ -113,7 +122,7 @@ always @(posedge clk_8) begin
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if(dtack_timeout != 4'd15) begin
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if(bus_ok)
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dtack_timeout <= 4'd0;
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else
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else if(clkcnt == 3) // increase timout at the end of the cpu cycle
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dtack_timeout <= dtack_timeout + 4'd1;
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end
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end
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@ -464,7 +473,7 @@ ste_joystick ste_joystick (
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.uds (tg68_uds ),
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.lds (tg68_lds ),
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.rw (tg68_rw ),
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.dout (ste_joy_data_out),
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.dout (ste_joy_data_out)
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);
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ethernec ethernec (
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@ -764,12 +773,7 @@ end
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/* -------------------------------------------------------------------------- */
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/* ------------------------------ TG68 CPU interface ---------------------- */
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/* -------------------------------------------------------------------------- */
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// the 128 Mhz cpu clock is gated by clkena. Since the CPU cannot run at full 128MHz
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// speed a certain amount of idle cycles have to be inserted between two subsequent
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// cpu clocks. This idle time is implemented using the cpu_throttle counter.
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reg [3:0] cpu_throttle;
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reg clkena;
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reg iCacheStore;
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reg dCacheStore;
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@ -793,43 +797,48 @@ reg cpu_fast_cycle; // signal indicating that the cpu runs from cache,
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wire tg68_reset;
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wire peripheral_reset = reset || !tg68_reset;
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// the CPU throttle counter limits the CPU speed to a rate the tg68 core can
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// handle. With a throttle of "4" the core will run effectively at 32MHz which
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// is equivalent to ~64MHz on a real 68000. This speed will never be achieved
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// since memory and peripheral access slows the cpu further
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localparam CPU_THROTTLE = 4'd6;
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reg [3:0] clkcnt;
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reg trigger /* synthesis noprune */;
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reg panic /* synthesis noprune */;
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// 32MHz counter running synchronous to the 8Mhz clock. This is used to
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// synchronize the 32MHz cpu to the 8MHz system bus
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reg [1:0] clkcnt;
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always @(posedge clk_32) begin
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// count 0..3 within a 8MHz cycle
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if(((clkcnt == 3) && ( clk_8 == 0)) ||
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((clkcnt == 0) && ( clk_8 == 1)) ||
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((clkcnt != 3) && (clkcnt != 0)))
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clkcnt <= clkcnt + 2'd1;
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end
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always @(posedge clk_128) begin
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// count 0..15 within a 8MHz cycle
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if(((clkcnt == 15) && ( clk_8 == 0)) ||
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((clkcnt == 0) && ( clk_8 == 1)) ||
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((clkcnt != 15) && (clkcnt != 0)))
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clkcnt <= clkcnt + 4'd1;
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// generate signal indicating the CPU may run from cache (cpu is active,
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// performs a read and the caches are able to provide the requested data)
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wire cacheReady = !br && steroids && (tg68_busstate[0] == 1'b0) && cache_hit;
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// a clkena delayed by 180 deg is being used to
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// read from the cache
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reg clkenaD;
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always @(posedge clk_32)
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clkenaD <= clkena;
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// the TG68 core works on the rising clock edge. We thus prepare everything
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// on the falling clock edge
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always @(negedge clk_32) begin
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// default: cpu does not run
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clkena <= 1'b0;
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iCacheStore <= 1'b0;
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dCacheStore <= 1'b0;
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cacheUpdate <= 1'b0;
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trigger <= 1'b0;
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panic <= 1'b0;
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if(clkcnt == 15) begin
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if(clkcnt == 3) begin
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// 8Mhz cycle must not start directly after the cpu has been clocked
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// as the address may not be stable then
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// cpuDoes8MhzCycle has same timing as tg68_as
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if(!clkena && !br) cpuDoes8MhzCycle <= 1'b1;
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cpu_fast_cycle <= 1'b0;
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if(!clkena && !br && tg68_busstate != 2'b01) cpuDoes8MhzCycle <= 1'b1;
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// tg68 core does not provide a as signal, so we generate it
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tg68_as <= !clkena && (tg68_busstate != 2'b01) && !br;
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tg68_as <= (!clkena && tg68_busstate != 2'b01) && !br;
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cpu_fast_cycle <= 1'b0;
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// all other output signals are simply latched to make sure
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// they don't change within a 8Mhz cycle even if the CPU
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// advances. This would be a problem if e.g. The CPU would try
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@ -842,32 +851,29 @@ always @(posedge clk_128) begin
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tg68_fc <= tg68_fc_S;
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end
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// evaluate cache one cycle before cpu is allowed to access the bus again
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// to make sure cache signals are routed to the cpu if the cpu is supposed
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// to use it
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if(cpu_throttle == 4'd1) // tg68_busstate[0] == 0 -> cpu read access
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if(!br && steroids && (tg68_busstate[0] == 1'b0) && cache_hit)
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cacheRead <= 1'b1;
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if(clkena)
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cacheRead <= 1'b0;
|
||||
cacheRead <= cacheReady;
|
||||
|
||||
// only run cpu if throttle counter has run down
|
||||
if((cpu_throttle == 4'd0) && !reset) begin
|
||||
if(!reset) begin
|
||||
|
||||
// cpu does internal processing -> let it do this immediately
|
||||
// cpu wants to read and the requested data is available from the cache -> run immediately
|
||||
if((tg68_busstate == 2'b01) || cacheRead) begin
|
||||
if(cacheReady && !br) begin
|
||||
clkena <= 1'b1;
|
||||
|
||||
// cpu must never try to fetch instructions from non-mem
|
||||
if((tg68_busstate == 2'b00) && !cpu2mem)
|
||||
panic <= 1'b1;
|
||||
|
||||
cpu_throttle <= CPU_THROTTLE;
|
||||
cpuDoes8MhzCycle <= 1'b0;
|
||||
cpu_fast_cycle <= 1'b1;
|
||||
end else begin
|
||||
end else
|
||||
|
||||
// cpu does internal processing -> let it do this immediately
|
||||
// cpu wants to read and the requested data is available from the cache -> run immediately
|
||||
|
||||
// todo: non steroids can run this full throttle
|
||||
if((tg68_busstate == 2'b01) && !br) begin
|
||||
clkena <= 1'b1;
|
||||
|
||||
cpuDoes8MhzCycle <= 1'b0;
|
||||
cpu_fast_cycle <= 1'b1;
|
||||
end else
|
||||
|
||||
begin
|
||||
// this ends a normal 8MHz bus cycle. This requires that the
|
||||
// cpu/chipset had the entire cycle and not e.g. started just in
|
||||
// the middle. This is verified using the cpuDoes8MhzCycle signal
|
||||
@ -875,23 +881,10 @@ always @(posedge clk_128) begin
|
||||
// runs from cache
|
||||
|
||||
// clkcnt == 14 -> clkena in cycle 15 -> cpu runs in cycle 15
|
||||
if((clkcnt == 13) && cpuDoes8MhzCycle && cpu_cycle && !br && (tg68_dtack || tg68_berr)) begin
|
||||
if((clkcnt == 3) && cpuDoes8MhzCycle && cpu_cycle && !br && (tg68_dtack || tg68_berr)) begin
|
||||
clkena <= 1'b1;
|
||||
cpu_throttle <= CPU_THROTTLE;
|
||||
cpuDoes8MhzCycle <= 1'b0;
|
||||
|
||||
// cpu must never try to fetch instructions from non-mem
|
||||
if((tg68_busstate == 2'b00) && !cpu2mem)
|
||||
panic <= 1'b1;
|
||||
|
||||
// ---------- cache debugging ---------------
|
||||
// if the cache reports a hit, it should be the same data that's also
|
||||
// returned by ram. Otherwise the cache is broken
|
||||
// if(cache_hit && (tg68_busstate[0] == 1'b0)) begin
|
||||
// if(cache_data_out != system_data_out)
|
||||
// trigger <= 1'b1;
|
||||
// end
|
||||
|
||||
|
||||
if(cacheable && tg68_dtack) begin
|
||||
// store data in instruction cache on cpu instruction read
|
||||
if(tg68_busstate == 2'b00)
|
||||
@ -907,8 +900,7 @@ always @(posedge clk_128) begin
|
||||
end
|
||||
end
|
||||
end
|
||||
end else
|
||||
cpu_throttle <= cpu_throttle - 4'd1;
|
||||
end
|
||||
end
|
||||
|
||||
// TODO: generate cacheUpdate from ram_wr, so other bus masters also trigger this
|
||||
@ -922,7 +914,7 @@ wire [15:0] cpu_data_in = cacheRead?cache_data_out:system_data_out;
|
||||
|
||||
|
||||
TG68KdotC_Kernel #(2,2,2,2,2,2) tg68k (
|
||||
.clk (clk_128 ),
|
||||
.clk (clk_32 ),
|
||||
.nReset (~reset ),
|
||||
.clkena_in (clkena ),
|
||||
.data_in (cpu_data_in ),
|
||||
@ -968,6 +960,7 @@ cache data_cache (
|
||||
.flush ( br ),
|
||||
|
||||
// use the tg68_*_S signals here to quickly react on cpu requests
|
||||
.strobe ( clkenaD ),
|
||||
.addr ( tg68_adr_S[23:1] ),
|
||||
.ds ( { ~tg68_lds_S, ~tg68_uds_S } ),
|
||||
|
||||
@ -995,6 +988,7 @@ cache instruction_cache (
|
||||
.flush ( br ),
|
||||
|
||||
// use the tg68_*_S signals here to quickly react on cpu requests
|
||||
.strobe ( clkenaD ),
|
||||
.addr ( tg68_adr_S[23:1] ),
|
||||
.ds ( { ~tg68_lds_S, ~tg68_uds_S } ),
|
||||
|
||||
@ -1032,7 +1026,7 @@ wire cpu2ram = (!cpu2lowrom) && (
|
||||
((MEM14M || MEM8M) && (tg68_adr[23:22] == 2'b01)) || // 8MB
|
||||
(MEM14M && ((tg68_adr[23:22] == 2'b10) || // 12MB
|
||||
(tg68_adr[23:21] == 3'b110))) || // 14MB
|
||||
(steroids && (tg68_adr[23:19] == 5'b11101)) || // 512k at $e80000 for STEroids
|
||||
// (steroids && (tg68_adr[23:19] == 5'b11101)) || // 512k at $e80000 for STEroids
|
||||
(viking_enable && (tg68_adr[23:18] == 6'b110000)) // 256k at 0xc00000 for viking card
|
||||
);
|
||||
|
||||
@ -1135,7 +1129,7 @@ sdram sdram (
|
||||
.ds ( { ram_uds, ram_lds } ),
|
||||
.we ( ram_wr ),
|
||||
.oe ( ram_oe ),
|
||||
.dout ( ram_data_out_64 ),
|
||||
.dout ( ram_data_out_64 )
|
||||
);
|
||||
|
||||
// multiplex spi_do, drive it from user_io if that's selected, drive
|
||||
|
||||
@ -215,6 +215,11 @@ always @(negedge clk) begin
|
||||
// writing the data register triggers the transfer
|
||||
if((sel && !rw && (addr == 5'h11)) || (mw_cnt != 0)) begin
|
||||
|
||||
// decrease shift counter. Do this before the register write as
|
||||
// register write has priority and should reload the counter
|
||||
if(mw_cnt != 0)
|
||||
mw_cnt <= mw_cnt - 7'd1;
|
||||
|
||||
if(sel && !rw && (addr == 5'h11)) begin
|
||||
// first bit is evaluated imediately
|
||||
mw_data_reg <= { din[14:0], 1'b0 };
|
||||
@ -233,10 +238,6 @@ always @(negedge clk) begin
|
||||
mw_clk <= mw_mask_reg[15];
|
||||
end
|
||||
|
||||
// decrease shift counter
|
||||
if(mw_cnt != 0)
|
||||
mw_cnt <= mw_cnt - 7'd1;
|
||||
|
||||
// indicate end of transfer
|
||||
mw_done <= (mw_cnt == 7'h01);
|
||||
end
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user