diff --git a/cores/c64/rtl/c1541/c1541_logic.vhd b/cores/c64/rtl/c1541/c1541_logic.vhd
index f9e5965..0918857 100644
--- a/cores/c64/rtl/c1541/c1541_logic.vhd
+++ b/cores/c64/rtl/c1541/c1541_logic.vhd
@@ -20,9 +20,9 @@ entity c1541_logic is
     reset           : in std_logic;
 
     -- serial bus
-    sb_data_oe      : out std_logic;
+    sb_data_oe      : buffer std_logic;
     sb_data_in      : in std_logic;
-    sb_clk_oe       : out std_logic;
+    sb_clk_oe       : buffer std_logic;
     sb_clk_in       : in std_logic;
     sb_atn_oe       : out std_logic;
     sb_atn_in       : in std_logic;
@@ -161,19 +161,13 @@ begin
   uc1_pa_i(0) <= tr00_sense_n;
   uc1_pa_i(7 downto 1) <= (others => '0');  -- NC
   -- PB
-  uc1_pb_i(0) <=  '1' when sb_data_in = '0' else
-                  '1' when (uc1_pb_o(1) = '1' and uc1_pb_oe_n(1) = '0') else  -- DAR comment : external OR wired
-                  '1' when atn = '1' else                                     -- DAR comment : external OR wired 
-                  '0';
-  sb_data_oe <=   '1' when (uc1_pb_o(1) = '1' and uc1_pb_oe_n(1) = '0') else
-                  '1' when atn = '1' else
-                  '0';
-  uc1_pb_i(2) <=  '1' when sb_clk_in = '0' else
-                  '1' when (uc1_pb_o(3) = '1' and uc1_pb_oe_n(3) = '0') else  -- DAR comment : external OR wired
-                  '0';
-  sb_clk_oe <=    '1' when (uc1_pb_o(3) = '1' and uc1_pb_oe_n(3) = '0') else '0';
-		
-  atna <= uc1_pb_o(4); -- when uc1_pc_oe = '1'
+
+  uc1_pb_i(0) <=  not (sb_data_in and sb_data_oe);
+  sb_data_oe <=   not (uc1_pb_o(1) or uc1_pb_oe_n(1)) and not atn;
+  uc1_pb_i(2) <=  not (sb_clk_in and sb_clk_oe);
+  sb_clk_oe <=    not (uc1_pb_o(3) or uc1_pb_oe_n(3));
+
+  atna <= uc1_pb_o(4) or uc1_pb_oe_n(4);
   uc1_pb_i(6 downto 5) <= DEVICE_SELECT xor ds;     -- allows override
   uc1_pb_i(7) <= not sb_atn_in;
 
diff --git a/cores/c64/rtl/c1541/c1541_sd.vhd b/cores/c64/rtl/c1541/c1541_sd.vhd
index 1fe44ae..7b5649b 100644
--- a/cores/c64/rtl/c1541/c1541_sd.vhd
+++ b/cores/c64/rtl/c1541/c1541_sd.vhd
@@ -161,9 +161,9 @@ begin
     sb_clk_oe  => iec_clk_o,
     sb_atn_oe  => iec_atn_o,
 		
-    sb_data_in => not iec_data_i,
-    sb_clk_in  => not iec_clk_i,
-    sb_atn_in  => not iec_atn_i,
+    sb_data_in => iec_data_i,
+    sb_clk_in  => iec_clk_i,
+    sb_atn_in  => iec_atn_i,
     
     -- drive-side interface
     ds              => "00",     -- device select
diff --git a/cores/c64/rtl/fpga64_sid_iec.vhd b/cores/c64/rtl/fpga64_sid_iec.vhd
index 5de3027..5d22262 100644
--- a/cores/c64/rtl/fpga64_sid_iec.vhd
+++ b/cores/c64/rtl/fpga64_sid_iec.vhd
@@ -842,9 +842,9 @@ div1m: process(clk32)				-- this process devides 32 MHz to 1MHz (for the SID)
 		end if;
 	end process;
 
-	iec_data_o <= cia2_pao(5);
-	iec_clk_o <= cia2_pao(4);
-	iec_atn_o <= cia2_pao(3);
+	iec_data_o <= not cia2_pao(5);
+	iec_clk_o <= not cia2_pao(4);
+	iec_atn_o <= not cia2_pao(3);
 	ramDataOut <= "00" & unsigned(cia2_pao)(5 downto 3) & "000" when sysCycle >= CYCLE_IEC0 and sysCycle <= CYCLE_IEC3 else cpuDo;
 	ramAddr <= systemAddr when (phi0_cpu = '1') or (phi0_vic = '1') else (others => '0');
 	ramWe <= '0' when sysCycle = CYCLE_IEC2 or sysCycle = CYCLE_IEC3 else not systemWe;
@@ -896,8 +896,8 @@ div1m: process(clk32)				-- this process devides 32 MHz to 1MHz (for the SID)
 		end if;
 		if rising_edge(clk32) then
 			if sysCycle = CYCLE_IEC1 then
-				cia2_pai(7) <= not(iec_data_i or cia2_pao(5));
-				cia2_pai(6) <= not(iec_clk_i or cia2_pao(4));
+				cia2_pai(7) <= iec_data_i and not cia2_pao(5);
+				cia2_pai(6) <= iec_clk_i and not cia2_pao(4);
 			end if;	
 		end if;
 	end process;