From 84d5cf353574f59233b0458907576afdde86087c Mon Sep 17 00:00:00 2001 From: Sebastien Delestaing Date: Tue, 11 Oct 2016 13:16:02 +0200 Subject: [PATCH] [NES] Improvements to Mapper16 --- cores/nes/src/mmu.v | 21 +++++++-------------- 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/cores/nes/src/mmu.v b/cores/nes/src/mmu.v index 19af78e..056a0f8 100644 --- a/cores/nes/src/mmu.v +++ b/cores/nes/src/mmu.v @@ -1092,7 +1092,7 @@ module Mapper16(input clk, input ce, input reset, input [31:0] flags, input [15:0] prg_ain, output [21:0] prg_aout, input prg_read, prg_write, // Read / write signals - input [7:0] prg_din, output reg [7:0] prg_dout, + input [7:0] prg_din, output [7:0] prg_dout, output prg_allow, // Enable access to memory for the specified operation. input [13:0] chr_ain, output [21:0] chr_aout, output chr_allow, // Allow write @@ -1109,7 +1109,7 @@ module Mapper16(input clk, input ce, input reset, reg [15:0] irq_counter; always @(posedge clk) if (reset) begin - prg_bank <= 0; + prg_bank <= 4'hF; chr_bank_0 <= 0; chr_bank_1 <= 0; chr_bank_2 <= 0; @@ -1181,23 +1181,16 @@ module Mapper16(input clk, input ce, input reset, 7: chrsel = chr_bank_7; endcase end - assign chr_aout = {4'b10_00, chrsel, chr_ain[9:0]}; // 1kB banks + assign chr_aout = {4'b10_00, chrsel, chr_ain[9:0]}; // 1kB banks wire [21:0] prg_aout_tmp = {4'b00_00, prgsel, prg_ain[13:0]}; // 16kB banks - //assign prg_aout = {4'b00_00, prgsel, prg_ain[13:0]}; // 16kB banks - // Read from EEPROM - always @* begin - prg_dout = 8'hFF; // By default open bus. - if (prg_read && prg_is_ram) begin // Reading from $6000 up to $7FFF access the EEPROM - prg_dout = 8'h00; // We don't emulate EEPROM, but games expect something else than open bus. - end - end - - wire prg_is_ram = prg_ain >= 'h6000 && prg_ain < 'h8000; + wire prg_is_ram = (prg_ain >= 'h6000) && (prg_ain < 'h8000); wire [21:0] prg_ram = {9'b11_1100_000, prg_ain[12:0]}; assign prg_aout = prg_is_ram ? prg_ram : prg_aout_tmp; + assign prg_dout = prg_is_ram ? 8'h00 : 8'hFF; // EEPROM stub - assign prg_allow = prg_ain[15] && !prg_write || prg_is_ram; + assign prg_allow = prg_ain[15] && !prg_write || + prg_is_ram; assign chr_allow = flags[15]; assign vram_ce = chr_ain[13]; endmodule