diff --git a/cores/c16/c16_mist.qsf b/cores/c16/c16_mist.qsf index 5d54c9f..f8f9a2d 100644 --- a/cores/c16/c16_mist.qsf +++ b/cores/c16/c16_mist.qsf @@ -118,7 +118,6 @@ set_location_assignment PIN_66 -to SDRAM_nWE set_location_assignment PIN_59 -to SDRAM_nCS set_location_assignment PIN_33 -to SDRAM_CKE set_location_assignment PIN_43 -to SDRAM_CLK -set_location_assignment PLL_1 -to "pll:pll|altpll:altpll_component" # Classic Timing Assignments # ========================== @@ -167,7 +166,7 @@ set_global_assignment -name USE_CONFIGURATION_DEVICE OFF # SignalTap II Assignments # ======================== set_global_assignment -name ENABLE_SIGNALTAP OFF -set_global_assignment -name USE_SIGNALTAP_FILE output_files/stp1.stp +set_global_assignment -name USE_SIGNALTAP_FILE output_files/ioctl.stp # Power Estimation Assignments # ============================ @@ -257,6 +256,22 @@ set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12] set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13] set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14] set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[0] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[1] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[2] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[3] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[4] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[5] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[6] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[7] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[8] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[9] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[10] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[11] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[12] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[13] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[14] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[15] set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[0] set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[1] set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[2] @@ -357,4 +372,6 @@ set_global_assignment -name QIP_FILE rom_reconfig_pal.qip set_global_assignment -name QIP_FILE rom_reconfig_ntsc.qip set_global_assignment -name QIP_FILE pll_reconfig.qip set_global_assignment -name ENABLE_DRC_SETTINGS ON +set_global_assignment -name SIGNALTAP_FILE output_files/ioctl.stp +set_location_assignment PLL_1 -to pll_c16|altpll_component|auto_generated|pll1 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/cores/c16/c16_mist.v b/cores/c16/c16_mist.v index e2f5a91..c03f8df 100644 --- a/cores/c16/c16_mist.v +++ b/cores/c16/c16_mist.v @@ -118,8 +118,8 @@ wire c16_sdram_oe = !c16_cas && c16_rw; // multiplex c16 and ioctl signals wire [15:0] mux_sdram_addr = c16_wait?ioctl_sdram_addr:c16_sdram_addr; wire [7:0] mux_sdram_data = c16_wait?ioctl_sdram_data:c16_sdram_data; -wire mux_sdram_wr = c16_wait?ioctl_sdram_write:c16_sdram_wr; -wire mux_sdram_oe = c16_wait?1'b0:c16_sdram_oe; +wire mux_sdram_wr = clkref ? (c16_wait?ioctl_sdram_write:c16_sdram_wr) : 0; +wire mux_sdram_oe = clkref ? (c16_wait?1'b0:c16_sdram_oe) : 0; wire [15:0] sdram_din = { mux_sdram_data, mux_sdram_data }; wire [14:0] sdram_addr_64k = mux_sdram_addr[15:1]; // 64k mapping @@ -135,7 +135,7 @@ wire [15:0] sdram_dout; wire [7:0] c16_din = zp_overwrite?zp_ovl_dout: (c16_a_low[0]?sdram_dout[15:8]:sdram_dout[7:0]); -assign SDRAM_CLK = ~clk28; +assign SDRAM_CLK = clk28; // synchronize sdram state machine with the ras/cas phases of the c16 reg last_ras; diff --git a/cores/c16/sdram.v b/cores/c16/sdram.v index d9fcb0b..2575d19 100644 --- a/cores/c16/sdram.v +++ b/cores/c16/sdram.v @@ -23,7 +23,7 @@ module sdram ( // interface to the MT48LC16M16 chip - inout [15:0] sd_data, // 16 bit bidirectional data bus + inout reg [15:0] sd_data, // 16 bit bidirectional data bus output reg [12:0] sd_addr, // 13 bit multiplexed address bus output reg [1:0] sd_dqm, // two byte masks output reg[1:0] sd_ba, // two banks @@ -33,13 +33,13 @@ module sdram ( output sd_cas, // columns address select // cpu/chipset interface - input init, // init signal after FPGA config to initialize RAM - input clk, // sdram is accessed at up to 128MHz - input clkref, // reference clock to sync to + input init, // init signal after FPGA config to initialize RAM + input clk, // sdram is accessed at up to 128MHz + input clkref, // reference clock to sync to - input [15:0] din, // data input from chipset/cpu - output [15:0] dout, // data output to chipset/cpu - input [24:0] addr, // 25 bit word address + input [15:0] din, // data input from chipset/cpu + output reg [15:0] dout, // data output to chipset/cpu + input [24:0] addr, // 25 bit word address input [1:0] ds, // data strobe for hi/low byte input oe, // cpu/chipset requests read input we // cpu/chipset requests write @@ -49,7 +49,7 @@ module sdram ( localparam RASCAS_DELAY = 3'd2; // tRCD>=20ns -> 2 cycles@64MHz localparam BURST_LENGTH = 3'b000; // 000=none, 001=2, 010=4, 011=8 localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved -localparam CAS_LATENCY = 3'd3; // 2/3 allowed +localparam CAS_LATENCY = 3'd2; // 2/3 allowed localparam OP_MODE = 2'b00; // only 00 (standard operation) allowed localparam NO_WRITE_BURST = 1'b1; // 0= write burst enabled, 1=only single access write @@ -61,18 +61,19 @@ localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, B localparam STATE_IDLE = 4'd0; // first state in cycle localparam STATE_CMD_START = 4'd1; // state in which a new command can be started -localparam STATE_CMD_CONT = STATE_CMD_START + RASCAS_DELAY - 3'd1; // 4 command can be continued -localparam STATE_LAST = 4'd15; // last state in cycle +localparam STATE_CMD_CONT = STATE_CMD_START + RASCAS_DELAY - 1'd1; // 2 command can be continued +localparam STATE_DATA_READY= STATE_CMD_CONT + CAS_LATENCY + 1'd1; +localparam STATE_LAST = 4'd7; // last state in cycle -reg [3:0] q /* synthesis noprune */; +reg [2:0] q /* synthesis noprune */; always @(posedge clk) begin - // 32Mhz counter synchronous to 4 Mhz clock - // force counter to pass state 5->6 exactly after the rising edge of clkref - // since clkref is two clocks early - if(((q == 14) && ( clkref == 0)) || - ((q == 15) && ( clkref == 1)) || - ((q != 14) && (q != 15))) - q <= q + 4'd1; + reg last_clkref; + last_clkref <= clkref; + + // Sync SDRAM cycle to rising edge of clkref + q <= q + 1'd1; + if (~last_clkref & clkref) q <= 0; + end // --------------------------------------------------------------------- @@ -111,12 +112,9 @@ assign sd_ras = sd_cmd[2]; assign sd_cas = sd_cmd[1]; assign sd_we = sd_cmd[0]; -assign sd_data = we?din:16'bZZZZZZZZZZZZZZZZ; - -assign dout = sd_data; - always @(posedge clk) begin sd_cmd <= CMD_INHIBIT; + sd_data <= 16'bZZZZZZZZZZZZZZZZ; if(reset != 0) begin sd_ba <= 2'b00; @@ -143,7 +141,10 @@ always @(posedge clk) begin end else if(q == STATE_CMD_CONT) begin if(we) sd_cmd <= CMD_WRITE; else if(oe) sd_cmd <= CMD_READ; - end + if(we) sd_data <= din; + end else if(q == STATE_DATA_READY) begin + if(oe) dout <= sd_data; + end end end