diff --git a/cores/mist/clock.v b/cores/mist/clock.v index b0d0827..e4fd9c0 100644 --- a/cores/mist/clock.v +++ b/cores/mist/clock.v @@ -37,50 +37,37 @@ `timescale 1 ps / 1 ps // synopsys translate_on module clock ( - areset, inclk0, c0, c1, c2, - c3, locked); - input areset; input inclk0; output c0; output c1; output c2; - output c3; output locked; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_off -`endif - tri0 areset; -`ifndef ALTERA_RESERVED_QIS -// synopsys translate_on -`endif wire [4:0] sub_wire0; - wire sub_wire3; - wire [0:0] sub_wire8 = 1'h0; - wire [2:2] sub_wire5 = sub_wire0[2:2]; - wire [0:0] sub_wire4 = sub_wire0[0:0]; - wire [3:3] sub_wire2 = sub_wire0[3:3]; + wire sub_wire2; + wire [0:0] sub_wire7 = 1'h0; + wire [2:2] sub_wire4 = sub_wire0[2:2]; + wire [0:0] sub_wire3 = sub_wire0[0:0]; wire [1:1] sub_wire1 = sub_wire0[1:1]; wire c1 = sub_wire1; - wire c3 = sub_wire2; - wire locked = sub_wire3; - wire c0 = sub_wire4; - wire c2 = sub_wire5; - wire sub_wire6 = inclk0; - wire [1:0] sub_wire7 = {sub_wire8, sub_wire6}; + wire locked = sub_wire2; + wire c0 = sub_wire3; + wire c2 = sub_wire4; + wire sub_wire5 = inclk0; + wire [1:0] sub_wire6 = {sub_wire7, sub_wire5}; altpll altpll_component ( - .areset (areset), - .inclk (sub_wire7), + .inclk (sub_wire6), .clk (sub_wire0), - .locked (sub_wire3), + .locked (sub_wire2), .activeclock (), + .areset (1'b0), .clkbad (), .clkena ({6{1'b1}}), .clkloss (), @@ -114,23 +101,19 @@ module clock ( .vcooverrange (), .vcounderrange ()); defparam - altpll_component.bandwidth_type = "LOW", - altpll_component.clk0_divide_by = 18, + altpll_component.bandwidth_type = "AUTO", + altpll_component.clk0_divide_by = 27, altpll_component.clk0_duty_cycle = 50, - altpll_component.clk0_multiply_by = 85, + altpll_component.clk0_multiply_by = 128, altpll_component.clk0_phase_shift = "0", - altpll_component.clk1_divide_by = 72, + altpll_component.clk1_divide_by = 27, altpll_component.clk1_duty_cycle = 50, - altpll_component.clk1_multiply_by = 85, + altpll_component.clk1_multiply_by = 32, altpll_component.clk1_phase_shift = "0", - altpll_component.clk2_divide_by = 18, + altpll_component.clk2_divide_by = 27, altpll_component.clk2_duty_cycle = 50, - altpll_component.clk2_multiply_by = 85, + altpll_component.clk2_multiply_by = 128, altpll_component.clk2_phase_shift = "-2500", - altpll_component.clk3_divide_by = 5625, - altpll_component.clk3_duty_cycle = 50, - altpll_component.clk3_multiply_by = 512, - altpll_component.clk3_phase_shift = "0", altpll_component.compensate_clock = "CLK0", altpll_component.inclk0_input_frequency = 37037, altpll_component.intended_device_family = "Cyclone III", @@ -139,7 +122,7 @@ module clock ( altpll_component.operation_mode = "NORMAL", altpll_component.pll_type = "AUTO", altpll_component.port_activeclock = "PORT_UNUSED", - altpll_component.port_areset = "PORT_USED", + altpll_component.port_areset = "PORT_UNUSED", altpll_component.port_clkbad0 = "PORT_UNUSED", altpll_component.port_clkbad1 = "PORT_UNUSED", altpll_component.port_clkloss = "PORT_UNUSED", @@ -166,7 +149,7 @@ module clock ( altpll_component.port_clk0 = "PORT_USED", altpll_component.port_clk1 = "PORT_USED", altpll_component.port_clk2 = "PORT_USED", - altpll_component.port_clk3 = "PORT_USED", + altpll_component.port_clk3 = "PORT_UNUSED", altpll_component.port_clk4 = "PORT_UNUSED", altpll_component.port_clk5 = "PORT_UNUSED", altpll_component.port_clkena0 = "PORT_UNUSED", @@ -193,8 +176,8 @@ endmodule // Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz" // Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low" -// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "0" -// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1" +// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" // Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1" @@ -203,19 +186,16 @@ endmodule // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" -// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "18" -// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "72" -// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "18" -// Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "1" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "27" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" -// Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "127.500000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "31.875000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "127.500000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "2.457600" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "128.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "32.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "128.000000" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -236,44 +216,36 @@ endmodule // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "deg" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT3 STRING "ps" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" // Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" -// Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0" -// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "85" -// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "85" -// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "85" -// Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "128" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "128.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "32.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ3 STRING "2.45760000" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE3 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "128.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT3 STRING "MHz" // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-2500.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT3 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT3 STRING "ps" // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" -// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" +// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0" // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0" @@ -296,38 +268,31 @@ endmodule // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" -// Retrieval info: PRIVATE: STICKY_CLK3 STRING "1" // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: USE_CLK0 STRING "1" // Retrieval info: PRIVATE: USE_CLK1 STRING "1" // Retrieval info: PRIVATE: USE_CLK2 STRING "1" -// Retrieval info: PRIVATE: USE_CLK3 STRING "1" // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" // Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA3 STRING "0" // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW" -// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "18" +// Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "85" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "128" // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "72" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "85" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "32" // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "18" +// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "27" // Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "85" +// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "128" // Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-2500" -// Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "5625" -// Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK3_MULTIPLY_BY NUMERIC "512" -// Retrieval info: CONSTANT: CLK3_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" @@ -335,7 +300,7 @@ endmodule // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL" // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO" // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED" -// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED" @@ -362,7 +327,7 @@ endmodule // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED" @@ -378,20 +343,16 @@ endmodule // Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF" // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" -// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" // Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" -// Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3" // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" -// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0 // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 // Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 -// Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 // Retrieval info: GEN_FILE: TYPE_NORMAL clock.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL clock.ppf TRUE diff --git a/cores/mist/dma.v b/cores/mist/dma.v index 0d643f1..1e9adc8 100644 --- a/cores/mist/dma.v +++ b/cores/mist/dma.v @@ -294,7 +294,7 @@ end // 32 byte dma fifo (actually a 16 word fifo) reg [15:0] fifo [15:0]; reg [3:0] fifo_wptr; // word pointers -reg [3:0] fifo_rptr; +reg [3:0] fifo_rptr; wire [3:0] fifo_ptr_diff = fifo_wptr - fifo_rptr; reg [2:0] fifo_read_cnt; // fifo read transfer word counter reg [2:0] fifo_write_cnt; // fifo write transfer word counter diff --git a/cores/mist/fdc.v b/cores/mist/fdc.v index 65bc499..b0ca3e1 100644 --- a/cores/mist/fdc.v +++ b/cores/mist/fdc.v @@ -203,7 +203,7 @@ always @(negedge clk or posedge reset) begin delay <= 31'd200000; // 25ms delay end - if(cpu_din[7:3] == 3'b001) begin // STEP + if(cpu_din[7:5] == 3'b001) begin // STEP delay <= 31'd20000; // 2.5ms delay if(cpu_din[4]) // update flag track <= (step_dir == 1)?(track + 8'd1):(track - 8'd1); diff --git a/cores/mist/mist_top.v b/cores/mist/mist_top.v index b9d9292..448f782 100644 --- a/cores/mist/mist_top.v +++ b/cores/mist/mist_top.v @@ -675,41 +675,21 @@ wire pll_locked; wire clk_8; wire clk_32; wire clk_128; -wire clk_mfp; // use pll clock clock ( - .areset (1'b0 ), // async reset input .inclk0 (CLOCK_27[0] ), // input clock (27MHz) .c0 (clk_128 ), // output clock c0 (128MHz) .c1 (clk_32 ), // output clock c1 (32MHz) .c2 (SDRAM_CLK ), // output clock c2 (128MHz) -// .c3 (clk_mfp ), // output clock c3 (2.4576MHz) .locked (pll_locked ) // pll locked output ); -reg clk_64; -always @(posedge clk_128) - clk_64 <= !clk_64; - -//reg clk_32; -//always @(posedge clk_64) -// clk_32 <= !clk_32; //// 8MHz clock //// reg [1:0] clk_cnt; reg [1:0] bus_cycle; -// MFP clock -// required: 2.4576 MHz -// derived from 27MHZ: 27*74/824 = 2.457525 MHz => 0.003% error -// derived from 31.875MHz: 31.875*33/428=2.457652 MHz => 0.002% error -// derived from 127.5 MHz: 127.5*58/3009 = 2.457627 MHz => 0.001% error -// use pll -pll_mfp1 pll_mfp1 ( - .inclk0 (clk_128 ), // input clock (127.5MHz) - .c0 (clk_mfp ) // output clock c0 (2.457627MHz) -); always @ (posedge clk_32, negedge pll_locked) begin if (!pll_locked) begin @@ -724,6 +704,20 @@ end assign clk_8 = clk_cnt[1]; +// MFP clock +// required: 2.4576 MHz +// mfp clock is clk_128*2457600/128000000 -> 12/625 -> toggle at 24/625 +reg clk_mfp; +reg [9:0] clk_mfp_div; +always @(posedge clk_128) begin + if(clk_mfp_div < 625) + clk_mfp_div <= clk_mfp_div + 10'd24; + else begin + clk_mfp_div <= clk_mfp_div - 10'd625 + 10'd24; + clk_mfp <= ~clk_mfp; + end +end + // tg68 bus interface. These are the signals which are latched // for the 8MHz bus. wire [15:0] tg68_dat_in; diff --git a/cores/mist/shifter.v b/cores/mist/shifter.v index ffcbbef..8bf2010 100644 --- a/cores/mist/shifter.v +++ b/cores/mist/shifter.v @@ -102,26 +102,16 @@ assign st_de = ~de; always @(posedge clk) begin st_hs <= h_sync; - // hsync irq is generated after the rightmost border pixel column has been displayed - - // hsync starts at begin of blanking phase -// if(hcnt == (t1_h_blank_right)) -// st_hs <= 1'b1; - - // hsync ends at begin of left border -// if(hcnt == (t4_h_border_left - 10'd16)) -// st_hs <= 1'b0; - // vsync irq is generated right after the last border line has been displayed // v_event is the begin of hsync. The hatari video.h says vbi happens 64 clock cycles // ST hor counter runs at 16Mhz, thus the trigger is 128 events after h_sync if(hcnt == v_event) begin // vsync starts at begin of blanking phase - if(vcnt == t7_v_blank_bot + 10'd4) st_vs <= 1'b1; + if(vcnt == t7_v_blank_bot) st_vs <= 1'b1; // vsync ends at begin of top border - if(vcnt == t10_v_border_top + 10'd0) st_vs <= 1'b0; + if(vcnt == t10_v_border_top) st_vs <= 1'b0; end end @@ -442,8 +432,8 @@ always @(posedge clk) begin end // trigger in line 284/285 - if((vcnt[8:1] == 8'd133)||(vcnt[8:1] == 8'd134)||(vcnt[8:1] == 8'd135)|| - (vcnt[8:1] == 8'd136)||(vcnt[8:1] == 8'd137)||(vcnt[8:1] == 8'd138)) begin + if((vcnt[8:1] == 8'd140)||(vcnt[8:1] == 8'd141)||(vcnt[8:1] == 8'd142)|| + (vcnt[8:1] == 8'd143)||(vcnt[8:1] == 8'd144)||(vcnt[8:1] == 8'd145)) begin // syncmode has changed from 1 to 0 (50 to 60 hz) if((syncmode[1] == 1'b0) && (last_syncmode == 1'b1)) top_overscan_cnt <= 4'd15; diff --git a/cores/mist/video.v b/cores/mist/video.v index 551ffba..80cfc79 100644 --- a/cores/mist/video.v +++ b/cores/mist/video.v @@ -72,7 +72,8 @@ assign read = viking_enable?viking_read:shifter_read; // if we use 15khz signals without scan doubler then we need // to create a composite sync on hsync wire enable_csync = sd_15khz_detected && scandoubler_disable; -wire csync = shifter_hs == shifter_vs; +// wire csync = shifter_hs == shifter_vs; +wire csync = shifter_sd_adjusted_hs == shifter_sd_adjusted_vs; assign hs = enable_csync?csync:stvid_hs; assign vs = enable_csync?1'b1:stvid_vs; @@ -95,8 +96,8 @@ osd osd ( .ss ( ss ), // feed ST video signal into OSD - .hs ( stvid_hs ), - .vs ( stvid_vs ), + .hs ( stvid_hs ), + .vs ( stvid_vs ), .r_in ( {stvid_r, 2'b00}), .g_in ( {stvid_g, 2'b00}), @@ -156,7 +157,7 @@ wire sd_hs, sd_vs; wire [3:0] sd_r, sd_g, sd_b; scandoubler scandoubler ( - .clk ( clk_32 ), // 31.875 MHz + .clk ( clk_32 ), // 33.000 MHz .clk_16 ( clk_16 ), .scanlines ( scanlines ), diff --git a/cores/mist/video_modes.v b/cores/mist/video_modes.v index caa0b85..867a1bf 100644 --- a/cores/mist/video_modes.v +++ b/cores/mist/video_modes.v @@ -29,7 +29,7 @@ // clocks on real sts: // PAL 32084988 Hz // NTSC 32042400 Hz -// MIST 31875000 Hz +// MIST 32000000 Hz // real ST timing @@ -95,7 +95,8 @@ conf pal50_conf( .h_ds(10'd640), .h_fp( 10'd80), .h_s( 10'd64), .h_bp( 10'd80), .h_lb(10'd80), .h_rb(10'd80), .h_sp(1'b1), // .h_ds(10'd640), .h_fp( 10'd80), .h_s( 10'd80), .h_bp( 10'd24), .h_lb(10'd72), .h_rb(10'd128), .h_sp(1'b1), // .h_ds(10'd640), .h_fp( 10'd80), .h_s( 10'd80), .h_bp( 10'd24), .h_lb(10'd56), .h_rb(10'd144), .h_sp(1'b1), - .v_ds(10'd200), .v_fp( 10'd15), .v_s( 10'd3), .v_bp( 10'd15), .v_tb(10'd40), .v_bb(10'd40), .v_sp(1'b1), +// .v_ds(10'd200), .v_fp( 10'd15), .v_s( 10'd3), .v_bp( 10'd15), .v_tb(10'd40), .v_bb(10'd40), .v_sp(1'b1), + .v_ds(10'd200), .v_fp( 10'd15), .v_s( 10'd3), .v_bp( 10'd4), .v_tb(10'd40), .v_bb(10'd51), .v_sp(1'b1), .str (pal50_config_str) );