diff --git a/cores/archie/fpga/mist/archimedes_mist_top.qsf b/cores/archie/fpga/mist/archimedes_mist_top.qsf
index b0a7283..d2524c8 100644
--- a/cores/archie/fpga/mist/archimedes_mist_top.qsf
+++ b/cores/archie/fpga/mist/archimedes_mist_top.qsf
@@ -134,7 +134,6 @@ set_location_assignment PIN_80 -to AUDIO_R
 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to DRAM_*
 set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_*
 set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_*
-set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_*
 
 set_global_assignment -name ENABLE_SIGNALTAP OFF
 set_global_assignment -name USE_SIGNALTAP_FILE signal_tap.stp
@@ -219,4 +218,6 @@ set_global_assignment -name VERILOG_FILE ../../rtl/amber/a23_alu.v
 set_global_assignment -name VERILOG_FILE ../../rtl/archimedes_top.v
 set_global_assignment -name VERILOG_FILE ../../rtl/sdram/sdram_top.v
 set_global_assignment -name VERILOG_FILE ../../rtl/sdram/sdram_init.v
+set_instance_assignment -name FAST_INPUT_REGISTER ON -to DRAM_DQ[*]
+set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[*]
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/cores/archie/fpga/mist/archimedes_mist_top.sdc b/cores/archie/fpga/mist/archimedes_mist_top.sdc
index bd7f196..5968ff0 100644
--- a/cores/archie/fpga/mist/archimedes_mist_top.sdc
+++ b/cores/archie/fpga/mist/archimedes_mist_top.sdc
@@ -70,8 +70,8 @@ set_input_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|
 # Set Output Delay
 #**************************************************************
 
-set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -max 1.5 [get_ports {DRAM_D* DRAM_A* DRAM_BA* DRAM_n* DRAM_CKE}]
-set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -min -0.8 [get_ports {DRAM_D* DRAM_A* DRAM_BA* DRAM_n* DRAM_CKE}]
+set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -max 1.5 [get_ports {DRAM_A* DRAM_BA* DRAM_CAS_N DRAM_CKE DRAM_CS_N DRAM_D* DRAM_RAS_N DRAM_WE_N}]
+set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[1]}] -min -0.8 [get_ports {DRAM_A* DRAM_BA* DRAM_CAS_N DRAM_CKE DRAM_CS_N DRAM_D* DRAM_RAS_N DRAM_WE_N}]
 set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[3]}] -max 1.5 [get_ports DRAM_CLK]
 set_output_delay -clock [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[3]}] -min -0.8 [get_ports DRAM_CLK]
 
diff --git a/cores/archie/rtl/sdram/sdram_top.v b/cores/archie/rtl/sdram/sdram_top.v
index 72cefe8..31668a3 100644
--- a/cores/archie/rtl/sdram/sdram_top.v
+++ b/cores/archie/rtl/sdram/sdram_top.v
@@ -32,15 +32,15 @@ module sdram_top (
 	input			sd_clk,		// sdram is accessed at 128MHz
 	input			sd_rst,		// reset the sdram controller.
 	output			sd_cke,		// clock enable.
-	inout  [15:0]	sd_dq,		// 16 bit bidirectional data bus
-	output [12:0]	sd_addr,	// 13 bit multiplexed address bus
+	inout  reg[15:0]sd_dq,		// 16 bit bidirectional data bus
+	output reg[12:0]sd_addr,	// 13 bit multiplexed address bus
 	output reg[1:0]	sd_dqm = 2'b00,		// two byte masks
 	output reg[1:0]	sd_ba = 2'b00,		// two banks
 	output			sd_cs_n,	// a single chip select
 	output			sd_we_n,	// write enable
 	output			sd_ras_n,	// row address select
 	output			sd_cas_n,	// columns address select
-	output			sd_ready,	// sd ready.
+	output reg		sd_ready = 0,	// sd ready.
 
 	// cpu/chipset interface
 
@@ -60,13 +60,14 @@ module sdram_top (
 
 localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, BURST_LENGTH}; 
 
+reg [3:0]	t;
+reg [4:0]	reset;
 
 reg[31:0]	sd_dat	  = 0;	// data output to chipset/cpu
 reg[31:0]	sd_dat_nxt = 0;	// data output to chipset/cpu
 
 reg			sd_stb 	= 1'b0; // copy of the wishbone bus signal.
 reg			sd_we 	= 1'b0; // copy of the wishbone bus signal.
-reg			sd_wr   = 1'b0;
 reg			sd_cyc 	= 1'b0; // copy of the wishbone bus signal.
 reg			sd_burst = 1'b0;
 
@@ -74,37 +75,20 @@ reg	[3:0]	sd_cycle= 4'd0;
 reg			sd_done = 1'b0;
 
 reg [3:0] 	sd_cmd 	= 4'd0;   // current command sent to sd ram
-reg	[12:0]	sd_a	= 13'd0;
-reg [15:0]	sd_q	= 16'd0;  // data to output during write phase.
-
 
 reg [9:0]	sd_refresh = 10'd0;
 reg			sd_auto_refresh = 1'b0; 
 
-wire [3:0]	sd_init_cmd;
-wire [12:0]	sd_init_a;
-
 wire 		sd_reading;
 wire		sd_writing;
 
-sdram_init #
-(
-	.MODE(MODE)
-)
-INIT (
-	
-	.sd_clk	( sd_clk		),
-	.sd_rst ( sd_rst		),
-	.sd_cmd	( sd_init_cmd	),
-	.sd_a	( sd_init_a		),
-	.sd_rdy	( sd_ready		)
+initial begin 
+	t			= 4'd0;
+	reset 		= 5'h1f;
+	sd_addr		= 13'd0;
+	sd_cmd 		= CMD_INHIBIT;
+end
 
-);
-
-
-// output data during the write phase. 
-assign sd_dq = (sd_wr === 1'b1) ? sd_q : 16'bZZZZZZZZZZZZZZZZ;
- 
 localparam CYCLE_RAS_START = 4'd1;  
 localparam CYCLE_RFSH_START = CYCLE_RAS_START; 
 localparam CYCLE_CAS0 		= CYCLE_RFSH_START  + RASCAS_DELAY; 
@@ -123,163 +107,149 @@ localparam RAM_CLK		   = 128000000;
 localparam REFRESH_PERIOD  = (RAM_CLK / (16 * 8192)) - CYCLE_END;
  
 always @(posedge sd_clk) begin 
+
+	if (sd_rst) begin 
+		t			<= 4'd0;
+		reset 	<= 5'h1f;
+		sd_addr	<= 13'd0;
+		sd_ready  <= 0;
+	end else begin
+		sd_dq <= 16'bZZZZZZZZZZZZZZZZ;
+		if (!sd_ready) begin
+			t <= t + 4'd1;
+
+			if (t ==4'hF) begin 
+				reset <= reset - 5'd1;		
+			end
+
+			if (t == 4'h0) begin 
+
+				if(reset == 13) begin
+					$display("precharging all banks");
+					sd_cmd 		<= CMD_PRECHARGE;
+					sd_addr[10] 	<= 1'b1;      // precharge all banks
+				end
+
+				if(reset == 2) begin
+					sd_cmd 		<= CMD_LOAD_MODE;
+					sd_addr		<= MODE;
+				end
+
+				if(reset == 1) begin
+					$display("loading mode");
+					sd_cmd 		<= CMD_LOAD_MODE;
+					sd_addr		<= MODE;
+				end
+
+				if(reset == 0) sd_ready <= 1;
+			end
+		end else begin
 	
-	// bring the wishbone bus signal into the ram clock domain.
-     
-	sd_wr	<= 1'b0; // default to not writing.
-	sd_we	<= wb_we;
-	sd_cmd	<= CMD_INHIBIT;
-	
-	   if (wb_stb & wb_cyc & ~wb_ack) begin 
-	      
-			sd_stb	<= wb_stb;
-            sd_cyc	<= wb_cyc;
-	      
-	   end
-   	   
-	   sd_refresh <= sd_refresh + 9'd1;
-		
-		// this is the auto refresh code.
-		// it kicks in so that 8192 auto refreshes are 
-		// issued in a 64ms period. Other bus operations 
-		// are stalled during this period.
-		if ((sd_refresh > REFRESH_PERIOD) && (sd_cycle == 4'd0)) begin 
-		   
-			sd_auto_refresh <= 1'b1;
-			sd_refresh		<= 10'd0;
-			
-		end else if (sd_auto_refresh) begin 
-		
-			// while the cycle is active count.
-			sd_cycle <= sd_cycle + 3'd1;
-			
-			case (sd_cycle) 
-				
+			// bring the wishbone bus signal into the ram clock domain.
+
+			sd_we	<= wb_we;
+			sd_cmd	<= CMD_INHIBIT;
+			if (wb_stb & wb_cyc & ~wb_ack) begin 
+				sd_stb	<= wb_stb;
+				sd_cyc	<= wb_cyc;
+			end
+
+			sd_refresh <= sd_refresh + 9'd1;
+
+			// this is the auto refresh code.
+			// it kicks in so that 8192 auto refreshes are 
+			// issued in a 64ms period. Other bus operations 
+			// are stalled during this period.
+			if ((sd_refresh > REFRESH_PERIOD) && (sd_cycle == 4'd0)) begin 
+				sd_auto_refresh <= 1'b1;
+				sd_refresh		<= 10'd0;
+			end else if (sd_auto_refresh) begin 
+				// while the cycle is active count.
+				sd_cycle <= sd_cycle + 3'd1;
+				case (sd_cycle) 
 				CYCLE_RFSH_START: begin 
-				
 					sd_cmd	<= CMD_AUTO_REFRESH;
-					
 				end
 
 				CYCLE_RFSH_END: begin 
-				
 					// reset the count.
 					sd_auto_refresh <= 1'b0;
-				        sd_cycle <= 4'd0;
-				   
+					sd_cycle <= 4'd0;
 				end
-				
-			endcase
-			
-		end else if (sd_cyc | (sd_cycle != 0)) begin 
-			
-			// while the cycle is active count.
-			sd_cycle <= sd_cycle + 3'd1;
-			//sd_cmd		<= CMD_NOP;
-			
-			case (sd_cycle)
-			
+				endcase
+
+			end else if (sd_cyc | (sd_cycle != 0)) begin 
+
+				// while the cycle is active count.
+				sd_cycle <= sd_cycle + 3'd1;
+				//sd_cmd		<= CMD_NOP;
+				case (sd_cycle)
 				CYCLE_RAS_START: begin 
-				
 					sd_cmd 	<= CMD_ACTIVE;
-					sd_a 	<= { 1'b0, wb_adr[20:9] };
+					sd_addr	<= { 1'b0, wb_adr[20:9] };
 					sd_ba 	<= wb_adr[22:21];
-					
+
 					if(sd_reading) begin 
 						sd_dqm <= 2'b00;
 					end else begin 
 						sd_dqm <= 2'b11;
 					end
-					
 				end
-				
+
 				// this is the first CAS cycle
 				CYCLE_CAS0: begin 
-					
 					// always, always read on a 32bit boundary and completely ignore the lsb of wb_adr.
-					sd_a <= { 4'b0000, wb_adr[23], wb_adr[8:2], 1'b0 };  // no auto precharge
+					sd_addr <= { 4'b0000, wb_adr[23], wb_adr[8:2], 1'b0 };  // no auto precharge
 					sd_dqm		<= ~wb_sel[1:0];
-					
-					if (sd_reading) begin 
-						
-						sd_cmd <= CMD_READ;
-					
-					end else if (sd_writing) begin 
-						
-						sd_cmd		<= CMD_WRITE;
-						sd_q	 		<= wb_dat_i[15:0];
-						sd_wr			<= 1'b1;
 
-					end
-					
-				end
-				
-				CYCLE_CAS1: begin 
-					
-					// now we access the second part of the 32 bit location.
-					sd_a <= { 4'b0010, wb_adr[23], wb_adr[8:2], 1'b1 };  // auto precharge
-					sd_dqm		<= ~wb_sel[3:2];
-					
 					if (sd_reading) begin 
-						
 						sd_cmd <= CMD_READ;
-						
-						if (burst_mode & can_burst) begin 
-						
-							sd_a[10] <= 1'b0;
-							sd_burst <= 1'b1; 
-						
-						end
-					
 					end else if (sd_writing) begin 
-					
 						sd_cmd		<= CMD_WRITE;
-						sd_q 		<= wb_dat_i[31:16];
+						sd_dq	 		<= wb_dat_i[15:0];
+					end
+				end
+
+				CYCLE_CAS1: begin 
+					// now we access the second part of the 32 bit location.
+					sd_addr <= { 4'b0010, wb_adr[23], wb_adr[8:2], 1'b1 };  // auto precharge
+					sd_dqm		<= ~wb_sel[3:2];
+					if (sd_reading) begin 
+						sd_cmd <= CMD_READ;
+						if (burst_mode & can_burst) begin 
+							sd_addr[10] <= 1'b0;
+							sd_burst <= 1'b1; 
+						end
+					end else if (sd_writing) begin 
+						sd_cmd		<= CMD_WRITE;
+						sd_dq 		<= wb_dat_i[31:16];
 						sd_done		<= 1'b1;
-						sd_wr		<= 1'b1;
-					
 					end 
-					
 				end
 				
 				CYCLE_CAS2: begin 
-					
 					if (sd_burst) begin 
-					
 						// always, always read on a 32bit boundary and completely ignore the lsb of wb_adr.
-						sd_a <= { 4'b0000, wb_adr[23], wb_adr[8:3], 2'b10 };  // no auto precharge
+						sd_addr <= { 4'b0000, wb_adr[23], wb_adr[8:3], 2'b10 };  // no auto precharge
 						sd_dqm		<= ~wb_sel[1:0];
-						
 						if (sd_reading) begin 
-							
 							sd_cmd <= CMD_READ;
-						
 						end  
-						
 					end
-					
 				end
-				
+
 				CYCLE_CAS3: begin 
-					
 					if (sd_burst) begin 
-					
 						// always, always read on a 32bit boundary and completely ignore the lsb of wb_adr.
-						sd_a 	<= { 4'b0010, wb_adr[23], wb_adr[8:3], 2'b11 };  // no auto precharge
+						sd_addr	<= { 4'b0010, wb_adr[23], wb_adr[8:3], 2'b11 };  // no auto precharge
 						sd_dqm	<= ~wb_sel[3:2];
-						
 						if (sd_reading) begin 
-							
 							sd_cmd <= CMD_READ;
-						
 						end  
-						
 					end
-					
 				end
-				
+
 				CYCLE_READ0: begin 
-				
 					if (sd_writing) begin
 						// if we are writing then the sd_done signal has been high for 
 						// enough clock cycles. we can end the cycle here. 
@@ -287,66 +257,45 @@ always @(posedge sd_clk) begin
 						sd_cycle <= 4'd0;
 						sd_cyc <= 1'b0;
 						sd_stb <= 1'b0;
-						
 					end
-				
 					if (sd_reading) begin 
-						
 					        sd_dat[15:0] <= sd_dq;
-					
 					end 
-				
 				end
-				
-				CYCLE_READ1: begin 
 
+				CYCLE_READ1: begin 
 					if (sd_reading) begin 
-					
 						sd_dat[31:16] <= sd_dq;
 						sd_done			<= 1'b1;
-					
 					end
-				
 				end
-				
+
 				CYCLE_READ2: begin 
-
 					if (sd_reading) begin 
-					
 						sd_dat_nxt[15:0] <= sd_dq;
-					
 					end
-				
 				end
-				
-				CYCLE_READ3: begin 
 
+				CYCLE_READ3: begin 
 					if (sd_reading) begin 
-					
 						sd_dat_nxt[31:16] <= sd_dq;
-						
 					end
-				
 				end
-				
+
 				CYCLE_END: begin 
 					sd_burst <= 1'b0;
 					sd_done 	<= 1'b0;
 					sd_cyc <= 1'b0;
 					sd_stb <= 1'b0;
 				end
-				
-			endcase
-		
-			
-		end else begin
-			
-
-			sd_done		<= 1'd0;
-			sd_cycle 	<= 4'd0;
-			sd_burst <= 1'b0;
-		
+				endcase
+			end else begin
+				sd_done		<= 1'd0;
+				sd_cycle 	<= 4'd0;
+				sd_burst <= 1'b0;
+			end
 		end
+	end
 end
 
 reg wb_burst;
@@ -388,11 +337,10 @@ assign sd_reading = sd_stb & sd_cyc & ~sd_we;
 assign sd_writing = sd_stb & sd_cyc & sd_we;
 
 // drive control signals according to current command
-assign sd_cs_n  = sd_ready 	? sd_cmd[3] : sd_init_cmd[3];
-assign sd_ras_n = sd_ready 	? sd_cmd[2] : sd_init_cmd[2];
-assign sd_cas_n = sd_ready 	? sd_cmd[1] : sd_init_cmd[1];
-assign sd_we_n  = sd_ready 	? sd_cmd[0] : sd_init_cmd[0];
-assign sd_addr	= sd_ready	? sd_a		: sd_init_a;
+assign sd_cs_n  = sd_cmd[3];
+assign sd_ras_n = sd_cmd[2];
+assign sd_cas_n = sd_cmd[1];
+assign sd_we_n  = sd_cmd[0];
 assign sd_cke	= 1'b1;
 
 endmodule
diff --git a/cores/c16/c1541/c1541_sd.vhd b/cores/c16/c1541/c1541_sd.vhd
index 86a954b..1fe44ae 100644
--- a/cores/c16/c1541/c1541_sd.vhd
+++ b/cores/c16/c1541/c1541_sd.vhd
@@ -8,13 +8,11 @@
 --
 -- c1541_logic    from : Mark McDougall
 -- spi_controller from : Michel Stempin, Stephen A. Edwards
--- via6522        from : Arnim Laeuger, Mark McDougall, MikeJ
+-- via6522        from : Gideon Zweijtzer  <gideon.zweijtzer@gmail.com>
 -- T65            from : Daniel Wallner, MikeJ, ehenciak
 --
--- c1541_logic    modified for : slow down CPU (EOI ack missed by real c64)
---                             : remove iec internal OR wired
---                             : synched atn_in (sometime no IRQ with real c64)
--- spi_controller modified for : sector start and size adapted + busy signal
+-- c1541_logic    modified for  : remove iec internal OR wired
+-- spi_controller replaced with mist_sd_card
 -- via6522        modified for : no modification
 --
 --
@@ -35,6 +33,7 @@ port(
 	
 	disk_num : in std_logic_vector(9 downto 0);
 	disk_change : in std_logic;
+	disk_readonly : in std_logic;
 
 	iec_atn_i  : in std_logic;
 	iec_data_i : in std_logic;
@@ -111,6 +110,9 @@ signal track_modified   : std_logic;
 signal sector_offset    : std_logic;
 signal save_track_stage : std_logic_vector(3 downto 0);
 
+signal wps_flag : std_logic;
+signal change_timer : integer;
+
 signal dbg_sector : std_logic_vector(4 downto 0); 
 signal dbg_adr_fetch : std_logic_vector(15 downto 0); 
 
@@ -173,7 +175,7 @@ begin
     freq            => freq,     -- motor frequency
     sync_n          => sync_n,   -- reading SYNC bytes
     byte_n          => byte_n,   -- byte ready
-    wps_n           => '1',      -- write-protect sense (0 = protected)
+    wps_n           => not wps_flag,      -- write-protect sense (0 = protected)
     tr00_sense_n    => '1',      -- track 0 sense (unused?)
     act             => act,      -- activity LED
 
@@ -267,7 +269,22 @@ port map
 --
 --	dbg_state => dbg_sd_state
 --);
-	
+
+wps_flag <= disk_readonly when change_timer = 0 else not disk_readonly;
+
+process (clk32,reset)
+begin
+	if reset = '1' then
+		change_timer <= 0;
+	elsif rising_edge(clk32) then
+		if disk_change = '1' then
+			change_timer <= 1000000;
+		elsif change_timer /= 0 then
+			change_timer <= change_timer - 1;
+		end if;
+	end if;
+end process;
+
 process (clk32)
 begin
 	if rising_edge(clk32) then
diff --git a/cores/c16/c16_mist.qsf b/cores/c16/c16_mist.qsf
index 85f6097..5d54c9f 100644
--- a/cores/c16/c16_mist.qsf
+++ b/cores/c16/c16_mist.qsf
@@ -127,7 +127,7 @@ set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
 
 # Analysis & Synthesis Assignments
 # ================================
-set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
 set_global_assignment -name FAMILY "Cyclone III"
 set_global_assignment -name TOP_LEVEL_ENTITY c16_mist
 set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP
@@ -144,7 +144,7 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
 set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
 set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ON
 set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA ON
-set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA
+set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
 set_global_assignment -name DEVICE EP3C25E144C8
 set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL"
 set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
@@ -324,8 +324,6 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CONF_DATA0
 set_global_assignment -name VERILOG_INPUT_VERSION VERILOG_2001
 set_global_assignment -name VERILOG_SHOW_LMF_MAPPING_MESSAGES OFF
 set_global_assignment -name VHDL_FILE gen_ram.vhd
-set_global_assignment -name QIP_FILE pll_ntsc.qip
-set_global_assignment -name QIP_FILE pll_pal.qip
 set_global_assignment -name VERILOG_FILE data_io.v
 set_global_assignment -name VERILOG_FILE sdram.v
 set_global_assignment -name VERILOG_FILE osd.v
@@ -353,4 +351,10 @@ set_global_assignment -name VHDL_FILE t65/T65_ALU.vhd
 set_global_assignment -name VHDL_FILE t65/T65.vhd
 set_global_assignment -name SIGNALTAP_FILE output_files/stp1.stp
 set_global_assignment -name SYSTEMVERILOG_FILE rgb2ypbpr.sv
+set_global_assignment -name QIP_FILE pll_c1541.qip
+set_global_assignment -name QIP_FILE pll_c16.qip
+set_global_assignment -name QIP_FILE rom_reconfig_pal.qip
+set_global_assignment -name QIP_FILE rom_reconfig_ntsc.qip
+set_global_assignment -name QIP_FILE pll_reconfig.qip
+set_global_assignment -name ENABLE_DRC_SETTINGS ON
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/cores/c16/c16_mist.sdc b/cores/c16/c16_mist.sdc
index 45e736e..f80a943 100644
--- a/cores/c16/c16_mist.sdc
+++ b/cores/c16/c16_mist.sdc
@@ -33,21 +33,22 @@ derive_pll_clocks -create_base_clocks
 derive_clock_uncertainty
 
 # Clock groups
-set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[*]}]
-set_clock_groups -asynchronous -group [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[1]}] -group [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[0]}]
-set_clock_groups -asynchronous -group [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[1]}] -group [get_clocks {pll_ntsc|altpll_component|auto_generated|pll1|clk[0]}]
-
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll_c1541|altpll_component|auto_generated|pll1|clk[*]}]
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[*]}]
+set_clock_groups -asynchronous -group [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[*]}] -group [get_clocks {pll_c1541|altpll_component|auto_generated|pll1|clk[*]}]
 
 # Some relaxed constrain to the VGA pins. The signals should arrive together, the delay is not really important.
-set_output_delay -clock [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[0]}] -max 0 [get_ports {VGA_*}]
-set_output_delay -clock [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[0]}] -min -5 [get_ports {VGA_*}]
+set_output_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -max 0 [get_ports {VGA_*}]
+set_output_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -min -5 [get_ports {VGA_*}]
 
 # SDRAM delays
-set_input_delay -clock [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[0]}] -max 6.4 [get_ports SDRAM_DQ[*]]
-set_input_delay -clock [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[0]}] -min 3.2 [get_ports SDRAM_DQ[*]]
+set_input_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -max 6.4 [get_ports SDRAM_DQ[*]]
+set_input_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -min 3.2 [get_ports SDRAM_DQ[*]]
 
-set_output_delay -clock [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
-set_output_delay -clock [get_clocks {pll_pal|altpll_component|auto_generated|pll1|clk[0]}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+set_output_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+set_output_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+set_output_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_ports {SDRAM_CLK}]
+set_output_delay -clock [get_clocks {pll_c16|altpll_component|auto_generated|pll1|clk[0]}] -min -0.8 [get_ports {SDRAM_CLK}]
 
 set_false_path -to [get_ports {AUDIO_L}]
 set_false_path -to [get_ports {AUDIO_R}]
diff --git a/cores/c16/c16_mist.v b/cores/c16/c16_mist.v
index 8d477b1..e2f5a91 100644
--- a/cores/c16/c16_mist.v
+++ b/cores/c16/c16_mist.v
@@ -57,7 +57,6 @@ module c16_mist (
    output [5:0]  VGA_B
 );
 
-parameter MODE_PAL = 1'b1;
 // -------------------------------------------------------------------------
 // ------------------------------ user_io ----------------------------------
 // -------------------------------------------------------------------------
@@ -72,13 +71,14 @@ parameter MODE_PAL = 1'b1;
 parameter CONF_STR = {
         "C16;PRG;",
 		  "S,D64,Mount Disk;",
+        "F,ROM,Load Kernal;",
         "O2,Scanlines,Off,On;",
         "O3,Joysticks,Normal,Swapped;",
 		  "O4,Memory,64k,16k;",
         "T5,Reset;"
 };
 
-parameter CONF_STR_LEN = 8+17+20+28+18+9;
+parameter CONF_STR_LEN = 8+17+18+20+28+18+9;
 
 // the status register is controlled by the on screen display (OSD)
 wire [7:0] status;
@@ -277,7 +277,7 @@ wire [7:0] ioctl_data;
 wire [4:0] ioctl_index;
 wire ioctl_downloading;
 
-wire rom_download = ioctl_downloading && (ioctl_index == 5'd0);
+wire rom_download = ioctl_downloading && ((ioctl_index == 5'd0) || (ioctl_index == 5'd3));
 wire prg_download = ioctl_downloading && (ioctl_index == 5'd1);
 
 // halt cpu when it's done with the current cycle
@@ -511,15 +511,15 @@ always @(negedge clk28) begin
 	if(ioctl_rom_wr && !last_ioctl_rom_wr) begin
 		rom_dl_data  <= ioctl_data;
 		rom_dl_addr  <= ioctl_addr[13:0];
-		c1541_dl_wr  <= !ioctl_addr[15:14];
-		kernal_dl_wr <= ioctl_addr[15:14] == 2'd1;
-		basic_dl_wr  <= ioctl_addr[15:14] == 2'd2;
+		c1541_dl_wr  <= !ioctl_addr[15:14] && ioctl_index == 5'd0;
+		kernal_dl_wr <= ioctl_addr[15:14] == 2'd1 || ioctl_index == 5'd3;
+		basic_dl_wr  <= ioctl_addr[15:14] == 2'd2 && ioctl_index == 5'd0;
 	end else
 		{ kernal_dl_wr, basic_dl_wr, c1541_dl_wr } <= 0;
 end
 
 // include the c16 itself
-C16 #(.MODE_PAL(MODE_PAL)) c16 (
+C16 c16 (
 	.CLK28   ( clk28 ),
 	.RESET   ( reset ),
 	.WAIT    ( c16_wait ),
@@ -571,8 +571,8 @@ C16 #(.MODE_PAL(MODE_PAL)) c16 (
 
 // the FPGATED uses two different clocks for NTSC and PAL mode.
 // Switching the clocks may crash the system. We might need to force a reset it.
-wire clk28 = MODE_PAL?clk28_pal:clk28_ntsc;
-wire pll_locked = pll_pal_locked && pll_ntsc_locked;
+wire pll_locked = pll_c1541_locked && pll_c16_locked;
+wire ntsc = ~c16_pal;
 
 // tv15hkz has quarter the pixel rate, so we need a 7mhz clock for the OSD
 reg clk7;
@@ -588,22 +588,127 @@ always @(posedge clk28) begin
 end
 
 // A PLL to derive the system clock from the MiSTs 27MHz
-wire clk32;
-wire pll_pal_locked, clk28_pal;
-pll_pal pll_pal (
-	 .inclk0( CLOCK_27        ),
-	 .c0(     clk28_pal       ),
-	 .c1(     clk32           ),
-	 .locked( pll_pal_locked  )
+wire pll_c1541_locked, clk32;
+pll_c1541 pll_c1541 (
+    .inclk0 ( CLOCK_27          ),
+    .c0     ( clk32             ),
+    .locked ( pll_c1541_locked  )
 );
 
-wire pll_ntsc_locked, clk28_ntsc;
-pll_ntsc pll_ntsc (
-	 .inclk0( CLOCK_27         ),
-	 .c0(     clk28_ntsc       ),
-	 .locked( pll_ntsc_locked  )
+wire pll_c16_locked, clk28;
+pll_c16 pll_c16 (
+    .inclk0(CLOCK_27),
+    .c0(clk28),
+    .areset(pll_areset),
+    .scanclk(pll_scanclk),
+    .scandata(pll_scandata),
+    .scanclkena(pll_scanclkena),
+    .configupdate(pll_configupdate),
+    .scandataout(pll_scandataout),
+    .scandone(pll_scandone),
+    .locked(pll_c16_locked)
 );
 
+wire       pll_reconfig_busy;
+wire       pll_areset;
+wire       pll_configupdate;
+wire       pll_scanclk;
+wire       pll_scanclkena;
+wire       pll_scandata;
+wire       pll_scandataout;
+wire       pll_scandone;
+reg        pll_reconfig_reset;
+wire [7:0] pll_rom_address;
+wire       pll_rom_q;
+reg        pll_write_from_rom;
+wire       pll_write_rom_ena;
+reg        pll_reconfig;
+wire       q_reconfig_ntsc;
+wire       q_reconfig_pal;
+
+rom_reconfig_pal rom_reconfig_pal
+(
+    .address(pll_rom_address),
+    .clock(clk32),
+    .rden(pll_write_rom_ena),
+    .q(q_reconfig_pal)
+);
+
+rom_reconfig_ntsc rom_reconfig_ntsc
+(
+    .address(pll_rom_address),
+    .clock(clk32),
+    .rden(pll_write_rom_ena),
+    .q(q_reconfig_ntsc)
+);
+
+assign pll_rom_q = ntsc ? q_reconfig_ntsc : q_reconfig_pal;
+
+pll_reconfig pll_reconfig_inst
+(
+    .busy(pll_reconfig_busy),
+    .clock(clk32),
+    .counter_param(0),
+    .counter_type(0),
+    .data_in(0),
+    .pll_areset(pll_areset),
+    .pll_areset_in(0),
+    .pll_configupdate(pll_configupdate),
+    .pll_scanclk(pll_scanclk),
+    .pll_scanclkena(pll_scanclkena),
+    .pll_scandata(pll_scandata),
+    .pll_scandataout(pll_scandataout),
+    .pll_scandone(pll_scandone),
+    .read_param(0),
+    .reconfig(pll_reconfig),
+    .reset(pll_reconfig_reset),
+    .reset_rom_address(0),
+    .rom_address_out(pll_rom_address),
+    .rom_data_in(pll_rom_q),
+    .write_from_rom(pll_write_from_rom),
+    .write_param(0),
+    .write_rom_ena(pll_write_rom_ena)
+);
+
+always @(posedge clk32) begin
+    reg ntsc_d, ntsc_d2, ntsc_d3;
+    reg [1:0] pll_reconfig_state = 0;
+    reg [9:0] pll_reconfig_timeout;
+
+    ntsc_d <= ntsc;
+    ntsc_d2 <= ntsc_d;
+    pll_write_from_rom <= 0;
+    pll_reconfig <= 0;
+    pll_reconfig_reset <= 0;
+    case (pll_reconfig_state)
+    2'b00:
+    begin
+        ntsc_d3 <= ntsc_d2;
+        if (ntsc_d2 ^ ntsc_d3) begin
+            pll_write_from_rom <= 1;
+            pll_reconfig_state <= 2'b01;
+        end
+    end
+    2'b01: pll_reconfig_state <= 2'b10;
+    2'b10:
+        if (~pll_reconfig_busy) begin
+            pll_reconfig <= 1;
+            pll_reconfig_state <= 2'b11;
+            pll_reconfig_timeout <= 10'd1000;
+        end
+    2'b11:
+    begin
+        pll_reconfig_timeout <= pll_reconfig_timeout - 1'd1;
+        if (pll_reconfig_timeout == 10'd1) begin
+            // pll_reconfig stuck in busy state
+            pll_reconfig_reset <= 1;
+            pll_reconfig_state <= 2'b00;
+        end
+        if (~pll_reconfig & ~pll_reconfig_busy) pll_reconfig_state <= 2'b00;
+    end
+    default: ;
+    endcase
+end
 // ---------------------------------------------------------------------------------
 // ----------------------------------- floppy 1541 ---------------------------------
 // ---------------------------------------------------------------------------------
diff --git a/cores/c16/osd.v b/cores/c16/osd.v
index 460fb0d..cf32be8 100644
--- a/cores/c16/osd.v
+++ b/cores/c16/osd.v
@@ -141,8 +141,9 @@ end
 reg [9:0] v_cnt;
 reg [9:0] vs_low, vs_high;
 wire vs_pol = vs_high < vs_low;
-wire [9:0] v_dsp_width = vs_pol?vs_low:vs_high;
-wire [9:0] v_dsp_ctr = { 1'b0, v_dsp_width[9:1] };
+wire [9:0] v_dsp_height = vs_pol?vs_low:vs_high;
+wire [9:0] v_dsp_ctr = { 1'b0, v_dsp_height[9:1] };
+wire doublescan = (v_dsp_height>350);
 
 always @(posedge clk_sys) begin
 	reg hsD, vsD;
@@ -172,8 +173,8 @@ end
 // area in which OSD is being displayed
 wire [9:0] h_osd_start = h_dsp_ctr + OSD_X_OFFSET - (OSD_WIDTH >> 1);
 wire [9:0] h_osd_end   = h_dsp_ctr + OSD_X_OFFSET + (OSD_WIDTH >> 1) - 1;
-wire [9:0] v_osd_start = v_dsp_ctr + OSD_Y_OFFSET - (OSD_HEIGHT >> 1);
-wire [9:0] v_osd_end   = v_dsp_ctr + OSD_Y_OFFSET + (OSD_HEIGHT >> 1) - 1;
+wire [9:0] v_osd_start = v_dsp_ctr + OSD_Y_OFFSET - (doublescan ? OSD_HEIGHT : OSD_HEIGHT >> 1);
+wire [9:0] v_osd_end   = v_dsp_ctr + OSD_Y_OFFSET + (doublescan ? OSD_HEIGHT : OSD_HEIGHT >> 1) - 1;
 
 reg h_osd_active, v_osd_active;
 always @(posedge clk_sys) begin
@@ -189,14 +190,12 @@ end
 
 wire osd_de = osd_enable && h_osd_active && v_osd_active;
 
-wire [7:0] osd_hcnt = h_cnt - h_osd_start + 7'd1;  // one pixel offset for osd_byte register
-wire [6:0] osd_vcnt = v_cnt - v_osd_start;
-
-wire osd_pixel = osd_byte[osd_vcnt[3:1]];
+wire [9:0] osd_hcnt = h_cnt - h_osd_start + 7'd1;  // one pixel offset for osd_byte register
+wire [9:0] osd_vcnt = v_cnt - v_osd_start;
 
 reg [7:0] osd_byte; 
-always @(posedge clk_sys)
-  if (ce_pix) osd_byte <= osd_buffer[{osd_vcnt[6:4], osd_hcnt}];
+always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}];
+wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]];
 
 wire [2:0] osd_color = OSD_COLOR;
 assign red_out   = !osd_de?red_in:  {osd_pixel, osd_pixel, osd_color[2], red_in[5:3]  };
diff --git a/cores/c16/pll_c1541.ppf b/cores/c16/pll_c1541.ppf
new file mode 100644
index 0000000..f99f613
--- /dev/null
+++ b/cores/c16/pll_c1541.ppf
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="pll_c1541" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
diff --git a/cores/c16/pll_ntsc.qip b/cores/c16/pll_c1541.qip
similarity index 82%
rename from cores/c16/pll_ntsc.qip
rename to cores/c16/pll_c1541.qip
index 4a8f47e..6cb00bc 100644
--- a/cores/c16/pll_ntsc.qip
+++ b/cores/c16/pll_c1541.qip
@@ -1,4 +1,4 @@
 set_global_assignment -name IP_TOOL_NAME "ALTPLL"
 set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_ntsc.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_ntsc.ppf"]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_c1541.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_c1541.ppf"]
diff --git a/cores/c16/pll_ntsc.v b/cores/c16/pll_c1541.v
similarity index 92%
rename from cores/c16/pll_ntsc.v
rename to cores/c16/pll_c1541.v
index 2a6abf2..2502ece 100644
--- a/cores/c16/pll_ntsc.v
+++ b/cores/c16/pll_c1541.v
@@ -4,7 +4,7 @@
 // MODULE: altpll 
 
 // ============================================================
-// File Name: pll_ntsc.v
+// File Name: pll_c1541.v
 // Megafunction Name(s):
 // 			altpll
 //
@@ -36,7 +36,7 @@
 // synopsys translate_off
 `timescale 1 ps / 1 ps
 // synopsys translate_on
-module pll_ntsc (
+module pll_c1541 (
 	inclk0,
 	c0,
 	locked);
@@ -94,14 +94,14 @@ module pll_ntsc (
 				.vcounderrange ());
 	defparam
 		altpll_component.bandwidth_type = "AUTO",
-		altpll_component.clk0_divide_by = 270000,
+		altpll_component.clk0_divide_by = 27,
 		altpll_component.clk0_duty_cycle = 50,
-		altpll_component.clk0_multiply_by = 286363,
+		altpll_component.clk0_multiply_by = 32,
 		altpll_component.clk0_phase_shift = "0",
 		altpll_component.compensate_clock = "CLK0",
 		altpll_component.inclk0_input_frequency = 37037,
 		altpll_component.intended_device_family = "Cyclone III",
-		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_ntsc",
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_c1541",
 		altpll_component.lpm_type = "altpll",
 		altpll_component.operation_mode = "NORMAL",
 		altpll_component.pll_type = "AUTO",
@@ -171,9 +171,9 @@ endmodule
 // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
 // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "183"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
 // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "28.636299"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "32.000000"
 // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -196,9 +196,9 @@ endmodule
 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
 // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
 // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "191"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
 // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.63630000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "32.00000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
@@ -216,7 +216,7 @@ endmodule
 // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
 // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
 // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_ntsc.mif"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_c1541.mif"
 // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
 // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
@@ -224,7 +224,7 @@ endmodule
 // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
 // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
 // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.000"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
 // Retrieval info: PRIVATE: SPREAD_USE STRING "0"
 // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
 // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
@@ -237,9 +237,9 @@ endmodule
 // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "270000"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
 // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "286363"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "32"
 // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
 // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
@@ -298,12 +298,12 @@ endmodule
 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.ppf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_ntsc_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c1541.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c1541.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c1541.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c1541.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c1541.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c1541_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c1541_bb.v FALSE
 // Retrieval info: LIB_FILE: altera_mf
 // Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/cores/c16/pll_c16.ppf b/cores/c16/pll_c16.ppf
new file mode 100644
index 0000000..d91f722
--- /dev/null
+++ b/cores/c16/pll_c16.ppf
@@ -0,0 +1,17 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="pll_c16" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="areset" direction="input" scope="external"  />
+<pin name="configupdate" direction="input" scope="external"  />
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="scanclk" direction="input" scope="external" source="clock"  />
+<pin name="scanclkena" direction="input" scope="external"  />
+<pin name="scandata" direction="input" scope="external"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+<pin name="scandataout" direction="output" scope="external"  />
+<pin name="scandone" direction="output" scope="external"  />
+
+</global>
+</pinplan>
diff --git a/cores/c16/pll_pal.qip b/cores/c16/pll_c16.qip
similarity index 84%
rename from cores/c16/pll_pal.qip
rename to cores/c16/pll_c16.qip
index 6c4dccc..4814ee0 100644
--- a/cores/c16/pll_pal.qip
+++ b/cores/c16/pll_c16.qip
@@ -1,4 +1,4 @@
 set_global_assignment -name IP_TOOL_NAME "ALTPLL"
 set_global_assignment -name IP_TOOL_VERSION "13.1"
-set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_pal.v"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_pal.ppf"]
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_c16.v"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_c16.ppf"]
diff --git a/cores/c16/pll_pal.v b/cores/c16/pll_c16.v
similarity index 73%
rename from cores/c16/pll_pal.v
rename to cores/c16/pll_c16.v
index d2028ba..5f36cd0 100644
--- a/cores/c16/pll_pal.v
+++ b/cores/c16/pll_c16.v
@@ -4,7 +4,7 @@
 // MODULE: altpll 
 
 // ============================================================
-// File Name: pll_pal.v
+// File Name: pll_c16.v
 // Megafunction Name(s):
 // 			altpll
 //
@@ -36,39 +36,68 @@
 // synopsys translate_off
 `timescale 1 ps / 1 ps
 // synopsys translate_on
-module pll_pal (
+module pll_c16 (
+	areset,
+	configupdate,
 	inclk0,
+	scanclk,
+	scanclkena,
+	scandata,
 	c0,
-	c1,
-	locked);
+	locked,
+	scandataout,
+	scandone);
 
+	input	  areset;
+	input	  configupdate;
 	input	  inclk0;
+	input	  scanclk;
+	input	  scanclkena;
+	input	  scandata;
 	output	  c0;
-	output	  c1;
 	output	  locked;
+	output	  scandataout;
+	output	  scandone;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  areset;
+	tri0	  configupdate;
+	tri0	  scanclkena;
+	tri0	  scandata;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
 
 	wire [4:0] sub_wire0;
 	wire  sub_wire2;
-	wire [0:0] sub_wire6 = 1'h0;
-	wire [0:0] sub_wire3 = sub_wire0[0:0];
-	wire [1:1] sub_wire1 = sub_wire0[1:1];
-	wire  c1 = sub_wire1;
-	wire  locked = sub_wire2;
-	wire  c0 = sub_wire3;
-	wire  sub_wire4 = inclk0;
-	wire [1:0] sub_wire5 = {sub_wire6, sub_wire4};
+	wire  sub_wire3;
+	wire  sub_wire4;
+	wire [0:0] sub_wire7 = 1'h0;
+	wire [0:0] sub_wire1 = sub_wire0[0:0];
+	wire  c0 = sub_wire1;
+	wire  scandataout = sub_wire2;
+	wire  scandone = sub_wire3;
+	wire  locked = sub_wire4;
+	wire  sub_wire5 = inclk0;
+	wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
 
 	altpll	altpll_component (
-				.inclk (sub_wire5),
+				.areset (areset),
+				.configupdate (configupdate),
+				.inclk (sub_wire6),
+				.scanclk (scanclk),
+				.scanclkena (scanclkena),
+				.scandata (scandata),
 				.clk (sub_wire0),
-				.locked (sub_wire2),
+				.scandataout (sub_wire2),
+				.scandone (sub_wire3),
+				.locked (sub_wire4),
 				.activeclock (),
-				.areset (1'b0),
 				.clkbad (),
 				.clkena ({6{1'b1}}),
 				.clkloss (),
 				.clkswitch (1'b0),
-				.configupdate (1'b0),
 				.enable0 (),
 				.enable1 (),
 				.extclk (),
@@ -85,11 +114,6 @@ module pll_pal (
 				.phaseupdown (1'b1),
 				.pllena (1'b1),
 				.scanaclr (1'b0),
-				.scanclk (1'b0),
-				.scanclkena (1'b1),
-				.scandata (1'b0),
-				.scandataout (),
-				.scandone (),
 				.scanread (1'b0),
 				.scanwrite (1'b0),
 				.sclkout0 (),
@@ -98,28 +122,24 @@ module pll_pal (
 				.vcounderrange ());
 	defparam
 		altpll_component.bandwidth_type = "AUTO",
-		altpll_component.clk0_divide_by = 39,
+		altpll_component.clk0_divide_by = 27000000,
 		altpll_component.clk0_duty_cycle = 50,
-		altpll_component.clk0_multiply_by = 41,
+		altpll_component.clk0_multiply_by = 28375151,
 		altpll_component.clk0_phase_shift = "0",
-		altpll_component.clk1_divide_by = 27,
-		altpll_component.clk1_duty_cycle = 50,
-		altpll_component.clk1_multiply_by = 32,
-		altpll_component.clk1_phase_shift = "0",
 		altpll_component.compensate_clock = "CLK0",
 		altpll_component.inclk0_input_frequency = 37037,
 		altpll_component.intended_device_family = "Cyclone III",
-		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_pal",
+		altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll_c16",
 		altpll_component.lpm_type = "altpll",
 		altpll_component.operation_mode = "NORMAL",
 		altpll_component.pll_type = "AUTO",
 		altpll_component.port_activeclock = "PORT_UNUSED",
-		altpll_component.port_areset = "PORT_UNUSED",
+		altpll_component.port_areset = "PORT_USED",
 		altpll_component.port_clkbad0 = "PORT_UNUSED",
 		altpll_component.port_clkbad1 = "PORT_UNUSED",
 		altpll_component.port_clkloss = "PORT_UNUSED",
 		altpll_component.port_clkswitch = "PORT_UNUSED",
-		altpll_component.port_configupdate = "PORT_UNUSED",
+		altpll_component.port_configupdate = "PORT_USED",
 		altpll_component.port_fbin = "PORT_UNUSED",
 		altpll_component.port_inclk0 = "PORT_USED",
 		altpll_component.port_inclk1 = "PORT_UNUSED",
@@ -131,15 +151,15 @@ module pll_pal (
 		altpll_component.port_phaseupdown = "PORT_UNUSED",
 		altpll_component.port_pllena = "PORT_UNUSED",
 		altpll_component.port_scanaclr = "PORT_UNUSED",
-		altpll_component.port_scanclk = "PORT_UNUSED",
-		altpll_component.port_scanclkena = "PORT_UNUSED",
-		altpll_component.port_scandata = "PORT_UNUSED",
-		altpll_component.port_scandataout = "PORT_UNUSED",
-		altpll_component.port_scandone = "PORT_UNUSED",
+		altpll_component.port_scanclk = "PORT_USED",
+		altpll_component.port_scanclkena = "PORT_USED",
+		altpll_component.port_scandata = "PORT_USED",
+		altpll_component.port_scandataout = "PORT_USED",
+		altpll_component.port_scandone = "PORT_USED",
 		altpll_component.port_scanread = "PORT_UNUSED",
 		altpll_component.port_scanwrite = "PORT_UNUSED",
 		altpll_component.port_clk0 = "PORT_USED",
-		altpll_component.port_clk1 = "PORT_USED",
+		altpll_component.port_clk1 = "PORT_UNUSED",
 		altpll_component.port_clk2 = "PORT_UNUSED",
 		altpll_component.port_clk3 = "PORT_UNUSED",
 		altpll_component.port_clk4 = "PORT_UNUSED",
@@ -155,7 +175,8 @@ module pll_pal (
 		altpll_component.port_extclk2 = "PORT_UNUSED",
 		altpll_component.port_extclk3 = "PORT_UNUSED",
 		altpll_component.self_reset_on_loss_lock = "OFF",
-		altpll_component.width_clock = 5;
+		altpll_component.width_clock = 5,
+		altpll_component.scan_chain_mif_file = "pll_c16_pal.mif";
 
 
 endmodule
@@ -179,12 +200,9 @@ endmodule
 // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
 // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "39"
-// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
 // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "28.384615"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "32.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "28.375153"
 // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -205,28 +223,20 @@ endmodule
 // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
 // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
 // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
 // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
 // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
-// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
-// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "41"
-// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
+// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
 // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
-// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.37500000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "32.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
+// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "28.37515200"
+// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
-// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
 // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
 // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
-// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
 // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
-// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
+// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
 // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
 // Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
 // Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
@@ -235,38 +245,31 @@ endmodule
 // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
 // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
 // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
-// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_pal.mif"
-// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
+// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_c16_pal.mif"
+// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1"
 // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
 // Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
 // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
 // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
 // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
-// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.000"
+// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
 // Retrieval info: PRIVATE: SPREAD_USE STRING "0"
 // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
 // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
-// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
 // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
 // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 // Retrieval info: PRIVATE: USE_CLK0 STRING "1"
-// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
 // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
-// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
 // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
 // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
-// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "39"
+// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27000000"
 // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "41"
+// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "28375151"
 // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
-// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "32"
-// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
@@ -274,12 +277,12 @@ endmodule
 // Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
 // Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
 // Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
@@ -291,15 +294,15 @@ endmodule
 // Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
-// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
+// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_USED"
 // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
-// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
@@ -316,22 +319,38 @@ endmodule
 // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
 // Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "OFF"
 // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+// Retrieval info: CONSTANT: scan_chain_mif_file STRING "pll_c16_pal.mif"
 // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
 // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
-// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+// Retrieval info: USED_PORT: configupdate 0 0 0 0 INPUT GND "configupdate"
 // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
 // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+// Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
+// Retrieval info: USED_PORT: scanclkena 0 0 0 0 INPUT GND "scanclkena"
+// Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata"
+// Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout"
+// Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone"
+// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+// Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0
 // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+// Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
+// Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
+// Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.v TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.ppf TRUE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.inc FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.cmp FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal.bsf FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_inst.v FALSE
-// Retrieval info: GEN_FILE: TYPE_NORMAL pll_pal_bb.v FALSE
+// Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0
+// Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16.ppf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16_bb.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16.mif FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16_ntsc.mif TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_c16_pal.mif TRUE
 // Retrieval info: LIB_FILE: altera_mf
 // Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/cores/c16/pll_c16_ntsc.mif b/cores/c16/pll_c16_ntsc.mif
new file mode 100644
index 0000000..cf24b53
--- /dev/null
+++ b/cores/c16/pll_c16_ntsc.mif
@@ -0,0 +1,174 @@
+-- Copyright (C) 1991-2014 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- MIF file representing initial state of PLL Scan Chain
+--    Device Family: Cyclone III
+--    Device Part: -
+--    Device Speed Grade: 8
+--    PLL Scan Chain: Fast PLL (144 bits)
+--    File Name: /home/gyurco/git/mist-board/cores/c16/pll_c16_ntsc.mif
+--    Generated: Thu Feb 14 11:24:12 2019
+
+WIDTH=1;
+DEPTH=144;
+
+ADDRESS_RADIX=UNS;
+DATA_RADIX=UNS;
+
+CONTENT BEGIN
+	0    :   0; -- Reserved Bits = 0 (1 bit(s))
+	1    :   0; -- Reserved Bits = 0 (1 bit(s))
+	2    :   0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
+	3    :   0;
+	4    :   1; -- Loop Filter Resistance = 16 (5 bit(s)) (Setting 16)
+	5    :   0;
+	6    :   0;
+	7    :   0;
+	8    :   0;
+	9    :   0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2)
+	10   :   0; -- Reserved Bits = 0 (5 bit(s))
+	11   :   0;
+	12   :   0;
+	13   :   0;
+	14   :   0;
+	15   :   0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
+	16   :   0;
+	17   :   1;
+	18   :   0; -- N counter: Bypass = 0 (1 bit(s))
+	19   :   0; -- N counter: High Count = 2 (8 bit(s))
+	20   :   0;
+	21   :   0;
+	22   :   0;
+	23   :   0;
+	24   :   0;
+	25   :   1;
+	26   :   0;
+	27   :   1; -- N counter: Odd Division = 1 (1 bit(s))
+	28   :   0; -- N counter: Low Count = 1 (8 bit(s))
+	29   :   0;
+	30   :   0;
+	31   :   0;
+	32   :   0;
+	33   :   0;
+	34   :   0;
+	35   :   1;
+	36   :   0; -- M counter: Bypass = 0 (1 bit(s))
+	37   :   0; -- M counter: High Count = 35 (8 bit(s))
+	38   :   0;
+	39   :   1;
+	40   :   0;
+	41   :   0;
+	42   :   0;
+	43   :   1;
+	44   :   1;
+	45   :   0; -- M counter: Odd Division = 0 (1 bit(s))
+	46   :   0; -- M counter: Low Count = 35 (8 bit(s))
+	47   :   0;
+	48   :   1;
+	49   :   0;
+	50   :   0;
+	51   :   0;
+	52   :   1;
+	53   :   1;
+	54   :   0; -- clk0 counter: Bypass = 0 (1 bit(s))
+	55   :   0; -- clk0 counter: High Count = 11 (8 bit(s))
+	56   :   0;
+	57   :   0;
+	58   :   0;
+	59   :   1;
+	60   :   0;
+	61   :   1;
+	62   :   1;
+	63   :   0; -- clk0 counter: Odd Division = 0 (1 bit(s))
+	64   :   0; -- clk0 counter: Low Count = 11 (8 bit(s))
+	65   :   0;
+	66   :   0;
+	67   :   0;
+	68   :   1;
+	69   :   0;
+	70   :   1;
+	71   :   1;
+	72   :   1; -- clk1 counter: Bypass = 1 (1 bit(s))
+	73   :   0; -- clk1 counter: High Count = 0 (8 bit(s))
+	74   :   0;
+	75   :   0;
+	76   :   0;
+	77   :   0;
+	78   :   0;
+	79   :   0;
+	80   :   0;
+	81   :   0; -- clk1 counter: Odd Division = 0 (1 bit(s))
+	82   :   0; -- clk1 counter: Low Count = 0 (8 bit(s))
+	83   :   0;
+	84   :   0;
+	85   :   0;
+	86   :   0;
+	87   :   0;
+	88   :   0;
+	89   :   0;
+	90   :   1; -- clk2 counter: Bypass = 1 (1 bit(s))
+	91   :   0; -- clk2 counter: High Count = 0 (8 bit(s))
+	92   :   0;
+	93   :   0;
+	94   :   0;
+	95   :   0;
+	96   :   0;
+	97   :   0;
+	98   :   0;
+	99   :   0; -- clk2 counter: Odd Division = 0 (1 bit(s))
+	100  :   0; -- clk2 counter: Low Count = 0 (8 bit(s))
+	101  :   0;
+	102  :   0;
+	103  :   0;
+	104  :   0;
+	105  :   0;
+	106  :   0;
+	107  :   0;
+	108  :   1; -- clk3 counter: Bypass = 1 (1 bit(s))
+	109  :   0; -- clk3 counter: High Count = 0 (8 bit(s))
+	110  :   0;
+	111  :   0;
+	112  :   0;
+	113  :   0;
+	114  :   0;
+	115  :   0;
+	116  :   0;
+	117  :   0; -- clk3 counter: Odd Division = 0 (1 bit(s))
+	118  :   0; -- clk3 counter: Low Count = 0 (8 bit(s))
+	119  :   0;
+	120  :   0;
+	121  :   0;
+	122  :   0;
+	123  :   0;
+	124  :   0;
+	125  :   0;
+	126  :   1; -- clk4 counter: Bypass = 1 (1 bit(s))
+	127  :   0; -- clk4 counter: High Count = 0 (8 bit(s))
+	128  :   0;
+	129  :   0;
+	130  :   0;
+	131  :   0;
+	132  :   0;
+	133  :   0;
+	134  :   0;
+	135  :   0; -- clk4 counter: Odd Division = 0 (1 bit(s))
+	136  :   0; -- clk4 counter: Low Count = 0 (8 bit(s))
+	137  :   0;
+	138  :   0;
+	139  :   0;
+	140  :   0;
+	141  :   0;
+	142  :   0;
+	143  :   0;
+END;
diff --git a/cores/c16/pll_c16_pal.mif b/cores/c16/pll_c16_pal.mif
new file mode 100644
index 0000000..1e58c39
--- /dev/null
+++ b/cores/c16/pll_c16_pal.mif
@@ -0,0 +1,174 @@
+-- Copyright (C) 1991-2014 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- MIF file representing initial state of PLL Scan Chain
+--    Device Family: Cyclone III
+--    Device Part: -
+--    Device Speed Grade: 8
+--    PLL Scan Chain: Fast PLL (144 bits)
+--    File Name: /home/gyurco/git/mist-board/cores/c16/pll_c16_pal.mif
+--    Generated: Thu Feb 14 11:25:48 2019
+
+WIDTH=1;
+DEPTH=144;
+
+ADDRESS_RADIX=UNS;
+DATA_RADIX=UNS;
+
+CONTENT BEGIN
+	0    :   0; -- Reserved Bits = 0 (1 bit(s))
+	1    :   0; -- Reserved Bits = 0 (1 bit(s))
+	2    :   0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
+	3    :   0;
+	4    :   1; -- Loop Filter Resistance = 20 (5 bit(s)) (Setting 20)
+	5    :   0;
+	6    :   1;
+	7    :   0;
+	8    :   0;
+	9    :   0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2)
+	10   :   0; -- Reserved Bits = 0 (5 bit(s))
+	11   :   0;
+	12   :   0;
+	13   :   0;
+	14   :   0;
+	15   :   0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
+	16   :   0;
+	17   :   1;
+	18   :   0; -- N counter: Bypass = 0 (1 bit(s))
+	19   :   0; -- N counter: High Count = 2 (8 bit(s))
+	20   :   0;
+	21   :   0;
+	22   :   0;
+	23   :   0;
+	24   :   0;
+	25   :   1;
+	26   :   0;
+	27   :   1; -- N counter: Odd Division = 1 (1 bit(s))
+	28   :   0; -- N counter: Low Count = 1 (8 bit(s))
+	29   :   0;
+	30   :   0;
+	31   :   0;
+	32   :   0;
+	33   :   0;
+	34   :   0;
+	35   :   1;
+	36   :   0; -- M counter: Bypass = 0 (1 bit(s))
+	37   :   0; -- M counter: High Count = 21 (8 bit(s))
+	38   :   0;
+	39   :   0;
+	40   :   1;
+	41   :   0;
+	42   :   1;
+	43   :   0;
+	44   :   1;
+	45   :   1; -- M counter: Odd Division = 1 (1 bit(s))
+	46   :   0; -- M counter: Low Count = 20 (8 bit(s))
+	47   :   0;
+	48   :   0;
+	49   :   1;
+	50   :   0;
+	51   :   1;
+	52   :   0;
+	53   :   0;
+	54   :   0; -- clk0 counter: Bypass = 0 (1 bit(s))
+	55   :   0; -- clk0 counter: High Count = 7 (8 bit(s))
+	56   :   0;
+	57   :   0;
+	58   :   0;
+	59   :   0;
+	60   :   1;
+	61   :   1;
+	62   :   1;
+	63   :   1; -- clk0 counter: Odd Division = 1 (1 bit(s))
+	64   :   0; -- clk0 counter: Low Count = 6 (8 bit(s))
+	65   :   0;
+	66   :   0;
+	67   :   0;
+	68   :   0;
+	69   :   1;
+	70   :   1;
+	71   :   0;
+	72   :   1; -- clk1 counter: Bypass = 1 (1 bit(s))
+	73   :   0; -- clk1 counter: High Count = 0 (8 bit(s))
+	74   :   0;
+	75   :   0;
+	76   :   0;
+	77   :   0;
+	78   :   0;
+	79   :   0;
+	80   :   0;
+	81   :   0; -- clk1 counter: Odd Division = 0 (1 bit(s))
+	82   :   0; -- clk1 counter: Low Count = 0 (8 bit(s))
+	83   :   0;
+	84   :   0;
+	85   :   0;
+	86   :   0;
+	87   :   0;
+	88   :   0;
+	89   :   0;
+	90   :   1; -- clk2 counter: Bypass = 1 (1 bit(s))
+	91   :   0; -- clk2 counter: High Count = 0 (8 bit(s))
+	92   :   0;
+	93   :   0;
+	94   :   0;
+	95   :   0;
+	96   :   0;
+	97   :   0;
+	98   :   0;
+	99   :   0; -- clk2 counter: Odd Division = 0 (1 bit(s))
+	100  :   0; -- clk2 counter: Low Count = 0 (8 bit(s))
+	101  :   0;
+	102  :   0;
+	103  :   0;
+	104  :   0;
+	105  :   0;
+	106  :   0;
+	107  :   0;
+	108  :   1; -- clk3 counter: Bypass = 1 (1 bit(s))
+	109  :   0; -- clk3 counter: High Count = 0 (8 bit(s))
+	110  :   0;
+	111  :   0;
+	112  :   0;
+	113  :   0;
+	114  :   0;
+	115  :   0;
+	116  :   0;
+	117  :   0; -- clk3 counter: Odd Division = 0 (1 bit(s))
+	118  :   0; -- clk3 counter: Low Count = 0 (8 bit(s))
+	119  :   0;
+	120  :   0;
+	121  :   0;
+	122  :   0;
+	123  :   0;
+	124  :   0;
+	125  :   0;
+	126  :   1; -- clk4 counter: Bypass = 1 (1 bit(s))
+	127  :   0; -- clk4 counter: High Count = 0 (8 bit(s))
+	128  :   0;
+	129  :   0;
+	130  :   0;
+	131  :   0;
+	132  :   0;
+	133  :   0;
+	134  :   0;
+	135  :   0; -- clk4 counter: Odd Division = 0 (1 bit(s))
+	136  :   0; -- clk4 counter: Low Count = 0 (8 bit(s))
+	137  :   0;
+	138  :   0;
+	139  :   0;
+	140  :   0;
+	141  :   0;
+	142  :   0;
+	143  :   0;
+END;
diff --git a/cores/c16/pll_reconfig.qip b/cores/c16/pll_reconfig.qip
new file mode 100644
index 0000000..7754768
--- /dev/null
+++ b/cores/c16/pll_reconfig.qip
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL_RECONFIG"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll_reconfig.v"]
diff --git a/cores/c16/pll_reconfig.v b/cores/c16/pll_reconfig.v
new file mode 100644
index 0000000..e3f99c8
--- /dev/null
+++ b/cores/c16/pll_reconfig.v
@@ -0,0 +1,1624 @@
+// megafunction wizard: %ALTPLL_RECONFIG%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altpll_reconfig 
+
+// ============================================================
+// File Name: pll_reconfig.v
+// Megafunction Name(s):
+// 			altpll_reconfig
+//
+// Simulation Library Files(s):
+// 			altera_mf;cycloneiii;lpm
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.4 Build 182 03/12/2014 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2014 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+//altpll_reconfig CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone III" init_from_rom="NO" scan_init_file="./pll_c16_pal.mif" busy clock counter_param counter_type data_in data_out pll_areset pll_areset_in pll_configupdate pll_scanclk pll_scanclkena pll_scandata pll_scandataout pll_scandone read_param reconfig reset reset_rom_address rom_address_out rom_data_in write_from_rom write_param write_rom_ena
+//VERSION_BEGIN 13.1 cbx_altpll_reconfig 2014:03:12:19:24:28:SJ cbx_altsyncram 2014:03:12:19:24:28:SJ cbx_cycloneii 2014:03:12:19:24:28:SJ cbx_lpm_add_sub 2014:03:12:19:24:28:SJ cbx_lpm_compare 2014:03:12:19:24:28:SJ cbx_lpm_counter 2014:03:12:19:24:28:SJ cbx_lpm_decode 2014:03:12:19:24:28:SJ cbx_lpm_mux 2014:03:12:19:24:28:SJ cbx_mgl 2014:03:12:19:35:38:SJ cbx_stratix 2014:03:12:19:24:28:SJ cbx_stratixii 2014:03:12:19:24:28:SJ cbx_stratixiii 2014:03:12:19:24:28:SJ cbx_stratixv 2014:03:12:19:24:28:SJ cbx_util_mgl 2014:03:12:19:24:28:SJ  VERSION_END
+// synthesis VERILOG_INPUT_VERSION VERILOG_2001
+// altera message_off 10463
+
+
+//synthesis_resources = altsyncram 1 lpm_add_sub 2 lpm_compare 1 lpm_counter 8 lpm_decode 1 lut 3 reg 102 
+//synopsys translate_off
+`timescale 1 ps / 1 ps
+//synopsys translate_on
+(* ALTERA_ATTRIBUTE = {"ADV_NETLIST_OPT_ALLOWED=\"NEVER_ALLOW\";suppress_da_rule_internal=C106;{-to le_comb10} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=2;{-to le_comb8} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=0;{-to le_comb9} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=1"} *)
+module  pll_reconfig_pllrcfg_dc61
+	( 
+	busy,
+	clock,
+	counter_param,
+	counter_type,
+	data_in,
+	data_out,
+	pll_areset,
+	pll_areset_in,
+	pll_configupdate,
+	pll_scanclk,
+	pll_scanclkena,
+	pll_scandata,
+	pll_scandataout,
+	pll_scandone,
+	read_param,
+	reconfig,
+	reset,
+	reset_rom_address,
+	rom_address_out,
+	rom_data_in,
+	write_from_rom,
+	write_param,
+	write_rom_ena) /* synthesis synthesis_clearbox=2 */;
+	output   busy;
+	input   clock;
+	input   [2:0]  counter_param;
+	input   [3:0]  counter_type;
+	input   [8:0]  data_in;
+	output   [8:0]  data_out;
+	output   pll_areset;
+	input   pll_areset_in;
+	output   pll_configupdate;
+	output   pll_scanclk;
+	output   pll_scanclkena;
+	output   pll_scandata;
+	input   pll_scandataout;
+	input   pll_scandone;
+	input   read_param;
+	input   reconfig;
+	input   reset;
+	input   reset_rom_address;
+	output   [7:0]  rom_address_out;
+	input   rom_data_in;
+	input   write_from_rom;
+	input   write_param;
+	output   write_rom_ena;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0   [2:0]  counter_param;
+	tri0   [3:0]  counter_type;
+	tri0   [8:0]  data_in;
+	tri0   pll_areset_in;
+	tri0   pll_scandataout;
+	tri0   pll_scandone;
+	tri0   read_param;
+	tri0   reconfig;
+	tri0   reset_rom_address;
+	tri0   rom_data_in;
+	tri0   write_from_rom;
+	tri0   write_param;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire  [0:0]   wire_altsyncram4_q_a;
+	wire  wire_le_comb10_combout;
+	wire  wire_le_comb8_combout;
+	wire  wire_le_comb9_combout;
+	reg	[7:0]	addr_from_rom;
+	reg	[7:0]	addr_from_rom2;
+	reg	areset_init_state_1;
+	reg	areset_state;
+	reg	C0_data_state;
+	reg	C0_ena_state;
+	reg	C1_data_state;
+	reg	C1_ena_state;
+	reg	C2_data_state;
+	reg	C2_ena_state;
+	reg	C3_data_state;
+	reg	C3_ena_state;
+	reg	C4_data_state;
+	reg	C4_ena_state;
+	reg	configupdate2_state;
+	reg	configupdate3_state;
+	reg	configupdate_state;
+	reg	[2:0]	counter_param_latch_reg;
+	reg	[3:0]	counter_type_latch_reg;
+	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+	reg	idle_state;
+	reg	[0:0]	nominal_data0;
+	reg	[0:0]	nominal_data1;
+	reg	[0:0]	nominal_data2;
+	reg	[0:0]	nominal_data3;
+	reg	[0:0]	nominal_data4;
+	reg	[0:0]	nominal_data5;
+	reg	[0:0]	nominal_data6;
+	reg	[0:0]	nominal_data7;
+	reg	[0:0]	nominal_data8;
+	reg	[0:0]	nominal_data9;
+	reg	[0:0]	nominal_data10;
+	reg	[0:0]	nominal_data11;
+	reg	[0:0]	nominal_data12;
+	reg	[0:0]	nominal_data13;
+	reg	[0:0]	nominal_data14;
+	reg	[0:0]	nominal_data15;
+	reg	[0:0]	nominal_data16;
+	reg	[0:0]	nominal_data17;
+	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+	reg	read_data_nominal_state;
+	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+	reg	read_data_state;
+	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+	reg	read_first_nominal_state;
+	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+	reg	read_first_state;
+	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+	reg	read_init_nominal_state;
+	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+	reg	read_init_state;
+	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+	reg	read_last_nominal_state;
+	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+	reg	read_last_state;
+	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+	reg	reconfig_counter_state;
+	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+	reg	reconfig_init_state;
+	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+	reg	reconfig_post_state;
+	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+	reg	reconfig_seq_data_state;
+	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+	reg	reconfig_seq_ena_state;
+	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+	reg	reconfig_wait_state;
+	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=HIGH"} *)
+	reg	reset_state;
+	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+	reg	rom_data_state;
+	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+	reg	rom_first_state;
+	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+	reg	rom_init_state;
+	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+	reg	rom_last_state;
+	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+	reg	rom_second_last_state;
+	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+	reg	rom_second_state;
+	reg	[0:0]	shift_reg0;
+	reg	[0:0]	shift_reg1;
+	reg	[0:0]	shift_reg2;
+	reg	[0:0]	shift_reg3;
+	reg	[0:0]	shift_reg4;
+	reg	[0:0]	shift_reg5;
+	reg	[0:0]	shift_reg6;
+	reg	[0:0]	shift_reg7;
+	reg	[0:0]	shift_reg8;
+	reg	[0:0]	shift_reg9;
+	reg	[0:0]	shift_reg10;
+	reg	[0:0]	shift_reg11;
+	reg	[0:0]	shift_reg12;
+	reg	[0:0]	shift_reg13;
+	reg	[0:0]	shift_reg14;
+	reg	[0:0]	shift_reg15;
+	reg	[0:0]	shift_reg16;
+	reg	[0:0]	shift_reg17;
+	wire	[17:0]	wire_shift_reg_ena;
+	reg	tmp_nominal_data_out_state;
+	reg	tmp_seq_ena_state;
+	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+	reg	write_data_state;
+	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+	reg	write_init_nominal_state;
+	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+	reg	write_init_state;
+	(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
+	reg	write_nominal_state;
+	wire  [8:0]   wire_add_sub5_result;
+	wire  [7:0]   wire_add_sub6_result;
+	wire  wire_cmpr7_aeb;
+	wire  [7:0]   wire_cntr1_q;
+	wire  [7:0]   wire_cntr12_q;
+	wire  [5:0]   wire_cntr13_q;
+	wire  [7:0]   wire_cntr14_q;
+	wire  [4:0]   wire_cntr15_q;
+	wire  [7:0]   wire_cntr16_q;
+	wire  [7:0]   wire_cntr2_q;
+	wire  [4:0]   wire_cntr3_q;
+	wire  [4:0]   wire_decode11_eq;
+	wire  addr_counter_enable;
+	wire  [7:0]  addr_counter_out;
+	wire  addr_counter_sload;
+	wire  [7:0]  addr_counter_sload_value;
+	wire  [7:0]  addr_decoder_out;
+	wire  [7:0]  c0_wire;
+	wire  [7:0]  c1_wire;
+	wire  [7:0]  c2_wire;
+	wire  [7:0]  c3_wire;
+	wire  [7:0]  c4_wire;
+	wire  [7:0]  const_scan_chain_size;
+	wire  [2:0]  counter_param_latch;
+	wire  [3:0]  counter_type_latch;
+	wire  [2:0]  cuda_combout_wire;
+	wire  dummy_scandataout;
+	wire  [2:0]  encode_out;
+	wire  input_latch_enable;
+	wire  power_up;
+	wire  read_addr_counter_done;
+	wire  read_addr_counter_enable;
+	wire  [7:0]  read_addr_counter_out;
+	wire  read_addr_counter_sload;
+	wire  [7:0]  read_addr_counter_sload_value;
+	wire  [7:0]  read_addr_decoder_out;
+	wire  read_nominal_out;
+	wire  reconfig_addr_counter_enable;
+	wire  [7:0]  reconfig_addr_counter_out;
+	wire  reconfig_addr_counter_sload;
+	wire  [7:0]  reconfig_addr_counter_sload_value;
+	wire  reconfig_done;
+	wire  reconfig_post_done;
+	wire  reconfig_width_counter_done;
+	wire  reconfig_width_counter_enable;
+	wire  reconfig_width_counter_sload;
+	wire  [5:0]  reconfig_width_counter_sload_value;
+	wire  rom_width_counter_done;
+	wire  rom_width_counter_enable;
+	wire  rom_width_counter_sload;
+	wire  [7:0]  rom_width_counter_sload_value;
+	wire  rotate_addr_counter_enable;
+	wire  [7:0]  rotate_addr_counter_out;
+	wire  rotate_addr_counter_sload;
+	wire  [7:0]  rotate_addr_counter_sload_value;
+	wire  [4:0]  rotate_decoder_wires;
+	wire  rotate_width_counter_done;
+	wire  rotate_width_counter_enable;
+	wire  rotate_width_counter_sload;
+	wire  [4:0]  rotate_width_counter_sload_value;
+	wire  [7:0]  scan_cache_address;
+	wire  scan_cache_in;
+	wire  scan_cache_out;
+	wire  scan_cache_write_enable;
+	wire  sel_param_bypass_LF_unused;
+	wire  sel_param_c;
+	wire  sel_param_high_i_postscale;
+	wire  sel_param_low_r;
+	wire  sel_param_nominal_count;
+	wire  sel_param_odd_CP_unused;
+	wire  sel_type_c0;
+	wire  sel_type_c1;
+	wire  sel_type_c2;
+	wire  sel_type_c3;
+	wire  sel_type_c4;
+	wire  sel_type_cplf;
+	wire  sel_type_m;
+	wire  sel_type_n;
+	wire  sel_type_vco;
+	wire  [7:0]  seq_addr_wire;
+	wire  [5:0]  seq_sload_value;
+	wire  shift_reg_clear;
+	wire  shift_reg_load_enable;
+	wire  shift_reg_load_nominal_enable;
+	wire  shift_reg_serial_in;
+	wire  shift_reg_serial_out;
+	wire  shift_reg_shift_enable;
+	wire  shift_reg_shift_nominal_enable;
+	wire  [7:0]  shift_reg_width_select;
+	wire  w1565w;
+	wire  w1592w;
+	wire  w64w;
+	wire  width_counter_done;
+	wire  width_counter_enable;
+	wire  width_counter_sload;
+	wire  [4:0]  width_counter_sload_value;
+	wire  [4:0]  width_decoder_out;
+	wire  [7:0]  width_decoder_select;
+
+	altsyncram   altsyncram4
+	( 
+	.address_a(scan_cache_address),
+	.clock0(clock),
+	.data_a({scan_cache_in}),
+	.eccstatus(),
+	.q_a(wire_altsyncram4_q_a),
+	.q_b(),
+	.wren_a(scan_cache_write_enable)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.aclr0(1'b0),
+	.aclr1(1'b0),
+	.address_b({1{1'b1}}),
+	.addressstall_a(1'b0),
+	.addressstall_b(1'b0),
+	.byteena_a({1{1'b1}}),
+	.byteena_b({1{1'b1}}),
+	.clock1(1'b1),
+	.clocken0(1'b1),
+	.clocken1(1'b1),
+	.clocken2(1'b1),
+	.clocken3(1'b1),
+	.data_b({1{1'b1}}),
+	.rden_a(1'b1),
+	.rden_b(1'b1),
+	.wren_b(1'b0)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		altsyncram4.init_file = "./pll_c16_pal.mif",
+		altsyncram4.numwords_a = 144,
+		altsyncram4.operation_mode = "SINGLE_PORT",
+		altsyncram4.width_a = 1,
+		altsyncram4.width_byteena_a = 1,
+		altsyncram4.widthad_a = 8,
+		altsyncram4.intended_device_family = "Cyclone III",
+		altsyncram4.lpm_type = "altsyncram";
+	cycloneiii_lcell_comb   le_comb10
+	( 
+	.combout(wire_le_comb10_combout),
+	.cout(),
+	.dataa(encode_out[0]),
+	.datab(encode_out[1]),
+	.datac(encode_out[2]),
+	.cin(1'b0),
+	.datad(1'b0)
+	);
+	defparam
+		le_comb10.dont_touch = "on",
+		le_comb10.lut_mask = 16'hF0F0,
+		le_comb10.sum_lutc_input = "datac",
+		le_comb10.lpm_type = "cycloneiii_lcell_comb";
+	cycloneiii_lcell_comb   le_comb8
+	( 
+	.combout(wire_le_comb8_combout),
+	.cout(),
+	.dataa(encode_out[0]),
+	.datab(encode_out[1]),
+	.datac(encode_out[2]),
+	.cin(1'b0),
+	.datad(1'b0)
+	);
+	defparam
+		le_comb8.dont_touch = "on",
+		le_comb8.lut_mask = 16'hAAAA,
+		le_comb8.sum_lutc_input = "datac",
+		le_comb8.lpm_type = "cycloneiii_lcell_comb";
+	cycloneiii_lcell_comb   le_comb9
+	( 
+	.combout(wire_le_comb9_combout),
+	.cout(),
+	.dataa(encode_out[0]),
+	.datab(encode_out[1]),
+	.datac(encode_out[2]),
+	.cin(1'b0),
+	.datad(1'b0)
+	);
+	defparam
+		le_comb9.dont_touch = "on",
+		le_comb9.lut_mask = 16'hCCCC,
+		le_comb9.sum_lutc_input = "datac",
+		le_comb9.lpm_type = "cycloneiii_lcell_comb";
+	// synopsys translate_off
+	initial
+		addr_from_rom = 0;
+	// synopsys translate_on
+	always @ ( posedge clock)
+		  addr_from_rom <= read_addr_counter_out;
+	// synopsys translate_off
+	initial
+		addr_from_rom2 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock)
+		  addr_from_rom2 <= addr_from_rom;
+	// synopsys translate_off
+	initial
+		areset_init_state_1 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock)
+		  areset_init_state_1 <= pll_scandone;
+	// synopsys translate_off
+	initial
+		areset_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock)
+		  areset_state <= (areset_init_state_1 & (~ reset));
+	// synopsys translate_off
+	initial
+		C0_data_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock)
+		  C0_data_state <= (C0_ena_state | (C0_data_state & (~ rotate_width_counter_done)));
+	// synopsys translate_off
+	initial
+		C0_ena_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock)
+		  C0_ena_state <= (C1_data_state & rotate_width_counter_done);
+	// synopsys translate_off
+	initial
+		C1_data_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock)
+		  C1_data_state <= (C1_ena_state | (C1_data_state & (~ rotate_width_counter_done)));
+	// synopsys translate_off
+	initial
+		C1_ena_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock)
+		  C1_ena_state <= (C2_data_state & rotate_width_counter_done);
+	// synopsys translate_off
+	initial
+		C2_data_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock)
+		  C2_data_state <= (C2_ena_state | (C2_data_state & (~ rotate_width_counter_done)));
+	// synopsys translate_off
+	initial
+		C2_ena_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock)
+		  C2_ena_state <= (C3_data_state & rotate_width_counter_done);
+	// synopsys translate_off
+	initial
+		C3_data_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock)
+		  C3_data_state <= (C3_ena_state | (C3_data_state & (~ rotate_width_counter_done)));
+	// synopsys translate_off
+	initial
+		C3_ena_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock)
+		  C3_ena_state <= (C4_data_state & rotate_width_counter_done);
+	// synopsys translate_off
+	initial
+		C4_data_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock)
+		  C4_data_state <= (C4_ena_state | (C4_data_state & (~ rotate_width_counter_done)));
+	// synopsys translate_off
+	initial
+		C4_ena_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock)
+		  C4_ena_state <= reconfig_init_state;
+	// synopsys translate_off
+	initial
+		configupdate2_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock)
+		  configupdate2_state <= configupdate_state;
+	// synopsys translate_off
+	initial
+		configupdate3_state = 0;
+	// synopsys translate_on
+	always @ ( negedge clock)
+		  configupdate3_state <= configupdate2_state;
+	// synopsys translate_off
+	initial
+		configupdate_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock)
+		  configupdate_state <= reconfig_post_state;
+	// synopsys translate_off
+	initial
+		counter_param_latch_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) counter_param_latch_reg <= 3'b0;
+		else if  (input_latch_enable == 1'b1)   counter_param_latch_reg <= counter_param;
+	// synopsys translate_off
+	initial
+		counter_type_latch_reg = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) counter_type_latch_reg <= 4'b0;
+		else if  (input_latch_enable == 1'b1)   counter_type_latch_reg <= counter_type;
+	// synopsys translate_off
+	initial
+		idle_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) idle_state <= 1'b0;
+		else  idle_state <= (((((((((((((idle_state & (~ read_param)) & (~ write_param)) & (~ reconfig)) & (~ write_from_rom)) | read_last_state) | (write_data_state & width_counter_done)) | (write_nominal_state & width_counter_done)) | read_last_nominal_state) | (reconfig_wait_state & reconfig_done)) | ((rom_data_state & rom_width_counter_done) & (~ reset_rom_address))) | (rom_second_last_state & (~ reset_rom_address))) | (rom_last_state & (~ reset_rom_address))) | reset_state);
+	// synopsys translate_off
+	initial
+		nominal_data0 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) nominal_data0 <= 1'b0;
+		else  nominal_data0 <= wire_add_sub6_result[0];
+	// synopsys translate_off
+	initial
+		nominal_data1 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) nominal_data1 <= 1'b0;
+		else  nominal_data1 <= wire_add_sub6_result[1];
+	// synopsys translate_off
+	initial
+		nominal_data2 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) nominal_data2 <= 1'b0;
+		else  nominal_data2 <= wire_add_sub6_result[2];
+	// synopsys translate_off
+	initial
+		nominal_data3 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) nominal_data3 <= 1'b0;
+		else  nominal_data3 <= wire_add_sub6_result[3];
+	// synopsys translate_off
+	initial
+		nominal_data4 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) nominal_data4 <= 1'b0;
+		else  nominal_data4 <= wire_add_sub6_result[4];
+	// synopsys translate_off
+	initial
+		nominal_data5 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) nominal_data5 <= 1'b0;
+		else  nominal_data5 <= wire_add_sub6_result[5];
+	// synopsys translate_off
+	initial
+		nominal_data6 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) nominal_data6 <= 1'b0;
+		else  nominal_data6 <= wire_add_sub6_result[6];
+	// synopsys translate_off
+	initial
+		nominal_data7 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) nominal_data7 <= 1'b0;
+		else  nominal_data7 <= wire_add_sub6_result[7];
+	// synopsys translate_off
+	initial
+		nominal_data8 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) nominal_data8 <= 1'b0;
+		else  nominal_data8 <= data_in[0];
+	// synopsys translate_off
+	initial
+		nominal_data9 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) nominal_data9 <= 1'b0;
+		else  nominal_data9 <= data_in[1];
+	// synopsys translate_off
+	initial
+		nominal_data10 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) nominal_data10 <= 1'b0;
+		else  nominal_data10 <= data_in[2];
+	// synopsys translate_off
+	initial
+		nominal_data11 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) nominal_data11 <= 1'b0;
+		else  nominal_data11 <= data_in[3];
+	// synopsys translate_off
+	initial
+		nominal_data12 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) nominal_data12 <= 1'b0;
+		else  nominal_data12 <= data_in[4];
+	// synopsys translate_off
+	initial
+		nominal_data13 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) nominal_data13 <= 1'b0;
+		else  nominal_data13 <= data_in[5];
+	// synopsys translate_off
+	initial
+		nominal_data14 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) nominal_data14 <= 1'b0;
+		else  nominal_data14 <= data_in[6];
+	// synopsys translate_off
+	initial
+		nominal_data15 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) nominal_data15 <= 1'b0;
+		else  nominal_data15 <= data_in[7];
+	// synopsys translate_off
+	initial
+		nominal_data16 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) nominal_data16 <= 1'b0;
+		else  nominal_data16 <= data_in[8];
+	// synopsys translate_off
+	initial
+		nominal_data17 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) nominal_data17 <= 1'b0;
+		else  nominal_data17 <= wire_cmpr7_aeb;
+	// synopsys translate_off
+	initial
+		read_data_nominal_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) read_data_nominal_state <= 1'b0;
+		else  read_data_nominal_state <= ((read_first_nominal_state & (~ width_counter_done)) | (read_data_nominal_state & (~ width_counter_done)));
+	// synopsys translate_off
+	initial
+		read_data_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) read_data_state <= 1'b0;
+		else  read_data_state <= ((read_first_state & (~ width_counter_done)) | (read_data_state & (~ width_counter_done)));
+	// synopsys translate_off
+	initial
+		read_first_nominal_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) read_first_nominal_state <= 1'b0;
+		else  read_first_nominal_state <= read_init_nominal_state;
+	// synopsys translate_off
+	initial
+		read_first_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) read_first_state <= 1'b0;
+		else  read_first_state <= read_init_state;
+	// synopsys translate_off
+	initial
+		read_init_nominal_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) read_init_nominal_state <= 1'b0;
+		else  read_init_nominal_state <= ((idle_state & read_param) & ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0]));
+	// synopsys translate_off
+	initial
+		read_init_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) read_init_state <= 1'b0;
+		else  read_init_state <= ((idle_state & read_param) & (~ ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0])));
+	// synopsys translate_off
+	initial
+		read_last_nominal_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) read_last_nominal_state <= 1'b0;
+		else  read_last_nominal_state <= ((read_first_nominal_state & width_counter_done) | (read_data_nominal_state & width_counter_done));
+	// synopsys translate_off
+	initial
+		read_last_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) read_last_state <= 1'b0;
+		else  read_last_state <= ((read_first_state & width_counter_done) | (read_data_state & width_counter_done));
+	// synopsys translate_off
+	initial
+		reconfig_counter_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) reconfig_counter_state <= 1'b0;
+		else  reconfig_counter_state <= ((((((((((reconfig_init_state | C0_data_state) | C1_data_state) | C2_data_state) | C3_data_state) | C4_data_state) | C0_ena_state) | C1_ena_state) | C2_ena_state) | C3_ena_state) | C4_ena_state);
+	// synopsys translate_off
+	initial
+		reconfig_init_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) reconfig_init_state <= 1'b0;
+		else  reconfig_init_state <= (idle_state & reconfig);
+	// synopsys translate_off
+	initial
+		reconfig_post_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) reconfig_post_state <= 1'b0;
+		else  reconfig_post_state <= ((reconfig_seq_data_state & reconfig_width_counter_done) | (reconfig_post_state & (~ reconfig_post_done)));
+	// synopsys translate_off
+	initial
+		reconfig_seq_data_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) reconfig_seq_data_state <= 1'b0;
+		else  reconfig_seq_data_state <= (reconfig_seq_ena_state | (reconfig_seq_data_state & (~ reconfig_width_counter_done)));
+	// synopsys translate_off
+	initial
+		reconfig_seq_ena_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) reconfig_seq_ena_state <= 1'b0;
+		else  reconfig_seq_ena_state <= tmp_seq_ena_state;
+	// synopsys translate_off
+	initial
+		reconfig_wait_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) reconfig_wait_state <= 1'b0;
+		else  reconfig_wait_state <= ((reconfig_post_state & reconfig_post_done) | (reconfig_wait_state & (~ reconfig_done)));
+	// synopsys translate_off
+	initial
+		reset_state = {1{1'b1}};
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) reset_state <= {1{1'b1}};
+		else  reset_state <= power_up;
+	// synopsys translate_off
+	initial
+		rom_data_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) rom_data_state <= 1'b0;
+		else  rom_data_state <= (rom_second_state | ((rom_data_state & (~ read_addr_counter_done)) & (~ reset_rom_address)));
+	// synopsys translate_off
+	initial
+		rom_first_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) rom_first_state <= 1'b0;
+		else  rom_first_state <= rom_init_state;
+	// synopsys translate_off
+	initial
+		rom_init_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) rom_init_state <= 1'b0;
+		else  rom_init_state <= (((((idle_state & write_from_rom) | (rom_first_state & reset_rom_address)) | (rom_second_state & reset_rom_address)) | (rom_data_state & reset_rom_address)) | (rom_second_last_state & reset_rom_address));
+	// synopsys translate_off
+	initial
+		rom_last_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) rom_last_state <= 1'b0;
+		else  rom_last_state <= (rom_second_last_state & (~ reset_rom_address));
+	// synopsys translate_off
+	initial
+		rom_second_last_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) rom_second_last_state <= 1'b0;
+		else  rom_second_last_state <= ((rom_data_state & read_addr_counter_done) & (~ reset_rom_address));
+	// synopsys translate_off
+	initial
+		rom_second_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) rom_second_state <= 1'b0;
+		else  rom_second_state <= (rom_first_state & (~ reset_rom_address));
+	// synopsys translate_off
+	initial
+		shift_reg0 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) shift_reg0 <= 1'b0;
+		else if  (wire_shift_reg_ena[0:0] == 1'b1) 
+			if (shift_reg_clear == 1'b1) shift_reg0 <= 1'b0;
+			else  shift_reg0 <= ((((shift_reg_load_nominal_enable & nominal_data17[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg_serial_in)) | (shift_reg_shift_nominal_enable & shift_reg_serial_in));
+	// synopsys translate_off
+	initial
+		shift_reg1 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) shift_reg1 <= 1'b0;
+		else if  (wire_shift_reg_ena[1:1] == 1'b1) 
+			if (shift_reg_clear == 1'b1) shift_reg1 <= 1'b0;
+			else  shift_reg1 <= ((((shift_reg_load_nominal_enable & nominal_data16[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg0[0:0])) | (shift_reg_shift_nominal_enable & shift_reg0[0:0]));
+	// synopsys translate_off
+	initial
+		shift_reg2 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) shift_reg2 <= 1'b0;
+		else if  (wire_shift_reg_ena[2:2] == 1'b1) 
+			if (shift_reg_clear == 1'b1) shift_reg2 <= 1'b0;
+			else  shift_reg2 <= ((((shift_reg_load_nominal_enable & nominal_data15[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg1[0:0])) | (shift_reg_shift_nominal_enable & shift_reg1[0:0]));
+	// synopsys translate_off
+	initial
+		shift_reg3 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) shift_reg3 <= 1'b0;
+		else if  (wire_shift_reg_ena[3:3] == 1'b1) 
+			if (shift_reg_clear == 1'b1) shift_reg3 <= 1'b0;
+			else  shift_reg3 <= ((((shift_reg_load_nominal_enable & nominal_data14[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg2[0:0])) | (shift_reg_shift_nominal_enable & shift_reg2[0:0]));
+	// synopsys translate_off
+	initial
+		shift_reg4 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) shift_reg4 <= 1'b0;
+		else if  (wire_shift_reg_ena[4:4] == 1'b1) 
+			if (shift_reg_clear == 1'b1) shift_reg4 <= 1'b0;
+			else  shift_reg4 <= ((((shift_reg_load_nominal_enable & nominal_data13[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg3[0:0])) | (shift_reg_shift_nominal_enable & shift_reg3[0:0]));
+	// synopsys translate_off
+	initial
+		shift_reg5 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) shift_reg5 <= 1'b0;
+		else if  (wire_shift_reg_ena[5:5] == 1'b1) 
+			if (shift_reg_clear == 1'b1) shift_reg5 <= 1'b0;
+			else  shift_reg5 <= ((((shift_reg_load_nominal_enable & nominal_data12[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg4[0:0])) | (shift_reg_shift_nominal_enable & shift_reg4[0:0]));
+	// synopsys translate_off
+	initial
+		shift_reg6 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) shift_reg6 <= 1'b0;
+		else if  (wire_shift_reg_ena[6:6] == 1'b1) 
+			if (shift_reg_clear == 1'b1) shift_reg6 <= 1'b0;
+			else  shift_reg6 <= ((((shift_reg_load_nominal_enable & nominal_data11[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg5[0:0])) | (shift_reg_shift_nominal_enable & shift_reg5[0:0]));
+	// synopsys translate_off
+	initial
+		shift_reg7 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) shift_reg7 <= 1'b0;
+		else if  (wire_shift_reg_ena[7:7] == 1'b1) 
+			if (shift_reg_clear == 1'b1) shift_reg7 <= 1'b0;
+			else  shift_reg7 <= ((((shift_reg_load_nominal_enable & nominal_data10[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg6[0:0])) | (shift_reg_shift_nominal_enable & shift_reg6[0:0]));
+	// synopsys translate_off
+	initial
+		shift_reg8 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) shift_reg8 <= 1'b0;
+		else if  (wire_shift_reg_ena[8:8] == 1'b1) 
+			if (shift_reg_clear == 1'b1) shift_reg8 <= 1'b0;
+			else  shift_reg8 <= ((((shift_reg_load_nominal_enable & nominal_data9[0:0]) | (shift_reg_load_enable & w64w)) | (shift_reg_shift_enable & shift_reg7[0:0])) | (shift_reg_shift_nominal_enable & shift_reg7[0:0]));
+	// synopsys translate_off
+	initial
+		shift_reg9 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) shift_reg9 <= 1'b0;
+		else if  (wire_shift_reg_ena[9:9] == 1'b1) 
+			if (shift_reg_clear == 1'b1) shift_reg9 <= 1'b0;
+			else  shift_reg9 <= ((((shift_reg_load_nominal_enable & nominal_data8[0:0]) | (shift_reg_load_enable & data_in[8])) | (shift_reg_shift_enable & shift_reg8[0:0])) | (shift_reg_shift_nominal_enable & shift_reg8[0:0]));
+	// synopsys translate_off
+	initial
+		shift_reg10 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) shift_reg10 <= 1'b0;
+		else if  (wire_shift_reg_ena[10:10] == 1'b1) 
+			if (shift_reg_clear == 1'b1) shift_reg10 <= 1'b0;
+			else  shift_reg10 <= ((((shift_reg_load_nominal_enable & nominal_data7[0:0]) | (shift_reg_load_enable & data_in[7])) | (shift_reg_shift_enable & shift_reg9[0:0])) | (shift_reg_shift_nominal_enable & shift_reg9[0:0]));
+	// synopsys translate_off
+	initial
+		shift_reg11 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) shift_reg11 <= 1'b0;
+		else if  (wire_shift_reg_ena[11:11] == 1'b1) 
+			if (shift_reg_clear == 1'b1) shift_reg11 <= 1'b0;
+			else  shift_reg11 <= ((((shift_reg_load_nominal_enable & nominal_data6[0:0]) | (shift_reg_load_enable & data_in[6])) | (shift_reg_shift_enable & shift_reg10[0:0])) | (shift_reg_shift_nominal_enable & shift_reg10[0:0]));
+	// synopsys translate_off
+	initial
+		shift_reg12 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) shift_reg12 <= 1'b0;
+		else if  (wire_shift_reg_ena[12:12] == 1'b1) 
+			if (shift_reg_clear == 1'b1) shift_reg12 <= 1'b0;
+			else  shift_reg12 <= ((((shift_reg_load_nominal_enable & nominal_data5[0:0]) | (shift_reg_load_enable & data_in[5])) | (shift_reg_shift_enable & shift_reg11[0:0])) | (shift_reg_shift_nominal_enable & shift_reg11[0:0]));
+	// synopsys translate_off
+	initial
+		shift_reg13 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) shift_reg13 <= 1'b0;
+		else if  (wire_shift_reg_ena[13:13] == 1'b1) 
+			if (shift_reg_clear == 1'b1) shift_reg13 <= 1'b0;
+			else  shift_reg13 <= ((((shift_reg_load_nominal_enable & nominal_data4[0:0]) | (shift_reg_load_enable & data_in[4])) | (shift_reg_shift_enable & shift_reg12[0:0])) | (shift_reg_shift_nominal_enable & shift_reg12[0:0]));
+	// synopsys translate_off
+	initial
+		shift_reg14 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) shift_reg14 <= 1'b0;
+		else if  (wire_shift_reg_ena[14:14] == 1'b1) 
+			if (shift_reg_clear == 1'b1) shift_reg14 <= 1'b0;
+			else  shift_reg14 <= ((((shift_reg_load_nominal_enable & nominal_data3[0:0]) | (shift_reg_load_enable & data_in[3])) | (shift_reg_shift_enable & shift_reg13[0:0])) | (shift_reg_shift_nominal_enable & shift_reg13[0:0]));
+	// synopsys translate_off
+	initial
+		shift_reg15 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) shift_reg15 <= 1'b0;
+		else if  (wire_shift_reg_ena[15:15] == 1'b1) 
+			if (shift_reg_clear == 1'b1) shift_reg15 <= 1'b0;
+			else  shift_reg15 <= ((((shift_reg_load_nominal_enable & nominal_data2[0:0]) | (shift_reg_load_enable & data_in[2])) | (shift_reg_shift_enable & shift_reg14[0:0])) | (shift_reg_shift_nominal_enable & shift_reg14[0:0]));
+	// synopsys translate_off
+	initial
+		shift_reg16 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) shift_reg16 <= 1'b0;
+		else if  (wire_shift_reg_ena[16:16] == 1'b1) 
+			if (shift_reg_clear == 1'b1) shift_reg16 <= 1'b0;
+			else  shift_reg16 <= ((((shift_reg_load_nominal_enable & nominal_data1[0:0]) | (shift_reg_load_enable & data_in[1])) | (shift_reg_shift_enable & shift_reg15[0:0])) | (shift_reg_shift_nominal_enable & shift_reg15[0:0]));
+	// synopsys translate_off
+	initial
+		shift_reg17 = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) shift_reg17 <= 1'b0;
+		else if  (wire_shift_reg_ena[17:17] == 1'b1) 
+			if (shift_reg_clear == 1'b1) shift_reg17 <= 1'b0;
+			else  shift_reg17 <= ((((shift_reg_load_nominal_enable & nominal_data0[0:0]) | (shift_reg_load_enable & data_in[0])) | (shift_reg_shift_enable & shift_reg16[0:0])) | (shift_reg_shift_nominal_enable & shift_reg16[0:0]));
+	assign
+		wire_shift_reg_ena = {18{((((shift_reg_load_enable | shift_reg_shift_enable) | shift_reg_load_nominal_enable) | shift_reg_shift_nominal_enable) | shift_reg_clear)}};
+	// synopsys translate_off
+	initial
+		tmp_nominal_data_out_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock)
+		  tmp_nominal_data_out_state <= ((read_last_nominal_state & (~ idle_state)) | (tmp_nominal_data_out_state & idle_state));
+	// synopsys translate_off
+	initial
+		tmp_seq_ena_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock)
+		  tmp_seq_ena_state <= (reconfig_counter_state & (C0_data_state & rotate_width_counter_done));
+	// synopsys translate_off
+	initial
+		write_data_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) write_data_state <= 1'b0;
+		else  write_data_state <= (write_init_state | (write_data_state & (~ width_counter_done)));
+	// synopsys translate_off
+	initial
+		write_init_nominal_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) write_init_nominal_state <= 1'b0;
+		else  write_init_nominal_state <= ((idle_state & write_param) & ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0]));
+	// synopsys translate_off
+	initial
+		write_init_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) write_init_state <= 1'b0;
+		else  write_init_state <= ((idle_state & write_param) & (~ ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0])));
+	// synopsys translate_off
+	initial
+		write_nominal_state = 0;
+	// synopsys translate_on
+	always @ ( posedge clock or  posedge reset)
+		if (reset == 1'b1) write_nominal_state <= 1'b0;
+		else  write_nominal_state <= (write_init_nominal_state | (write_nominal_state & (~ width_counter_done)));
+	lpm_add_sub   add_sub5
+	( 
+	.cin(1'b0),
+	.cout(),
+	.dataa({1'b0, shift_reg8[0:0], shift_reg7[0:0], shift_reg6[0:0], shift_reg5[0:0], shift_reg4[0:0], shift_reg3[0:0], shift_reg2[0:0], shift_reg1[0:0]}),
+	.datab({1'b0, shift_reg17[0:0], shift_reg16[0:0], shift_reg15[0:0], shift_reg14[0:0], shift_reg13[0:0], shift_reg12[0:0], shift_reg11[0:0], shift_reg10[0:0]}),
+	.overflow(),
+	.result(wire_add_sub5_result)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.aclr(1'b0),
+	.add_sub(1'b1),
+	.clken(1'b1),
+	.clock(1'b0)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		add_sub5.lpm_width = 9,
+		add_sub5.lpm_type = "lpm_add_sub";
+	lpm_add_sub   add_sub6
+	( 
+	.cin(data_in[0]),
+	.cout(),
+	.dataa({data_in[8:1]}),
+	.overflow(),
+	.result(wire_add_sub6_result)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.aclr(1'b0),
+	.add_sub(1'b1),
+	.clken(1'b1),
+	.clock(1'b0),
+	.datab({8{1'b0}})
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		add_sub6.lpm_width = 8,
+		add_sub6.lpm_type = "lpm_add_sub";
+	lpm_compare   cmpr7
+	( 
+	.aeb(wire_cmpr7_aeb),
+	.agb(),
+	.ageb(),
+	.alb(),
+	.aleb(),
+	.aneb(),
+	.dataa({data_in[7:0]}),
+	.datab(8'b00000001)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.aclr(1'b0),
+	.clken(1'b1),
+	.clock(1'b0)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		cmpr7.lpm_width = 8,
+		cmpr7.lpm_type = "lpm_compare";
+	lpm_counter   cntr1
+	( 
+	.clock(clock),
+	.cnt_en(addr_counter_enable),
+	.cout(),
+	.data(addr_counter_sload_value),
+	.eq(),
+	.q(wire_cntr1_q),
+	.sload(addr_counter_sload)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.aclr(1'b0),
+	.aload(1'b0),
+	.aset(1'b0),
+	.cin(1'b1),
+	.clk_en(1'b1),
+	.sclr(1'b0),
+	.sset(1'b0),
+	.updown(1'b1)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		cntr1.lpm_direction = "DOWN",
+		cntr1.lpm_modulus = 144,
+		cntr1.lpm_port_updown = "PORT_UNUSED",
+		cntr1.lpm_width = 8,
+		cntr1.lpm_type = "lpm_counter";
+	lpm_counter   cntr12
+	( 
+	.clock(clock),
+	.cnt_en(reconfig_addr_counter_enable),
+	.cout(),
+	.data(reconfig_addr_counter_sload_value),
+	.eq(),
+	.q(wire_cntr12_q),
+	.sload(reconfig_addr_counter_sload)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.aclr(1'b0),
+	.aload(1'b0),
+	.aset(1'b0),
+	.cin(1'b1),
+	.clk_en(1'b1),
+	.sclr(1'b0),
+	.sset(1'b0),
+	.updown(1'b1)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		cntr12.lpm_direction = "DOWN",
+		cntr12.lpm_modulus = 144,
+		cntr12.lpm_port_updown = "PORT_UNUSED",
+		cntr12.lpm_width = 8,
+		cntr12.lpm_type = "lpm_counter";
+	lpm_counter   cntr13
+	( 
+	.clock(clock),
+	.cnt_en(reconfig_width_counter_enable),
+	.cout(),
+	.data(reconfig_width_counter_sload_value),
+	.eq(),
+	.q(wire_cntr13_q),
+	.sload(reconfig_width_counter_sload)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.aclr(1'b0),
+	.aload(1'b0),
+	.aset(1'b0),
+	.cin(1'b1),
+	.clk_en(1'b1),
+	.sclr(1'b0),
+	.sset(1'b0),
+	.updown(1'b1)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		cntr13.lpm_direction = "DOWN",
+		cntr13.lpm_port_updown = "PORT_UNUSED",
+		cntr13.lpm_width = 6,
+		cntr13.lpm_type = "lpm_counter";
+	lpm_counter   cntr14
+	( 
+	.clock(clock),
+	.cnt_en(rom_width_counter_enable),
+	.cout(),
+	.data(rom_width_counter_sload_value),
+	.eq(),
+	.q(wire_cntr14_q),
+	.sload(rom_width_counter_sload)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.aclr(1'b0),
+	.aload(1'b0),
+	.aset(1'b0),
+	.cin(1'b1),
+	.clk_en(1'b1),
+	.sclr(1'b0),
+	.sset(1'b0),
+	.updown(1'b1)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		cntr14.lpm_direction = "DOWN",
+		cntr14.lpm_port_updown = "PORT_UNUSED",
+		cntr14.lpm_width = 8,
+		cntr14.lpm_type = "lpm_counter";
+	lpm_counter   cntr15
+	( 
+	.clock(clock),
+	.cnt_en(rotate_width_counter_enable),
+	.cout(),
+	.data(rotate_width_counter_sload_value),
+	.eq(),
+	.q(wire_cntr15_q),
+	.sload(rotate_width_counter_sload)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.aclr(1'b0),
+	.aload(1'b0),
+	.aset(1'b0),
+	.cin(1'b1),
+	.clk_en(1'b1),
+	.sclr(1'b0),
+	.sset(1'b0),
+	.updown(1'b1)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		cntr15.lpm_direction = "DOWN",
+		cntr15.lpm_port_updown = "PORT_UNUSED",
+		cntr15.lpm_width = 5,
+		cntr15.lpm_type = "lpm_counter";
+	lpm_counter   cntr16
+	( 
+	.clock(clock),
+	.cnt_en(rotate_addr_counter_enable),
+	.cout(),
+	.data(rotate_addr_counter_sload_value),
+	.eq(),
+	.q(wire_cntr16_q),
+	.sload(rotate_addr_counter_sload)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.aclr(1'b0),
+	.aload(1'b0),
+	.aset(1'b0),
+	.cin(1'b1),
+	.clk_en(1'b1),
+	.sclr(1'b0),
+	.sset(1'b0),
+	.updown(1'b1)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		cntr16.lpm_direction = "DOWN",
+		cntr16.lpm_modulus = 144,
+		cntr16.lpm_port_updown = "PORT_UNUSED",
+		cntr16.lpm_width = 8,
+		cntr16.lpm_type = "lpm_counter";
+	lpm_counter   cntr2
+	( 
+	.clock(clock),
+	.cnt_en(read_addr_counter_enable),
+	.cout(),
+	.data(read_addr_counter_sload_value),
+	.eq(),
+	.q(wire_cntr2_q),
+	.sload(read_addr_counter_sload)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.aclr(1'b0),
+	.aload(1'b0),
+	.aset(1'b0),
+	.cin(1'b1),
+	.clk_en(1'b1),
+	.sclr(1'b0),
+	.sset(1'b0),
+	.updown(1'b1)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		cntr2.lpm_direction = "UP",
+		cntr2.lpm_port_updown = "PORT_UNUSED",
+		cntr2.lpm_width = 8,
+		cntr2.lpm_type = "lpm_counter";
+	lpm_counter   cntr3
+	( 
+	.clock(clock),
+	.cnt_en(width_counter_enable),
+	.cout(),
+	.data(width_counter_sload_value),
+	.eq(),
+	.q(wire_cntr3_q),
+	.sload(width_counter_sload)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.aclr(1'b0),
+	.aload(1'b0),
+	.aset(1'b0),
+	.cin(1'b1),
+	.clk_en(1'b1),
+	.sclr(1'b0),
+	.sset(1'b0),
+	.updown(1'b1)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		cntr3.lpm_direction = "DOWN",
+		cntr3.lpm_port_updown = "PORT_UNUSED",
+		cntr3.lpm_width = 5,
+		cntr3.lpm_type = "lpm_counter";
+	lpm_decode   decode11
+	( 
+	.data(cuda_combout_wire),
+	.eq(wire_decode11_eq)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_off
+	`endif
+	,
+	.aclr(1'b0),
+	.clken(1'b1),
+	.clock(1'b0),
+	.enable(1'b1)
+	`ifndef FORMAL_VERIFICATION
+	// synopsys translate_on
+	`endif
+	);
+	defparam
+		decode11.lpm_decodes = 5,
+		decode11.lpm_width = 3,
+		decode11.lpm_type = "lpm_decode";
+	assign
+		addr_counter_enable = (write_data_state | write_nominal_state),
+		addr_counter_out = wire_cntr1_q,
+		addr_counter_sload = (write_init_state | write_init_nominal_state),
+		addr_counter_sload_value = (addr_decoder_out & {8{(write_init_state | write_init_nominal_state)}}),
+		addr_decoder_out = ((((((((((((((((((((((((((((((((((({{7{1'b0}}, (sel_type_cplf & sel_param_bypass_LF_unused)} | {{6{1'b0}}, {2{(sel_type_cplf & sel_param_c)}}}) | {{4{1'b0}}, (sel_type_cplf & sel_param_low_r), {3{1'b0}}}) | {{4{1'b0}}, (sel_type_vco & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_vco & sel_param_high_i_postscale)}) | {{4{1'b0}}, {3{(sel_type_cplf & sel_param_odd_CP_unused)}}, 1'b0}) | {{3{1'b0}}, (sel_type_cplf & sel_param_high_i_postscale), {3{1'b0}}, (sel_type_cplf & sel_param_high_i_postscale)}) | {{3{1'b0}}, (sel_type_n & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_n & sel_param_bypass_LF_unused), 1'b0}) | {{3{1'b0}}, {2{(sel_type_n & sel_param_high_i_postscale)}}, 1'b0, (sel_type_n & sel_param_high_i_postscale), 1'b0}) | {{3{1'b0}}, {2{(sel_type_n & sel_param_odd_CP_unused)}}, 1'b0, {2{(sel_type_n & sel_param_odd_CP_unused)}}}) | {{2{1'b0}}, (sel_type_n & sel_param_low_r), {3{1'b0}}, {2{(sel_type_n & sel_param_low_r)}}}) | {{2{1'b0}}, (sel_type_n & sel_param_nominal_count), {3{1'b0}}, {2{(sel_type_n & sel_param_nominal_count)}}}) | {{2{1'b0}}, (sel_type_m & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_m & sel_param_bypass_LF_unused), {2{1'b0}}}) | {{2{1'b0}}, (sel_type_m & sel_param_high_i_postscale), 1'b0, {2{(sel_type_m & sel_param_high_i_postscale)}}, {2{1'b0}}}) | {{2{1'b0}}, (sel_type_m & sel_param_odd_CP_unused), 1'b0, {2{(sel_type_m & sel_param_odd_CP_unused)}}, 1'b0, (sel_type_m & sel_param_odd_CP_unused)}) | {{2{1'b0}}, {2{(sel_type_m & sel_param_low_r)}}, 1'b0, (sel_type_m & sel_param_low_r), 1'b0, (sel_type_m & sel_param_low_r)}) | {{2{1'b0}}, {2{(sel_type_m & sel_param_nominal_count)}}, 1'b0, (sel_type_m & sel_param_nominal_count), 1'b0, (sel_type_m & sel_param_nominal_count)}) | {{2{1'b0}}, {2{(sel_type_c0 & sel_param_bypass_LF_unused)}}, 1'b0, {2{(sel_type_c0 & sel_param_bypass_LF_unused)}}, 1'b0}) | {{2{1'b0}}, {5{(sel_type_c0 & sel_param_high_i_postscale)}}, 1'b0}) | {{2{1'b0}}, {6{(sel_type_c0 & sel_param_odd_CP_unused)}}}) | {1'b0, (sel_type_c0 & sel_param_low_r
+), {3{1'b0}}, {3{(sel_type_c0 & sel_param_low_r)}}}) | {1'b0, (sel_type_c1 & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_c1 & sel_param_bypass_LF_unused), {3{1'b0}}}) | {1'b0, (sel_type_c1 & sel_param_high_i_postscale), 1'b0, (sel_type_c1 & sel_param_high_i_postscale), {4{1'b0}}}) | {1'b0, (sel_type_c1 & sel_param_odd_CP_unused), 1'b0, (sel_type_c1 & sel_param_odd_CP_unused), {3{1'b0}}, (sel_type_c1 & sel_param_odd_CP_unused)}) | {1'b0, (sel_type_c1 & sel_param_low_r), 1'b0, {2{(sel_type_c1 & sel_param_low_r)}}, {2{1'b0}}, (sel_type_c1 & sel_param_low_r)}) | {1'b0, (sel_type_c2 & sel_param_bypass_LF_unused), 1'b0, {2{(sel_type_c2 & sel_param_bypass_LF_unused)}}, 1'b0, (sel_type_c2 & sel_param_bypass_LF_unused), 1'b0}) | {1'b0, {2{(sel_type_c2 & sel_param_high_i_postscale)}}, {3{1'b0}}, (sel_type_c2 & sel_param_high_i_postscale), 1'b0}) | {1'b0, {2{(sel_type_c2 & sel_param_odd_CP_unused)}}, {3{1'b0}}, {2{(sel_type_c2 & sel_param_odd_CP_unused)}}}) | {1'b0, {2{(sel_type_c2 & sel_param_low_r)}}, 1'b0, (sel_type_c2 & sel_param_low_r), 1'b0, {2{(sel_type_c2 & sel_param_low_r)}}}) | {1'b0, {2{(sel_type_c3 & sel_param_bypass_LF_unused)}}, 1'b0, {2{(sel_type_c3 & sel_param_bypass_LF_unused)}}, {2{1'b0}}}) | {1'b0, {3{(sel_type_c3 & sel_param_high_i_postscale)}}, 1'b0, (sel_type_c3 & sel_param_high_i_postscale), {2{1'b0}}}) | {1'b0, {3{(sel_type_c3 & sel_param_odd_CP_unused)}}, 1'b0, (sel_type_c3 & sel_param_odd_CP_unused), 1'b0, (sel_type_c3 & sel_param_odd_CP_unused)}) | {1'b0, {5{(sel_type_c3 & sel_param_low_r)}}, 1'b0, (sel_type_c3 & sel_param_low_r)}) | {1'b0, {6{(sel_type_c4 & sel_param_bypass_LF_unused)}}, 1'b0}) | {(sel_type_c4 & sel_param_high_i_postscale), {4{1'b0}}, {2{(sel_type_c4 & sel_param_high_i_postscale)}}, 1'b0}) | {(sel_type_c4 & sel_param_odd_CP_unused), {4{1'b0}}, {3{(sel_type_c4 & sel_param_odd_CP_unused)}}}) | {(sel_type_c4 & sel_param_low_r), {3{1'b0}}, {4{(sel_type_c4 & sel_param_low_r)}}}),
+		busy = ((~ idle_state) | areset_state),
+		c0_wire = 8'b01000111,
+		c1_wire = 8'b01011001,
+		c2_wire = 8'b01101011,
+		c3_wire = 8'b01111101,
+		c4_wire = 8'b10001111,
+		const_scan_chain_size = 8'b10001111,
+		counter_param_latch = counter_param_latch_reg,
+		counter_type_latch = counter_type_latch_reg,
+		cuda_combout_wire = {wire_le_comb10_combout, wire_le_comb9_combout, wire_le_comb8_combout},
+		data_out = {((shift_reg8[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[8] & read_nominal_out)), ((shift_reg7[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[7] & read_nominal_out)), ((shift_reg6[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[6] & read_nominal_out)), ((shift_reg5[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[5] & read_nominal_out)), ((shift_reg4[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[4] & read_nominal_out)), ((shift_reg3[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[3] & read_nominal_out)), ((shift_reg2[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[2] & read_nominal_out)), ((shift_reg1[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[1] & read_nominal_out)), ((shift_reg0[0:0] & (~ read_nominal_out)) | (wire_add_sub5_result[0] & read_nominal_out))},
+		dummy_scandataout = pll_scandataout,
+		encode_out = {C4_ena_state, (C2_ena_state | C3_ena_state), (C1_ena_state | C3_ena_state)},
+		input_latch_enable = (idle_state & (write_param | read_param)),
+		pll_areset = (pll_areset_in | (areset_state & reconfig_wait_state)),
+		pll_configupdate = (configupdate_state & (~ configupdate3_state)),
+		pll_scanclk = clock,
+		pll_scanclkena = ((rotate_width_counter_enable & (~ rotate_width_counter_done)) | reconfig_seq_data_state),
+		pll_scandata = (scan_cache_out & ((rotate_width_counter_enable | reconfig_seq_data_state) | reconfig_post_state)),
+		power_up = ((((((((((((((((((((((((((~ reset_state) & (~ idle_state)) & (~ read_init_state)) & (~ read_first_state)) & (~ read_data_state)) & (~ read_last_state)) & (~ read_init_nominal_state)) & (~ read_first_nominal_state)) & (~ read_data_nominal_state)) & (~ read_last_nominal_state)) & (~ write_init_state)) & (~ write_data_state)) & (~ write_init_nominal_state)) & (~ write_nominal_state)) & (~ reconfig_init_state)) & (~ reconfig_counter_state)) & (~ reconfig_seq_ena_state)) & (~ reconfig_seq_data_state)) & (~ reconfig_post_state)) & (~ reconfig_wait_state)) & (~ rom_init_state)) & (~ rom_first_state)) & (~ rom_second_state)) & (~ rom_data_state)) & (~ rom_second_last_state)) & (~ rom_last_state)),
+		read_addr_counter_done = (((((((wire_cntr2_q[0] & wire_cntr2_q[1]) & wire_cntr2_q[2]) & wire_cntr2_q[3]) & (~ wire_cntr2_q[4])) & (~ wire_cntr2_q[5])) & (~ wire_cntr2_q[6])) & wire_cntr2_q[7]),
+		read_addr_counter_enable = ((((read_first_state | read_data_state) | read_first_nominal_state) | read_data_nominal_state) | ((rom_data_state | rom_first_state) | rom_second_state)),
+		read_addr_counter_out = wire_cntr2_q,
+		read_addr_counter_sload = ((read_init_state | read_init_nominal_state) | rom_init_state),
+		read_addr_counter_sload_value = (read_addr_decoder_out & {8{(read_init_state | read_init_nominal_state)}}),
+		read_addr_decoder_out = ((((((((((((((((((((((((((((((((((({8{1'b0}} | {{6{1'b0}}, (sel_type_cplf & sel_param_c), 1'b0}) | {{5{1'b0}}, (sel_type_cplf & sel_param_low_r), {2{1'b0}}}) | {{4{1'b0}}, (sel_type_vco & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_vco & sel_param_high_i_postscale)}) | {{4{1'b0}}, (sel_type_cplf & sel_param_odd_CP_unused), 1'b0, (sel_type_cplf & sel_param_odd_CP_unused), 1'b0}) | {{4{1'b0}}, {4{(sel_type_cplf & sel_param_high_i_postscale)}}}) | {{3{1'b0}}, (sel_type_n & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_n & sel_param_bypass_LF_unused), 1'b0}) | {{3{1'b0}}, (sel_type_n & sel_param_high_i_postscale), {2{1'b0}}, {2{(sel_type_n & sel_param_high_i_postscale)}}}) | {{3{1'b0}}, {2{(sel_type_n & sel_param_odd_CP_unused)}}, 1'b0, {2{(sel_type_n & sel_param_odd_CP_unused)}}}) | {{3{1'b0}}, {3{(sel_type_n & sel_param_low_r)}}, {2{1'b0}}}) | {{3{1'b0}}, (sel_type_n & sel_param_nominal_count), {2{1'b0}}, (sel_type_n & sel_param_nominal_count), 1'b0}) | {{2{1'b0}}, (sel_type_m & sel_param_bypass_LF_unused), {2{1'b0}}, (sel_type_m & sel_param_bypass_LF_unused), {2{1'b0}}}) | {{2{1'b0}}, (sel_type_m & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_m & sel_param_high_i_postscale), 1'b0, (sel_type_m & sel_param_high_i_postscale)}) | {{2{1'b0}}, (sel_type_m & sel_param_odd_CP_unused), 1'b0, {2{(sel_type_m & sel_param_odd_CP_unused)}}, 1'b0, (sel_type_m & sel_param_odd_CP_unused)}) | {{2{1'b0}}, (sel_type_m & sel_param_low_r), 1'b0, {3{(sel_type_m & sel_param_low_r)}}, 1'b0}) | {{2{1'b0}}, (sel_type_m & sel_param_nominal_count), {2{1'b0}}, (sel_type_m & sel_param_nominal_count), {2{1'b0}}}) | {{2{1'b0}}, {2{(sel_type_c0 & sel_param_bypass_LF_unused)}}, 1'b0, {2{(sel_type_c0 & sel_param_bypass_LF_unused)}}, 1'b0}) | {{2{1'b0}}, {2{(sel_type_c0 & sel_param_high_i_postscale)}}, 1'b0, {3{(sel_type_c0 & sel_param_high_i_postscale)}}}) | {{2{1'b0}}, {6{(sel_type_c0 & sel_param_odd_CP_unused)}}}) | {1'b0, (sel_type_c0 & sel_param_low_r), {6{1'b0}}}) | {1'b0, (sel_type_c1 & sel_param_bypass_LF_unused
+), {2{1'b0}}, (sel_type_c1 & sel_param_bypass_LF_unused), {3{1'b0}}}) | {1'b0, (sel_type_c1 & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_c1 & sel_param_high_i_postscale), {2{1'b0}}, (sel_type_c1 & sel_param_high_i_postscale)}) | {1'b0, (sel_type_c1 & sel_param_odd_CP_unused), 1'b0, (sel_type_c1 & sel_param_odd_CP_unused), {3{1'b0}}, (sel_type_c1 & sel_param_odd_CP_unused)}) | {1'b0, (sel_type_c1 & sel_param_low_r), 1'b0, (sel_type_c1 & sel_param_low_r), {2{1'b0}}, (sel_type_c1 & sel_param_low_r), 1'b0}) | {1'b0, (sel_type_c2 & sel_param_bypass_LF_unused), 1'b0, {2{(sel_type_c2 & sel_param_bypass_LF_unused)}}, 1'b0, (sel_type_c2 & sel_param_bypass_LF_unused), 1'b0}) | {1'b0, (sel_type_c2 & sel_param_high_i_postscale), 1'b0, {2{(sel_type_c2 & sel_param_high_i_postscale)}}, 1'b0, {2{(sel_type_c2 & sel_param_high_i_postscale)}}}) | {1'b0, {2{(sel_type_c2 & sel_param_odd_CP_unused)}}, {3{1'b0}}, {2{(sel_type_c2 & sel_param_odd_CP_unused)}}}) | {1'b0, {2{(sel_type_c2 & sel_param_low_r)}}, {2{1'b0}}, (sel_type_c2 & sel_param_low_r), {2{1'b0}}}) | {1'b0, {2{(sel_type_c3 & sel_param_bypass_LF_unused)}}, 1'b0, {2{(sel_type_c3 & sel_param_bypass_LF_unused)}}, {2{1'b0}}}) | {1'b0, {2{(sel_type_c3 & sel_param_high_i_postscale)}}, 1'b0, {2{(sel_type_c3 & sel_param_high_i_postscale)}}, 1'b0, (sel_type_c3 & sel_param_high_i_postscale)}) | {1'b0, {3{(sel_type_c3 & sel_param_odd_CP_unused)}}, 1'b0, (sel_type_c3 & sel_param_odd_CP_unused), 1'b0, (sel_type_c3 & sel_param_odd_CP_unused)}) | {1'b0, {3{(sel_type_c3 & sel_param_low_r)}}, 1'b0, {2{(sel_type_c3 & sel_param_low_r)}}, 1'b0}) | {1'b0, {6{(sel_type_c4 & sel_param_bypass_LF_unused)}}, 1'b0}) | {1'b0, {7{(sel_type_c4 & sel_param_high_i_postscale)}}}) | {(sel_type_c4 & sel_param_odd_CP_unused), {4{1'b0}}, {3{(sel_type_c4 & sel_param_odd_CP_unused)}}}) | {(sel_type_c4 & sel_param_low_r), {3{1'b0}}, (sel_type_c4 & sel_param_low_r), {3{1'b0}}}),
+		read_nominal_out = tmp_nominal_data_out_state,
+		reconfig_addr_counter_enable = reconfig_seq_data_state,
+		reconfig_addr_counter_out = wire_cntr12_q,
+		reconfig_addr_counter_sload = reconfig_seq_ena_state,
+		reconfig_addr_counter_sload_value = ({8{reconfig_seq_ena_state}} & seq_addr_wire),
+		reconfig_done = ((~ pll_scandone) & (dummy_scandataout | (~ dummy_scandataout))),
+		reconfig_post_done = pll_scandone,
+		reconfig_width_counter_done = ((((((~ wire_cntr13_q[0]) & (~ wire_cntr13_q[1])) & (~ wire_cntr13_q[2])) & (~ wire_cntr13_q[3])) & (~ wire_cntr13_q[4])) & (~ wire_cntr13_q[5])),
+		reconfig_width_counter_enable = reconfig_seq_data_state,
+		reconfig_width_counter_sload = reconfig_seq_ena_state,
+		reconfig_width_counter_sload_value = ({6{reconfig_seq_ena_state}} & seq_sload_value),
+		rom_address_out = (read_addr_counter_out & {8{((rom_first_state | rom_second_state) | rom_data_state)}}),
+		rom_width_counter_done = ((((((((~ wire_cntr14_q[0]) & (~ wire_cntr14_q[1])) & (~ wire_cntr14_q[2])) & (~ wire_cntr14_q[3])) & (~ wire_cntr14_q[4])) & (~ wire_cntr14_q[5])) & (~ wire_cntr14_q[6])) & (~ wire_cntr14_q[7])),
+		rom_width_counter_enable = ((rom_data_state | rom_last_state) | rom_second_last_state),
+		rom_width_counter_sload = rom_init_state,
+		rom_width_counter_sload_value = const_scan_chain_size,
+		rotate_addr_counter_enable = ((((C0_data_state | C1_data_state) | C2_data_state) | C3_data_state) | C4_data_state),
+		rotate_addr_counter_out = wire_cntr16_q,
+		rotate_addr_counter_sload = ((((C0_ena_state | C1_ena_state) | C2_ena_state) | C3_ena_state) | C4_ena_state),
+		rotate_addr_counter_sload_value = (((((c0_wire & {8{rotate_decoder_wires[0]}}) | (c1_wire & {8{rotate_decoder_wires[1]}})) | (c2_wire & {8{rotate_decoder_wires[2]}})) | (c3_wire & {8{rotate_decoder_wires[3]}})) | (c4_wire & {8{rotate_decoder_wires[4]}})),
+		rotate_decoder_wires = wire_decode11_eq,
+		rotate_width_counter_done = (((((~ wire_cntr15_q[0]) & (~ wire_cntr15_q[1])) & (~ wire_cntr15_q[2])) & (~ wire_cntr15_q[3])) & (~ wire_cntr15_q[4])),
+		rotate_width_counter_enable = ((((C0_data_state | C1_data_state) | C2_data_state) | C3_data_state) | C4_data_state),
+		rotate_width_counter_sload = ((((C0_ena_state | C1_ena_state) | C2_ena_state) | C3_ena_state) | C4_ena_state),
+		rotate_width_counter_sload_value = 5'b10010,
+		scan_cache_address = (((((addr_counter_out & {8{addr_counter_enable}}) | (rotate_addr_counter_out & {8{rotate_addr_counter_enable}})) | (reconfig_addr_counter_out & {8{reconfig_addr_counter_enable}})) | ((read_addr_counter_out & {8{read_addr_counter_enable}}) & {8{(~ (rom_data_state | rom_first_state))}})) | ({8{(rom_width_counter_enable & ((rom_data_state | rom_second_last_state) | rom_last_state))}} & addr_from_rom2)),
+		scan_cache_in = ((shift_reg_serial_out & (~ (((rom_first_state | rom_data_state) | rom_second_last_state) | rom_last_state))) | (rom_data_in & (((rom_first_state | rom_data_state) | rom_second_last_state) | rom_last_state))),
+		scan_cache_out = wire_altsyncram4_q_a[0],
+		scan_cache_write_enable = ((((write_data_state | write_nominal_state) | rom_data_state) | rom_second_last_state) | rom_last_state),
+		sel_param_bypass_LF_unused = (((~ counter_param_latch[0]) & (~ counter_param_latch[1])) & counter_param_latch[2]),
+		sel_param_c = (((~ counter_param_latch[0]) & counter_param_latch[1]) & (~ counter_param_latch[2])),
+		sel_param_high_i_postscale = (((~ counter_param_latch[0]) & (~ counter_param_latch[1])) & (~ counter_param_latch[2])),
+		sel_param_low_r = ((counter_param_latch[0] & (~ counter_param_latch[1])) & (~ counter_param_latch[2])),
+		sel_param_nominal_count = ((counter_param_latch[0] & counter_param_latch[1]) & counter_param_latch[2]),
+		sel_param_odd_CP_unused = ((counter_param_latch[0] & (~ counter_param_latch[1])) & counter_param_latch[2]),
+		sel_type_c0 = ((((~ counter_type_latch[0]) & (~ counter_type_latch[1])) & counter_type_latch[2]) & (~ counter_type_latch[3])),
+		sel_type_c1 = (((counter_type_latch[0] & (~ counter_type_latch[1])) & counter_type_latch[2]) & (~ counter_type_latch[3])),
+		sel_type_c2 = ((((~ counter_type_latch[0]) & counter_type_latch[1]) & counter_type_latch[2]) & (~ counter_type_latch[3])),
+		sel_type_c3 = (((counter_type_latch[0] & counter_type_latch[1]) & counter_type_latch[2]) & (~ counter_type_latch[3])),
+		sel_type_c4 = ((((~ counter_type_latch[0]) & (~ counter_type_latch[1])) & (~ counter_type_latch[2])) & counter_type_latch[3]),
+		sel_type_cplf = ((((~ counter_type_latch[0]) & counter_type_latch[1]) & (~ counter_type_latch[2])) & (~ counter_type_latch[3])),
+		sel_type_m = (((counter_type_latch[0] & (~ counter_type_latch[1])) & (~ counter_type_latch[2])) & (~ counter_type_latch[3])),
+		sel_type_n = ((((~ counter_type_latch[0]) & (~ counter_type_latch[1])) & (~ counter_type_latch[2])) & (~ counter_type_latch[3])),
+		sel_type_vco = (((counter_type_latch[0] & counter_type_latch[1]) & (~ counter_type_latch[2])) & (~ counter_type_latch[3])),
+		seq_addr_wire = 8'b00110101,
+		seq_sload_value = 6'b110110,
+		shift_reg_clear = (read_init_state | read_init_nominal_state),
+		shift_reg_load_enable = ((idle_state & write_param) & (~ ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0]))),
+		shift_reg_load_nominal_enable = ((idle_state & write_param) & ((((((~ counter_type[3]) & (~ counter_type[2])) & (~ counter_type[1])) & counter_param[2]) & counter_param[1]) & counter_param[0])),
+		shift_reg_serial_in = scan_cache_out,
+		shift_reg_serial_out = ((((((((shift_reg17[0:0] & shift_reg_width_select[0]) | (shift_reg17[0:0] & shift_reg_width_select[1])) | (shift_reg17[0:0] & shift_reg_width_select[2])) | (shift_reg17[0:0] & shift_reg_width_select[3])) | (shift_reg17[0:0] & shift_reg_width_select[4])) | (shift_reg17[0:0] & shift_reg_width_select[5])) | (shift_reg17[0:0] & shift_reg_width_select[6])) | (shift_reg17[0:0] & shift_reg_width_select[7])),
+		shift_reg_shift_enable = ((read_data_state | read_last_state) | write_data_state),
+		shift_reg_shift_nominal_enable = ((read_data_nominal_state | read_last_nominal_state) | write_nominal_state),
+		shift_reg_width_select = width_decoder_select,
+		w1565w = 1'b0,
+		w1592w = 1'b0,
+		w64w = 1'b0,
+		width_counter_done = (((((~ wire_cntr3_q[0]) & (~ wire_cntr3_q[1])) & (~ wire_cntr3_q[2])) & (~ wire_cntr3_q[3])) & (~ wire_cntr3_q[4])),
+		width_counter_enable = ((((read_first_state | read_data_state) | write_data_state) | read_data_nominal_state) | write_nominal_state),
+		width_counter_sload = (((read_init_state | write_init_state) | read_init_nominal_state) | write_init_nominal_state),
+		width_counter_sload_value = width_decoder_out,
+		width_decoder_out = ((((({5{1'b0}} | {width_decoder_select[2], {3{1'b0}}, width_decoder_select[2]}) | {{4{1'b0}}, width_decoder_select[3]}) | {{2{1'b0}}, {3{width_decoder_select[5]}}}) | {{3{1'b0}}, width_decoder_select[6], 1'b0}) | {{2{1'b0}}, width_decoder_select[7], {2{1'b0}}}),
+		width_decoder_select = {((sel_type_cplf & sel_param_low_r) | (sel_type_cplf & sel_param_odd_CP_unused)), (sel_type_cplf & sel_param_high_i_postscale), ((((((((((((((sel_type_n & sel_param_high_i_postscale) | (sel_type_n & sel_param_low_r)) | (sel_type_m & sel_param_high_i_postscale)) | (sel_type_m & sel_param_low_r)) | (sel_type_c0 & sel_param_high_i_postscale)) | (sel_type_c0 & sel_param_low_r)) | (sel_type_c1 & sel_param_high_i_postscale)) | (sel_type_c1 & sel_param_low_r)) | (sel_type_c2 & sel_param_high_i_postscale)) | (sel_type_c2 & sel_param_low_r)) | (sel_type_c3 & sel_param_high_i_postscale)) | (sel_type_c3 & sel_param_low_r)) | (sel_type_c4 & sel_param_high_i_postscale)) | (sel_type_c4 & sel_param_low_r)), w1592w, ((sel_type_cplf & sel_param_bypass_LF_unused) | (sel_type_cplf & sel_param_c)), ((sel_type_n & sel_param_nominal_count) | (sel_type_m & sel_param_nominal_count)), w1565w, (((((((((((((((sel_type_vco & sel_param_high_i_postscale) | (sel_type_n & sel_param_bypass_LF_unused)) | (sel_type_n & sel_param_odd_CP_unused)) | (sel_type_m & sel_param_bypass_LF_unused)) | (sel_type_m & sel_param_odd_CP_unused)) | (sel_type_c0 & sel_param_bypass_LF_unused)) | (sel_type_c0 & sel_param_odd_CP_unused)) | (sel_type_c1 & sel_param_bypass_LF_unused)) | (sel_type_c1 & sel_param_odd_CP_unused)) | (sel_type_c2 & sel_param_bypass_LF_unused)) | (sel_type_c2 & sel_param_odd_CP_unused)) | (sel_type_c3 & sel_param_bypass_LF_unused)) | (sel_type_c3 & sel_param_odd_CP_unused)) | (sel_type_c4 & sel_param_bypass_LF_unused)) | (sel_type_c4 & sel_param_odd_CP_unused))},
+		write_rom_ena = ((rom_first_state | rom_second_state) | (rom_data_state & (~ rom_width_counter_done)));
+endmodule //pll_reconfig_pllrcfg_dc61
+//VALID FILE
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module pll_reconfig (
+	clock,
+	counter_param,
+	counter_type,
+	data_in,
+	pll_areset_in,
+	pll_scandataout,
+	pll_scandone,
+	read_param,
+	reconfig,
+	reset,
+	reset_rom_address,
+	rom_data_in,
+	write_from_rom,
+	write_param,
+	busy,
+	data_out,
+	pll_areset,
+	pll_configupdate,
+	pll_scanclk,
+	pll_scanclkena,
+	pll_scandata,
+	rom_address_out,
+	write_rom_ena)/* synthesis synthesis_clearbox = 2 */;
+
+	input	  clock;
+	input	[2:0]  counter_param;
+	input	[3:0]  counter_type;
+	input	[8:0]  data_in;
+	input	  pll_areset_in;
+	input	  pll_scandataout;
+	input	  pll_scandone;
+	input	  read_param;
+	input	  reconfig;
+	input	  reset;
+	input	  reset_rom_address;
+	input	  rom_data_in;
+	input	  write_from_rom;
+	input	  write_param;
+	output	  busy;
+	output	[8:0]  data_out;
+	output	  pll_areset;
+	output	  pll_configupdate;
+	output	  pll_scanclk;
+	output	  pll_scanclkena;
+	output	  pll_scandata;
+	output	[7:0]  rom_address_out;
+	output	  write_rom_ena;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri0	  pll_areset_in;
+	tri0	  reset_rom_address;
+	tri0	  rom_data_in;
+	tri0	  write_from_rom;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire  sub_wire0;
+	wire [8:0] sub_wire1;
+	wire  sub_wire2;
+	wire  sub_wire3;
+	wire  sub_wire4;
+	wire [7:0] sub_wire5;
+	wire  sub_wire6;
+	wire  sub_wire7;
+	wire  sub_wire8;
+	wire  pll_configupdate = sub_wire0;
+	wire [8:0] data_out = sub_wire1[8:0];
+	wire  pll_scanclk = sub_wire2;
+	wire  pll_scanclkena = sub_wire3;
+	wire  pll_scandata = sub_wire4;
+	wire [7:0] rom_address_out = sub_wire5[7:0];
+	wire  busy = sub_wire6;
+	wire  pll_areset = sub_wire7;
+	wire  write_rom_ena = sub_wire8;
+
+	pll_reconfig_pllrcfg_dc61	pll_reconfig_pllrcfg_dc61_component (
+				.counter_param (counter_param),
+				.data_in (data_in),
+				.counter_type (counter_type),
+				.pll_areset_in (pll_areset_in),
+				.pll_scandataout (pll_scandataout),
+				.pll_scandone (pll_scandone),
+				.reset (reset),
+				.write_from_rom (write_from_rom),
+				.write_param (write_param),
+				.clock (clock),
+				.read_param (read_param),
+				.reconfig (reconfig),
+				.reset_rom_address (reset_rom_address),
+				.rom_data_in (rom_data_in),
+				.pll_configupdate (sub_wire0),
+				.data_out (sub_wire1),
+				.pll_scanclk (sub_wire2),
+				.pll_scanclkena (sub_wire3),
+				.pll_scandata (sub_wire4),
+				.rom_address_out (sub_wire5),
+				.busy (sub_wire6),
+				.pll_areset (sub_wire7),
+				.write_rom_ena (sub_wire8))/* synthesis synthesis_clearbox=2
+	 clearbox_macroname = altpll_reconfig
+	 clearbox_defparam = "init_from_rom=NO;intended_device_family=Cyclone III;scan_init_file=./pll_c16_pal.mif;" */;
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: CHAIN_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_NAME STRING "./pll_c16_pal.mif"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: USE_INIT_FILE STRING "1"
+// Retrieval info: CONSTANT: INIT_FROM_ROM STRING "NO"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: SCAN_INIT_FILE STRING "./pll_c16_pal.mif"
+// Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+// Retrieval info: USED_PORT: counter_param 0 0 3 0 INPUT NODEFVAL "counter_param[2..0]"
+// Retrieval info: USED_PORT: counter_type 0 0 4 0 INPUT NODEFVAL "counter_type[3..0]"
+// Retrieval info: USED_PORT: data_in 0 0 9 0 INPUT NODEFVAL "data_in[8..0]"
+// Retrieval info: USED_PORT: data_out 0 0 9 0 OUTPUT NODEFVAL "data_out[8..0]"
+// Retrieval info: USED_PORT: pll_areset 0 0 0 0 OUTPUT NODEFVAL "pll_areset"
+// Retrieval info: USED_PORT: pll_areset_in 0 0 0 0 INPUT GND "pll_areset_in"
+// Retrieval info: USED_PORT: pll_configupdate 0 0 0 0 OUTPUT NODEFVAL "pll_configupdate"
+// Retrieval info: USED_PORT: pll_scanclk 0 0 0 0 OUTPUT NODEFVAL "pll_scanclk"
+// Retrieval info: USED_PORT: pll_scanclkena 0 0 0 0 OUTPUT NODEFVAL "pll_scanclkena"
+// Retrieval info: USED_PORT: pll_scandata 0 0 0 0 OUTPUT NODEFVAL "pll_scandata"
+// Retrieval info: USED_PORT: pll_scandataout 0 0 0 0 INPUT NODEFVAL "pll_scandataout"
+// Retrieval info: USED_PORT: pll_scandone 0 0 0 0 INPUT NODEFVAL "pll_scandone"
+// Retrieval info: USED_PORT: read_param 0 0 0 0 INPUT NODEFVAL "read_param"
+// Retrieval info: USED_PORT: reconfig 0 0 0 0 INPUT NODEFVAL "reconfig"
+// Retrieval info: USED_PORT: reset 0 0 0 0 INPUT NODEFVAL "reset"
+// Retrieval info: USED_PORT: reset_rom_address 0 0 0 0 INPUT GND "reset_rom_address"
+// Retrieval info: USED_PORT: rom_address_out 0 0 8 0 OUTPUT NODEFVAL "rom_address_out[7..0]"
+// Retrieval info: USED_PORT: rom_data_in 0 0 0 0 INPUT GND "rom_data_in"
+// Retrieval info: USED_PORT: write_from_rom 0 0 0 0 INPUT GND "write_from_rom"
+// Retrieval info: USED_PORT: write_param 0 0 0 0 INPUT NODEFVAL "write_param"
+// Retrieval info: USED_PORT: write_rom_ena 0 0 0 0 OUTPUT NODEFVAL "write_rom_ena"
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @counter_param 0 0 3 0 counter_param 0 0 3 0
+// Retrieval info: CONNECT: @counter_type 0 0 4 0 counter_type 0 0 4 0
+// Retrieval info: CONNECT: @data_in 0 0 9 0 data_in 0 0 9 0
+// Retrieval info: CONNECT: @pll_areset_in 0 0 0 0 pll_areset_in 0 0 0 0
+// Retrieval info: CONNECT: @pll_scandataout 0 0 0 0 pll_scandataout 0 0 0 0
+// Retrieval info: CONNECT: @pll_scandone 0 0 0 0 pll_scandone 0 0 0 0
+// Retrieval info: CONNECT: @read_param 0 0 0 0 read_param 0 0 0 0
+// Retrieval info: CONNECT: @reconfig 0 0 0 0 reconfig 0 0 0 0
+// Retrieval info: CONNECT: @reset 0 0 0 0 reset 0 0 0 0
+// Retrieval info: CONNECT: @reset_rom_address 0 0 0 0 reset_rom_address 0 0 0 0
+// Retrieval info: CONNECT: @rom_data_in 0 0 0 0 rom_data_in 0 0 0 0
+// Retrieval info: CONNECT: @write_from_rom 0 0 0 0 write_from_rom 0 0 0 0
+// Retrieval info: CONNECT: @write_param 0 0 0 0 write_param 0 0 0 0
+// Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
+// Retrieval info: CONNECT: data_out 0 0 9 0 @data_out 0 0 9 0
+// Retrieval info: CONNECT: pll_areset 0 0 0 0 @pll_areset 0 0 0 0
+// Retrieval info: CONNECT: pll_configupdate 0 0 0 0 @pll_configupdate 0 0 0 0
+// Retrieval info: CONNECT: pll_scanclk 0 0 0 0 @pll_scanclk 0 0 0 0
+// Retrieval info: CONNECT: pll_scanclkena 0 0 0 0 @pll_scanclkena 0 0 0 0
+// Retrieval info: CONNECT: pll_scandata 0 0 0 0 @pll_scandata 0 0 0 0
+// Retrieval info: CONNECT: rom_address_out 0 0 8 0 @rom_address_out 0 0 8 0
+// Retrieval info: CONNECT: write_rom_ena 0 0 0 0 @write_rom_ena 0 0 0 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_reconfig.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_reconfig.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_reconfig.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_reconfig.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_reconfig_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL pll_reconfig_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
+// Retrieval info: LIB_FILE: cycloneiii
+// Retrieval info: LIB_FILE: lpm
diff --git a/cores/c16/rom_reconfig_ntsc.qip b/cores/c16/rom_reconfig_ntsc.qip
new file mode 100644
index 0000000..8103d80
--- /dev/null
+++ b/cores/c16/rom_reconfig_ntsc.qip
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "rom_reconfig_ntsc.v"]
diff --git a/cores/c16/rom_reconfig_ntsc.v b/cores/c16/rom_reconfig_ntsc.v
new file mode 100644
index 0000000..ebff5a6
--- /dev/null
+++ b/cores/c16/rom_reconfig_ntsc.v
@@ -0,0 +1,164 @@
+// megafunction wizard: %ROM: 1-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: rom_reconfig_ntsc.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.4 Build 182 03/12/2014 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2014 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module rom_reconfig_ntsc (
+	address,
+	clock,
+	rden,
+	q);
+
+	input	[7:0]  address;
+	input	  clock;
+	input	  rden;
+	output	[0:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+	tri1	  rden;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [0:0] sub_wire0;
+	wire [0:0] q = sub_wire0[0:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (address),
+				.clock0 (clock),
+				.rden_a (rden),
+				.q_a (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.address_b (1'b1),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_a (1'b1),
+				.data_b (1'b1),
+				.eccstatus (),
+				.q_b (),
+				.rden_b (1'b1),
+				.wren_a (1'b0),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_a = "NONE",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+		altsyncram_component.init_file = "pll_c16_ntsc.mif",
+		altsyncram_component.intended_device_family = "Cyclone III",
+		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 256,
+		altsyncram_component.operation_mode = "ROM",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_reg_a = "CLOCK0",
+		altsyncram_component.widthad_a = 8,
+		altsyncram_component.width_a = 1,
+		altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clken NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING "pll_c16_ntsc.mif"
+// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
+// Retrieval info: PRIVATE: WidthData NUMERIC "1"
+// Retrieval info: PRIVATE: rden NUMERIC "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: INIT_FILE STRING "pll_c16_ntsc.mif"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
+// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
+// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 1 0 @q_a 0 0 1 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/cores/c16/rom_reconfig_pal.qip b/cores/c16/rom_reconfig_pal.qip
new file mode 100644
index 0000000..dee85fc
--- /dev/null
+++ b/cores/c16/rom_reconfig_pal.qip
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "rom_reconfig_pal.v"]
diff --git a/cores/c16/rom_reconfig_pal.v b/cores/c16/rom_reconfig_pal.v
new file mode 100644
index 0000000..7813fa3
--- /dev/null
+++ b/cores/c16/rom_reconfig_pal.v
@@ -0,0 +1,164 @@
+// megafunction wizard: %ROM: 1-PORT%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: altsyncram 
+
+// ============================================================
+// File Name: rom_reconfig_pal.v
+// Megafunction Name(s):
+// 			altsyncram
+//
+// Simulation Library Files(s):
+// 			altera_mf
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 13.1.4 Build 182 03/12/2014 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2014 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions 
+//and other software and tools, and its AMPP partner logic 
+//functions, and any output files from any of the foregoing 
+//(including device programming or simulation files), and any 
+//associated documentation or information are expressly subject 
+//to the terms and conditions of the Altera Program License 
+//Subscription Agreement, Altera MegaCore Function License 
+//Agreement, or other applicable license agreement, including, 
+//without limitation, that your use is for the sole purpose of 
+//programming logic devices manufactured by Altera and sold by 
+//Altera or its authorized distributors.  Please refer to the 
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module rom_reconfig_pal (
+	address,
+	clock,
+	rden,
+	q);
+
+	input	[7:0]  address;
+	input	  clock;
+	input	  rden;
+	output	[0:0]  q;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_off
+`endif
+	tri1	  clock;
+	tri1	  rden;
+`ifndef ALTERA_RESERVED_QIS
+// synopsys translate_on
+`endif
+
+	wire [0:0] sub_wire0;
+	wire [0:0] q = sub_wire0[0:0];
+
+	altsyncram	altsyncram_component (
+				.address_a (address),
+				.clock0 (clock),
+				.rden_a (rden),
+				.q_a (sub_wire0),
+				.aclr0 (1'b0),
+				.aclr1 (1'b0),
+				.address_b (1'b1),
+				.addressstall_a (1'b0),
+				.addressstall_b (1'b0),
+				.byteena_a (1'b1),
+				.byteena_b (1'b1),
+				.clock1 (1'b1),
+				.clocken0 (1'b1),
+				.clocken1 (1'b1),
+				.clocken2 (1'b1),
+				.clocken3 (1'b1),
+				.data_a (1'b1),
+				.data_b (1'b1),
+				.eccstatus (),
+				.q_b (),
+				.rden_b (1'b1),
+				.wren_a (1'b0),
+				.wren_b (1'b0));
+	defparam
+		altsyncram_component.address_aclr_a = "NONE",
+		altsyncram_component.clock_enable_input_a = "BYPASS",
+		altsyncram_component.clock_enable_output_a = "BYPASS",
+		altsyncram_component.init_file = "pll_c16_pal.mif",
+		altsyncram_component.intended_device_family = "Cyclone III",
+		altsyncram_component.lpm_hint = "ENABLE_RUNTIME_MOD=NO",
+		altsyncram_component.lpm_type = "altsyncram",
+		altsyncram_component.numwords_a = 256,
+		altsyncram_component.operation_mode = "ROM",
+		altsyncram_component.outdata_aclr_a = "NONE",
+		altsyncram_component.outdata_reg_a = "CLOCK0",
+		altsyncram_component.widthad_a = 8,
+		altsyncram_component.width_a = 1,
+		altsyncram_component.width_byteena_a = 1;
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+// Retrieval info: PRIVATE: Clken NUMERIC "0"
+// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+// Retrieval info: PRIVATE: MIFfilename STRING "pll_c16_pal.mif"
+// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+// Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+// Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
+// Retrieval info: PRIVATE: WidthData NUMERIC "1"
+// Retrieval info: PRIVATE: rden NUMERIC "1"
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+// Retrieval info: CONSTANT: INIT_FILE STRING "pll_c16_pal.mif"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+// Retrieval info: CONSTANT: WIDTH_A NUMERIC "1"
+// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+// Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+// Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
+// Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
+// Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
+// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
+// Retrieval info: CONNECT: q 0 0 1 0 @q_a 0 0 1 0
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal.inc FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal.cmp FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal.bsf FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal_inst.v FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal_bb.v FALSE
+// Retrieval info: LIB_FILE: altera_mf
diff --git a/cores/c64/C64_mist.qsf b/cores/c64/C64_mist.qsf
index 63b23f7..ad96e0b 100644
--- a/cores/c64/C64_mist.qsf
+++ b/cores/c64/C64_mist.qsf
@@ -166,7 +166,7 @@ set_global_assignment -name USE_CONFIGURATION_DEVICE OFF
 # SignalTap II Assignments
 # ========================
 set_global_assignment -name ENABLE_SIGNALTAP OFF
-set_global_assignment -name USE_SIGNALTAP_FILE output_files/sid.stp
+set_global_assignment -name USE_SIGNALTAP_FILE output_files/pll.stp
 
 # Power Estimation Assignments
 # ============================
@@ -320,6 +320,7 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CONF_DATA0
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
 set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top
 set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
+set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF
 set_global_assignment -name VERILOG_FILE rtl/sid8580/sid_voice.v
 set_global_assignment -name VERILOG_FILE rtl/sid8580/sid_filters.v
 set_global_assignment -name VERILOG_FILE rtl/sid8580/sid_envelope.v
@@ -375,6 +376,13 @@ set_global_assignment -name VHDL_FILE rtl/t65/T65_Pack.vhd
 set_global_assignment -name VHDL_FILE rtl/t65/T65_MCode.vhd
 set_global_assignment -name VHDL_FILE rtl/t65/T65_ALU.vhd
 set_global_assignment -name VHDL_FILE rtl/t65/T65.vhd
-set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF
 set_global_assignment -name SIGNALTAP_FILE output_files/sid.stp
+set_global_assignment -name QIP_FILE rtl/mist/pll.qip
+set_global_assignment -name QIP_FILE rtl/mist/pll_c64.qip
+set_global_assignment -name QIP_FILE rtl/mist/pll_c64_reconfig.qip
+set_global_assignment -name QIP_FILE rtl/mist/rom_reconfig_pal.qip
+set_global_assignment -name QIP_FILE rtl/mist/rom_reconfig_ntsc.qip
+set_global_assignment -name SIGNALTAP_FILE output_files/pll.stp
+set_location_assignment PIN_46 -to UART_TX
+set_location_assignment PIN_31 -to UART_RX
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/cores/c64/C64_mist.sdc b/cores/c64/C64_mist.sdc
index 91b4b27..7e94cbb 100644
--- a/cores/c64/C64_mist.sdc
+++ b/cores/c64/C64_mist.sdc
@@ -34,6 +34,8 @@ derive_clock_uncertainty
 
 # Clock groups
 set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {pll_2|altpll_component|auto_generated|pll1|clk[*]}]
+set_clock_groups -asynchronous -group [get_clocks {pll_2|altpll_component|auto_generated|pll1|clk[0]}] -group [get_clocks {pll|altpll_component|auto_generated|pll1|clk[*]}]
 
 
 # Some relaxed constrain to the VGA pins. The signals should arrive together, the delay is not really important.
@@ -41,11 +43,11 @@ set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|cl
 set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -min -5 [get_ports {VGA_*}]
 
 # SDRAM delays
-set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -max 6.4 [get_ports SDRAM_DQ[*]]
-set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -min 3.2 [get_ports SDRAM_DQ[*]]
+set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -max 6.4 [get_ports SDRAM_DQ[*]]
+set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -min 3.2 [get_ports SDRAM_DQ[*]]
 
-set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
-set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
 
 set_multicycle_path -from {video_mixer:vmixer|scandoubler:scandoubler|Hq2x:Hq2x|*} -to {VGA_*[*]} -setup 4
 set_multicycle_path -from {video_mixer:vmixer|scandoubler:scandoubler|Hq2x:Hq2x|*} -to {VGA_*[*]} -hold 3
@@ -53,6 +55,8 @@ set_multicycle_path -from {video_mixer:vmixer|scandoubler:scandoubler|Hq2x:Hq2x|
 set_multicycle_path -to {VGA_*[*]} -setup 4
 set_multicycle_path -to {VGA_*[*]} -hold 3
 
+set_false_path -from [get_ports {UART_RX}]
+set_false_path -to [get_ports {UART_TX}]
 set_false_path -to [get_ports {AUDIO_L}]
 set_false_path -to [get_ports {AUDIO_R}]
 set_false_path -to [get_ports {LED}]
diff --git a/cores/c64/PLLJ_PLLSPE_INFO.txt b/cores/c64/PLLJ_PLLSPE_INFO.txt
deleted file mode 100644
index 9c5acfa..0000000
--- a/cores/c64/PLLJ_PLLSPE_INFO.txt
+++ /dev/null
@@ -1,5 +0,0 @@
-PLL_Name	pll:pll|altpll:altpll_component|pll_altpll:auto_generated|pll1
-PLLJITTER	25
-PLLSPEmax	84
-PLLSPEmin	-53
-
diff --git a/cores/c64/rtl/fpga64_sid_iec.vhd b/cores/c64/rtl/fpga64_sid_iec.vhd
index b5b606d..f651b20 100644
--- a/cores/c64/rtl/fpga64_sid_iec.vhd
+++ b/cores/c64/rtl/fpga64_sid_iec.vhd
@@ -86,9 +86,6 @@ entity fpga64_sid_iec is
 		-- joystick interface
 		joyA        : in  unsigned(6 downto 0);
 		joyB        : in  unsigned(6 downto 0);
-		-- 4 player interface
-		joyC			: in  unsigned(6 downto 0);
-		joyD			: in  unsigned(6 downto 0);
 
 		-- serial port, for connection to pheripherals
 		serioclk    : out std_logic;
@@ -110,6 +107,22 @@ entity fpga64_sid_iec is
 		iec_atn_o	: out std_logic;
 --		iec_atn_i	: in  std_logic;
 
+		-- user port
+		cnt1_in		: in std_logic := '1';
+		cnt1_out	: out std_logic;
+		cnt2_in		: in std_logic := '1';
+		cnt2_out	: out std_logic;
+		sp1_in		: in std_logic := '1';
+		sp1_out		: out std_logic;
+		sp2_in		: in std_logic := '1';
+		sp2_out		: out std_logic;
+		flag2_n		: in std_logic := '1';
+		pc2_n		: out std_logic;
+		pa2_in		: in std_logic;
+		pa2_out		: out std_logic;
+		pb_in 		: in std_logic_vector(7 downto 0);
+		pb_out		: out std_logic_vector(7 downto 0);
+
 		-- CIA
 		cia_mode    : in std_logic;
 
@@ -204,18 +217,14 @@ architecture rtl of fpga64_sid_iec is
 	signal theScanCode: unsigned(7 downto 0);
 
 	-- I/O
-	signal cia1_pai: unsigned(7 downto 0);
-	signal cia1_pao: unsigned(7 downto 0);
-	signal cia1_pad: unsigned(7 downto 0);
-	signal cia1_pbi: unsigned(7 downto 0);
-	signal cia1_pbo: unsigned(7 downto 0);
-	signal cia1_pbd: unsigned(7 downto 0);
-	signal cia2_pai: unsigned(7 downto 0);
-	signal cia2_pao: unsigned(7 downto 0);
-	signal cia2_pad: unsigned(7 downto 0);
-	signal cia2_pbi: unsigned(7 downto 0);
-	signal cia2_pbo: unsigned(7 downto 0);
-	signal cia2_pbd: unsigned(7 downto 0);
+	signal cia1_pai: std_logic_vector(7 downto 0);
+	signal cia1_pao: std_logic_vector(7 downto 0);
+	signal cia1_pbi: std_logic_vector(7 downto 0);
+	signal cia1_pbo: std_logic_vector(7 downto 0);
+	signal cia2_pai: std_logic_vector(7 downto 0);
+	signal cia2_pao: std_logic_vector(7 downto 0);
+	signal cia2_pbi: std_logic_vector(7 downto 0);
+	signal cia2_pbo: std_logic_vector(7 downto 0);
 
 	signal debugWE: std_logic := '0';
 	signal debugData: unsigned(7 downto 0) := (others => '0');
@@ -677,9 +686,11 @@ div1m: process(clk32)				-- this process devides 32 MHz to 1MHz (for the SID)
             pb_in => std_logic_vector(cia1_pbi),
             unsigned(pb_out) => cia1_pbo,
 
-            flag_n => '1',
-            sp_in => '1',
-            cnt_in => '1',
+            flag_n => flag2_n,
+            sp_in => sp1_in,
+            sp_out => sp1_out,
+            cnt_in => cnt1_in,
+            cnt_out => cnt1_out,
 
             pc_n => open,
             tod => vicVSync,
@@ -705,11 +716,13 @@ div1m: process(clk32)				-- this process devides 32 MHz to 1MHz (for the SID)
             pb_in => std_logic_vector(cia2_pbi),
             unsigned(pb_out) => cia2_pbo,
 
-            flag_n => '1',
-            sp_in => '1',
-            cnt_in => '1',
+            flag_n => flag2_n,
+            sp_in => sp2_in,
+            sp_out => sp2_out,
+            cnt_in => cnt2_in,
+            cnt_out => cnt2_out,
 
-            pc_n => open,
+            pc_n => pc2_n,
             tod => vicVSync,
             irq_n => irq_cia2
 		);
@@ -757,11 +770,11 @@ div1m: process(clk32)				-- this process devides 32 MHz to 1MHz (for the SID)
 
 			joyA => (not joyA(4 downto 0)),
 			joyB => (not joyB(4 downto 0)),
-			pai => cia1_pao,
-			pbi => cia1_pbo,
-			pao => cia1_pai,
-			pbo => cia1_pbi,
-			
+			pai => unsigned(cia1_pao),
+			pbi => unsigned(cia1_pbo),
+			std_logic_vector(pao) => cia1_pai,
+			std_logic_vector(pbo) => cia1_pbi,
+
 			videoKey => videoKey,
 			traceKey => open,
 			trace2Key => trace2Key,
@@ -808,7 +821,7 @@ div1m: process(clk32)				-- this process devides 32 MHz to 1MHz (for the SID)
 	iec_data_o <= cia2_pao(5);
 	iec_clk_o <= cia2_pao(4);
 	iec_atn_o <= cia2_pao(3);
-	ramDataOut <= "00" & cia2_pao(5 downto 3) & "000" when sysCycle >= CYCLE_IEC0 and sysCycle <= CYCLE_IEC3 else cpuDo;
+	ramDataOut <= "00" & unsigned(cia2_pao)(5 downto 3) & "000" when sysCycle >= CYCLE_IEC0 and sysCycle <= CYCLE_IEC3 else cpuDo;
 	ramAddr <= systemAddr when (phi0_cpu = '1') or (phi0_vic = '1') else (others => '0');
 	ramWe <= '0' when sysCycle = CYCLE_IEC2 or sysCycle = CYCLE_IEC3 else not systemWe;
 	ramCE <= '0' when sysCycle /= CYCLE_IDLE0 and sysCycle /= CYCLE_IDLE1 and sysCycle /= CYCLE_IDLE2 and 
@@ -884,10 +897,10 @@ div1m: process(clk32)				-- this process devides 32 MHz to 1MHz (for the SID)
 	end process;
 
 	cia2_pai(5 downto 0) <= cia2_pao(5 downto 0);
-	cia2_pbi(7 downto 6) <= cia2_pbo(7 downto 6);
-
-	-- Protovision 4 player interface
-	cia2_pbi(5 downto 0) <= not joyC(5 downto 0) when cia2_pbo(7) = '1' else not joyD(5 downto 0);
+	cia2_pai(2) <= pa2_in;
+	pa2_out <= cia2_pao(2);
+	cia2_pbi <= pb_in;
+	pb_out <= cia2_pbo;
 
 -- -----------------------------------------------------------------------
 -- VIC bank to address lines
diff --git a/cores/c64/rtl/mist/c64_mist.vhd b/cores/c64/rtl/mist/c64_mist.vhd
index 5fbb291..2d426c1 100644
--- a/cores/c64/rtl/mist/c64_mist.vhd
+++ b/cores/c64/rtl/mist/c64_mist.vhd
@@ -68,7 +68,10 @@ entity c64_mist is port
    SPI_DI     : in    std_logic;
    SPI_SS2    : in    std_logic;
    SPI_SS3    : in    std_logic;
-   CONF_DATA0 : in    std_logic
+   CONF_DATA0 : in    std_logic;
+
+   UART_RX    : in    std_logic;
+   UART_TX    : out   std_logic
 );
 end c64_mist;
 
@@ -126,14 +129,16 @@ constant CONF_STR : string :=
 	"S,D64,Mount Disk;"&
 	"F,PRG,Load File;"&
 	"F,CRT,Load Cartridge;" &--3
---	"F,TAP,Load File;"&--4
---	"F,T64,Load File;"&--5
+	"F,ROM,Load Kernal;"&
+--	"F,TAP,Load File;"&--5
+--	"F,T64,Load File;"&--6
 	"OG,Disk Write,Enable,Disable;"&
 	"O2,Video standard,PAL,NTSC;"&
 	"O8A,Scandoubler Fx,None,HQ2x-320,HQ2x-160,CRT 25%,CRT 50%;"&
 	"ODF,SID,6581 Mono,6581 Stereo,8580 Mono,8580 Stereo,Pseudo Stereo;"&
-	"O3,Joysticks,normal,swapped;"&
 	"O6,Audio filter,On,Off;"&
+	"O3,Joysticks,normal,swapped;"&
+	"O7,Userport,4-player IF,UART;"&
 	"O4,CIA Model,6256,8521;"&
 --	"OB,BIOS,C64,C64GS;" &
 	"T5,Reset & Detach Cartridge;";
@@ -255,9 +260,9 @@ component cartridge port
 	IOE			: in  std_logic;									-- IOE signal &DE00
 	IOF			: in  std_logic;									-- IOF signal &DF00
 
-	clk32			: in  std_logic;									-- 32mhz clock source
-	reset			: in  std_logic;									-- reset signal
-	reset_out	: out std_logic;									-- reset signal
+	clk32		: in  std_logic;							-- 32mhz clock source
+	reset		: in  std_logic;							-- reset signal
+	reset_out	: out std_logic;							-- reset signal
 
 	cart_id		: in  std_logic_vector(15 downto 0);		-- cart ID or cart type
 	cart_exrom  : in  std_logic_vector(7 downto 0);			-- CRT file EXROM status
@@ -289,8 +294,27 @@ component cartridge port
 
 end component cartridge;
 
-	signal pll_locked_in: std_logic_vector(1 downto 0);
-	signal pll_locked: std_logic;
+	signal pll_locked_in : std_logic_vector(1 downto 0);
+	signal pll_locked : std_logic;
+	signal pll_areset : std_logic;
+	signal pll_scanclk : std_logic;
+	signal pll_scandata : std_logic;
+	signal pll_scanclkena : std_logic;
+	signal pll_configupdate : std_logic;
+	signal pll_scandataout : std_logic;
+	signal pll_scandone : std_logic;
+	signal pll_rom_address : std_logic_vector(7 downto 0);
+	signal pll_write_rom_ena : std_logic;
+	signal pll_write_from_rom : std_logic;
+	signal pll_reconfig : std_logic;
+	signal pll_reconfig_busy : std_logic;
+	signal pll_reconfig_reset : std_logic;
+	signal pll_reconfig_state : std_logic_vector(1 downto 0) := "00";
+	signal pll_reconfig_timeout : integer;
+	signal q_reconfig_pal : std_logic_vector(0 downto 0);
+	signal q_reconfig_ntsc : std_logic_vector(0 downto 0);
+	signal pll_rom_q : std_logic;
+
 	signal c1541_reset: std_logic;
 	signal idle: std_logic;
 	signal ces: std_logic_vector(3 downto 0);
@@ -349,6 +373,7 @@ end component cartridge;
 	
 	signal c1541rom_wr   : std_logic;
 	signal c64rom_wr     : std_logic;
+	signal c64rom_addr   : std_logic_vector(13 downto 0);
 
 	signal joyA : std_logic_vector(31 downto 0);
 	signal joyB : std_logic_vector(31 downto 0);
@@ -405,18 +430,27 @@ end component cartridge;
 	signal c1541_iec_data_i : std_logic;
 	signal c1541_iec_clk_i  : std_logic;
 
+	signal pa2_in	: std_logic;
+	signal pa2_out  : std_logic;
+	signal pb_in	: std_logic_vector(7 downto 0);
+	signal pb_out	: std_logic_vector(7 downto 0);
+	signal flag2_n  : std_logic;
+
 	signal tv15Khz_mode   : std_logic;
 	signal ypbpr          : std_logic;
-	signal ntsc_init_mode : std_logic;
+	signal ntsc_init_mode : std_logic := '0';
+	signal ntsc_init_mode_d: std_logic;
+	signal ntsc_init_mode_d2: std_logic;
+	signal ntsc_init_mode_d3: std_logic;
 
 	alias  c64_addr_int : unsigned is unsigned(c64_addr);
 	alias  c64_data_in_int   : unsigned is unsigned(c64_data_in);
 	signal c64_data_in16: std_logic_vector(15 downto 0);
 	alias  c64_data_out_int   : unsigned is unsigned(c64_data_out);
 
-	signal clk_ram : std_logic;
-	signal clk32 : std_logic;
-	signal clk16 : std_logic;
+	signal c64_clk : std_logic;	-- 31.527mhz (PAL), 32.727mhz(NTSC) clock source
+	signal clk_ram : std_logic; -- 2 x c64_clk
+	signal clk32   : std_logic; -- 32mhz
 	signal ce_8  : std_logic;
 	signal ce_4  : std_logic;
 	signal hq2x160 : std_logic;
@@ -465,7 +499,7 @@ begin
 	user_io_d : user_io
 	generic map (STRLEN => CONF_STR'length)
 	port map (
-		clk_sys => clk32,
+		clk_sys => c64_clk,
 		clk_sd  => clk32,
 
 		SPI_CLK => SPI_SCK,
@@ -503,7 +537,7 @@ begin
 
 	data_io_d: data_io
 	port map (
-		clk_sys => clk32,
+		clk_sys => c64_clk,
 		SPI_SCK => SPI_SCK,
 		SPI_SS2 => SPI_SS2,
 		SPI_DI => SPI_DI,
@@ -530,7 +564,7 @@ begin
 		mem_ce => not ram_ce,
 		mem_ce_out => mem_ce,
 
-	 	clk32 => clk32,			
+		clk32 => c64_clk,
 		reset => reset_n,
 		reset_out => reset_crt,
 		
@@ -579,9 +613,9 @@ begin
 	sdram_ce <= mem_ce when iec_cycle='0' else ioctl_iec_cycle_used;
 	sdram_we <= not ram_we when iec_cycle='0' else ioctl_iec_cycle_used;
 
-	process(clk32)
+	process(c64_clk)
 	begin
-		if falling_edge(clk32) then
+		if falling_edge(c64_clk) then
 
 			old_download <= ioctl_download;
 			iec_cycleD <= iec_cycle;
@@ -655,7 +689,7 @@ begin
 						end if;
 					end if;
 					
-					if ioctl_index = 4 then
+					if ioctl_index = 5 then
 						if ioctl_addr = 0 then
 							ioctl_load_addr <= '0' & X"200000";
 							ioctl_ram_data <= ioctl_data;
@@ -694,13 +728,13 @@ begin
 		end if;
 	end process;
 
-	c64rom_wr   <= ioctl_wr when (ioctl_index = 0) and (ioctl_addr(14) = '0') and (ioctl_download = '1') else '0';
+	c64rom_wr   <= ioctl_wr when (((ioctl_index = 0) and (ioctl_addr(14) = '0')) or (ioctl_index = 4)) and (ioctl_download = '1') else '0';
+	c64rom_addr <= ioctl_addr(13 downto 0) when ioctl_index = 0 else '1' & ioctl_addr(12 downto 0);
 	c1541rom_wr <= ioctl_wr when (ioctl_index = 0) and (ioctl_addr(14) = '1') and (ioctl_download = '1') else '0';
 
-	process(clk32)
+	process(c64_clk)
 	begin
-		if rising_edge(clk32) then
-			clk16 <= not clk16;
+		if rising_edge(c64_clk) then
 			clkdiv <= std_logic_vector(unsigned(clkdiv)+1);
 			if(clkdiv(1 downto 0) = "00") then
 				ce_8 <= '1';
@@ -717,25 +751,121 @@ begin
 
 	ntsc_init_mode <= status(2);
 
-   -- second  to generate 64mhz clock and phase shifted ram clock	
-	pll : entity work.pll
+	pll_rom_pal : entity work.rom_reconfig_pal
 	port map(
-		inclk0 => CLOCK_27,
-		c0 => clk_ram,
-		c1 => SDRAM_CLK,
-		c2 => clk32,
-		locked => pll_locked
+		address => pll_rom_address,
+		clock => clk32,
+		rden => pll_write_rom_ena,
+		q => q_reconfig_pal
+	);
+
+	pll_rom_ntsc : entity work.rom_reconfig_ntsc
+	port map(
+		address => pll_rom_address,
+		clock => clk32,
+		rden => pll_write_rom_ena,
+		q => q_reconfig_ntsc
+	);
+
+	pll_rom_q <= q_reconfig_pal(0) when ntsc_init_mode_d2 = '0' else q_reconfig_ntsc(0);
+
+	pll_c64_reconfig : entity work.pll_c64_reconfig
+	port map (
+		busy => pll_reconfig_busy,
+		clock  => clk32,
+		counter_param => (others => '0'),
+		counter_type => (others => '0'),
+		data_in => (others => '0'),
+		pll_areset => pll_areset,
+		pll_areset_in  => '0',
+		pll_configupdate => pll_configupdate,
+		pll_scanclk => pll_scanclk,
+		pll_scanclkena => pll_scanclkena,
+		pll_scandata => pll_scandata,
+		pll_scandataout => pll_scandataout,
+        pll_scandone => pll_scandone,
+		read_param => '0',
+        reconfig => pll_reconfig,
+		reset => pll_reconfig_reset,
+		reset_rom_address => '0',
+		rom_address_out => pll_rom_address,
+		rom_data_in => pll_rom_q,
+		write_from_rom => pll_write_from_rom,
+		write_param  => '0',
+        write_rom_ena => pll_write_rom_ena
 	);
 
 	process(clk32)
 	begin
 		if rising_edge(clk32) then
+			ntsc_init_mode_d <= ntsc_init_mode;
+			ntsc_init_mode_d2 <= ntsc_init_mode_d;
+			pll_write_from_rom <= '0';
+			pll_reconfig <= '0';
+			pll_reconfig_reset <= '0';
+			case pll_reconfig_state is
+			when "00" =>
+				ntsc_init_mode_d3 <= ntsc_init_mode_d2;
+				if ntsc_init_mode_d3 /= ntsc_init_mode_d2 then
+					pll_write_from_rom <= '1';
+					pll_reconfig_state <= "01";
+				end if;
+			when "01" =>
+				pll_reconfig_state <= "10";
+			when "10" =>
+				if pll_reconfig_busy = '0' then
+					pll_reconfig <= '1';
+					pll_reconfig_state <= "11";
+					pll_reconfig_timeout <= 1000;
+				end if;
+			when "11" =>
+				pll_reconfig_timeout <= pll_reconfig_timeout - 1;
+				if pll_reconfig_timeout = 1 then
+					pll_reconfig_reset <= '1'; -- sometimes pll reconfig stuck in busy state
+					pll_reconfig_state <= "00";
+				end if;
+				if pll_reconfig = '0' and pll_reconfig_busy = '0' then
+					pll_reconfig_state <= "00";
+				end if;
+			when others => null;
+			end case;
+		end if;
+	end process;
+
+	-- clock for C64 and SDRAM
+	pll : entity work.pll_c64
+	port map(
+		inclk0 => CLOCK_27,
+		c0 => c64_clk,
+		c1 => clk_ram,
+		areset => pll_areset,
+		scanclk => pll_scanclk,
+		scandata => pll_scandata,
+		scanclkena => pll_scanclkena,
+		configupdate => pll_configupdate,
+		scandataout => pll_scandataout,
+		scandone => pll_scandone
+	);
+	SDRAM_CLK <= not clk_ram;
+
+	-- clock for 1541
+	pll_2 : entity work.pll
+	port map(
+		inclk0 => CLOCK_27,
+		c0 => clk32,
+		locked => pll_locked
+	);
+
+	process(c64_clk)
+	begin
+		if rising_edge(c64_clk) then
 			-- Reset by:
 			-- Button at device, IO controller reboot, OSD or FPGA startup
 			if status(0)='1' or pll_locked = '0' then
 				reset_counter <= 1000000;
 				reset_n <= '0';
-			elsif buttons(1)='1' or status(5)='1' or reset_key = '1' or reset_crt='1' or (ioctl_download='1' and ioctl_index = 3) then
+			elsif buttons(1)='1' or status(5)='1' or reset_key = '1' or reset_crt='1' or
+			(ioctl_download='1' and (ioctl_index = 3 or ioctl_index = 4)) then
 				reset_counter <= 255;
 				reset_n <= '0';
 			elsif ioctl_download ='1' then
@@ -783,7 +913,7 @@ begin
 
 	dac : sigma_delta_dac
 	port map (
-		clk => clk32,
+		clk => c64_clk,
 		ldatasum => audio_data_l(17 downto 3),
 		rdatasum => audio_data_r(17 downto 3),
 		aleft => AUDIO_L,
@@ -793,7 +923,7 @@ begin
 
 	fpga64 : entity work.fpga64_sid_iec
 	port map(
-		clk32 => clk32,
+		clk32 => c64_clk,
 		reset_n => reset_n,
 		c64gs => status(11),-- not enough BRAM
 		kbd_clk => not ps2_clk,
@@ -828,8 +958,6 @@ begin
 		ba => open,
 		joyA => unsigned(joyA_c64),
 		joyB => unsigned(joyB_c64),
-		joyC => unsigned(joyC_c64),
-		joyD => unsigned(joyD_c64),
 		serioclk => open,
 		ces => ces,
 		SIDclk => open,
@@ -845,15 +973,43 @@ begin
 		iec_data_i => c64_iec_data_i,
 		iec_clk_i  => c64_iec_clk_i,
 --		iec_atn_i  => not c64_iec_atn_i,
+		pa2_in => pa2_in,
+		pa2_out => pa2_out,
+		pb_in => pb_in,
+		pb_out => pb_out,
+		flag2_n => flag2_n,
 		cia_mode => status(4),
 		disk_num => open,
-		c64rom_addr => ioctl_addr(13 downto 0),
+		c64rom_addr => c64rom_addr,
 		c64rom_data => ioctl_data,
 		c64rom_wr => c64rom_wr,
 --		cart_detach_key => cart_detach_key,
 		reset_key => reset_key
 	);
 
+	-- connect user port
+	process (pa2_out, pb_out, joyC_c64, joyD_c64, UART_RX, status)
+	begin
+		pa2_in <= pa2_out;
+		if status(7) = '0' then
+			-- Protovision 4 player interface
+			flag2_n <= '1';
+			UART_TX <= '0';
+			pb_in(7 downto 6) <= pb_out(7 downto 6);
+			if pb_out(7) = '1' then
+				pb_in(5 downto 0) <= not joyC_c64(5 downto 0);
+			else
+				pb_in(5 downto 0) <= not joyD_c64(5 downto 0);
+			end if;
+		else
+			-- UART
+			pb_in(7 downto 1) <= pb_out(7 downto 1);
+			flag2_n <= UART_RX;
+			pb_in(0) <= UART_RX;
+			UART_TX <= pa2_out;
+		end if;
+	end process;
+
 	disk_readonly <= status(16);
 
     c64_iec_data_i <= c1541_iec_data_o;
@@ -863,12 +1019,12 @@ begin
 	c1541_iec_data_i <= c64_iec_data_o;
 	c1541_iec_clk_i  <= c64_iec_clk_o;
 
-	process(clk32, reset_n)
+	process(c64_clk, reset_n)
 		variable reset_cnt : integer range 0 to 32000000;
 	begin
 		if reset_n = '0' then
 			reset_cnt := 100000;
-		elsif rising_edge(clk32) then
+		elsif rising_edge(c64_clk) then
 			if reset_cnt /= 0 then
 				reset_cnt := reset_cnt - 1;
 			end if;
@@ -887,7 +1043,7 @@ begin
 		clk32 => clk32,
 		reset => c1541_reset,
 
-		c1541rom_clk => clk32,
+		c1541rom_clk => c64_clk,
 		c1541rom_addr => ioctl_addr(13 downto 0),
 		c1541rom_data => ioctl_data,
 		c1541rom_wr => c1541rom_wr,
@@ -918,7 +1074,7 @@ begin
 
 	comp_sync : entity work.composite_sync
 	port map(
-		clk32 => clk32,
+		clk32 => c64_clk,
 		hsync => hsync,
 		vsync => vsync,
 		ntsc  => ntsc_init_mode,
@@ -935,9 +1091,9 @@ begin
 	hq2x <= status(9) xor status(8);
 	ce_pix_actual <= ce_4 when hq2x160='1' else ce_8;
 	
-	process(clk32)
+	process(c64_clk)
 	begin
-		if rising_edge(clk32) then
+		if rising_edge(c64_clk) then
 			if((old_vsync = '0') and (vsync_out = '1')) then
 				if(status(10 downto 8)="010") then
 					hq2x160 <= '1';
diff --git a/cores/c64/rtl/mist/pll.ppf b/cores/c64/rtl/mist/pll.ppf
new file mode 100644
index 0000000..547d702
--- /dev/null
+++ b/cores/c64/rtl/mist/pll.ppf
@@ -0,0 +1,10 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="pll" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+
+</global>
+</pinplan>
diff --git a/cores/c64/rtl/mist/pll.qip b/cores/c64/rtl/mist/pll.qip
new file mode 100644
index 0000000..4866536
--- /dev/null
+++ b/cores/c64/rtl/mist/pll.qip
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"]
diff --git a/cores/c64/rtl/mist/pll.vhd b/cores/c64/rtl/mist/pll.vhd
index 1e72638..a293a4f 100644
--- a/cores/c64/rtl/mist/pll.vhd
+++ b/cores/c64/rtl/mist/pll.vhd
@@ -14,7 +14,7 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 13.1.4 Build 182 03/12/2014 SJ Full Version
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
 -- ************************************************************
 
 
@@ -44,8 +44,6 @@ ENTITY pll IS
 	(
 		inclk0		: IN STD_LOGIC  := '0';
 		c0		: OUT STD_LOGIC ;
-		c1		: OUT STD_LOGIC ;
-		c2		: OUT STD_LOGIC ;
 		locked		: OUT STD_LOGIC 
 	);
 END pll;
@@ -57,11 +55,9 @@ ARCHITECTURE SYN OF pll IS
 	SIGNAL sub_wire1	: STD_LOGIC ;
 	SIGNAL sub_wire2	: STD_LOGIC ;
 	SIGNAL sub_wire3	: STD_LOGIC ;
-	SIGNAL sub_wire4	: STD_LOGIC ;
-	SIGNAL sub_wire5	: STD_LOGIC ;
-	SIGNAL sub_wire6	: STD_LOGIC_VECTOR (1 DOWNTO 0);
-	SIGNAL sub_wire7_bv	: BIT_VECTOR (0 DOWNTO 0);
-	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire4	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire5_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (0 DOWNTO 0);
 
 
 
@@ -72,14 +68,6 @@ ARCHITECTURE SYN OF pll IS
 		clk0_duty_cycle		: NATURAL;
 		clk0_multiply_by		: NATURAL;
 		clk0_phase_shift		: STRING;
-		clk1_divide_by		: NATURAL;
-		clk1_duty_cycle		: NATURAL;
-		clk1_multiply_by		: NATURAL;
-		clk1_phase_shift		: STRING;
-		clk2_divide_by		: NATURAL;
-		clk2_duty_cycle		: NATURAL;
-		clk2_multiply_by		: NATURAL;
-		clk2_phase_shift		: STRING;
 		inclk0_input_frequency		: NATURAL;
 		intended_device_family		: STRING;
 		lpm_hint		: STRING;
@@ -138,33 +126,21 @@ ARCHITECTURE SYN OF pll IS
 	END COMPONENT;
 
 BEGIN
-	sub_wire7_bv(0 DOWNTO 0) <= "0";
-	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
-	sub_wire4    <= sub_wire0(2);
-	sub_wire3    <= sub_wire0(0);
-	sub_wire1    <= sub_wire0(1);
-	c1    <= sub_wire1;
+	sub_wire5_bv(0 DOWNTO 0) <= "0";
+	sub_wire5    <= To_stdlogicvector(sub_wire5_bv);
+	sub_wire1    <= sub_wire0(0);
+	c0    <= sub_wire1;
 	locked    <= sub_wire2;
-	c0    <= sub_wire3;
-	c2    <= sub_wire4;
-	sub_wire5    <= inclk0;
-	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
+	sub_wire3    <= inclk0;
+	sub_wire4    <= sub_wire5(0 DOWNTO 0) & sub_wire3;
 
 	altpll_component : altpll
 	GENERIC MAP (
 		bandwidth_type => "AUTO",
 		clk0_divide_by => 27,
 		clk0_duty_cycle => 50,
-		clk0_multiply_by => 64,
+		clk0_multiply_by => 32,
 		clk0_phase_shift => "0",
-		clk1_divide_by => 27,
-		clk1_duty_cycle => 50,
-		clk1_multiply_by => 64,
-		clk1_phase_shift => "-2604",
-		clk2_divide_by => 27,
-		clk2_duty_cycle => 50,
-		clk2_multiply_by => 32,
-		clk2_phase_shift => "0",
 		inclk0_input_frequency => 37037,
 		intended_device_family => "Cyclone III",
 		lpm_hint => "CBX_MODULE_PREFIX=pll",
@@ -197,8 +173,8 @@ BEGIN
 		port_scanread => "PORT_UNUSED",
 		port_scanwrite => "PORT_UNUSED",
 		port_clk0 => "PORT_USED",
-		port_clk1 => "PORT_USED",
-		port_clk2 => "PORT_USED",
+		port_clk1 => "PORT_UNUSED",
+		port_clk2 => "PORT_UNUSED",
 		port_clk3 => "PORT_UNUSED",
 		port_clk4 => "PORT_UNUSED",
 		port_clk5 => "PORT_UNUSED",
@@ -216,7 +192,7 @@ BEGIN
 		width_clock => 5
 	)
 	PORT MAP (
-		inclk => sub_wire6,
+		inclk => sub_wire4,
 		clk => sub_wire0,
 		locked => sub_wire2
 	);
@@ -245,14 +221,8 @@ END SYN;
 -- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
 -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9"
--- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
--- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
--- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "64.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "64.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "32.000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "32.000000"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -273,34 +243,18 @@ END SYN;
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
 -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
 -- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
 -- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
--- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
 -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "48"
--- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "7"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
--- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "64.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "64.00000000"
--- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "32.00000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "32.00000000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
 -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
 -- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-60.00000000"
--- Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
--- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps"
 -- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
 -- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
@@ -323,33 +277,19 @@ END SYN;
 -- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
 -- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
 -- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
--- Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
 -- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
 -- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
 -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
 -- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
--- Retrieval info: PRIVATE: USE_CLK2 STRING "1"
 -- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
--- Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
 -- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
 -- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
 -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
 -- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27"
 -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "64"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "32"
 -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
--- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "64"
--- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-2604"
--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "27"
--- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "32"
--- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
 -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
 -- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
@@ -381,8 +321,8 @@ END SYN;
 -- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
--- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
 -- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
@@ -401,15 +341,11 @@ END SYN;
 -- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
 -- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
 -- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
--- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
--- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
 -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
 -- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
 -- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
--- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
--- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
 -- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE
diff --git a/cores/c64/rtl/mist/pll_c64.ppf b/cores/c64/rtl/mist/pll_c64.ppf
new file mode 100644
index 0000000..254d6a5
--- /dev/null
+++ b/cores/c64/rtl/mist/pll_c64.ppf
@@ -0,0 +1,18 @@
+<?xml version="1.0" encoding="UTF-8" ?>
+<!DOCTYPE pinplan>
+<pinplan intended_family="Cyclone III" variation_name="pll_c64" megafunction_name="ALTPLL" specifies="all_ports">
+<global>
+<pin name="areset" direction="input" scope="external"  />
+<pin name="configupdate" direction="input" scope="external"  />
+<pin name="inclk0" direction="input" scope="external" source="clock"  />
+<pin name="scanclk" direction="input" scope="external" source="clock"  />
+<pin name="scanclkena" direction="input" scope="external"  />
+<pin name="scandata" direction="input" scope="external"  />
+<pin name="c0" direction="output" scope="external" source="clock"  />
+<pin name="c1" direction="output" scope="external" source="clock"  />
+<pin name="locked" direction="output" scope="external"  />
+<pin name="scandataout" direction="output" scope="external"  />
+<pin name="scandone" direction="output" scope="external"  />
+
+</global>
+</pinplan>
diff --git a/cores/c64/rtl/mist/pll_c64.qip b/cores/c64/rtl/mist/pll_c64.qip
new file mode 100644
index 0000000..8603569
--- /dev/null
+++ b/cores/c64/rtl/mist/pll_c64.qip
@@ -0,0 +1,4 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_c64.vhd"]
+set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll_c64.ppf"]
diff --git a/cores/c64/rtl/mist/pll_c64.vhd b/cores/c64/rtl/mist/pll_c64.vhd
new file mode 100644
index 0000000..509f190
--- /dev/null
+++ b/cores/c64/rtl/mist/pll_c64.vhd
@@ -0,0 +1,436 @@
+-- megafunction wizard: %ALTPLL%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll 
+
+-- ============================================================
+-- File Name: pll_c64.vhd
+-- Megafunction Name(s):
+-- 			altpll
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.all;
+
+ENTITY pll_c64 IS
+	PORT
+	(
+		areset		: IN STD_LOGIC  := '0';
+		configupdate		: IN STD_LOGIC  := '0';
+		inclk0		: IN STD_LOGIC  := '0';
+		scanclk		: IN STD_LOGIC  := '1';
+		scanclkena		: IN STD_LOGIC  := '0';
+		scandata		: IN STD_LOGIC  := '0';
+		c0		: OUT STD_LOGIC ;
+		c1		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC ;
+		scandataout		: OUT STD_LOGIC ;
+		scandone		: OUT STD_LOGIC 
+	);
+END pll_c64;
+
+
+ARCHITECTURE SYN OF pll_c64 IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (4 DOWNTO 0);
+	SIGNAL sub_wire1	: STD_LOGIC ;
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC ;
+	SIGNAL sub_wire6	: STD_LOGIC ;
+	SIGNAL sub_wire7	: STD_LOGIC_VECTOR (1 DOWNTO 0);
+	SIGNAL sub_wire8_bv	: BIT_VECTOR (0 DOWNTO 0);
+	SIGNAL sub_wire8	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+
+
+	COMPONENT altpll
+	GENERIC (
+		bandwidth_type		: STRING;
+		clk0_divide_by		: NATURAL;
+		clk0_duty_cycle		: NATURAL;
+		clk0_multiply_by		: NATURAL;
+		clk0_phase_shift		: STRING;
+		clk1_divide_by		: NATURAL;
+		clk1_duty_cycle		: NATURAL;
+		clk1_multiply_by		: NATURAL;
+		clk1_phase_shift		: STRING;
+		compensate_clock		: STRING;
+		inclk0_input_frequency		: NATURAL;
+		intended_device_family		: STRING;
+		lpm_hint		: STRING;
+		lpm_type		: STRING;
+		operation_mode		: STRING;
+		pll_type		: STRING;
+		port_activeclock		: STRING;
+		port_areset		: STRING;
+		port_clkbad0		: STRING;
+		port_clkbad1		: STRING;
+		port_clkloss		: STRING;
+		port_clkswitch		: STRING;
+		port_configupdate		: STRING;
+		port_fbin		: STRING;
+		port_inclk0		: STRING;
+		port_inclk1		: STRING;
+		port_locked		: STRING;
+		port_pfdena		: STRING;
+		port_phasecounterselect		: STRING;
+		port_phasedone		: STRING;
+		port_phasestep		: STRING;
+		port_phaseupdown		: STRING;
+		port_pllena		: STRING;
+		port_scanaclr		: STRING;
+		port_scanclk		: STRING;
+		port_scanclkena		: STRING;
+		port_scandata		: STRING;
+		port_scandataout		: STRING;
+		port_scandone		: STRING;
+		port_scanread		: STRING;
+		port_scanwrite		: STRING;
+		port_clk0		: STRING;
+		port_clk1		: STRING;
+		port_clk2		: STRING;
+		port_clk3		: STRING;
+		port_clk4		: STRING;
+		port_clk5		: STRING;
+		port_clkena0		: STRING;
+		port_clkena1		: STRING;
+		port_clkena2		: STRING;
+		port_clkena3		: STRING;
+		port_clkena4		: STRING;
+		port_clkena5		: STRING;
+		port_extclk0		: STRING;
+		port_extclk1		: STRING;
+		port_extclk2		: STRING;
+		port_extclk3		: STRING;
+		self_reset_on_loss_lock		: STRING;
+		width_clock		: NATURAL;
+		scan_chain_mif_file		: STRING
+	);
+	PORT (
+			areset	: IN STD_LOGIC ;
+			configupdate	: IN STD_LOGIC ;
+			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
+			scanclk	: IN STD_LOGIC ;
+			scanclkena	: IN STD_LOGIC ;
+			scandata	: IN STD_LOGIC ;
+			scandataout	: OUT STD_LOGIC ;
+			scandone	: OUT STD_LOGIC ;
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
+			locked	: OUT STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	sub_wire8_bv(0 DOWNTO 0) <= "0";
+	sub_wire8    <= To_stdlogicvector(sub_wire8_bv);
+	sub_wire2    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
+	c1    <= sub_wire1;
+	c0    <= sub_wire2;
+	scandataout    <= sub_wire3;
+	scandone    <= sub_wire4;
+	locked    <= sub_wire5;
+	sub_wire6    <= inclk0;
+	sub_wire7    <= sub_wire8(0 DOWNTO 0) & sub_wire6;
+
+	altpll_component : altpll
+	GENERIC MAP (
+		bandwidth_type => "AUTO",
+		clk0_divide_by => 6,
+		clk0_duty_cycle => 50,
+		clk0_multiply_by => 7,
+		clk0_phase_shift => "0",
+		clk1_divide_by => 3,
+		clk1_duty_cycle => 50,
+		clk1_multiply_by => 7,
+		clk1_phase_shift => "0",
+		compensate_clock => "CLK0",
+		inclk0_input_frequency => 37037,
+		intended_device_family => "Cyclone III",
+		lpm_hint => "CBX_MODULE_PREFIX=pll_c64",
+		lpm_type => "altpll",
+		operation_mode => "NORMAL",
+		pll_type => "AUTO",
+		port_activeclock => "PORT_UNUSED",
+		port_areset => "PORT_USED",
+		port_clkbad0 => "PORT_UNUSED",
+		port_clkbad1 => "PORT_UNUSED",
+		port_clkloss => "PORT_UNUSED",
+		port_clkswitch => "PORT_UNUSED",
+		port_configupdate => "PORT_USED",
+		port_fbin => "PORT_UNUSED",
+		port_inclk0 => "PORT_USED",
+		port_inclk1 => "PORT_UNUSED",
+		port_locked => "PORT_USED",
+		port_pfdena => "PORT_UNUSED",
+		port_phasecounterselect => "PORT_UNUSED",
+		port_phasedone => "PORT_UNUSED",
+		port_phasestep => "PORT_UNUSED",
+		port_phaseupdown => "PORT_UNUSED",
+		port_pllena => "PORT_UNUSED",
+		port_scanaclr => "PORT_UNUSED",
+		port_scanclk => "PORT_USED",
+		port_scanclkena => "PORT_USED",
+		port_scandata => "PORT_USED",
+		port_scandataout => "PORT_USED",
+		port_scandone => "PORT_USED",
+		port_scanread => "PORT_UNUSED",
+		port_scanwrite => "PORT_UNUSED",
+		port_clk0 => "PORT_USED",
+		port_clk1 => "PORT_USED",
+		port_clk2 => "PORT_UNUSED",
+		port_clk3 => "PORT_UNUSED",
+		port_clk4 => "PORT_UNUSED",
+		port_clk5 => "PORT_UNUSED",
+		port_clkena0 => "PORT_UNUSED",
+		port_clkena1 => "PORT_UNUSED",
+		port_clkena2 => "PORT_UNUSED",
+		port_clkena3 => "PORT_UNUSED",
+		port_clkena4 => "PORT_UNUSED",
+		port_clkena5 => "PORT_UNUSED",
+		port_extclk0 => "PORT_UNUSED",
+		port_extclk1 => "PORT_UNUSED",
+		port_extclk2 => "PORT_UNUSED",
+		port_extclk3 => "PORT_UNUSED",
+		self_reset_on_loss_lock => "ON",
+		width_clock => 5,
+		scan_chain_mif_file => "pll_c64_pal.mif"
+	)
+	PORT MAP (
+		areset => areset,
+		configupdate => configupdate,
+		inclk => sub_wire7,
+		scanclk => scanclk,
+		scanclkena => scanclkena,
+		scandata => scandata,
+		clk => sub_wire0,
+		scandataout => sub_wire3,
+		scandone => sub_wire4,
+		locked => sub_wire5
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
+-- Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
+-- Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
+-- Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
+-- Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
+-- Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
+-- Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
+-- Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
+-- Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0"
+-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
+-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "6"
+-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "3"
+-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
+-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "31.500000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "63.000000"
+-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
+-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
+-- Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
+-- Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "27.000"
+-- Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
+-- Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
+-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
+-- Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
+-- Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
+-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "7"
+-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "7"
+-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "31.52000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "63.04000000"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
+-- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "deg"
+-- Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
+-- Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
+-- Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
+-- Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
+-- Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
+-- Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_c64_pal.mif"
+-- Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1"
+-- Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1"
+-- Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
+-- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
+-- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
+-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
+-- Retrieval info: PRIVATE: SPREAD_USE STRING "0"
+-- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
+-- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
+-- Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_CLK0 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLK1 STRING "1"
+-- Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
+-- Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
+-- Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
+-- Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "6"
+-- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "7"
+-- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "3"
+-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
+-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "7"
+-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
+-- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
+-- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
+-- Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
+-- Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
+-- Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
+-- Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON"
+-- Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5"
+-- Retrieval info: CONSTANT: scan_chain_mif_file STRING "pll_c64_pal.mif"
+-- Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]"
+-- Retrieval info: USED_PORT: @inclk 0 0 2 0 INPUT_CLK_EXT VCC "@inclk[1..0]"
+-- Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
+-- Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
+-- Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
+-- Retrieval info: USED_PORT: configupdate 0 0 0 0 INPUT GND "configupdate"
+-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
+-- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
+-- Retrieval info: USED_PORT: scanclk 0 0 0 0 INPUT_CLK_EXT VCC "scanclk"
+-- Retrieval info: USED_PORT: scanclkena 0 0 0 0 INPUT GND "scanclkena"
+-- Retrieval info: USED_PORT: scandata 0 0 0 0 INPUT GND "scandata"
+-- Retrieval info: USED_PORT: scandataout 0 0 0 0 OUTPUT VCC "scandataout"
+-- Retrieval info: USED_PORT: scandone 0 0 0 0 OUTPUT VCC "scandone"
+-- Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
+-- Retrieval info: CONNECT: @configupdate 0 0 0 0 configupdate 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
+-- Retrieval info: CONNECT: @scanclk 0 0 0 0 scanclk 0 0 0 0
+-- Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0
+-- Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0
+-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
+-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0
+-- Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_c64.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_c64.ppf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_c64.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_c64.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_c64.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_c64_inst.vhd FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_c64_pal.mif TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_c64_ntsc.mif TRUE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: CBX_MODULE_PREFIX: ON
diff --git a/cores/c64/rtl/mist/pll_c64_ntsc.mif b/cores/c64/rtl/mist/pll_c64_ntsc.mif
new file mode 100644
index 0000000..b335402
--- /dev/null
+++ b/cores/c64/rtl/mist/pll_c64_ntsc.mif
@@ -0,0 +1,174 @@
+-- Copyright (C) 1991-2014 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- MIF file representing initial state of PLL Scan Chain
+--    Device Family: Cyclone III
+--    Device Part: -
+--    Device Speed Grade: 8
+--    PLL Scan Chain: Fast PLL (144 bits)
+--    File Name: /home/gyuri/git/mist-board/cores/c64/rtl/mist/pll_c64_ntsc.mif
+--    Generated: Sun Feb 10 18:12:08 2019
+
+WIDTH=1;
+DEPTH=144;
+
+ADDRESS_RADIX=UNS;
+DATA_RADIX=UNS;
+
+CONTENT BEGIN
+	0    :   0; -- Reserved Bits = 0 (1 bit(s))
+	1    :   0; -- Reserved Bits = 0 (1 bit(s))
+	2    :   0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
+	3    :   0;
+	4    :   0; -- Loop Filter Resistance = 8 (5 bit(s)) (Setting 8)
+	5    :   1;
+	6    :   0;
+	7    :   0;
+	8    :   0;
+	9    :   0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2)
+	10   :   0; -- Reserved Bits = 0 (5 bit(s))
+	11   :   0;
+	12   :   0;
+	13   :   0;
+	14   :   0;
+	15   :   0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
+	16   :   0;
+	17   :   1;
+	18   :   0; -- N counter: Bypass = 0 (1 bit(s))
+	19   :   0; -- N counter: High Count = 3 (8 bit(s))
+	20   :   0;
+	21   :   0;
+	22   :   0;
+	23   :   0;
+	24   :   0;
+	25   :   1;
+	26   :   1;
+	27   :   1; -- N counter: Odd Division = 1 (1 bit(s))
+	28   :   0; -- N counter: Low Count = 2 (8 bit(s))
+	29   :   0;
+	30   :   0;
+	31   :   0;
+	32   :   0;
+	33   :   0;
+	34   :   1;
+	35   :   0;
+	36   :   0; -- M counter: Bypass = 0 (1 bit(s))
+	37   :   0; -- M counter: High Count = 49 (8 bit(s))
+	38   :   0;
+	39   :   1;
+	40   :   1;
+	41   :   0;
+	42   :   0;
+	43   :   0;
+	44   :   1;
+	45   :   1; -- M counter: Odd Division = 1 (1 bit(s))
+	46   :   0; -- M counter: Low Count = 48 (8 bit(s))
+	47   :   0;
+	48   :   1;
+	49   :   1;
+	50   :   0;
+	51   :   0;
+	52   :   0;
+	53   :   0;
+	54   :   0; -- clk0 counter: Bypass = 0 (1 bit(s))
+	55   :   0; -- clk0 counter: High Count = 8 (8 bit(s))
+	56   :   0;
+	57   :   0;
+	58   :   0;
+	59   :   1;
+	60   :   0;
+	61   :   0;
+	62   :   0;
+	63   :   0; -- clk0 counter: Odd Division = 0 (1 bit(s))
+	64   :   0; -- clk0 counter: Low Count = 8 (8 bit(s))
+	65   :   0;
+	66   :   0;
+	67   :   0;
+	68   :   1;
+	69   :   0;
+	70   :   0;
+	71   :   0;
+	72   :   0; -- clk1 counter: Bypass = 0 (1 bit(s))
+	73   :   0; -- clk1 counter: High Count = 4 (8 bit(s))
+	74   :   0;
+	75   :   0;
+	76   :   0;
+	77   :   0;
+	78   :   1;
+	79   :   0;
+	80   :   0;
+	81   :   0; -- clk1 counter: Odd Division = 0 (1 bit(s))
+	82   :   0; -- clk1 counter: Low Count = 4 (8 bit(s))
+	83   :   0;
+	84   :   0;
+	85   :   0;
+	86   :   0;
+	87   :   1;
+	88   :   0;
+	89   :   0;
+	90   :   1; -- clk2 counter: Bypass = 1 (1 bit(s))
+	91   :   0; -- clk2 counter: High Count = 0 (8 bit(s))
+	92   :   0;
+	93   :   0;
+	94   :   0;
+	95   :   0;
+	96   :   0;
+	97   :   0;
+	98   :   0;
+	99   :   0; -- clk2 counter: Odd Division = 0 (1 bit(s))
+	100  :   0; -- clk2 counter: Low Count = 0 (8 bit(s))
+	101  :   0;
+	102  :   0;
+	103  :   0;
+	104  :   0;
+	105  :   0;
+	106  :   0;
+	107  :   0;
+	108  :   1; -- clk3 counter: Bypass = 1 (1 bit(s))
+	109  :   0; -- clk3 counter: High Count = 0 (8 bit(s))
+	110  :   0;
+	111  :   0;
+	112  :   0;
+	113  :   0;
+	114  :   0;
+	115  :   0;
+	116  :   0;
+	117  :   0; -- clk3 counter: Odd Division = 0 (1 bit(s))
+	118  :   0; -- clk3 counter: Low Count = 0 (8 bit(s))
+	119  :   0;
+	120  :   0;
+	121  :   0;
+	122  :   0;
+	123  :   0;
+	124  :   0;
+	125  :   0;
+	126  :   1; -- clk4 counter: Bypass = 1 (1 bit(s))
+	127  :   0; -- clk4 counter: High Count = 0 (8 bit(s))
+	128  :   0;
+	129  :   0;
+	130  :   0;
+	131  :   0;
+	132  :   0;
+	133  :   0;
+	134  :   0;
+	135  :   0; -- clk4 counter: Odd Division = 0 (1 bit(s))
+	136  :   0; -- clk4 counter: Low Count = 0 (8 bit(s))
+	137  :   0;
+	138  :   0;
+	139  :   0;
+	140  :   0;
+	141  :   0;
+	142  :   0;
+	143  :   0;
+END;
diff --git a/cores/c64/rtl/mist/pll_c64_pal.mif b/cores/c64/rtl/mist/pll_c64_pal.mif
new file mode 100644
index 0000000..d0bc170
--- /dev/null
+++ b/cores/c64/rtl/mist/pll_c64_pal.mif
@@ -0,0 +1,174 @@
+-- Copyright (C) 1991-2014 Altera Corporation
+-- Your use of Altera Corporation's design tools, logic functions 
+-- and other software and tools, and its AMPP partner logic 
+-- functions, and any output files from any of the foregoing 
+-- (including device programming or simulation files), and any 
+-- associated documentation or information are expressly subject 
+-- to the terms and conditions of the Altera Program License 
+-- Subscription Agreement, Altera MegaCore Function License 
+-- Agreement, or other applicable license agreement, including, 
+-- without limitation, that your use is for the sole purpose of 
+-- programming logic devices manufactured by Altera and sold by 
+-- Altera or its authorized distributors.  Please refer to the 
+-- applicable agreement for further details.
+
+-- MIF file representing initial state of PLL Scan Chain
+--    Device Family: Cyclone III
+--    Device Part: -
+--    Device Speed Grade: 8
+--    PLL Scan Chain: Fast PLL (144 bits)
+--    File Name: /home/gyuri/git/mist-board/cores/c64/rtl/mist/pll_c64_pal.mif
+--    Generated: Sun Feb 10 22:52:34 2019
+
+WIDTH=1;
+DEPTH=144;
+
+ADDRESS_RADIX=UNS;
+DATA_RADIX=UNS;
+
+CONTENT BEGIN
+	0    :   0; -- Reserved Bits = 0 (1 bit(s))
+	1    :   0; -- Reserved Bits = 0 (1 bit(s))
+	2    :   0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0)
+	3    :   0;
+	4    :   1; -- Loop Filter Resistance = 24 (5 bit(s)) (Setting 24)
+	5    :   1;
+	6    :   0;
+	7    :   0;
+	8    :   0;
+	9    :   0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2)
+	10   :   0; -- Reserved Bits = 0 (5 bit(s))
+	11   :   0;
+	12   :   0;
+	13   :   0;
+	14   :   0;
+	15   :   0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1)
+	16   :   0;
+	17   :   1;
+	18   :   1; -- N counter: Bypass = 1 (1 bit(s))
+	19   :   0; -- N counter: High Count = 0 (8 bit(s))
+	20   :   0;
+	21   :   0;
+	22   :   0;
+	23   :   0;
+	24   :   0;
+	25   :   0;
+	26   :   0;
+	27   :   0; -- N counter: Odd Division = 0 (1 bit(s))
+	28   :   0; -- N counter: Low Count = 0 (8 bit(s))
+	29   :   0;
+	30   :   0;
+	31   :   0;
+	32   :   0;
+	33   :   0;
+	34   :   0;
+	35   :   0;
+	36   :   0; -- M counter: Bypass = 0 (1 bit(s))
+	37   :   0; -- M counter: High Count = 11 (8 bit(s))
+	38   :   0;
+	39   :   0;
+	40   :   0;
+	41   :   1;
+	42   :   0;
+	43   :   1;
+	44   :   1;
+	45   :   1; -- M counter: Odd Division = 1 (1 bit(s))
+	46   :   0; -- M counter: Low Count = 10 (8 bit(s))
+	47   :   0;
+	48   :   0;
+	49   :   0;
+	50   :   1;
+	51   :   0;
+	52   :   1;
+	53   :   0;
+	54   :   0; -- clk0 counter: Bypass = 0 (1 bit(s))
+	55   :   0; -- clk0 counter: High Count = 9 (8 bit(s))
+	56   :   0;
+	57   :   0;
+	58   :   0;
+	59   :   1;
+	60   :   0;
+	61   :   0;
+	62   :   1;
+	63   :   0; -- clk0 counter: Odd Division = 0 (1 bit(s))
+	64   :   0; -- clk0 counter: Low Count = 9 (8 bit(s))
+	65   :   0;
+	66   :   0;
+	67   :   0;
+	68   :   1;
+	69   :   0;
+	70   :   0;
+	71   :   1;
+	72   :   0; -- clk1 counter: Bypass = 0 (1 bit(s))
+	73   :   0; -- clk1 counter: High Count = 5 (8 bit(s))
+	74   :   0;
+	75   :   0;
+	76   :   0;
+	77   :   0;
+	78   :   1;
+	79   :   0;
+	80   :   1;
+	81   :   1; -- clk1 counter: Odd Division = 1 (1 bit(s))
+	82   :   0; -- clk1 counter: Low Count = 4 (8 bit(s))
+	83   :   0;
+	84   :   0;
+	85   :   0;
+	86   :   0;
+	87   :   1;
+	88   :   0;
+	89   :   0;
+	90   :   1; -- clk2 counter: Bypass = 1 (1 bit(s))
+	91   :   0; -- clk2 counter: High Count = 0 (8 bit(s))
+	92   :   0;
+	93   :   0;
+	94   :   0;
+	95   :   0;
+	96   :   0;
+	97   :   0;
+	98   :   0;
+	99   :   0; -- clk2 counter: Odd Division = 0 (1 bit(s))
+	100  :   0; -- clk2 counter: Low Count = 0 (8 bit(s))
+	101  :   0;
+	102  :   0;
+	103  :   0;
+	104  :   0;
+	105  :   0;
+	106  :   0;
+	107  :   0;
+	108  :   1; -- clk3 counter: Bypass = 1 (1 bit(s))
+	109  :   0; -- clk3 counter: High Count = 0 (8 bit(s))
+	110  :   0;
+	111  :   0;
+	112  :   0;
+	113  :   0;
+	114  :   0;
+	115  :   0;
+	116  :   0;
+	117  :   0; -- clk3 counter: Odd Division = 0 (1 bit(s))
+	118  :   0; -- clk3 counter: Low Count = 0 (8 bit(s))
+	119  :   0;
+	120  :   0;
+	121  :   0;
+	122  :   0;
+	123  :   0;
+	124  :   0;
+	125  :   0;
+	126  :   1; -- clk4 counter: Bypass = 1 (1 bit(s))
+	127  :   0; -- clk4 counter: High Count = 0 (8 bit(s))
+	128  :   0;
+	129  :   0;
+	130  :   0;
+	131  :   0;
+	132  :   0;
+	133  :   0;
+	134  :   0;
+	135  :   0; -- clk4 counter: Odd Division = 0 (1 bit(s))
+	136  :   0; -- clk4 counter: Low Count = 0 (8 bit(s))
+	137  :   0;
+	138  :   0;
+	139  :   0;
+	140  :   0;
+	141  :   0;
+	142  :   0;
+	143  :   0;
+END;
diff --git a/cores/c64/rtl/mist/pll_c64_reconfig.qip b/cores/c64/rtl/mist/pll_c64_reconfig.qip
new file mode 100644
index 0000000..33a580b
--- /dev/null
+++ b/cores/c64/rtl/mist/pll_c64_reconfig.qip
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ALTPLL_RECONFIG"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "pll_c64_reconfig.vhd"]
diff --git a/cores/c64/rtl/mist/pll_c64_reconfig.vhd b/cores/c64/rtl/mist/pll_c64_reconfig.vhd
new file mode 100644
index 0000000..c92d7b6
--- /dev/null
+++ b/cores/c64/rtl/mist/pll_c64_reconfig.vhd
@@ -0,0 +1,2472 @@
+-- megafunction wizard: %ALTPLL_RECONFIG%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altpll_reconfig 
+
+-- ============================================================
+-- File Name: pll_c64_reconfig.vhd
+-- Megafunction Name(s):
+-- 			altpll_reconfig
+--
+-- Simulation Library Files(s):
+-- 			altera_mf;cycloneiii;lpm
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+--altpll_reconfig CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone III" busy clock counter_param counter_type data_in data_out pll_areset pll_areset_in pll_configupdate pll_scanclk pll_scanclkena pll_scandata pll_scandataout pll_scandone read_param reconfig reset reset_rom_address rom_address_out rom_data_in write_from_rom write_param write_rom_ena
+--VERSION_BEGIN 13.1 cbx_altpll_reconfig 2014:03:12:19:24:28:SJ cbx_altsyncram 2014:03:12:19:24:28:SJ cbx_cycloneii 2014:03:12:19:24:28:SJ cbx_lpm_add_sub 2014:03:12:19:24:28:SJ cbx_lpm_compare 2014:03:12:19:24:28:SJ cbx_lpm_counter 2014:03:12:19:24:28:SJ cbx_lpm_decode 2014:03:12:19:24:28:SJ cbx_lpm_mux 2014:03:12:19:24:28:SJ cbx_mgl 2014:03:12:19:35:38:SJ cbx_stratix 2014:03:12:19:24:28:SJ cbx_stratixii 2014:03:12:19:24:28:SJ cbx_stratixiii 2014:03:12:19:24:28:SJ cbx_stratixv 2014:03:12:19:24:28:SJ cbx_util_mgl 2014:03:12:19:24:28:SJ  VERSION_END
+
+ LIBRARY altera_mf;
+ USE altera_mf.all;
+
+ LIBRARY cycloneiii;
+ USE cycloneiii.all;
+
+ LIBRARY lpm;
+ USE lpm.all;
+
+--synthesis_resources = altsyncram 1 lpm_add_sub 2 lpm_compare 1 lpm_counter 8 lpm_decode 1 lut 3 reg 102 
+ LIBRARY ieee;
+ USE ieee.std_logic_1164.all;
+
+ ENTITY  pll_c64_reconfig_pllrcfg_fj11 IS 
+	 PORT 
+	 ( 
+		 busy	:	OUT  STD_LOGIC;
+		 clock	:	IN  STD_LOGIC;
+		 counter_param	:	IN  STD_LOGIC_VECTOR (2 DOWNTO 0) := (OTHERS => '0');
+		 counter_type	:	IN  STD_LOGIC_VECTOR (3 DOWNTO 0) := (OTHERS => '0');
+		 data_in	:	IN  STD_LOGIC_VECTOR (8 DOWNTO 0) := (OTHERS => '0');
+		 data_out	:	OUT  STD_LOGIC_VECTOR (8 DOWNTO 0);
+		 pll_areset	:	OUT  STD_LOGIC;
+		 pll_areset_in	:	IN  STD_LOGIC := '0';
+		 pll_configupdate	:	OUT  STD_LOGIC;
+		 pll_scanclk	:	OUT  STD_LOGIC;
+		 pll_scanclkena	:	OUT  STD_LOGIC;
+		 pll_scandata	:	OUT  STD_LOGIC;
+		 pll_scandataout	:	IN  STD_LOGIC := '0';
+		 pll_scandone	:	IN  STD_LOGIC := '0';
+		 read_param	:	IN  STD_LOGIC := '0';
+		 reconfig	:	IN  STD_LOGIC := '0';
+		 reset	:	IN  STD_LOGIC;
+		 reset_rom_address	:	IN  STD_LOGIC := '0';
+		 rom_address_out	:	OUT  STD_LOGIC_VECTOR (7 DOWNTO 0);
+		 rom_data_in	:	IN  STD_LOGIC := '0';
+		 write_from_rom	:	IN  STD_LOGIC := '0';
+		 write_param	:	IN  STD_LOGIC := '0';
+		 write_rom_ena	:	OUT  STD_LOGIC
+	 ); 
+ END pll_c64_reconfig_pllrcfg_fj11;
+
+ ARCHITECTURE RTL OF pll_c64_reconfig_pllrcfg_fj11 IS
+
+	 ATTRIBUTE synthesis_clearbox : natural;
+	 ATTRIBUTE synthesis_clearbox OF RTL : ARCHITECTURE IS 2;
+	 ATTRIBUTE ALTERA_ATTRIBUTE : string;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF RTL : ARCHITECTURE IS "ADV_NETLIST_OPT_ALLOWED=""NEVER_ALLOW"";suppress_da_rule_internal=C106;{-to le_comb10} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=2;{-to le_comb8} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=0;{-to le_comb9} PLL_SCAN_RECONFIG_COUNTER_REMAP_LCELL=1";
+
+	 SIGNAL  wire_altsyncram4_data_a	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_altsyncram4_q_a	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_le_comb10_combout	:	STD_LOGIC;
+	 SIGNAL  wire_le_comb8_combout	:	STD_LOGIC;
+	 SIGNAL  wire_le_comb9_combout	:	STD_LOGIC;
+	 SIGNAL	 addr_from_rom	:	STD_LOGIC_VECTOR(7 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 addr_from_rom2	:	STD_LOGIC_VECTOR(7 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 areset_init_state_1	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 areset_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 C0_data_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 C0_ena_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 C1_data_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 C1_ena_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL  wire_C1_ena_state_w_lg_q1786w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 C2_data_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 C2_ena_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL  wire_C2_ena_state_w_lg_q1787w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 C3_data_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 C3_ena_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 C4_data_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 C4_ena_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 configupdate2_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 configupdate3_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL  wire_configupdate3_state_w_lg_q1879w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 configupdate_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 counter_param_latch_reg	:	STD_LOGIC_VECTOR(2 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 counter_type_latch_reg	:	STD_LOGIC_VECTOR(3 DOWNTO 0)
+	 -- synopsys translate_off
+	  := (OTHERS => '0')
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 idle_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF idle_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_idle_state_w_lg_w_lg_w_lg_w_lg_q1743w1744w1745w1746w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_idle_state_w_lg_w_lg_w_lg_q1743w1744w1745w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_idle_state_w_lg_w_lg_q1743w1744w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_idle_state_w_lg_q1743w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_idle_state_w_lg_q1672w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_idle_state_w1747w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_idle_state_w_lg_w1747w1748w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_idle_state_w_lg_w_lg_w1747w1748w1749w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_idle_state_w_lg_w_lg_w_lg_w1747w1748w1749w1750w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 nominal_data0	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 nominal_data1	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 nominal_data2	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 nominal_data3	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 nominal_data4	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 nominal_data5	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 nominal_data6	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 nominal_data7	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 nominal_data8	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 nominal_data9	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 nominal_data10	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 nominal_data11	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 nominal_data12	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 nominal_data13	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 nominal_data14	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 nominal_data15	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 nominal_data16	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 nominal_data17	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 read_data_nominal_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF read_data_nominal_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_read_data_nominal_state_w_lg_q1772w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_read_data_nominal_state_w_lg_q1686w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 read_data_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF read_data_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_read_data_state_w_lg_q1765w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_read_data_state_w_lg_q1678w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 read_first_nominal_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF read_first_nominal_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_read_first_nominal_state_w_lg_q1773w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_read_first_nominal_state_w_lg_q1684w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 read_first_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF read_first_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_read_first_state_w_lg_q1766w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_read_first_state_w_lg_q1676w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_read_first_state_w_lg_w_lg_w_lg_q1894w1895w1896w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_read_first_state_w_lg_w_lg_q1894w1895w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_read_first_state_w_lg_q1894w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 read_init_nominal_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF read_init_nominal_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_read_init_nominal_state_w_lg_q1682w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 read_init_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF read_init_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_read_init_state_w_lg_q1674w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_read_init_state_w_lg_q1891w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 read_last_nominal_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF read_last_nominal_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_read_last_nominal_state_w_lg_q1917w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_read_last_nominal_state_w_lg_q1688w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 read_last_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF read_last_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_read_last_state_w_lg_q1680w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 reconfig_counter_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF reconfig_counter_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_reconfig_counter_state_w_lg_q1700w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 reconfig_init_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF reconfig_init_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_reconfig_init_state_w_lg_q1698w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 reconfig_post_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF reconfig_post_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_reconfig_post_state_w_lg_q1849w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_reconfig_post_state_w_lg_q1706w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 reconfig_seq_data_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF reconfig_seq_data_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_reconfig_seq_data_state_w_lg_q1704w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 reconfig_seq_ena_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF reconfig_seq_ena_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_reconfig_seq_ena_state_w_lg_q1903w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_reconfig_seq_ena_state_w_lg_q1904w	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  wire_reconfig_seq_ena_state_w_lg_q1702w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 reconfig_wait_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF reconfig_wait_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_reconfig_wait_state_w_lg_q1853w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_reconfig_wait_state_w_lg_q1708w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 reset_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '1'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF reset_state : SIGNAL IS "POWER_UP_LEVEL=HIGH";
+
+	 SIGNAL  wire_reset_state_w_lg_q1671w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 rom_data_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF rom_data_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_rom_data_state_w_lg_q1868w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_data_state_w_lg_q1889w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_data_state_w_lg_w_lg_q1897w1933w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_data_state_w_lg_q1716w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_data_state_w_lg_w_lg_q1897w1898w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_data_state_w_lg_w_lg_q1929w1930w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_data_state_w_lg_q1897w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_data_state_w_lg_q1929w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 rom_first_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF rom_first_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_rom_first_state_w_lg_w_lg_w_lg_w_lg_q1943w1944w1945w1947w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_first_state_w_lg_q1712w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_first_state_w_lg_w_lg_w_lg_q1943w1944w1945w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_first_state_w_lg_w_lg_q1943w1944w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_first_state_w_lg_w_lg_q1885w1886w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_first_state_w_lg_q1943w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_first_state_w_lg_q1885w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 rom_init_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF rom_init_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_rom_init_state_w_lg_q1710w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 rom_last_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF rom_last_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_rom_last_state_w_lg_q1753w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_last_state_w_lg_q1720w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 rom_second_last_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF rom_second_last_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_rom_second_last_state_w_lg_q1754w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_rom_second_last_state_w_lg_q1718w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 rom_second_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF rom_second_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_rom_second_state_w_lg_q1714w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 shift_reg0	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL  wire_shift_reg_w_lg_q217w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_shift_reg_w_lg_w_lg_q217w218w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 shift_reg1	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL  wire_shift_reg_w_lg_q223w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_shift_reg_w_lg_w_lg_q223w224w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 shift_reg2	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL  wire_shift_reg_w_lg_q228w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_shift_reg_w_lg_w_lg_q228w229w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 shift_reg3	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL  wire_shift_reg_w_lg_q233w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_shift_reg_w_lg_w_lg_q233w234w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 shift_reg4	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL  wire_shift_reg_w_lg_q238w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_shift_reg_w_lg_w_lg_q238w239w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 shift_reg5	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL  wire_shift_reg_w_lg_q243w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_shift_reg_w_lg_w_lg_q243w244w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 shift_reg6	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL  wire_shift_reg_w_lg_q248w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_shift_reg_w_lg_w_lg_q248w249w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 shift_reg7	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL  wire_shift_reg_w_lg_q253w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_shift_reg_w_lg_w_lg_q253w254w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 shift_reg8	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL  wire_shift_reg_w_lg_q258w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_shift_reg_w_lg_w_lg_q258w259w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 shift_reg9	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 shift_reg10	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 shift_reg11	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 shift_reg12	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 shift_reg13	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 shift_reg14	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 shift_reg15	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 shift_reg16	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 shift_reg17	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL  wire_shift_reg_w_lg_q262w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_shift_reg_w_lg_q264w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_shift_reg_w_lg_q267w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_shift_reg_w_lg_q270w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_shift_reg_w_lg_q273w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_shift_reg_w_lg_q276w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_shift_reg_w_lg_q279w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_shift_reg_w_lg_q282w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 wire_shift_reg_ena	:	STD_LOGIC_VECTOR(17 DOWNTO 0);
+	 SIGNAL	 tmp_nominal_data_out_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 tmp_seq_ena_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 SIGNAL	 write_data_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF write_data_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_write_data_state_w_lg_q1738w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_write_data_state_w_lg_q1692w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 write_init_nominal_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF write_init_nominal_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_write_init_nominal_state_w_lg_q1694w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 write_init_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF write_init_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_write_init_state_w_lg_q1690w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_write_init_state_w_lg_q1900w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL	 write_nominal_state	:	STD_LOGIC
+	 -- synopsys translate_off
+	  := '0'
+	 -- synopsys translate_on
+	 ;
+	 ATTRIBUTE ALTERA_ATTRIBUTE OF write_nominal_state : SIGNAL IS "POWER_UP_LEVEL=LOW";
+
+	 SIGNAL  wire_write_nominal_state_w_lg_q1737w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_write_nominal_state_w_lg_q1696w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_add_sub5_w_lg_w_result_range214w215w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_add_sub5_w_lg_w_result_range221w222w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_add_sub5_w_lg_w_result_range226w227w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_add_sub5_w_lg_w_result_range231w232w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_add_sub5_w_lg_w_result_range236w237w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_add_sub5_w_lg_w_result_range241w242w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_add_sub5_w_lg_w_result_range246w247w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_add_sub5_w_lg_w_result_range251w252w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_add_sub5_w_lg_w_result_range256w257w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_gnd	:	STD_LOGIC;
+	 SIGNAL  wire_add_sub5_dataa	:	STD_LOGIC_VECTOR (8 DOWNTO 0);
+	 SIGNAL  wire_add_sub5_datab	:	STD_LOGIC_VECTOR (8 DOWNTO 0);
+	 SIGNAL  wire_add_sub5_result	:	STD_LOGIC_VECTOR (8 DOWNTO 0);
+	 SIGNAL  wire_add_sub5_w_result_range214w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_add_sub5_w_result_range221w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_add_sub5_w_result_range226w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_add_sub5_w_result_range231w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_add_sub5_w_result_range236w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_add_sub5_w_result_range241w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_add_sub5_w_result_range246w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_add_sub5_w_result_range251w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_add_sub5_w_result_range256w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_add_sub6_dataa	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_add_sub6_result	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_cmpr7_aeb	:	STD_LOGIC;
+	 SIGNAL  wire_cmpr7_dataa	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_cmpr7_datab	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_cntr1_q	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_cntr12_q	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_cntr13_q	:	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  wire_cntr14_q	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_cntr15_q	:	STD_LOGIC_VECTOR (4 DOWNTO 0);
+	 SIGNAL  wire_cntr16_q	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_cntr2_q	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_cntr3_q	:	STD_LOGIC_VECTOR (4 DOWNTO 0);
+	 SIGNAL  wire_decode11_eq	:	STD_LOGIC_VECTOR (4 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w_lg_read_addr_counter_out1934w1935w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w_lg_rom_width_counter_enable1931w1932w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_w_lg_addr_counter_out1938w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_w_lg_addr_decoder_out1901w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_w_lg_c0_wire1828w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_w_lg_c1_wire1826w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_w_lg_c2_wire1824w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_w_lg_c3_wire1822w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_w_lg_c4_wire1820w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_w_lg_read_addr_counter_out1887w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_w_lg_read_addr_counter_out1934w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_w_lg_read_addr_decoder_out1893w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_w_lg_reconfig_addr_counter_out1936w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_w_lg_rom_data_in1946w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_rom_width_counter_enable1931w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_rotate_addr_counter_out1937w	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_w_lg_shift_reg_load_enable187w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_shift_reg_load_enable179w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_shift_reg_load_enable171w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_shift_reg_load_enable163w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_shift_reg_load_enable155w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_shift_reg_load_enable147w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_shift_reg_load_enable139w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_shift_reg_load_enable131w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_shift_reg_load_enable123w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_shift_reg_serial_out1948w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w_counter_param_latch_range294w379w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w_counter_type_latch_range284w710w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_dummy_scandataout1925w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_pll_scandone1927w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_read_addr_counter_done1867w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_read_nominal_out216w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_read_param1742w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_reconfig1740w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_reconfig_done1852w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_reconfig_post_done1848w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_reconfig_width_counter_done1845w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_reset1w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_reset_rom_address1752w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_rom_width_counter_done1888w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_rotate_width_counter_done1796w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_width_counter_done1764w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_write_from_rom1739w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_write_param1741w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w_counter_param_latch_range296w297w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w_counter_type_latch_range286w530w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w_lg_w_lg_w1329w1392w1452w1516w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w_lg_w1329w1392w1452w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w_lg_w_lg_w1361w1422w1483w1550w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w1329w1392w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w_lg_w1361w1422w1483w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w1329w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w1361w1422w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w_lg_w_lg_w_lg_w980w1055w1126w1195w1261w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w1361w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w_lg_w_lg_w980w1055w1126w1195w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w_lg_w_lg_w_lg_w1016w1091w1160w1228w1294w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w_lg_w980w1055w1126w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w_lg_w_lg_w1016w1091w1160w1228w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w980w1055w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w_lg_w1016w1091w1160w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w980w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w1016w1091w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w_lg_w_lg_w_lg_w_lg_w423w570w637w749w817w920w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w1016w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w63w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w_lg_w_lg_w_lg_w423w570w637w749w817w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w_lg_w_lg_w_lg_w571w672w784w850w951w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w_lg_w_lg_shift_reg_load_enable60w61w62w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w_lg_w_lg_w423w570w637w749w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w_lg_w_lg_w571w672w784w850w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w_lg_shift_reg_load_enable60w61w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w_lg_w423w570w637w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w_lg_w571w672w784w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_dummy_scandataout1926w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_shift_reg_load_enable60w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w301w378w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w381w495w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w423w570w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w571w672w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_lg_w675w885w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  addr_counter_enable :	STD_LOGIC;
+	 SIGNAL  addr_counter_out :	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  addr_counter_sload :	STD_LOGIC;
+	 SIGNAL  addr_counter_sload_value :	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  addr_decoder_out :	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  c0_wire :	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  c1_wire :	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  c2_wire :	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  c3_wire :	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  c4_wire :	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  const_scan_chain_size :	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  counter_param_latch :	STD_LOGIC_VECTOR (2 DOWNTO 0);
+	 SIGNAL  counter_type_latch :	STD_LOGIC_VECTOR (3 DOWNTO 0);
+	 SIGNAL  cuda_combout_wire :	STD_LOGIC_VECTOR (2 DOWNTO 0);
+	 SIGNAL  dummy_scandataout :	STD_LOGIC;
+	 SIGNAL  encode_out :	STD_LOGIC_VECTOR (2 DOWNTO 0);
+	 SIGNAL  input_latch_enable :	STD_LOGIC;
+	 SIGNAL  power_up :	STD_LOGIC;
+	 SIGNAL  read_addr_counter_done :	STD_LOGIC;
+	 SIGNAL  read_addr_counter_enable :	STD_LOGIC;
+	 SIGNAL  read_addr_counter_out :	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  read_addr_counter_sload :	STD_LOGIC;
+	 SIGNAL  read_addr_counter_sload_value :	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  read_addr_decoder_out :	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  read_nominal_out :	STD_LOGIC;
+	 SIGNAL  reconfig_addr_counter_enable :	STD_LOGIC;
+	 SIGNAL  reconfig_addr_counter_out :	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  reconfig_addr_counter_sload :	STD_LOGIC;
+	 SIGNAL  reconfig_addr_counter_sload_value :	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  reconfig_done :	STD_LOGIC;
+	 SIGNAL  reconfig_post_done :	STD_LOGIC;
+	 SIGNAL  reconfig_width_counter_done :	STD_LOGIC;
+	 SIGNAL  reconfig_width_counter_enable :	STD_LOGIC;
+	 SIGNAL  reconfig_width_counter_sload :	STD_LOGIC;
+	 SIGNAL  reconfig_width_counter_sload_value :	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  rom_width_counter_done :	STD_LOGIC;
+	 SIGNAL  rom_width_counter_enable :	STD_LOGIC;
+	 SIGNAL  rom_width_counter_sload :	STD_LOGIC;
+	 SIGNAL  rom_width_counter_sload_value :	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  rotate_addr_counter_enable :	STD_LOGIC;
+	 SIGNAL  rotate_addr_counter_out :	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  rotate_addr_counter_sload :	STD_LOGIC;
+	 SIGNAL  rotate_addr_counter_sload_value :	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  rotate_decoder_wires :	STD_LOGIC_VECTOR (4 DOWNTO 0);
+	 SIGNAL  rotate_width_counter_done :	STD_LOGIC;
+	 SIGNAL  rotate_width_counter_enable :	STD_LOGIC;
+	 SIGNAL  rotate_width_counter_sload :	STD_LOGIC;
+	 SIGNAL  rotate_width_counter_sload_value :	STD_LOGIC_VECTOR (4 DOWNTO 0);
+	 SIGNAL  scan_cache_address :	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  scan_cache_in :	STD_LOGIC;
+	 SIGNAL  scan_cache_out :	STD_LOGIC;
+	 SIGNAL  scan_cache_write_enable :	STD_LOGIC;
+	 SIGNAL  sel_param_bypass_LF_unused :	STD_LOGIC;
+	 SIGNAL  sel_param_c :	STD_LOGIC;
+	 SIGNAL  sel_param_high_i_postscale :	STD_LOGIC;
+	 SIGNAL  sel_param_low_r :	STD_LOGIC;
+	 SIGNAL  sel_param_nominal_count :	STD_LOGIC;
+	 SIGNAL  sel_param_odd_CP_unused :	STD_LOGIC;
+	 SIGNAL  sel_type_c0 :	STD_LOGIC;
+	 SIGNAL  sel_type_c1 :	STD_LOGIC;
+	 SIGNAL  sel_type_c2 :	STD_LOGIC;
+	 SIGNAL  sel_type_c3 :	STD_LOGIC;
+	 SIGNAL  sel_type_c4 :	STD_LOGIC;
+	 SIGNAL  sel_type_cplf :	STD_LOGIC;
+	 SIGNAL  sel_type_m :	STD_LOGIC;
+	 SIGNAL  sel_type_n :	STD_LOGIC;
+	 SIGNAL  sel_type_vco :	STD_LOGIC;
+	 SIGNAL  seq_addr_wire :	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  seq_sload_value :	STD_LOGIC_VECTOR (5 DOWNTO 0);
+	 SIGNAL  shift_reg_clear :	STD_LOGIC;
+	 SIGNAL  shift_reg_load_enable :	STD_LOGIC;
+	 SIGNAL  shift_reg_load_nominal_enable :	STD_LOGIC;
+	 SIGNAL  shift_reg_serial_in :	STD_LOGIC;
+	 SIGNAL  shift_reg_serial_out :	STD_LOGIC;
+	 SIGNAL  shift_reg_shift_enable :	STD_LOGIC;
+	 SIGNAL  shift_reg_shift_nominal_enable :	STD_LOGIC;
+	 SIGNAL  shift_reg_width_select :	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  w1019w :	STD_LOGIC;
+	 SIGNAL  w1056w :	STD_LOGIC;
+	 SIGNAL  w1092w :	STD_LOGIC;
+	 SIGNAL  w1127w :	STD_LOGIC;
+	 SIGNAL  w1163w :	STD_LOGIC;
+	 SIGNAL  w1196w :	STD_LOGIC;
+	 SIGNAL  w1229w :	STD_LOGIC;
+	 SIGNAL  w1262w :	STD_LOGIC;
+	 SIGNAL  w1297w :	STD_LOGIC;
+	 SIGNAL  w1330w :	STD_LOGIC;
+	 SIGNAL  w1362w :	STD_LOGIC;
+	 SIGNAL  w1393w :	STD_LOGIC;
+	 SIGNAL  w1424w :	STD_LOGIC;
+	 SIGNAL  w1453w :	STD_LOGIC;
+	 SIGNAL  w1484w :	STD_LOGIC;
+	 SIGNAL  w1517w :	STD_LOGIC;
+	 SIGNAL  w1565w :	STD_LOGIC;
+	 SIGNAL  w1592w :	STD_LOGIC;
+	 SIGNAL  w301w :	STD_LOGIC;
+	 SIGNAL  w341w :	STD_LOGIC;
+	 SIGNAL  w381w :	STD_LOGIC;
+	 SIGNAL  w423w :	STD_LOGIC;
+	 SIGNAL  w460w :	STD_LOGIC;
+	 SIGNAL  w496w :	STD_LOGIC;
+	 SIGNAL  w534w :	STD_LOGIC;
+	 SIGNAL  w571w :	STD_LOGIC;
+	 SIGNAL  w605w :	STD_LOGIC;
+	 SIGNAL  w638w :	STD_LOGIC;
+	 SIGNAL  w64w :	STD_LOGIC;
+	 SIGNAL  w675w :	STD_LOGIC;
+	 SIGNAL  w713w :	STD_LOGIC;
+	 SIGNAL  w750w :	STD_LOGIC;
+	 SIGNAL  w785w :	STD_LOGIC;
+	 SIGNAL  w818w :	STD_LOGIC;
+	 SIGNAL  w851w :	STD_LOGIC;
+	 SIGNAL  w888w :	STD_LOGIC;
+	 SIGNAL  w921w :	STD_LOGIC;
+	 SIGNAL  w952w :	STD_LOGIC;
+	 SIGNAL  w981w :	STD_LOGIC;
+	 SIGNAL  width_counter_done :	STD_LOGIC;
+	 SIGNAL  width_counter_enable :	STD_LOGIC;
+	 SIGNAL  width_counter_sload :	STD_LOGIC;
+	 SIGNAL  width_counter_sload_value :	STD_LOGIC_VECTOR (4 DOWNTO 0);
+	 SIGNAL  width_decoder_out :	STD_LOGIC_VECTOR (4 DOWNTO 0);
+	 SIGNAL  width_decoder_select :	STD_LOGIC_VECTOR (7 DOWNTO 0);
+	 SIGNAL  wire_w_counter_param_latch_range294w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_counter_param_latch_range296w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_counter_type_latch_range284w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_counter_type_latch_range286w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_data_in_range186w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_data_in_range178w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_data_in_range170w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_data_in_range162w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_data_in_range154w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_data_in_range146w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_data_in_range138w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_data_in_range130w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_data_in_range122w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_rotate_decoder_wires_range1827w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_rotate_decoder_wires_range1825w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_rotate_decoder_wires_range1823w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_rotate_decoder_wires_range1821w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_rotate_decoder_wires_range1819w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_shift_reg_width_select_range261w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_shift_reg_width_select_range263w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_shift_reg_width_select_range266w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_shift_reg_width_select_range269w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_shift_reg_width_select_range272w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_shift_reg_width_select_range275w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_shift_reg_width_select_range278w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 SIGNAL  wire_w_shift_reg_width_select_range281w	:	STD_LOGIC_VECTOR (0 DOWNTO 0);
+	 COMPONENT  altsyncram
+	 GENERIC 
+	 (
+		ADDRESS_ACLR_A	:	STRING := "UNUSED";
+		ADDRESS_ACLR_B	:	STRING := "NONE";
+		ADDRESS_REG_B	:	STRING := "CLOCK1";
+		BYTE_SIZE	:	NATURAL := 8;
+		BYTEENA_ACLR_A	:	STRING := "UNUSED";
+		BYTEENA_ACLR_B	:	STRING := "NONE";
+		BYTEENA_REG_B	:	STRING := "CLOCK1";
+		CLOCK_ENABLE_CORE_A	:	STRING := "USE_INPUT_CLKEN";
+		CLOCK_ENABLE_CORE_B	:	STRING := "USE_INPUT_CLKEN";
+		CLOCK_ENABLE_INPUT_A	:	STRING := "NORMAL";
+		CLOCK_ENABLE_INPUT_B	:	STRING := "NORMAL";
+		CLOCK_ENABLE_OUTPUT_A	:	STRING := "NORMAL";
+		CLOCK_ENABLE_OUTPUT_B	:	STRING := "NORMAL";
+		ECC_PIPELINE_STAGE_ENABLED	:	STRING := "FALSE";
+		ENABLE_ECC	:	STRING := "FALSE";
+		IMPLEMENT_IN_LES	:	STRING := "OFF";
+		INDATA_ACLR_A	:	STRING := "UNUSED";
+		INDATA_ACLR_B	:	STRING := "NONE";
+		INDATA_REG_B	:	STRING := "CLOCK1";
+		INIT_FILE	:	STRING := "UNUSED";
+		INIT_FILE_LAYOUT	:	STRING := "PORT_A";
+		MAXIMUM_DEPTH	:	NATURAL := 0;
+		NUMWORDS_A	:	NATURAL := 0;
+		NUMWORDS_B	:	NATURAL := 0;
+		OPERATION_MODE	:	STRING := "BIDIR_DUAL_PORT";
+		OUTDATA_ACLR_A	:	STRING := "NONE";
+		OUTDATA_ACLR_B	:	STRING := "NONE";
+		OUTDATA_REG_A	:	STRING := "UNREGISTERED";
+		OUTDATA_REG_B	:	STRING := "UNREGISTERED";
+		POWER_UP_UNINITIALIZED	:	STRING := "FALSE";
+		RAM_BLOCK_TYPE	:	STRING := "AUTO";
+		RDCONTROL_ACLR_B	:	STRING := "NONE";
+		RDCONTROL_REG_B	:	STRING := "CLOCK1";
+		READ_DURING_WRITE_MODE_MIXED_PORTS	:	STRING := "DONT_CARE";
+		read_during_write_mode_port_a	:	STRING := "NEW_DATA_NO_NBE_READ";
+		read_during_write_mode_port_b	:	STRING := "NEW_DATA_NO_NBE_READ";
+		WIDTH_A	:	NATURAL;
+		WIDTH_B	:	NATURAL := 1;
+		WIDTH_BYTEENA_A	:	NATURAL := 1;
+		WIDTH_BYTEENA_B	:	NATURAL := 1;
+		WIDTH_ECCSTATUS	:	NATURAL := 3;
+		WIDTHAD_A	:	NATURAL;
+		WIDTHAD_B	:	NATURAL := 1;
+		WRCONTROL_ACLR_A	:	STRING := "UNUSED";
+		WRCONTROL_ACLR_B	:	STRING := "NONE";
+		WRCONTROL_WRADDRESS_REG_B	:	STRING := "CLOCK1";
+		INTENDED_DEVICE_FAMILY	:	STRING := "Cyclone III";
+		lpm_hint	:	STRING := "UNUSED";
+		lpm_type	:	STRING := "altsyncram"
+	 );
+	 PORT
+	 ( 
+		aclr0	:	IN STD_LOGIC := '0';
+		aclr1	:	IN STD_LOGIC := '0';
+		address_a	:	IN STD_LOGIC_VECTOR(WIDTHAD_A-1 DOWNTO 0);
+		address_b	:	IN STD_LOGIC_VECTOR(WIDTHAD_B-1 DOWNTO 0) := (OTHERS => '1');
+		addressstall_a	:	IN STD_LOGIC := '0';
+		addressstall_b	:	IN STD_LOGIC := '0';
+		byteena_a	:	IN STD_LOGIC_VECTOR(WIDTH_BYTEENA_A-1 DOWNTO 0) := (OTHERS => '1');
+		byteena_b	:	IN STD_LOGIC_VECTOR(WIDTH_BYTEENA_B-1 DOWNTO 0) := (OTHERS => '1');
+		clock0	:	IN STD_LOGIC := '1';
+		clock1	:	IN STD_LOGIC := '1';
+		clocken0	:	IN STD_LOGIC := '1';
+		clocken1	:	IN STD_LOGIC := '1';
+		clocken2	:	IN STD_LOGIC := '1';
+		clocken3	:	IN STD_LOGIC := '1';
+		data_a	:	IN STD_LOGIC_VECTOR(WIDTH_A-1 DOWNTO 0) := (OTHERS => '1');
+		data_b	:	IN STD_LOGIC_VECTOR(WIDTH_B-1 DOWNTO 0) := (OTHERS => '1');
+		eccstatus	:	OUT STD_LOGIC_VECTOR(WIDTH_ECCSTATUS-1 DOWNTO 0);
+		q_a	:	OUT STD_LOGIC_VECTOR(WIDTH_A-1 DOWNTO 0);
+		q_b	:	OUT STD_LOGIC_VECTOR(WIDTH_B-1 DOWNTO 0);
+		rden_a	:	IN STD_LOGIC := '1';
+		rden_b	:	IN STD_LOGIC := '1';
+		wren_a	:	IN STD_LOGIC := '0';
+		wren_b	:	IN STD_LOGIC := '0'
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  cycloneiii_lcell_comb
+	 GENERIC 
+	 (
+		DONT_TOUCH	:	STRING := "off";
+		LUT_MASK	:	STD_LOGIC_VECTOR(15 DOWNTO 0) := "0000000000000000";
+		SUM_LUTC_INPUT	:	STRING := "datac";
+		lpm_type	:	STRING := "cycloneiii_lcell_comb"
+	 );
+	 PORT
+	 ( 
+		cin	:	IN STD_LOGIC := '0';
+		combout	:	OUT STD_LOGIC;
+		cout	:	OUT STD_LOGIC;
+		dataa	:	IN STD_LOGIC := '0';
+		datab	:	IN STD_LOGIC := '0';
+		datac	:	IN STD_LOGIC := '0';
+		datad	:	IN STD_LOGIC := '0'
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  lpm_add_sub
+	 GENERIC 
+	 (
+		LPM_DIRECTION	:	STRING := "DEFAULT";
+		LPM_PIPELINE	:	NATURAL := 0;
+		LPM_REPRESENTATION	:	STRING := "SIGNED";
+		LPM_WIDTH	:	NATURAL;
+		lpm_hint	:	STRING := "UNUSED";
+		lpm_type	:	STRING := "lpm_add_sub"
+	 );
+	 PORT
+	 ( 
+		aclr	:	IN STD_LOGIC := '0';
+		add_sub	:	IN STD_LOGIC := '1';
+		cin	:	IN STD_LOGIC := 'Z';
+		clken	:	IN STD_LOGIC := '1';
+		clock	:	IN STD_LOGIC := '0';
+		cout	:	OUT STD_LOGIC;
+		dataa	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
+		datab	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
+		overflow	:	OUT STD_LOGIC;
+		result	:	OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  lpm_compare
+	 GENERIC 
+	 (
+		LPM_PIPELINE	:	NATURAL := 0;
+		LPM_REPRESENTATION	:	STRING := "UNSIGNED";
+		LPM_WIDTH	:	NATURAL;
+		lpm_hint	:	STRING := "UNUSED";
+		lpm_type	:	STRING := "lpm_compare"
+	 );
+	 PORT
+	 ( 
+		aclr	:	IN STD_LOGIC := '0';
+		aeb	:	OUT STD_LOGIC;
+		agb	:	OUT STD_LOGIC;
+		ageb	:	OUT STD_LOGIC;
+		alb	:	OUT STD_LOGIC;
+		aleb	:	OUT STD_LOGIC;
+		aneb	:	OUT STD_LOGIC;
+		clken	:	IN STD_LOGIC := '1';
+		clock	:	IN STD_LOGIC := '0';
+		dataa	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
+		datab	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0')
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  lpm_counter
+	 GENERIC 
+	 (
+		lpm_avalue	:	STRING := "0";
+		lpm_direction	:	STRING := "DEFAULT";
+		lpm_modulus	:	NATURAL := 0;
+		lpm_port_updown	:	STRING := "PORT_CONNECTIVITY";
+		lpm_pvalue	:	STRING := "0";
+		lpm_svalue	:	STRING := "0";
+		lpm_width	:	NATURAL;
+		lpm_type	:	STRING := "lpm_counter"
+	 );
+	 PORT
+	 ( 
+		aclr	:	IN STD_LOGIC := '0';
+		aload	:	IN STD_LOGIC := '0';
+		aset	:	IN STD_LOGIC := '0';
+		cin	:	IN STD_LOGIC := '1';
+		clk_en	:	IN STD_LOGIC := '1';
+		clock	:	IN STD_LOGIC;
+		cnt_en	:	IN STD_LOGIC := '1';
+		cout	:	OUT STD_LOGIC;
+		data	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
+		eq	:	OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
+		q	:	OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
+		sclr	:	IN STD_LOGIC := '0';
+		sload	:	IN STD_LOGIC := '0';
+		sset	:	IN STD_LOGIC := '0';
+		updown	:	IN STD_LOGIC := '1'
+	 ); 
+	 END COMPONENT;
+	 COMPONENT  lpm_decode
+	 GENERIC 
+	 (
+		LPM_DECODES	:	NATURAL;
+		LPM_PIPELINE	:	NATURAL := 0;
+		LPM_WIDTH	:	NATURAL;
+		lpm_hint	:	STRING := "UNUSED";
+		lpm_type	:	STRING := "lpm_decode"
+	 );
+	 PORT
+	 ( 
+		aclr	:	IN STD_LOGIC := '0';
+		clken	:	IN STD_LOGIC := '1';
+		clock	:	IN STD_LOGIC := '0';
+		data	:	IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
+		enable	:	IN STD_LOGIC := '1';
+		eq	:	OUT STD_LOGIC_VECTOR(LPM_DECODES-1 DOWNTO 0)
+	 ); 
+	 END COMPONENT;
+ BEGIN
+
+	wire_gnd <= '0';
+	loop0 : FOR i IN 0 TO 7 GENERATE 
+		wire_w_lg_w_lg_read_addr_counter_out1934w1935w(i) <= wire_w_lg_read_addr_counter_out1934w(i) AND wire_rom_data_state_w_lg_w_lg_q1897w1933w(0);
+	END GENERATE loop0;
+	loop1 : FOR i IN 0 TO 7 GENERATE 
+		wire_w_lg_w_lg_rom_width_counter_enable1931w1932w(i) <= wire_w_lg_rom_width_counter_enable1931w(0) AND addr_from_rom2(i);
+	END GENERATE loop1;
+	loop2 : FOR i IN 0 TO 7 GENERATE 
+		wire_w_lg_addr_counter_out1938w(i) <= addr_counter_out(i) AND addr_counter_enable;
+	END GENERATE loop2;
+	loop3 : FOR i IN 0 TO 7 GENERATE 
+		wire_w_lg_addr_decoder_out1901w(i) <= addr_decoder_out(i) AND wire_write_init_state_w_lg_q1900w(0);
+	END GENERATE loop3;
+	loop4 : FOR i IN 0 TO 7 GENERATE 
+		wire_w_lg_c0_wire1828w(i) <= c0_wire(i) AND wire_w_rotate_decoder_wires_range1827w(0);
+	END GENERATE loop4;
+	loop5 : FOR i IN 0 TO 7 GENERATE 
+		wire_w_lg_c1_wire1826w(i) <= c1_wire(i) AND wire_w_rotate_decoder_wires_range1825w(0);
+	END GENERATE loop5;
+	loop6 : FOR i IN 0 TO 7 GENERATE 
+		wire_w_lg_c2_wire1824w(i) <= c2_wire(i) AND wire_w_rotate_decoder_wires_range1823w(0);
+	END GENERATE loop6;
+	loop7 : FOR i IN 0 TO 7 GENERATE 
+		wire_w_lg_c3_wire1822w(i) <= c3_wire(i) AND wire_w_rotate_decoder_wires_range1821w(0);
+	END GENERATE loop7;
+	loop8 : FOR i IN 0 TO 7 GENERATE 
+		wire_w_lg_c4_wire1820w(i) <= c4_wire(i) AND wire_w_rotate_decoder_wires_range1819w(0);
+	END GENERATE loop8;
+	loop9 : FOR i IN 0 TO 7 GENERATE 
+		wire_w_lg_read_addr_counter_out1887w(i) <= read_addr_counter_out(i) AND wire_rom_first_state_w_lg_w_lg_q1885w1886w(0);
+	END GENERATE loop9;
+	loop10 : FOR i IN 0 TO 7 GENERATE 
+		wire_w_lg_read_addr_counter_out1934w(i) <= read_addr_counter_out(i) AND read_addr_counter_enable;
+	END GENERATE loop10;
+	loop11 : FOR i IN 0 TO 7 GENERATE 
+		wire_w_lg_read_addr_decoder_out1893w(i) <= read_addr_decoder_out(i) AND wire_read_init_state_w_lg_q1891w(0);
+	END GENERATE loop11;
+	loop12 : FOR i IN 0 TO 7 GENERATE 
+		wire_w_lg_reconfig_addr_counter_out1936w(i) <= reconfig_addr_counter_out(i) AND reconfig_addr_counter_enable;
+	END GENERATE loop12;
+	wire_w_lg_rom_data_in1946w(0) <= rom_data_in AND wire_rom_first_state_w_lg_w_lg_w_lg_q1943w1944w1945w(0);
+	wire_w_lg_rom_width_counter_enable1931w(0) <= rom_width_counter_enable AND wire_rom_data_state_w_lg_w_lg_q1929w1930w(0);
+	loop13 : FOR i IN 0 TO 7 GENERATE 
+		wire_w_lg_rotate_addr_counter_out1937w(i) <= rotate_addr_counter_out(i) AND rotate_addr_counter_enable;
+	END GENERATE loop13;
+	wire_w_lg_shift_reg_load_enable187w(0) <= shift_reg_load_enable AND wire_w_data_in_range186w(0);
+	wire_w_lg_shift_reg_load_enable179w(0) <= shift_reg_load_enable AND wire_w_data_in_range178w(0);
+	wire_w_lg_shift_reg_load_enable171w(0) <= shift_reg_load_enable AND wire_w_data_in_range170w(0);
+	wire_w_lg_shift_reg_load_enable163w(0) <= shift_reg_load_enable AND wire_w_data_in_range162w(0);
+	wire_w_lg_shift_reg_load_enable155w(0) <= shift_reg_load_enable AND wire_w_data_in_range154w(0);
+	wire_w_lg_shift_reg_load_enable147w(0) <= shift_reg_load_enable AND wire_w_data_in_range146w(0);
+	wire_w_lg_shift_reg_load_enable139w(0) <= shift_reg_load_enable AND wire_w_data_in_range138w(0);
+	wire_w_lg_shift_reg_load_enable131w(0) <= shift_reg_load_enable AND wire_w_data_in_range130w(0);
+	wire_w_lg_shift_reg_load_enable123w(0) <= shift_reg_load_enable AND wire_w_data_in_range122w(0);
+	wire_w_lg_shift_reg_serial_out1948w(0) <= shift_reg_serial_out AND wire_rom_first_state_w_lg_w_lg_w_lg_w_lg_q1943w1944w1945w1947w(0);
+	wire_w_lg_w_counter_param_latch_range294w379w(0) <= wire_w_counter_param_latch_range294w(0) AND wire_w_lg_w_counter_param_latch_range296w297w(0);
+	wire_w_lg_w_counter_type_latch_range284w710w(0) <= wire_w_counter_type_latch_range284w(0) AND wire_w_lg_w_counter_type_latch_range286w530w(0);
+	wire_w_lg_dummy_scandataout1925w(0) <= NOT dummy_scandataout;
+	wire_w_lg_pll_scandone1927w(0) <= NOT pll_scandone;
+	wire_w_lg_read_addr_counter_done1867w(0) <= NOT read_addr_counter_done;
+	wire_w_lg_read_nominal_out216w(0) <= NOT read_nominal_out;
+	wire_w_lg_read_param1742w(0) <= NOT read_param;
+	wire_w_lg_reconfig1740w(0) <= NOT reconfig;
+	wire_w_lg_reconfig_done1852w(0) <= NOT reconfig_done;
+	wire_w_lg_reconfig_post_done1848w(0) <= NOT reconfig_post_done;
+	wire_w_lg_reconfig_width_counter_done1845w(0) <= NOT reconfig_width_counter_done;
+	wire_w_lg_reset1w(0) <= NOT reset;
+	wire_w_lg_reset_rom_address1752w(0) <= NOT reset_rom_address;
+	wire_w_lg_rom_width_counter_done1888w(0) <= NOT rom_width_counter_done;
+	wire_w_lg_rotate_width_counter_done1796w(0) <= NOT rotate_width_counter_done;
+	wire_w_lg_width_counter_done1764w(0) <= NOT width_counter_done;
+	wire_w_lg_write_from_rom1739w(0) <= NOT write_from_rom;
+	wire_w_lg_write_param1741w(0) <= NOT write_param;
+	wire_w_lg_w_counter_param_latch_range296w297w(0) <= NOT wire_w_counter_param_latch_range296w(0);
+	wire_w_lg_w_counter_type_latch_range286w530w(0) <= NOT wire_w_counter_type_latch_range286w(0);
+	wire_w_lg_w_lg_w_lg_w1329w1392w1452w1516w(0) <= wire_w_lg_w_lg_w1329w1392w1452w(0) OR w1484w;
+	wire_w_lg_w_lg_w1329w1392w1452w(0) <= wire_w_lg_w1329w1392w(0) OR w1424w;
+	wire_w_lg_w_lg_w_lg_w1361w1422w1483w1550w(0) <= wire_w_lg_w_lg_w1361w1422w1483w(0) OR w1517w;
+	wire_w_lg_w1329w1392w(0) <= wire_w1329w(0) OR w1362w;
+	wire_w_lg_w_lg_w1361w1422w1483w(0) <= wire_w_lg_w1361w1422w(0) OR w1453w;
+	wire_w1329w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w980w1055w1126w1195w1261w(0) OR w1297w;
+	wire_w_lg_w1361w1422w(0) <= wire_w1361w(0) OR w1393w;
+	wire_w_lg_w_lg_w_lg_w_lg_w980w1055w1126w1195w1261w(0) <= wire_w_lg_w_lg_w_lg_w980w1055w1126w1195w(0) OR w1229w;
+	wire_w1361w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w1016w1091w1160w1228w1294w(0) OR w1330w;
+	wire_w_lg_w_lg_w_lg_w980w1055w1126w1195w(0) <= wire_w_lg_w_lg_w980w1055w1126w(0) OR w1163w;
+	wire_w_lg_w_lg_w_lg_w_lg_w1016w1091w1160w1228w1294w(0) <= wire_w_lg_w_lg_w_lg_w1016w1091w1160w1228w(0) OR w1262w;
+	wire_w_lg_w_lg_w980w1055w1126w(0) <= wire_w_lg_w980w1055w(0) OR w1092w;
+	wire_w_lg_w_lg_w_lg_w1016w1091w1160w1228w(0) <= wire_w_lg_w_lg_w1016w1091w1160w(0) OR w1196w;
+	wire_w_lg_w980w1055w(0) <= wire_w980w(0) OR w1019w;
+	wire_w_lg_w_lg_w1016w1091w1160w(0) <= wire_w_lg_w1016w1091w(0) OR w1127w;
+	wire_w980w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w_lg_w423w570w637w749w817w920w(0) OR w952w;
+	wire_w_lg_w1016w1091w(0) <= wire_w1016w(0) OR w1056w;
+	wire_w_lg_w_lg_w_lg_w_lg_w_lg_w423w570w637w749w817w920w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w423w570w637w749w817w(0) OR w888w;
+	wire_w1016w(0) <= wire_w_lg_w_lg_w_lg_w_lg_w571w672w784w850w951w(0) OR w981w;
+	wire_w63w(0) <= wire_w_lg_w_lg_w_lg_shift_reg_load_enable60w61w62w(0) OR shift_reg_clear;
+	wire_w_lg_w_lg_w_lg_w_lg_w423w570w637w749w817w(0) <= wire_w_lg_w_lg_w_lg_w423w570w637w749w(0) OR w785w;
+	wire_w_lg_w_lg_w_lg_w_lg_w571w672w784w850w951w(0) <= wire_w_lg_w_lg_w_lg_w571w672w784w850w(0) OR w921w;
+	wire_w_lg_w_lg_w_lg_shift_reg_load_enable60w61w62w(0) <= wire_w_lg_w_lg_shift_reg_load_enable60w61w(0) OR shift_reg_shift_nominal_enable;
+	wire_w_lg_w_lg_w_lg_w423w570w637w749w(0) <= wire_w_lg_w_lg_w423w570w637w(0) OR w713w;
+	wire_w_lg_w_lg_w_lg_w571w672w784w850w(0) <= wire_w_lg_w_lg_w571w672w784w(0) OR w818w;
+	wire_w_lg_w_lg_shift_reg_load_enable60w61w(0) <= wire_w_lg_shift_reg_load_enable60w(0) OR shift_reg_load_nominal_enable;
+	wire_w_lg_w_lg_w423w570w637w(0) <= wire_w_lg_w423w570w(0) OR w605w;
+	wire_w_lg_w_lg_w571w672w784w(0) <= wire_w_lg_w571w672w(0) OR w750w;
+	wire_w_lg_dummy_scandataout1926w(0) <= dummy_scandataout OR wire_w_lg_dummy_scandataout1925w(0);
+	wire_w_lg_shift_reg_load_enable60w(0) <= shift_reg_load_enable OR shift_reg_shift_enable;
+	wire_w_lg_w301w378w(0) <= w301w OR w341w;
+	wire_w_lg_w381w495w(0) <= w381w OR w460w;
+	wire_w_lg_w423w570w(0) <= w423w OR w534w;
+	wire_w_lg_w571w672w(0) <= w571w OR w638w;
+	wire_w_lg_w675w885w(0) <= w675w OR w851w;
+	addr_counter_enable <= (write_data_state OR write_nominal_state);
+	addr_counter_out <= wire_cntr1_q;
+	addr_counter_sload <= wire_write_init_state_w_lg_q1900w(0);
+	addr_counter_sload_value <= wire_w_lg_addr_decoder_out1901w;
+	addr_decoder_out <= (((((((((((((((((((((((((((((((((((( "0" & "0" & "0" & "0" & "0" & "0" & "0" & w301w) OR ( "0" & "0" & "0" & "0" & "0" & "0" & w341w & w341w)) OR ( "0" & "0" & "0" & "0" & w381w & "0" & "0" & "0")) OR ( "0" & "0" & "0" & "0" & w423w & "0" & "0" & w423w)) OR ( "0" & "0" & "0" & "0" & w460w & w460w & w460w & "0")) OR ( "0" & "0" & "0" & w496w & "0" & "0" & "0" & w496w)) OR ( "0" & "0" & "0" & w534w & "0" & "0" & w534w & "0")) OR ( "0" & "0" & "0" & w571w & w571w & "0" & w571w & "0")) OR ( "0" & "0" & "0" & w605w & w605w & "0" & w605w & w605w)) OR ( "0" & "0" & w638w & "0" & "0" & "0" & w638w & w638w)) OR ( "0" & "0" & w675w & "0" & "0" & "0" & w675w & w675w)) OR ( "0" & "0" & w713w & "0" & "0" & w713w & "0" & "0")) OR ( "0" & "0" & w750w & "0" & w750w & w750w & "0" & "0")) OR ( "0" & "0" & w785w & "0" & w785w & w785w & "0" & w785w)) OR ( "0" & "0" & w818w & w818w & "0" & w818w & "0" & w818w)) OR ( "0" & "0" & w851w & w851w & "0" & w851w & "0" & w851w)) OR ( "0" & "0" & w888w & w888w & "0" & w888w & w888w & "0")) OR ( "0" & "0" & w921w & w921w & w921w & w921w & w921w & "0")) OR ( "0" & "0" & w952w & w952w & w952w & w952w & w952w & w952w)) OR ( "0" & w981w & "0" & "0" & "0" & w981w & w981w & w981w)) OR ( "0" & w1019w & "0" & "0" & w1019w & "0" & "0" & "0")) OR ( "0" & w1056w & "0" & w1056w & "0" & "0" & "0" & "0")) OR ( "0" & w1092w & "0" & w1092w & "0" & "0" & "0" & w1092w)) OR ( "0" & w1127w & "0" & w1127w & w1127w & "0" & "0" & w1127w)) OR ( "0" & w1163w & "0" & w1163w & w1163w & "0" & w1163w & "0")) OR ( "0" & w1196w & w1196w & "0" & "0" & "0" & w1196w & "0")) OR ( "0" & w1229w & w1229w & "0" & "0" & "0" & w1229w & w1229w)) OR ( "0" & w1262w & w1262w & "0" & w1262w & "0" & w1262w & w1262w)) OR ( "0" & w1297w & w1297w & "0" & w1297w & w1297w & "0" & "0")) OR ( "0" & w1330w & w1330w & w1330w & "0" & w1330w & "0" & "0")) OR ( "0" & w1362w & w1362w & w1362w & "0" & w1362w & "0" & w1362w)) OR ( "0" & w1393w & w1393w & w1393w & w1393w & w1393w & "0" & w1393w)) OR ( "0" & w1424w & w1424w & w1424w & w1424w
+ & w1424w & w1424w & "0")) OR ( w1453w & "0" & "0" & "0" & "0" & w1453w & w1453w & "0")) OR ( w1484w & "0" & "0" & "0" & "0" & w1484w & w1484w & w1484w)) OR ( w1517w & "0" & "0" & "0" & w1517w & w1517w & w1517w & w1517w));
+	busy <= (wire_idle_state_w_lg_q1672w(0) OR areset_state);
+	c0_wire <= "01000111";
+	c1_wire <= "01011001";
+	c2_wire <= "01101011";
+	c3_wire <= "01111101";
+	c4_wire <= "10001111";
+	const_scan_chain_size <= "10001111";
+	counter_param_latch <= counter_param_latch_reg;
+	counter_type_latch <= counter_type_latch_reg;
+	cuda_combout_wire <= ( wire_le_comb10_combout & wire_le_comb9_combout & wire_le_comb8_combout);
+	data_out <= ( wire_shift_reg_w_lg_w_lg_q258w259w & wire_shift_reg_w_lg_w_lg_q253w254w & wire_shift_reg_w_lg_w_lg_q248w249w & wire_shift_reg_w_lg_w_lg_q243w244w & wire_shift_reg_w_lg_w_lg_q238w239w & wire_shift_reg_w_lg_w_lg_q233w234w & wire_shift_reg_w_lg_w_lg_q228w229w & wire_shift_reg_w_lg_w_lg_q223w224w & wire_shift_reg_w_lg_w_lg_q217w218w);
+	dummy_scandataout <= pll_scandataout;
+	encode_out <= ( C4_ena_state & wire_C2_ena_state_w_lg_q1787w & wire_C1_ena_state_w_lg_q1786w);
+	input_latch_enable <= (idle_state AND (write_param OR read_param));
+	pll_areset <= (pll_areset_in OR (areset_state AND reconfig_wait_state));
+	pll_configupdate <= (configupdate_state AND wire_configupdate3_state_w_lg_q1879w(0));
+	pll_scanclk <= clock;
+	pll_scanclkena <= ((rotate_width_counter_enable AND wire_w_lg_rotate_width_counter_done1796w(0)) OR reconfig_seq_data_state);
+	pll_scandata <= (scan_cache_out AND ((rotate_width_counter_enable OR reconfig_seq_data_state) OR reconfig_post_state));
+	power_up <= (((((((((((((((((((((((((wire_reset_state_w_lg_q1671w(0) AND wire_idle_state_w_lg_q1672w(0)) AND wire_read_init_state_w_lg_q1674w(0)) AND wire_read_first_state_w_lg_q1676w(0)) AND wire_read_data_state_w_lg_q1678w(0)) AND wire_read_last_state_w_lg_q1680w(0)) AND wire_read_init_nominal_state_w_lg_q1682w(0)) AND wire_read_first_nominal_state_w_lg_q1684w(0)) AND wire_read_data_nominal_state_w_lg_q1686w(0)) AND wire_read_last_nominal_state_w_lg_q1688w(0)) AND wire_write_init_state_w_lg_q1690w(0)) AND wire_write_data_state_w_lg_q1692w(0)) AND wire_write_init_nominal_state_w_lg_q1694w(0)) AND wire_write_nominal_state_w_lg_q1696w(0)) AND wire_reconfig_init_state_w_lg_q1698w(0)) AND wire_reconfig_counter_state_w_lg_q1700w(0)) AND wire_reconfig_seq_ena_state_w_lg_q1702w(0)) AND wire_reconfig_seq_data_state_w_lg_q1704w(0)) AND wire_reconfig_post_state_w_lg_q1706w(0)) AND wire_reconfig_wait_state_w_lg_q1708w(0)) AND wire_rom_init_state_w_lg_q1710w(0)) AND wire_rom_first_state_w_lg_q1712w(0)) AND wire_rom_second_state_w_lg_q1714w(0)) AND wire_rom_data_state_w_lg_q1716w(0)) AND wire_rom_second_last_state_w_lg_q1718w(0)) AND wire_rom_last_state_w_lg_q1720w(0));
+	read_addr_counter_done <= (((((((wire_cntr2_q(0) AND wire_cntr2_q(1)) AND wire_cntr2_q(2)) AND wire_cntr2_q(3)) AND (NOT wire_cntr2_q(4))) AND (NOT wire_cntr2_q(5))) AND (NOT wire_cntr2_q(6))) AND wire_cntr2_q(7));
+	read_addr_counter_enable <= (wire_read_first_state_w_lg_w_lg_w_lg_q1894w1895w1896w(0) OR wire_rom_data_state_w_lg_w_lg_q1897w1898w(0));
+	read_addr_counter_out <= wire_cntr2_q;
+	read_addr_counter_sload <= (wire_read_init_state_w_lg_q1891w(0) OR rom_init_state);
+	read_addr_counter_sload_value <= wire_w_lg_read_addr_decoder_out1893w;
+	read_addr_decoder_out <= (((((((((((((((((((((((((((((((((((( "0" & "0" & "0" & "0" & "0" & "0" & "0" & "0") OR ( "0" & "0" & "0" & "0" & "0" & "0" & w341w & "0")) OR ( "0" & "0" & "0" & "0" & "0" & w381w & "0" & "0")) OR ( "0" & "0" & "0" & "0" & w423w & "0" & "0" & w423w)) OR ( "0" & "0" & "0" & "0" & w460w & "0" & w460w & "0")) OR ( "0" & "0" & "0" & "0" & w496w & w496w & w496w & w496w)) OR ( "0" & "0" & "0" & w534w & "0" & "0" & w534w & "0")) OR ( "0" & "0" & "0" & w571w & "0" & "0" & w571w & w571w)) OR ( "0" & "0" & "0" & w605w & w605w & "0" & w605w & w605w)) OR ( "0" & "0" & "0" & w638w & w638w & w638w & "0" & "0")) OR ( "0" & "0" & "0" & w675w & "0" & "0" & w675w & "0")) OR ( "0" & "0" & w713w & "0" & "0" & w713w & "0" & "0")) OR ( "0" & "0" & w750w & "0" & "0" & w750w & "0" & w750w)) OR ( "0" & "0" & w785w & "0" & w785w & w785w & "0" & w785w)) OR ( "0" & "0" & w818w & "0" & w818w & w818w & w818w & "0")) OR ( "0" & "0" & w851w & "0" & "0" & w851w & "0" & "0")) OR ( "0" & "0" & w888w & w888w & "0" & w888w & w888w & "0")) OR ( "0" & "0" & w921w & w921w & "0" & w921w & w921w & w921w)) OR ( "0" & "0" & w952w & w952w & w952w & w952w & w952w & w952w)) OR ( "0" & w981w & "0" & "0" & "0" & "0" & "0" & "0")) OR ( "0" & w1019w & "0" & "0" & w1019w & "0" & "0" & "0")) OR ( "0" & w1056w & "0" & "0" & w1056w & "0" & "0" & w1056w)) OR ( "0" & w1092w & "0" & w1092w & "0" & "0" & "0" & w1092w)) OR ( "0" & w1127w & "0" & w1127w & "0" & "0" & w1127w & "0")) OR ( "0" & w1163w & "0" & w1163w & w1163w & "0" & w1163w & "0")) OR ( "0" & w1196w & "0" & w1196w & w1196w & "0" & w1196w & w1196w)) OR ( "0" & w1229w & w1229w & "0" & "0" & "0" & w1229w & w1229w)) OR ( "0" & w1262w & w1262w & "0" & "0" & w1262w & "0" & "0")) OR ( "0" & w1297w & w1297w & "0" & w1297w & w1297w & "0" & "0")) OR ( "0" & w1330w & w1330w & "0" & w1330w & w1330w & "0" & w1330w)) OR ( "0" & w1362w & w1362w & w1362w & "0" & w1362w & "0" & w1362w)) OR ( "0" & w1393w & w1393w & w1393w & "0" & w1393w & w1393w & "0")) OR ( "0" & w1424w & w1424w & w1424w & w1424w & w1424w
+ & w1424w & "0")) OR ( "0" & w1453w & w1453w & w1453w & w1453w & w1453w & w1453w & w1453w)) OR ( w1484w & "0" & "0" & "0" & "0" & w1484w & w1484w & w1484w)) OR ( w1517w & "0" & "0" & "0" & w1517w & "0" & "0" & "0"));
+	read_nominal_out <= tmp_nominal_data_out_state;
+	reconfig_addr_counter_enable <= reconfig_seq_data_state;
+	reconfig_addr_counter_out <= wire_cntr12_q;
+	reconfig_addr_counter_sload <= reconfig_seq_ena_state;
+	reconfig_addr_counter_sload_value <= wire_reconfig_seq_ena_state_w_lg_q1903w;
+	reconfig_done <= (wire_w_lg_pll_scandone1927w(0) AND wire_w_lg_dummy_scandataout1926w(0));
+	reconfig_post_done <= pll_scandone;
+	reconfig_width_counter_done <= ((((((NOT wire_cntr13_q(0)) AND (NOT wire_cntr13_q(1))) AND (NOT wire_cntr13_q(2))) AND (NOT wire_cntr13_q(3))) AND (NOT wire_cntr13_q(4))) AND (NOT wire_cntr13_q(5)));
+	reconfig_width_counter_enable <= reconfig_seq_data_state;
+	reconfig_width_counter_sload <= reconfig_seq_ena_state;
+	reconfig_width_counter_sload_value <= wire_reconfig_seq_ena_state_w_lg_q1904w;
+	rom_address_out <= wire_w_lg_read_addr_counter_out1887w;
+	rom_width_counter_done <= ((((((((NOT wire_cntr14_q(0)) AND (NOT wire_cntr14_q(1))) AND (NOT wire_cntr14_q(2))) AND (NOT wire_cntr14_q(3))) AND (NOT wire_cntr14_q(4))) AND (NOT wire_cntr14_q(5))) AND (NOT wire_cntr14_q(6))) AND (NOT wire_cntr14_q(7)));
+	rom_width_counter_enable <= ((rom_data_state OR rom_last_state) OR rom_second_last_state);
+	rom_width_counter_sload <= rom_init_state;
+	rom_width_counter_sload_value <= const_scan_chain_size;
+	rotate_addr_counter_enable <= ((((C0_data_state OR C1_data_state) OR C2_data_state) OR C3_data_state) OR C4_data_state);
+	rotate_addr_counter_out <= wire_cntr16_q;
+	rotate_addr_counter_sload <= ((((C0_ena_state OR C1_ena_state) OR C2_ena_state) OR C3_ena_state) OR C4_ena_state);
+	rotate_addr_counter_sload_value <= ((((wire_w_lg_c0_wire1828w OR wire_w_lg_c1_wire1826w) OR wire_w_lg_c2_wire1824w) OR wire_w_lg_c3_wire1822w) OR wire_w_lg_c4_wire1820w);
+	rotate_decoder_wires <= wire_decode11_eq;
+	rotate_width_counter_done <= (((((NOT wire_cntr15_q(0)) AND (NOT wire_cntr15_q(1))) AND (NOT wire_cntr15_q(2))) AND (NOT wire_cntr15_q(3))) AND (NOT wire_cntr15_q(4)));
+	rotate_width_counter_enable <= ((((C0_data_state OR C1_data_state) OR C2_data_state) OR C3_data_state) OR C4_data_state);
+	rotate_width_counter_sload <= ((((C0_ena_state OR C1_ena_state) OR C2_ena_state) OR C3_ena_state) OR C4_ena_state);
+	rotate_width_counter_sload_value <= "10010";
+	scan_cache_address <= ((((wire_w_lg_addr_counter_out1938w OR wire_w_lg_rotate_addr_counter_out1937w) OR wire_w_lg_reconfig_addr_counter_out1936w) OR wire_w_lg_w_lg_read_addr_counter_out1934w1935w) OR wire_w_lg_w_lg_rom_width_counter_enable1931w1932w);
+	scan_cache_in <= (wire_w_lg_shift_reg_serial_out1948w(0) OR wire_w_lg_rom_data_in1946w(0));
+	scan_cache_out <= wire_altsyncram4_q_a(0);
+	scan_cache_write_enable <= ((((write_data_state OR write_nominal_state) OR rom_data_state) OR rom_second_last_state) OR rom_last_state);
+	sel_param_bypass_LF_unused <= (((NOT counter_param_latch(0)) AND wire_w_lg_w_counter_param_latch_range296w297w(0)) AND counter_param_latch(2));
+	sel_param_c <= (((NOT counter_param_latch(0)) AND counter_param_latch(1)) AND (NOT counter_param_latch(2)));
+	sel_param_high_i_postscale <= (((NOT counter_param_latch(0)) AND wire_w_lg_w_counter_param_latch_range296w297w(0)) AND (NOT counter_param_latch(2)));
+	sel_param_low_r <= (wire_w_lg_w_counter_param_latch_range294w379w(0) AND (NOT counter_param_latch(2)));
+	sel_param_nominal_count <= ((counter_param_latch(0) AND counter_param_latch(1)) AND counter_param_latch(2));
+	sel_param_odd_CP_unused <= (wire_w_lg_w_counter_param_latch_range294w379w(0) AND counter_param_latch(2));
+	sel_type_c0 <= ((((NOT counter_type_latch(0)) AND wire_w_lg_w_counter_type_latch_range286w530w(0)) AND counter_type_latch(2)) AND (NOT counter_type_latch(3)));
+	sel_type_c1 <= ((wire_w_lg_w_counter_type_latch_range284w710w(0) AND counter_type_latch(2)) AND (NOT counter_type_latch(3)));
+	sel_type_c2 <= ((((NOT counter_type_latch(0)) AND counter_type_latch(1)) AND counter_type_latch(2)) AND (NOT counter_type_latch(3)));
+	sel_type_c3 <= (((counter_type_latch(0) AND counter_type_latch(1)) AND counter_type_latch(2)) AND (NOT counter_type_latch(3)));
+	sel_type_c4 <= ((((NOT counter_type_latch(0)) AND wire_w_lg_w_counter_type_latch_range286w530w(0)) AND (NOT counter_type_latch(2))) AND counter_type_latch(3));
+	sel_type_cplf <= ((((NOT counter_type_latch(0)) AND counter_type_latch(1)) AND (NOT counter_type_latch(2))) AND (NOT counter_type_latch(3)));
+	sel_type_m <= ((wire_w_lg_w_counter_type_latch_range284w710w(0) AND (NOT counter_type_latch(2))) AND (NOT counter_type_latch(3)));
+	sel_type_n <= ((((NOT counter_type_latch(0)) AND wire_w_lg_w_counter_type_latch_range286w530w(0)) AND (NOT counter_type_latch(2))) AND (NOT counter_type_latch(3)));
+	sel_type_vco <= (((counter_type_latch(0) AND counter_type_latch(1)) AND (NOT counter_type_latch(2))) AND (NOT counter_type_latch(3)));
+	seq_addr_wire <= "00110101";
+	seq_sload_value <= "110110";
+	shift_reg_clear <= wire_read_init_state_w_lg_q1891w(0);
+	shift_reg_load_enable <= ((idle_state AND write_param) AND (NOT ((((((NOT counter_type(3)) AND (NOT counter_type(2))) AND (NOT counter_type(1))) AND counter_param(2)) AND counter_param(1)) AND counter_param(0))));
+	shift_reg_load_nominal_enable <= ((idle_state AND write_param) AND ((((((NOT counter_type(3)) AND (NOT counter_type(2))) AND (NOT counter_type(1))) AND counter_param(2)) AND counter_param(1)) AND counter_param(0)));
+	shift_reg_serial_in <= scan_cache_out;
+	shift_reg_serial_out <= (((((((wire_shift_reg_w_lg_q262w(0) OR wire_shift_reg_w_lg_q264w(0)) OR wire_shift_reg_w_lg_q267w(0)) OR wire_shift_reg_w_lg_q270w(0)) OR wire_shift_reg_w_lg_q273w(0)) OR wire_shift_reg_w_lg_q276w(0)) OR wire_shift_reg_w_lg_q279w(0)) OR wire_shift_reg_w_lg_q282w(0));
+	shift_reg_shift_enable <= ((read_data_state OR read_last_state) OR write_data_state);
+	shift_reg_shift_nominal_enable <= ((read_data_nominal_state OR read_last_nominal_state) OR write_nominal_state);
+	shift_reg_width_select <= width_decoder_select;
+	w1019w <= (sel_type_c1 AND sel_param_bypass_LF_unused);
+	w1056w <= (sel_type_c1 AND sel_param_high_i_postscale);
+	w1092w <= (sel_type_c1 AND sel_param_odd_CP_unused);
+	w1127w <= (sel_type_c1 AND sel_param_low_r);
+	w1163w <= (sel_type_c2 AND sel_param_bypass_LF_unused);
+	w1196w <= (sel_type_c2 AND sel_param_high_i_postscale);
+	w1229w <= (sel_type_c2 AND sel_param_odd_CP_unused);
+	w1262w <= (sel_type_c2 AND sel_param_low_r);
+	w1297w <= (sel_type_c3 AND sel_param_bypass_LF_unused);
+	w1330w <= (sel_type_c3 AND sel_param_high_i_postscale);
+	w1362w <= (sel_type_c3 AND sel_param_odd_CP_unused);
+	w1393w <= (sel_type_c3 AND sel_param_low_r);
+	w1424w <= (sel_type_c4 AND sel_param_bypass_LF_unused);
+	w1453w <= (sel_type_c4 AND sel_param_high_i_postscale);
+	w1484w <= (sel_type_c4 AND sel_param_odd_CP_unused);
+	w1517w <= (sel_type_c4 AND sel_param_low_r);
+	w1565w <= '0';
+	w1592w <= '0';
+	w301w <= (sel_type_cplf AND sel_param_bypass_LF_unused);
+	w341w <= (sel_type_cplf AND sel_param_c);
+	w381w <= (sel_type_cplf AND sel_param_low_r);
+	w423w <= (sel_type_vco AND sel_param_high_i_postscale);
+	w460w <= (sel_type_cplf AND sel_param_odd_CP_unused);
+	w496w <= (sel_type_cplf AND sel_param_high_i_postscale);
+	w534w <= (sel_type_n AND sel_param_bypass_LF_unused);
+	w571w <= (sel_type_n AND sel_param_high_i_postscale);
+	w605w <= (sel_type_n AND sel_param_odd_CP_unused);
+	w638w <= (sel_type_n AND sel_param_low_r);
+	w64w <= '0';
+	w675w <= (sel_type_n AND sel_param_nominal_count);
+	w713w <= (sel_type_m AND sel_param_bypass_LF_unused);
+	w750w <= (sel_type_m AND sel_param_high_i_postscale);
+	w785w <= (sel_type_m AND sel_param_odd_CP_unused);
+	w818w <= (sel_type_m AND sel_param_low_r);
+	w851w <= (sel_type_m AND sel_param_nominal_count);
+	w888w <= (sel_type_c0 AND sel_param_bypass_LF_unused);
+	w921w <= (sel_type_c0 AND sel_param_high_i_postscale);
+	w952w <= (sel_type_c0 AND sel_param_odd_CP_unused);
+	w981w <= (sel_type_c0 AND sel_param_low_r);
+	width_counter_done <= (((((NOT wire_cntr3_q(0)) AND (NOT wire_cntr3_q(1))) AND (NOT wire_cntr3_q(2))) AND (NOT wire_cntr3_q(3))) AND (NOT wire_cntr3_q(4)));
+	width_counter_enable <= (((wire_read_first_state_w_lg_q1894w(0) OR write_data_state) OR read_data_nominal_state) OR write_nominal_state);
+	width_counter_sload <= (((read_init_state OR write_init_state) OR read_init_nominal_state) OR write_init_nominal_state);
+	width_counter_sload_value <= width_decoder_out;
+	width_decoder_out <= (((((( "0" & "0" & "0" & "0" & "0") OR ( width_decoder_select(2) & "0" & "0" & "0" & width_decoder_select(2))) OR ( "0" & "0" & "0" & "0" & width_decoder_select(3))) OR ( "0" & "0" & width_decoder_select(5) & width_decoder_select(5) & width_decoder_select(5))) OR ( "0" & "0" & "0" & width_decoder_select(6) & "0")) OR ( "0" & "0" & width_decoder_select(7) & "0" & "0"));
+	width_decoder_select <= ( wire_w_lg_w381w495w & w496w & wire_w_lg_w_lg_w_lg_w1361w1422w1483w1550w & w1592w & wire_w_lg_w301w378w & wire_w_lg_w675w885w & w1565w & wire_w_lg_w_lg_w_lg_w1329w1392w1452w1516w);
+	write_rom_ena <= (wire_rom_first_state_w_lg_q1885w(0) OR wire_rom_data_state_w_lg_q1889w(0));
+	wire_w_counter_param_latch_range294w(0) <= counter_param_latch(0);
+	wire_w_counter_param_latch_range296w(0) <= counter_param_latch(1);
+	wire_w_counter_type_latch_range284w(0) <= counter_type_latch(0);
+	wire_w_counter_type_latch_range286w(0) <= counter_type_latch(1);
+	wire_w_data_in_range186w(0) <= data_in(0);
+	wire_w_data_in_range178w(0) <= data_in(1);
+	wire_w_data_in_range170w(0) <= data_in(2);
+	wire_w_data_in_range162w(0) <= data_in(3);
+	wire_w_data_in_range154w(0) <= data_in(4);
+	wire_w_data_in_range146w(0) <= data_in(5);
+	wire_w_data_in_range138w(0) <= data_in(6);
+	wire_w_data_in_range130w(0) <= data_in(7);
+	wire_w_data_in_range122w(0) <= data_in(8);
+	wire_w_rotate_decoder_wires_range1827w(0) <= rotate_decoder_wires(0);
+	wire_w_rotate_decoder_wires_range1825w(0) <= rotate_decoder_wires(1);
+	wire_w_rotate_decoder_wires_range1823w(0) <= rotate_decoder_wires(2);
+	wire_w_rotate_decoder_wires_range1821w(0) <= rotate_decoder_wires(3);
+	wire_w_rotate_decoder_wires_range1819w(0) <= rotate_decoder_wires(4);
+	wire_w_shift_reg_width_select_range261w(0) <= shift_reg_width_select(0);
+	wire_w_shift_reg_width_select_range263w(0) <= shift_reg_width_select(1);
+	wire_w_shift_reg_width_select_range266w(0) <= shift_reg_width_select(2);
+	wire_w_shift_reg_width_select_range269w(0) <= shift_reg_width_select(3);
+	wire_w_shift_reg_width_select_range272w(0) <= shift_reg_width_select(4);
+	wire_w_shift_reg_width_select_range275w(0) <= shift_reg_width_select(5);
+	wire_w_shift_reg_width_select_range278w(0) <= shift_reg_width_select(6);
+	wire_w_shift_reg_width_select_range281w(0) <= shift_reg_width_select(7);
+	wire_altsyncram4_data_a(0) <= ( scan_cache_in);
+	altsyncram4 :  altsyncram
+	  GENERIC MAP (
+		NUMWORDS_A => 144,
+		OPERATION_MODE => "SINGLE_PORT",
+		WIDTH_A => 1,
+		WIDTH_BYTEENA_A => 1,
+		WIDTHAD_A => 8,
+		INTENDED_DEVICE_FAMILY => "Cyclone III"
+	  )
+	  PORT MAP ( 
+		address_a => scan_cache_address,
+		clock0 => clock,
+		data_a => wire_altsyncram4_data_a,
+		q_a => wire_altsyncram4_q_a,
+		wren_a => scan_cache_write_enable
+	  );
+	le_comb10 :  cycloneiii_lcell_comb
+	  GENERIC MAP (
+		DONT_TOUCH => "on",
+		LUT_MASK => "1111000011110000",
+		SUM_LUTC_INPUT => "datac"
+	  )
+	  PORT MAP ( 
+		combout => wire_le_comb10_combout,
+		dataa => encode_out(0),
+		datab => encode_out(1),
+		datac => encode_out(2)
+	  );
+	le_comb8 :  cycloneiii_lcell_comb
+	  GENERIC MAP (
+		DONT_TOUCH => "on",
+		LUT_MASK => "1010101010101010",
+		SUM_LUTC_INPUT => "datac"
+	  )
+	  PORT MAP ( 
+		combout => wire_le_comb8_combout,
+		dataa => encode_out(0),
+		datab => encode_out(1),
+		datac => encode_out(2)
+	  );
+	le_comb9 :  cycloneiii_lcell_comb
+	  GENERIC MAP (
+		DONT_TOUCH => "on",
+		LUT_MASK => "1100110011001100",
+		SUM_LUTC_INPUT => "datac"
+	  )
+	  PORT MAP ( 
+		combout => wire_le_comb9_combout,
+		dataa => encode_out(0),
+		datab => encode_out(1),
+		datac => encode_out(2)
+	  );
+	PROCESS (clock)
+	BEGIN
+		IF (clock = '1' AND clock'event) THEN addr_from_rom <= read_addr_counter_out;
+		END IF;
+	END PROCESS;
+	PROCESS (clock)
+	BEGIN
+		IF (clock = '1' AND clock'event) THEN addr_from_rom2 <= addr_from_rom;
+		END IF;
+	END PROCESS;
+	PROCESS (clock)
+	BEGIN
+		IF (clock = '1' AND clock'event) THEN areset_init_state_1 <= pll_scandone;
+		END IF;
+	END PROCESS;
+	PROCESS (clock)
+	BEGIN
+		IF (clock = '1' AND clock'event) THEN areset_state <= (areset_init_state_1 AND wire_w_lg_reset1w(0));
+		END IF;
+	END PROCESS;
+	PROCESS (clock)
+	BEGIN
+		IF (clock = '1' AND clock'event) THEN C0_data_state <= (C0_ena_state OR (C0_data_state AND wire_w_lg_rotate_width_counter_done1796w(0)));
+		END IF;
+	END PROCESS;
+	PROCESS (clock)
+	BEGIN
+		IF (clock = '1' AND clock'event) THEN C0_ena_state <= (C1_data_state AND rotate_width_counter_done);
+		END IF;
+	END PROCESS;
+	PROCESS (clock)
+	BEGIN
+		IF (clock = '1' AND clock'event) THEN C1_data_state <= (C1_ena_state OR (C1_data_state AND wire_w_lg_rotate_width_counter_done1796w(0)));
+		END IF;
+	END PROCESS;
+	PROCESS (clock)
+	BEGIN
+		IF (clock = '1' AND clock'event) THEN C1_ena_state <= (C2_data_state AND rotate_width_counter_done);
+		END IF;
+	END PROCESS;
+	wire_C1_ena_state_w_lg_q1786w(0) <= C1_ena_state OR C3_ena_state;
+	PROCESS (clock)
+	BEGIN
+		IF (clock = '1' AND clock'event) THEN C2_data_state <= (C2_ena_state OR (C2_data_state AND wire_w_lg_rotate_width_counter_done1796w(0)));
+		END IF;
+	END PROCESS;
+	PROCESS (clock)
+	BEGIN
+		IF (clock = '1' AND clock'event) THEN C2_ena_state <= (C3_data_state AND rotate_width_counter_done);
+		END IF;
+	END PROCESS;
+	wire_C2_ena_state_w_lg_q1787w(0) <= C2_ena_state OR C3_ena_state;
+	PROCESS (clock)
+	BEGIN
+		IF (clock = '1' AND clock'event) THEN C3_data_state <= (C3_ena_state OR (C3_data_state AND wire_w_lg_rotate_width_counter_done1796w(0)));
+		END IF;
+	END PROCESS;
+	PROCESS (clock)
+	BEGIN
+		IF (clock = '1' AND clock'event) THEN C3_ena_state <= (C4_data_state AND rotate_width_counter_done);
+		END IF;
+	END PROCESS;
+	PROCESS (clock)
+	BEGIN
+		IF (clock = '1' AND clock'event) THEN C4_data_state <= (C4_ena_state OR (C4_data_state AND wire_w_lg_rotate_width_counter_done1796w(0)));
+		END IF;
+	END PROCESS;
+	PROCESS (clock)
+	BEGIN
+		IF (clock = '1' AND clock'event) THEN C4_ena_state <= reconfig_init_state;
+		END IF;
+	END PROCESS;
+	PROCESS (clock)
+	BEGIN
+		IF (clock = '1' AND clock'event) THEN configupdate2_state <= configupdate_state;
+		END IF;
+	END PROCESS;
+	PROCESS (clock)
+	BEGIN
+		IF (clock = '0' AND clock'event) THEN configupdate3_state <= configupdate2_state;
+		END IF;
+	END PROCESS;
+	wire_configupdate3_state_w_lg_q1879w(0) <= NOT configupdate3_state;
+	PROCESS (clock)
+	BEGIN
+		IF (clock = '1' AND clock'event) THEN configupdate_state <= reconfig_post_state;
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN counter_param_latch_reg <= (OTHERS => '0');
+		ELSIF (clock = '1' AND clock'event) THEN 
+			IF (input_latch_enable = '1') THEN counter_param_latch_reg <= counter_param;
+			END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN counter_type_latch_reg <= (OTHERS => '0');
+		ELSIF (clock = '1' AND clock'event) THEN 
+			IF (input_latch_enable = '1') THEN counter_type_latch_reg <= counter_type;
+			END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN idle_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN idle_state <= (((((wire_idle_state_w_lg_w_lg_w_lg_w1747w1748w1749w1750w(0) OR (reconfig_wait_state AND reconfig_done)) OR ((rom_data_state AND rom_width_counter_done) AND wire_w_lg_reset_rom_address1752w(0))) OR wire_rom_second_last_state_w_lg_q1754w(0)) OR wire_rom_last_state_w_lg_q1753w(0)) OR reset_state);
+		END IF;
+	END PROCESS;
+	wire_idle_state_w_lg_w_lg_w_lg_w_lg_q1743w1744w1745w1746w(0) <= wire_idle_state_w_lg_w_lg_w_lg_q1743w1744w1745w(0) AND wire_w_lg_write_from_rom1739w(0);
+	wire_idle_state_w_lg_w_lg_w_lg_q1743w1744w1745w(0) <= wire_idle_state_w_lg_w_lg_q1743w1744w(0) AND wire_w_lg_reconfig1740w(0);
+	wire_idle_state_w_lg_w_lg_q1743w1744w(0) <= wire_idle_state_w_lg_q1743w(0) AND wire_w_lg_write_param1741w(0);
+	wire_idle_state_w_lg_q1743w(0) <= idle_state AND wire_w_lg_read_param1742w(0);
+	wire_idle_state_w_lg_q1672w(0) <= NOT idle_state;
+	wire_idle_state_w1747w(0) <= wire_idle_state_w_lg_w_lg_w_lg_w_lg_q1743w1744w1745w1746w(0) OR read_last_state;
+	wire_idle_state_w_lg_w1747w1748w(0) <= wire_idle_state_w1747w(0) OR wire_write_data_state_w_lg_q1738w(0);
+	wire_idle_state_w_lg_w_lg_w1747w1748w1749w(0) <= wire_idle_state_w_lg_w1747w1748w(0) OR wire_write_nominal_state_w_lg_q1737w(0);
+	wire_idle_state_w_lg_w_lg_w_lg_w1747w1748w1749w1750w(0) <= wire_idle_state_w_lg_w_lg_w1747w1748w1749w(0) OR read_last_nominal_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN nominal_data0 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN nominal_data0 <= wire_add_sub6_result(0);
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN nominal_data1 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN nominal_data1 <= wire_add_sub6_result(1);
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN nominal_data2 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN nominal_data2 <= wire_add_sub6_result(2);
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN nominal_data3 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN nominal_data3 <= wire_add_sub6_result(3);
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN nominal_data4 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN nominal_data4 <= wire_add_sub6_result(4);
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN nominal_data5 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN nominal_data5 <= wire_add_sub6_result(5);
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN nominal_data6 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN nominal_data6 <= wire_add_sub6_result(6);
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN nominal_data7 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN nominal_data7 <= wire_add_sub6_result(7);
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN nominal_data8 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN nominal_data8 <= wire_w_data_in_range186w(0);
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN nominal_data9 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN nominal_data9 <= wire_w_data_in_range178w(0);
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN nominal_data10 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN nominal_data10 <= wire_w_data_in_range170w(0);
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN nominal_data11 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN nominal_data11 <= wire_w_data_in_range162w(0);
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN nominal_data12 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN nominal_data12 <= wire_w_data_in_range154w(0);
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN nominal_data13 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN nominal_data13 <= wire_w_data_in_range146w(0);
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN nominal_data14 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN nominal_data14 <= wire_w_data_in_range138w(0);
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN nominal_data15 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN nominal_data15 <= wire_w_data_in_range130w(0);
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN nominal_data16 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN nominal_data16 <= wire_w_data_in_range122w(0);
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN nominal_data17 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN nominal_data17 <= wire_cmpr7_aeb;
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN read_data_nominal_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN read_data_nominal_state <= (wire_read_first_nominal_state_w_lg_q1773w(0) OR wire_read_data_nominal_state_w_lg_q1772w(0));
+		END IF;
+	END PROCESS;
+	wire_read_data_nominal_state_w_lg_q1772w(0) <= read_data_nominal_state AND wire_w_lg_width_counter_done1764w(0);
+	wire_read_data_nominal_state_w_lg_q1686w(0) <= NOT read_data_nominal_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN read_data_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN read_data_state <= (wire_read_first_state_w_lg_q1766w(0) OR wire_read_data_state_w_lg_q1765w(0));
+		END IF;
+	END PROCESS;
+	wire_read_data_state_w_lg_q1765w(0) <= read_data_state AND wire_w_lg_width_counter_done1764w(0);
+	wire_read_data_state_w_lg_q1678w(0) <= NOT read_data_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN read_first_nominal_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN read_first_nominal_state <= read_init_nominal_state;
+		END IF;
+	END PROCESS;
+	wire_read_first_nominal_state_w_lg_q1773w(0) <= read_first_nominal_state AND wire_w_lg_width_counter_done1764w(0);
+	wire_read_first_nominal_state_w_lg_q1684w(0) <= NOT read_first_nominal_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN read_first_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN read_first_state <= read_init_state;
+		END IF;
+	END PROCESS;
+	wire_read_first_state_w_lg_q1766w(0) <= read_first_state AND wire_w_lg_width_counter_done1764w(0);
+	wire_read_first_state_w_lg_q1676w(0) <= NOT read_first_state;
+	wire_read_first_state_w_lg_w_lg_w_lg_q1894w1895w1896w(0) <= wire_read_first_state_w_lg_w_lg_q1894w1895w(0) OR read_data_nominal_state;
+	wire_read_first_state_w_lg_w_lg_q1894w1895w(0) <= wire_read_first_state_w_lg_q1894w(0) OR read_first_nominal_state;
+	wire_read_first_state_w_lg_q1894w(0) <= read_first_state OR read_data_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN read_init_nominal_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN read_init_nominal_state <= ((idle_state AND read_param) AND ((((((NOT counter_type(3)) AND (NOT counter_type(2))) AND (NOT counter_type(1))) AND counter_param(2)) AND counter_param(1)) AND counter_param(0)));
+		END IF;
+	END PROCESS;
+	wire_read_init_nominal_state_w_lg_q1682w(0) <= NOT read_init_nominal_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN read_init_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN read_init_state <= ((idle_state AND read_param) AND (NOT ((((((NOT counter_type(3)) AND (NOT counter_type(2))) AND (NOT counter_type(1))) AND counter_param(2)) AND counter_param(1)) AND counter_param(0))));
+		END IF;
+	END PROCESS;
+	wire_read_init_state_w_lg_q1674w(0) <= NOT read_init_state;
+	wire_read_init_state_w_lg_q1891w(0) <= read_init_state OR read_init_nominal_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN read_last_nominal_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN read_last_nominal_state <= ((read_first_nominal_state AND width_counter_done) OR (read_data_nominal_state AND width_counter_done));
+		END IF;
+	END PROCESS;
+	wire_read_last_nominal_state_w_lg_q1917w(0) <= read_last_nominal_state AND wire_idle_state_w_lg_q1672w(0);
+	wire_read_last_nominal_state_w_lg_q1688w(0) <= NOT read_last_nominal_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN read_last_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN read_last_state <= ((read_first_state AND width_counter_done) OR (read_data_state AND width_counter_done));
+		END IF;
+	END PROCESS;
+	wire_read_last_state_w_lg_q1680w(0) <= NOT read_last_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN reconfig_counter_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN reconfig_counter_state <= ((((((((((reconfig_init_state OR C0_data_state) OR C1_data_state) OR C2_data_state) OR C3_data_state) OR C4_data_state) OR C0_ena_state) OR C1_ena_state) OR C2_ena_state) OR C3_ena_state) OR C4_ena_state);
+		END IF;
+	END PROCESS;
+	wire_reconfig_counter_state_w_lg_q1700w(0) <= NOT reconfig_counter_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN reconfig_init_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN reconfig_init_state <= (idle_state AND reconfig);
+		END IF;
+	END PROCESS;
+	wire_reconfig_init_state_w_lg_q1698w(0) <= NOT reconfig_init_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN reconfig_post_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN reconfig_post_state <= ((reconfig_seq_data_state AND reconfig_width_counter_done) OR wire_reconfig_post_state_w_lg_q1849w(0));
+		END IF;
+	END PROCESS;
+	wire_reconfig_post_state_w_lg_q1849w(0) <= reconfig_post_state AND wire_w_lg_reconfig_post_done1848w(0);
+	wire_reconfig_post_state_w_lg_q1706w(0) <= NOT reconfig_post_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN reconfig_seq_data_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN reconfig_seq_data_state <= (reconfig_seq_ena_state OR (reconfig_seq_data_state AND wire_w_lg_reconfig_width_counter_done1845w(0)));
+		END IF;
+	END PROCESS;
+	wire_reconfig_seq_data_state_w_lg_q1704w(0) <= NOT reconfig_seq_data_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN reconfig_seq_ena_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN reconfig_seq_ena_state <= tmp_seq_ena_state;
+		END IF;
+	END PROCESS;
+	loop14 : FOR i IN 0 TO 7 GENERATE 
+		wire_reconfig_seq_ena_state_w_lg_q1903w(i) <= reconfig_seq_ena_state AND seq_addr_wire(i);
+	END GENERATE loop14;
+	loop15 : FOR i IN 0 TO 5 GENERATE 
+		wire_reconfig_seq_ena_state_w_lg_q1904w(i) <= reconfig_seq_ena_state AND seq_sload_value(i);
+	END GENERATE loop15;
+	wire_reconfig_seq_ena_state_w_lg_q1702w(0) <= NOT reconfig_seq_ena_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN reconfig_wait_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN reconfig_wait_state <= ((reconfig_post_state AND reconfig_post_done) OR wire_reconfig_wait_state_w_lg_q1853w(0));
+		END IF;
+	END PROCESS;
+	wire_reconfig_wait_state_w_lg_q1853w(0) <= reconfig_wait_state AND wire_w_lg_reconfig_done1852w(0);
+	wire_reconfig_wait_state_w_lg_q1708w(0) <= NOT reconfig_wait_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN reset_state <= '1';
+		ELSIF (clock = '1' AND clock'event) THEN reset_state <= power_up;
+		END IF;
+	END PROCESS;
+	wire_reset_state_w_lg_q1671w(0) <= NOT reset_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN rom_data_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN rom_data_state <= (rom_second_state OR (wire_rom_data_state_w_lg_q1868w(0) AND wire_w_lg_reset_rom_address1752w(0)));
+		END IF;
+	END PROCESS;
+	wire_rom_data_state_w_lg_q1868w(0) <= rom_data_state AND wire_w_lg_read_addr_counter_done1867w(0);
+	wire_rom_data_state_w_lg_q1889w(0) <= rom_data_state AND wire_w_lg_rom_width_counter_done1888w(0);
+	wire_rom_data_state_w_lg_w_lg_q1897w1933w(0) <= NOT wire_rom_data_state_w_lg_q1897w(0);
+	wire_rom_data_state_w_lg_q1716w(0) <= NOT rom_data_state;
+	wire_rom_data_state_w_lg_w_lg_q1897w1898w(0) <= wire_rom_data_state_w_lg_q1897w(0) OR rom_second_state;
+	wire_rom_data_state_w_lg_w_lg_q1929w1930w(0) <= wire_rom_data_state_w_lg_q1929w(0) OR rom_last_state;
+	wire_rom_data_state_w_lg_q1897w(0) <= rom_data_state OR rom_first_state;
+	wire_rom_data_state_w_lg_q1929w(0) <= rom_data_state OR rom_second_last_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN rom_first_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN rom_first_state <= rom_init_state;
+		END IF;
+	END PROCESS;
+	wire_rom_first_state_w_lg_w_lg_w_lg_w_lg_q1943w1944w1945w1947w(0) <= NOT wire_rom_first_state_w_lg_w_lg_w_lg_q1943w1944w1945w(0);
+	wire_rom_first_state_w_lg_q1712w(0) <= NOT rom_first_state;
+	wire_rom_first_state_w_lg_w_lg_w_lg_q1943w1944w1945w(0) <= wire_rom_first_state_w_lg_w_lg_q1943w1944w(0) OR rom_last_state;
+	wire_rom_first_state_w_lg_w_lg_q1943w1944w(0) <= wire_rom_first_state_w_lg_q1943w(0) OR rom_second_last_state;
+	wire_rom_first_state_w_lg_w_lg_q1885w1886w(0) <= wire_rom_first_state_w_lg_q1885w(0) OR rom_data_state;
+	wire_rom_first_state_w_lg_q1943w(0) <= rom_first_state OR rom_data_state;
+	wire_rom_first_state_w_lg_q1885w(0) <= rom_first_state OR rom_second_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN rom_init_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN rom_init_state <= (((((idle_state AND write_from_rom) OR (rom_first_state AND reset_rom_address)) OR (rom_second_state AND reset_rom_address)) OR (rom_data_state AND reset_rom_address)) OR (rom_second_last_state AND reset_rom_address));
+		END IF;
+	END PROCESS;
+	wire_rom_init_state_w_lg_q1710w(0) <= NOT rom_init_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN rom_last_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN rom_last_state <= wire_rom_second_last_state_w_lg_q1754w(0);
+		END IF;
+	END PROCESS;
+	wire_rom_last_state_w_lg_q1753w(0) <= rom_last_state AND wire_w_lg_reset_rom_address1752w(0);
+	wire_rom_last_state_w_lg_q1720w(0) <= NOT rom_last_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN rom_second_last_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN rom_second_last_state <= ((rom_data_state AND read_addr_counter_done) AND wire_w_lg_reset_rom_address1752w(0));
+		END IF;
+	END PROCESS;
+	wire_rom_second_last_state_w_lg_q1754w(0) <= rom_second_last_state AND wire_w_lg_reset_rom_address1752w(0);
+	wire_rom_second_last_state_w_lg_q1718w(0) <= NOT rom_second_last_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN rom_second_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN rom_second_state <= (rom_first_state AND wire_w_lg_reset_rom_address1752w(0));
+		END IF;
+	END PROCESS;
+	wire_rom_second_state_w_lg_q1714w(0) <= NOT rom_second_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN shift_reg0 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN 
+			IF (wire_shift_reg_ena(0) = '1') THEN 
+				IF (shift_reg_clear = '1') THEN shift_reg0 <= '0';
+				ELSE shift_reg0 <= ((((shift_reg_load_nominal_enable AND nominal_data17) OR (shift_reg_load_enable AND w64w)) OR (shift_reg_shift_enable AND shift_reg_serial_in)) OR (shift_reg_shift_nominal_enable AND shift_reg_serial_in));
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	wire_shift_reg_w_lg_q217w(0) <= shift_reg0 AND wire_w_lg_read_nominal_out216w(0);
+	wire_shift_reg_w_lg_w_lg_q217w218w(0) <= wire_shift_reg_w_lg_q217w(0) OR wire_add_sub5_w_lg_w_result_range214w215w(0);
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN shift_reg1 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN 
+			IF (wire_shift_reg_ena(1) = '1') THEN 
+				IF (shift_reg_clear = '1') THEN shift_reg1 <= '0';
+				ELSE shift_reg1 <= ((((shift_reg_load_nominal_enable AND nominal_data16) OR (shift_reg_load_enable AND w64w)) OR (shift_reg_shift_enable AND shift_reg0)) OR (shift_reg_shift_nominal_enable AND shift_reg0));
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	wire_shift_reg_w_lg_q223w(0) <= shift_reg1 AND wire_w_lg_read_nominal_out216w(0);
+	wire_shift_reg_w_lg_w_lg_q223w224w(0) <= wire_shift_reg_w_lg_q223w(0) OR wire_add_sub5_w_lg_w_result_range221w222w(0);
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN shift_reg2 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN 
+			IF (wire_shift_reg_ena(2) = '1') THEN 
+				IF (shift_reg_clear = '1') THEN shift_reg2 <= '0';
+				ELSE shift_reg2 <= ((((shift_reg_load_nominal_enable AND nominal_data15) OR (shift_reg_load_enable AND w64w)) OR (shift_reg_shift_enable AND shift_reg1)) OR (shift_reg_shift_nominal_enable AND shift_reg1));
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	wire_shift_reg_w_lg_q228w(0) <= shift_reg2 AND wire_w_lg_read_nominal_out216w(0);
+	wire_shift_reg_w_lg_w_lg_q228w229w(0) <= wire_shift_reg_w_lg_q228w(0) OR wire_add_sub5_w_lg_w_result_range226w227w(0);
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN shift_reg3 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN 
+			IF (wire_shift_reg_ena(3) = '1') THEN 
+				IF (shift_reg_clear = '1') THEN shift_reg3 <= '0';
+				ELSE shift_reg3 <= ((((shift_reg_load_nominal_enable AND nominal_data14) OR (shift_reg_load_enable AND w64w)) OR (shift_reg_shift_enable AND shift_reg2)) OR (shift_reg_shift_nominal_enable AND shift_reg2));
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	wire_shift_reg_w_lg_q233w(0) <= shift_reg3 AND wire_w_lg_read_nominal_out216w(0);
+	wire_shift_reg_w_lg_w_lg_q233w234w(0) <= wire_shift_reg_w_lg_q233w(0) OR wire_add_sub5_w_lg_w_result_range231w232w(0);
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN shift_reg4 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN 
+			IF (wire_shift_reg_ena(4) = '1') THEN 
+				IF (shift_reg_clear = '1') THEN shift_reg4 <= '0';
+				ELSE shift_reg4 <= ((((shift_reg_load_nominal_enable AND nominal_data13) OR (shift_reg_load_enable AND w64w)) OR (shift_reg_shift_enable AND shift_reg3)) OR (shift_reg_shift_nominal_enable AND shift_reg3));
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	wire_shift_reg_w_lg_q238w(0) <= shift_reg4 AND wire_w_lg_read_nominal_out216w(0);
+	wire_shift_reg_w_lg_w_lg_q238w239w(0) <= wire_shift_reg_w_lg_q238w(0) OR wire_add_sub5_w_lg_w_result_range236w237w(0);
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN shift_reg5 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN 
+			IF (wire_shift_reg_ena(5) = '1') THEN 
+				IF (shift_reg_clear = '1') THEN shift_reg5 <= '0';
+				ELSE shift_reg5 <= ((((shift_reg_load_nominal_enable AND nominal_data12) OR (shift_reg_load_enable AND w64w)) OR (shift_reg_shift_enable AND shift_reg4)) OR (shift_reg_shift_nominal_enable AND shift_reg4));
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	wire_shift_reg_w_lg_q243w(0) <= shift_reg5 AND wire_w_lg_read_nominal_out216w(0);
+	wire_shift_reg_w_lg_w_lg_q243w244w(0) <= wire_shift_reg_w_lg_q243w(0) OR wire_add_sub5_w_lg_w_result_range241w242w(0);
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN shift_reg6 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN 
+			IF (wire_shift_reg_ena(6) = '1') THEN 
+				IF (shift_reg_clear = '1') THEN shift_reg6 <= '0';
+				ELSE shift_reg6 <= ((((shift_reg_load_nominal_enable AND nominal_data11) OR (shift_reg_load_enable AND w64w)) OR (shift_reg_shift_enable AND shift_reg5)) OR (shift_reg_shift_nominal_enable AND shift_reg5));
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	wire_shift_reg_w_lg_q248w(0) <= shift_reg6 AND wire_w_lg_read_nominal_out216w(0);
+	wire_shift_reg_w_lg_w_lg_q248w249w(0) <= wire_shift_reg_w_lg_q248w(0) OR wire_add_sub5_w_lg_w_result_range246w247w(0);
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN shift_reg7 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN 
+			IF (wire_shift_reg_ena(7) = '1') THEN 
+				IF (shift_reg_clear = '1') THEN shift_reg7 <= '0';
+				ELSE shift_reg7 <= ((((shift_reg_load_nominal_enable AND nominal_data10) OR (shift_reg_load_enable AND w64w)) OR (shift_reg_shift_enable AND shift_reg6)) OR (shift_reg_shift_nominal_enable AND shift_reg6));
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	wire_shift_reg_w_lg_q253w(0) <= shift_reg7 AND wire_w_lg_read_nominal_out216w(0);
+	wire_shift_reg_w_lg_w_lg_q253w254w(0) <= wire_shift_reg_w_lg_q253w(0) OR wire_add_sub5_w_lg_w_result_range251w252w(0);
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN shift_reg8 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN 
+			IF (wire_shift_reg_ena(8) = '1') THEN 
+				IF (shift_reg_clear = '1') THEN shift_reg8 <= '0';
+				ELSE shift_reg8 <= ((((shift_reg_load_nominal_enable AND nominal_data9) OR (shift_reg_load_enable AND w64w)) OR (shift_reg_shift_enable AND shift_reg7)) OR (shift_reg_shift_nominal_enable AND shift_reg7));
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	wire_shift_reg_w_lg_q258w(0) <= shift_reg8 AND wire_w_lg_read_nominal_out216w(0);
+	wire_shift_reg_w_lg_w_lg_q258w259w(0) <= wire_shift_reg_w_lg_q258w(0) OR wire_add_sub5_w_lg_w_result_range256w257w(0);
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN shift_reg9 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN 
+			IF (wire_shift_reg_ena(9) = '1') THEN 
+				IF (shift_reg_clear = '1') THEN shift_reg9 <= '0';
+				ELSE shift_reg9 <= ((((shift_reg_load_nominal_enable AND nominal_data8) OR wire_w_lg_shift_reg_load_enable123w(0)) OR (shift_reg_shift_enable AND shift_reg8)) OR (shift_reg_shift_nominal_enable AND shift_reg8));
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN shift_reg10 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN 
+			IF (wire_shift_reg_ena(10) = '1') THEN 
+				IF (shift_reg_clear = '1') THEN shift_reg10 <= '0';
+				ELSE shift_reg10 <= ((((shift_reg_load_nominal_enable AND nominal_data7) OR wire_w_lg_shift_reg_load_enable131w(0)) OR (shift_reg_shift_enable AND shift_reg9)) OR (shift_reg_shift_nominal_enable AND shift_reg9));
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN shift_reg11 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN 
+			IF (wire_shift_reg_ena(11) = '1') THEN 
+				IF (shift_reg_clear = '1') THEN shift_reg11 <= '0';
+				ELSE shift_reg11 <= ((((shift_reg_load_nominal_enable AND nominal_data6) OR wire_w_lg_shift_reg_load_enable139w(0)) OR (shift_reg_shift_enable AND shift_reg10)) OR (shift_reg_shift_nominal_enable AND shift_reg10));
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN shift_reg12 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN 
+			IF (wire_shift_reg_ena(12) = '1') THEN 
+				IF (shift_reg_clear = '1') THEN shift_reg12 <= '0';
+				ELSE shift_reg12 <= ((((shift_reg_load_nominal_enable AND nominal_data5) OR wire_w_lg_shift_reg_load_enable147w(0)) OR (shift_reg_shift_enable AND shift_reg11)) OR (shift_reg_shift_nominal_enable AND shift_reg11));
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN shift_reg13 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN 
+			IF (wire_shift_reg_ena(13) = '1') THEN 
+				IF (shift_reg_clear = '1') THEN shift_reg13 <= '0';
+				ELSE shift_reg13 <= ((((shift_reg_load_nominal_enable AND nominal_data4) OR wire_w_lg_shift_reg_load_enable155w(0)) OR (shift_reg_shift_enable AND shift_reg12)) OR (shift_reg_shift_nominal_enable AND shift_reg12));
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN shift_reg14 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN 
+			IF (wire_shift_reg_ena(14) = '1') THEN 
+				IF (shift_reg_clear = '1') THEN shift_reg14 <= '0';
+				ELSE shift_reg14 <= ((((shift_reg_load_nominal_enable AND nominal_data3) OR wire_w_lg_shift_reg_load_enable163w(0)) OR (shift_reg_shift_enable AND shift_reg13)) OR (shift_reg_shift_nominal_enable AND shift_reg13));
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN shift_reg15 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN 
+			IF (wire_shift_reg_ena(15) = '1') THEN 
+				IF (shift_reg_clear = '1') THEN shift_reg15 <= '0';
+				ELSE shift_reg15 <= ((((shift_reg_load_nominal_enable AND nominal_data2) OR wire_w_lg_shift_reg_load_enable171w(0)) OR (shift_reg_shift_enable AND shift_reg14)) OR (shift_reg_shift_nominal_enable AND shift_reg14));
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN shift_reg16 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN 
+			IF (wire_shift_reg_ena(16) = '1') THEN 
+				IF (shift_reg_clear = '1') THEN shift_reg16 <= '0';
+				ELSE shift_reg16 <= ((((shift_reg_load_nominal_enable AND nominal_data1) OR wire_w_lg_shift_reg_load_enable179w(0)) OR (shift_reg_shift_enable AND shift_reg15)) OR (shift_reg_shift_nominal_enable AND shift_reg15));
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN shift_reg17 <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN 
+			IF (wire_shift_reg_ena(17) = '1') THEN 
+				IF (shift_reg_clear = '1') THEN shift_reg17 <= '0';
+				ELSE shift_reg17 <= ((((shift_reg_load_nominal_enable AND nominal_data0) OR wire_w_lg_shift_reg_load_enable187w(0)) OR (shift_reg_shift_enable AND shift_reg16)) OR (shift_reg_shift_nominal_enable AND shift_reg16));
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+	wire_shift_reg_w_lg_q262w(0) <= shift_reg17 AND wire_w_shift_reg_width_select_range261w(0);
+	wire_shift_reg_w_lg_q264w(0) <= shift_reg17 AND wire_w_shift_reg_width_select_range263w(0);
+	wire_shift_reg_w_lg_q267w(0) <= shift_reg17 AND wire_w_shift_reg_width_select_range266w(0);
+	wire_shift_reg_w_lg_q270w(0) <= shift_reg17 AND wire_w_shift_reg_width_select_range269w(0);
+	wire_shift_reg_w_lg_q273w(0) <= shift_reg17 AND wire_w_shift_reg_width_select_range272w(0);
+	wire_shift_reg_w_lg_q276w(0) <= shift_reg17 AND wire_w_shift_reg_width_select_range275w(0);
+	wire_shift_reg_w_lg_q279w(0) <= shift_reg17 AND wire_w_shift_reg_width_select_range278w(0);
+	wire_shift_reg_w_lg_q282w(0) <= shift_reg17 AND wire_w_shift_reg_width_select_range281w(0);
+	loop16 : FOR i IN 0 TO 17 GENERATE
+		wire_shift_reg_ena(i) <= wire_w63w(0);
+	END GENERATE loop16;
+	PROCESS (clock)
+	BEGIN
+		IF (clock = '1' AND clock'event) THEN tmp_nominal_data_out_state <= (wire_read_last_nominal_state_w_lg_q1917w(0) OR (tmp_nominal_data_out_state AND idle_state));
+		END IF;
+	END PROCESS;
+	PROCESS (clock)
+	BEGIN
+		IF (clock = '1' AND clock'event) THEN tmp_seq_ena_state <= (reconfig_counter_state AND (C0_data_state AND rotate_width_counter_done));
+		END IF;
+	END PROCESS;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN write_data_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN write_data_state <= (write_init_state OR (write_data_state AND wire_w_lg_width_counter_done1764w(0)));
+		END IF;
+	END PROCESS;
+	wire_write_data_state_w_lg_q1738w(0) <= write_data_state AND width_counter_done;
+	wire_write_data_state_w_lg_q1692w(0) <= NOT write_data_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN write_init_nominal_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN write_init_nominal_state <= ((idle_state AND write_param) AND ((((((NOT counter_type(3)) AND (NOT counter_type(2))) AND (NOT counter_type(1))) AND counter_param(2)) AND counter_param(1)) AND counter_param(0)));
+		END IF;
+	END PROCESS;
+	wire_write_init_nominal_state_w_lg_q1694w(0) <= NOT write_init_nominal_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN write_init_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN write_init_state <= ((idle_state AND write_param) AND (NOT ((((((NOT counter_type(3)) AND (NOT counter_type(2))) AND (NOT counter_type(1))) AND counter_param(2)) AND counter_param(1)) AND counter_param(0))));
+		END IF;
+	END PROCESS;
+	wire_write_init_state_w_lg_q1690w(0) <= NOT write_init_state;
+	wire_write_init_state_w_lg_q1900w(0) <= write_init_state OR write_init_nominal_state;
+	PROCESS (clock, reset)
+	BEGIN
+		IF (reset = '1') THEN write_nominal_state <= '0';
+		ELSIF (clock = '1' AND clock'event) THEN write_nominal_state <= (write_init_nominal_state OR (write_nominal_state AND wire_w_lg_width_counter_done1764w(0)));
+		END IF;
+	END PROCESS;
+	wire_write_nominal_state_w_lg_q1737w(0) <= write_nominal_state AND width_counter_done;
+	wire_write_nominal_state_w_lg_q1696w(0) <= NOT write_nominal_state;
+	wire_add_sub5_w_lg_w_result_range214w215w(0) <= wire_add_sub5_w_result_range214w(0) AND read_nominal_out;
+	wire_add_sub5_w_lg_w_result_range221w222w(0) <= wire_add_sub5_w_result_range221w(0) AND read_nominal_out;
+	wire_add_sub5_w_lg_w_result_range226w227w(0) <= wire_add_sub5_w_result_range226w(0) AND read_nominal_out;
+	wire_add_sub5_w_lg_w_result_range231w232w(0) <= wire_add_sub5_w_result_range231w(0) AND read_nominal_out;
+	wire_add_sub5_w_lg_w_result_range236w237w(0) <= wire_add_sub5_w_result_range236w(0) AND read_nominal_out;
+	wire_add_sub5_w_lg_w_result_range241w242w(0) <= wire_add_sub5_w_result_range241w(0) AND read_nominal_out;
+	wire_add_sub5_w_lg_w_result_range246w247w(0) <= wire_add_sub5_w_result_range246w(0) AND read_nominal_out;
+	wire_add_sub5_w_lg_w_result_range251w252w(0) <= wire_add_sub5_w_result_range251w(0) AND read_nominal_out;
+	wire_add_sub5_w_lg_w_result_range256w257w(0) <= wire_add_sub5_w_result_range256w(0) AND read_nominal_out;
+	wire_add_sub5_dataa <= ( "0" & shift_reg8 & shift_reg7 & shift_reg6 & shift_reg5 & shift_reg4 & shift_reg3 & shift_reg2 & shift_reg1);
+	wire_add_sub5_datab <= ( "0" & shift_reg17 & shift_reg16 & shift_reg15 & shift_reg14 & shift_reg13 & shift_reg12 & shift_reg11 & shift_reg10);
+	wire_add_sub5_w_result_range214w(0) <= wire_add_sub5_result(0);
+	wire_add_sub5_w_result_range221w(0) <= wire_add_sub5_result(1);
+	wire_add_sub5_w_result_range226w(0) <= wire_add_sub5_result(2);
+	wire_add_sub5_w_result_range231w(0) <= wire_add_sub5_result(3);
+	wire_add_sub5_w_result_range236w(0) <= wire_add_sub5_result(4);
+	wire_add_sub5_w_result_range241w(0) <= wire_add_sub5_result(5);
+	wire_add_sub5_w_result_range246w(0) <= wire_add_sub5_result(6);
+	wire_add_sub5_w_result_range251w(0) <= wire_add_sub5_result(7);
+	wire_add_sub5_w_result_range256w(0) <= wire_add_sub5_result(8);
+	add_sub5 :  lpm_add_sub
+	  GENERIC MAP (
+		LPM_WIDTH => 9
+	  )
+	  PORT MAP ( 
+		cin => wire_gnd,
+		dataa => wire_add_sub5_dataa,
+		datab => wire_add_sub5_datab,
+		result => wire_add_sub5_result
+	  );
+	wire_add_sub6_dataa <= ( data_in(8 DOWNTO 1));
+	add_sub6 :  lpm_add_sub
+	  GENERIC MAP (
+		LPM_WIDTH => 8
+	  )
+	  PORT MAP ( 
+		cin => data_in(0),
+		dataa => wire_add_sub6_dataa,
+		result => wire_add_sub6_result
+	  );
+	wire_cmpr7_dataa <= ( data_in(7 DOWNTO 0));
+	wire_cmpr7_datab <= "00000001";
+	cmpr7 :  lpm_compare
+	  GENERIC MAP (
+		LPM_WIDTH => 8
+	  )
+	  PORT MAP ( 
+		aeb => wire_cmpr7_aeb,
+		dataa => wire_cmpr7_dataa,
+		datab => wire_cmpr7_datab
+	  );
+	cntr1 :  lpm_counter
+	  GENERIC MAP (
+		lpm_direction => "DOWN",
+		lpm_modulus => 144,
+		lpm_port_updown => "PORT_UNUSED",
+		lpm_width => 8
+	  )
+	  PORT MAP ( 
+		clock => clock,
+		cnt_en => addr_counter_enable,
+		data => addr_counter_sload_value,
+		q => wire_cntr1_q,
+		sload => addr_counter_sload
+	  );
+	cntr12 :  lpm_counter
+	  GENERIC MAP (
+		lpm_direction => "DOWN",
+		lpm_modulus => 144,
+		lpm_port_updown => "PORT_UNUSED",
+		lpm_width => 8
+	  )
+	  PORT MAP ( 
+		clock => clock,
+		cnt_en => reconfig_addr_counter_enable,
+		data => reconfig_addr_counter_sload_value,
+		q => wire_cntr12_q,
+		sload => reconfig_addr_counter_sload
+	  );
+	cntr13 :  lpm_counter
+	  GENERIC MAP (
+		lpm_direction => "DOWN",
+		lpm_port_updown => "PORT_UNUSED",
+		lpm_width => 6
+	  )
+	  PORT MAP ( 
+		clock => clock,
+		cnt_en => reconfig_width_counter_enable,
+		data => reconfig_width_counter_sload_value,
+		q => wire_cntr13_q,
+		sload => reconfig_width_counter_sload
+	  );
+	cntr14 :  lpm_counter
+	  GENERIC MAP (
+		lpm_direction => "DOWN",
+		lpm_port_updown => "PORT_UNUSED",
+		lpm_width => 8
+	  )
+	  PORT MAP ( 
+		clock => clock,
+		cnt_en => rom_width_counter_enable,
+		data => rom_width_counter_sload_value,
+		q => wire_cntr14_q,
+		sload => rom_width_counter_sload
+	  );
+	cntr15 :  lpm_counter
+	  GENERIC MAP (
+		lpm_direction => "DOWN",
+		lpm_port_updown => "PORT_UNUSED",
+		lpm_width => 5
+	  )
+	  PORT MAP ( 
+		clock => clock,
+		cnt_en => rotate_width_counter_enable,
+		data => rotate_width_counter_sload_value,
+		q => wire_cntr15_q,
+		sload => rotate_width_counter_sload
+	  );
+	cntr16 :  lpm_counter
+	  GENERIC MAP (
+		lpm_direction => "DOWN",
+		lpm_modulus => 144,
+		lpm_port_updown => "PORT_UNUSED",
+		lpm_width => 8
+	  )
+	  PORT MAP ( 
+		clock => clock,
+		cnt_en => rotate_addr_counter_enable,
+		data => rotate_addr_counter_sload_value,
+		q => wire_cntr16_q,
+		sload => rotate_addr_counter_sload
+	  );
+	cntr2 :  lpm_counter
+	  GENERIC MAP (
+		lpm_direction => "UP",
+		lpm_port_updown => "PORT_UNUSED",
+		lpm_width => 8
+	  )
+	  PORT MAP ( 
+		clock => clock,
+		cnt_en => read_addr_counter_enable,
+		data => read_addr_counter_sload_value,
+		q => wire_cntr2_q,
+		sload => read_addr_counter_sload
+	  );
+	cntr3 :  lpm_counter
+	  GENERIC MAP (
+		lpm_direction => "DOWN",
+		lpm_port_updown => "PORT_UNUSED",
+		lpm_width => 5
+	  )
+	  PORT MAP ( 
+		clock => clock,
+		cnt_en => width_counter_enable,
+		data => width_counter_sload_value,
+		q => wire_cntr3_q,
+		sload => width_counter_sload
+	  );
+	decode11 :  lpm_decode
+	  GENERIC MAP (
+		LPM_DECODES => 5,
+		LPM_WIDTH => 3
+	  )
+	  PORT MAP ( 
+		data => cuda_combout_wire,
+		eq => wire_decode11_eq
+	  );
+
+ END RTL; --pll_c64_reconfig_pllrcfg_fj11
+--VALID FILE
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+ENTITY pll_c64_reconfig IS
+	PORT
+	(
+		clock		: IN STD_LOGIC ;
+		counter_param		: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+		counter_type		: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+		data_in		: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+		pll_areset_in		: IN STD_LOGIC  := '0';
+		pll_scandataout		: IN STD_LOGIC ;
+		pll_scandone		: IN STD_LOGIC ;
+		read_param		: IN STD_LOGIC ;
+		reconfig		: IN STD_LOGIC ;
+		reset		: IN STD_LOGIC ;
+		reset_rom_address		: IN STD_LOGIC  := '0';
+		rom_data_in		: IN STD_LOGIC  := '0';
+		write_from_rom		: IN STD_LOGIC  := '0';
+		write_param		: IN STD_LOGIC ;
+		busy		: OUT STD_LOGIC ;
+		data_out		: OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
+		pll_areset		: OUT STD_LOGIC ;
+		pll_configupdate		: OUT STD_LOGIC ;
+		pll_scanclk		: OUT STD_LOGIC ;
+		pll_scanclkena		: OUT STD_LOGIC ;
+		pll_scandata		: OUT STD_LOGIC ;
+		rom_address_out		: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+		write_rom_ena		: OUT STD_LOGIC 
+	);
+END pll_c64_reconfig;
+
+
+ARCHITECTURE RTL OF pll_c64_reconfig IS
+
+	ATTRIBUTE synthesis_clearbox: natural;
+	ATTRIBUTE synthesis_clearbox OF RTL: ARCHITECTURE IS 2;
+	ATTRIBUTE clearbox_macroname: string;
+	ATTRIBUTE clearbox_macroname OF RTL: ARCHITECTURE IS "altpll_reconfig";
+	ATTRIBUTE clearbox_defparam: string;
+	ATTRIBUTE clearbox_defparam OF RTL: ARCHITECTURE IS "intended_device_family=Cyclone III;";
+	SIGNAL sub_wire0	: STD_LOGIC ;
+	SIGNAL sub_wire1	: STD_LOGIC_VECTOR (8 DOWNTO 0);
+	SIGNAL sub_wire2	: STD_LOGIC ;
+	SIGNAL sub_wire3	: STD_LOGIC ;
+	SIGNAL sub_wire4	: STD_LOGIC ;
+	SIGNAL sub_wire5	: STD_LOGIC_VECTOR (7 DOWNTO 0);
+	SIGNAL sub_wire6	: STD_LOGIC ;
+	SIGNAL sub_wire7	: STD_LOGIC ;
+	SIGNAL sub_wire8	: STD_LOGIC ;
+
+
+
+	COMPONENT pll_c64_reconfig_pllrcfg_fj11
+	PORT (
+			counter_param	: IN STD_LOGIC_VECTOR (2 DOWNTO 0);
+			data_in	: IN STD_LOGIC_VECTOR (8 DOWNTO 0);
+			pll_configupdate	: OUT STD_LOGIC ;
+			counter_type	: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
+			data_out	: OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
+			pll_areset_in	: IN STD_LOGIC ;
+			pll_scanclk	: OUT STD_LOGIC ;
+			pll_scanclkena	: OUT STD_LOGIC ;
+			pll_scandata	: OUT STD_LOGIC ;
+			pll_scandataout	: IN STD_LOGIC ;
+			pll_scandone	: IN STD_LOGIC ;
+			rom_address_out	: OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+			busy	: OUT STD_LOGIC ;
+			pll_areset	: OUT STD_LOGIC ;
+			reset	: IN STD_LOGIC ;
+			write_from_rom	: IN STD_LOGIC ;
+			write_param	: IN STD_LOGIC ;
+			write_rom_ena	: OUT STD_LOGIC ;
+			clock	: IN STD_LOGIC ;
+			read_param	: IN STD_LOGIC ;
+			reconfig	: IN STD_LOGIC ;
+			reset_rom_address	: IN STD_LOGIC ;
+			rom_data_in	: IN STD_LOGIC 
+	);
+	END COMPONENT;
+
+BEGIN
+	pll_configupdate    <= sub_wire0;
+	data_out    <= sub_wire1(8 DOWNTO 0);
+	pll_scanclk    <= sub_wire2;
+	pll_scanclkena    <= sub_wire3;
+	pll_scandata    <= sub_wire4;
+	rom_address_out    <= sub_wire5(7 DOWNTO 0);
+	busy    <= sub_wire6;
+	pll_areset    <= sub_wire7;
+	write_rom_ena    <= sub_wire8;
+
+	pll_c64_reconfig_pllrcfg_fj11_component : pll_c64_reconfig_pllrcfg_fj11
+	PORT MAP (
+		counter_param => counter_param,
+		data_in => data_in,
+		counter_type => counter_type,
+		pll_areset_in => pll_areset_in,
+		pll_scandataout => pll_scandataout,
+		pll_scandone => pll_scandone,
+		reset => reset,
+		write_from_rom => write_from_rom,
+		write_param => write_param,
+		clock => clock,
+		read_param => read_param,
+		reconfig => reconfig,
+		reset_rom_address => reset_rom_address,
+		rom_data_in => rom_data_in,
+		pll_configupdate => sub_wire0,
+		data_out => sub_wire1,
+		pll_scanclk => sub_wire2,
+		pll_scanclkena => sub_wire3,
+		pll_scandata => sub_wire4,
+		rom_address_out => sub_wire5,
+		busy => sub_wire6,
+		pll_areset => sub_wire7,
+		write_rom_ena => sub_wire8
+	);
+
+
+
+END RTL;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: CHAIN_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_NAME STRING ""
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: USE_INIT_FILE STRING "0"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
+-- Retrieval info: USED_PORT: counter_param 0 0 3 0 INPUT NODEFVAL "counter_param[2..0]"
+-- Retrieval info: USED_PORT: counter_type 0 0 4 0 INPUT NODEFVAL "counter_type[3..0]"
+-- Retrieval info: USED_PORT: data_in 0 0 9 0 INPUT NODEFVAL "data_in[8..0]"
+-- Retrieval info: USED_PORT: data_out 0 0 9 0 OUTPUT NODEFVAL "data_out[8..0]"
+-- Retrieval info: USED_PORT: pll_areset 0 0 0 0 OUTPUT NODEFVAL "pll_areset"
+-- Retrieval info: USED_PORT: pll_areset_in 0 0 0 0 INPUT GND "pll_areset_in"
+-- Retrieval info: USED_PORT: pll_configupdate 0 0 0 0 OUTPUT NODEFVAL "pll_configupdate"
+-- Retrieval info: USED_PORT: pll_scanclk 0 0 0 0 OUTPUT NODEFVAL "pll_scanclk"
+-- Retrieval info: USED_PORT: pll_scanclkena 0 0 0 0 OUTPUT NODEFVAL "pll_scanclkena"
+-- Retrieval info: USED_PORT: pll_scandata 0 0 0 0 OUTPUT NODEFVAL "pll_scandata"
+-- Retrieval info: USED_PORT: pll_scandataout 0 0 0 0 INPUT NODEFVAL "pll_scandataout"
+-- Retrieval info: USED_PORT: pll_scandone 0 0 0 0 INPUT NODEFVAL "pll_scandone"
+-- Retrieval info: USED_PORT: read_param 0 0 0 0 INPUT NODEFVAL "read_param"
+-- Retrieval info: USED_PORT: reconfig 0 0 0 0 INPUT NODEFVAL "reconfig"
+-- Retrieval info: USED_PORT: reset 0 0 0 0 INPUT NODEFVAL "reset"
+-- Retrieval info: USED_PORT: reset_rom_address 0 0 0 0 INPUT GND "reset_rom_address"
+-- Retrieval info: USED_PORT: rom_address_out 0 0 8 0 OUTPUT NODEFVAL "rom_address_out[7..0]"
+-- Retrieval info: USED_PORT: rom_data_in 0 0 0 0 INPUT GND "rom_data_in"
+-- Retrieval info: USED_PORT: write_from_rom 0 0 0 0 INPUT GND "write_from_rom"
+-- Retrieval info: USED_PORT: write_param 0 0 0 0 INPUT NODEFVAL "write_param"
+-- Retrieval info: USED_PORT: write_rom_ena 0 0 0 0 OUTPUT NODEFVAL "write_rom_ena"
+-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @counter_param 0 0 3 0 counter_param 0 0 3 0
+-- Retrieval info: CONNECT: @counter_type 0 0 4 0 counter_type 0 0 4 0
+-- Retrieval info: CONNECT: @data_in 0 0 9 0 data_in 0 0 9 0
+-- Retrieval info: CONNECT: @pll_areset_in 0 0 0 0 pll_areset_in 0 0 0 0
+-- Retrieval info: CONNECT: @pll_scandataout 0 0 0 0 pll_scandataout 0 0 0 0
+-- Retrieval info: CONNECT: @pll_scandone 0 0 0 0 pll_scandone 0 0 0 0
+-- Retrieval info: CONNECT: @read_param 0 0 0 0 read_param 0 0 0 0
+-- Retrieval info: CONNECT: @reconfig 0 0 0 0 reconfig 0 0 0 0
+-- Retrieval info: CONNECT: @reset 0 0 0 0 reset 0 0 0 0
+-- Retrieval info: CONNECT: @reset_rom_address 0 0 0 0 reset_rom_address 0 0 0 0
+-- Retrieval info: CONNECT: @rom_data_in 0 0 0 0 rom_data_in 0 0 0 0
+-- Retrieval info: CONNECT: @write_from_rom 0 0 0 0 write_from_rom 0 0 0 0
+-- Retrieval info: CONNECT: @write_param 0 0 0 0 write_param 0 0 0 0
+-- Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
+-- Retrieval info: CONNECT: data_out 0 0 9 0 @data_out 0 0 9 0
+-- Retrieval info: CONNECT: pll_areset 0 0 0 0 @pll_areset 0 0 0 0
+-- Retrieval info: CONNECT: pll_configupdate 0 0 0 0 @pll_configupdate 0 0 0 0
+-- Retrieval info: CONNECT: pll_scanclk 0 0 0 0 @pll_scanclk 0 0 0 0
+-- Retrieval info: CONNECT: pll_scanclkena 0 0 0 0 @pll_scanclkena 0 0 0 0
+-- Retrieval info: CONNECT: pll_scandata 0 0 0 0 @pll_scandata 0 0 0 0
+-- Retrieval info: CONNECT: rom_address_out 0 0 8 0 @rom_address_out 0 0 8 0
+-- Retrieval info: CONNECT: write_rom_ena 0 0 0 0 @write_rom_ena 0 0 0 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_c64_reconfig.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_c64_reconfig.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_c64_reconfig.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_c64_reconfig.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_c64_reconfig_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
+-- Retrieval info: LIB_FILE: cycloneiii
+-- Retrieval info: LIB_FILE: lpm
diff --git a/cores/c64/rtl/mist/rom_reconfig_ntsc.qip b/cores/c64/rtl/mist/rom_reconfig_ntsc.qip
new file mode 100644
index 0000000..e896f5b
--- /dev/null
+++ b/cores/c64/rtl/mist/rom_reconfig_ntsc.qip
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "rom_reconfig_ntsc.vhd"]
diff --git a/cores/c64/rtl/mist/rom_reconfig_ntsc.vhd b/cores/c64/rtl/mist/rom_reconfig_ntsc.vhd
new file mode 100644
index 0000000..2750ca2
--- /dev/null
+++ b/cores/c64/rtl/mist/rom_reconfig_ntsc.vhd
@@ -0,0 +1,147 @@
+-- megafunction wizard: %ROM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: rom_reconfig_ntsc.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY rom_reconfig_ntsc IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		rden		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
+	);
+END rom_reconfig_ntsc;
+
+
+ARCHITECTURE SYN OF rom_reconfig_ntsc IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+BEGIN
+	q    <= sub_wire0(0 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => "pll_c64_ntsc.mif",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 256,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "CLOCK0",
+		widthad_a => 8,
+		width_a => 1,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		rden_a => rden,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "pll_c64_ntsc.mif"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "1"
+-- Retrieval info: PRIVATE: rden NUMERIC "1"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "pll_c64_ntsc.mif"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "1"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
+-- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
+-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 1 0 @q_a 0 0 1 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_ntsc_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/cores/c64/rtl/mist/rom_reconfig_pal.qip b/cores/c64/rtl/mist/rom_reconfig_pal.qip
new file mode 100644
index 0000000..880b2f9
--- /dev/null
+++ b/cores/c64/rtl/mist/rom_reconfig_pal.qip
@@ -0,0 +1,3 @@
+set_global_assignment -name IP_TOOL_NAME "ROM: 1-PORT"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
+set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "rom_reconfig_pal.vhd"]
diff --git a/cores/c64/rtl/mist/rom_reconfig_pal.vhd b/cores/c64/rtl/mist/rom_reconfig_pal.vhd
new file mode 100644
index 0000000..d14d6ae
--- /dev/null
+++ b/cores/c64/rtl/mist/rom_reconfig_pal.vhd
@@ -0,0 +1,147 @@
+-- megafunction wizard: %ROM: 1-PORT%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altsyncram 
+
+-- ============================================================
+-- File Name: rom_reconfig_pal.vhd
+-- Megafunction Name(s):
+-- 			altsyncram
+--
+-- Simulation Library Files(s):
+-- 			altera_mf
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2014 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+
+LIBRARY ieee;
+USE ieee.std_logic_1164.all;
+
+LIBRARY altera_mf;
+USE altera_mf.altera_mf_components.all;
+
+ENTITY rom_reconfig_pal IS
+	PORT
+	(
+		address		: IN STD_LOGIC_VECTOR (7 DOWNTO 0);
+		clock		: IN STD_LOGIC  := '1';
+		rden		: IN STD_LOGIC  := '1';
+		q		: OUT STD_LOGIC_VECTOR (0 DOWNTO 0)
+	);
+END rom_reconfig_pal;
+
+
+ARCHITECTURE SYN OF rom_reconfig_pal IS
+
+	SIGNAL sub_wire0	: STD_LOGIC_VECTOR (0 DOWNTO 0);
+
+BEGIN
+	q    <= sub_wire0(0 DOWNTO 0);
+
+	altsyncram_component : altsyncram
+	GENERIC MAP (
+		address_aclr_a => "NONE",
+		clock_enable_input_a => "BYPASS",
+		clock_enable_output_a => "BYPASS",
+		init_file => "pll_c64_pal.mif",
+		intended_device_family => "Cyclone III",
+		lpm_hint => "ENABLE_RUNTIME_MOD=NO",
+		lpm_type => "altsyncram",
+		numwords_a => 256,
+		operation_mode => "ROM",
+		outdata_aclr_a => "NONE",
+		outdata_reg_a => "CLOCK0",
+		widthad_a => 8,
+		width_a => 1,
+		width_byteena_a => 1
+	)
+	PORT MAP (
+		address_a => address,
+		clock0 => clock,
+		rden_a => rden,
+		q_a => sub_wire0
+	);
+
+
+
+END SYN;
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrByte NUMERIC "0"
+-- Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
+-- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
+-- Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
+-- Retrieval info: PRIVATE: Clken NUMERIC "0"
+-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
+-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
+-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
+-- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
+-- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
+-- Retrieval info: PRIVATE: MIFfilename STRING "pll_c64_pal.mif"
+-- Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "256"
+-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
+-- Retrieval info: PRIVATE: RegAddr NUMERIC "1"
+-- Retrieval info: PRIVATE: RegOutput NUMERIC "1"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: PRIVATE: SingleClock NUMERIC "1"
+-- Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
+-- Retrieval info: PRIVATE: WidthAddr NUMERIC "8"
+-- Retrieval info: PRIVATE: WidthData NUMERIC "1"
+-- Retrieval info: PRIVATE: rden NUMERIC "1"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
+-- Retrieval info: CONSTANT: INIT_FILE STRING "pll_c64_pal.mif"
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
+-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
+-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "256"
+-- Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
+-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
+-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "CLOCK0"
+-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "8"
+-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "1"
+-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
+-- Retrieval info: USED_PORT: address 0 0 8 0 INPUT NODEFVAL "address[7..0]"
+-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
+-- Retrieval info: USED_PORT: q 0 0 1 0 OUTPUT NODEFVAL "q[0..0]"
+-- Retrieval info: USED_PORT: rden 0 0 0 0 INPUT VCC "rden"
+-- Retrieval info: CONNECT: @address_a 0 0 8 0 address 0 0 8 0
+-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
+-- Retrieval info: CONNECT: @rden_a 0 0 0 0 rden 0 0 0 0
+-- Retrieval info: CONNECT: q 0 0 1 0 @q_a 0 0 1 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal.vhd TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal.inc FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal.cmp FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal.bsf FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL rom_reconfig_pal_inst.vhd FALSE
+-- Retrieval info: LIB_FILE: altera_mf
diff --git a/cores/c64/rtl/mos6526.v b/cores/c64/rtl/mos6526.v
index 66f5903..a51dc63 100644
--- a/cores/c64/rtl/mos6526.v
+++ b/cores/c64/rtl/mos6526.v
@@ -1,8 +1,7 @@
 // MOS6526
 // by Rayne
 // Timers & Interrupts are rewritten by slingshot
-// Passes all CIA Timer tests
-// TODO: check if Flag and Serial port interrupts are still working
+// Passes all Lorenz CIA Timer tests
 
 module mos6526 (
   input  wire       mode,   // 0 - 6526 "old", 1 - 8521 "new"
@@ -153,9 +152,14 @@ end
 
 // FLAG Input
 always @(posedge clk) begin
-  if (!res_n || int_reset) icr[4] <= 1'b0;
-  else if (!flag_n && flag_n_prev) icr[4] <= 1'b1;
-  if (phi2_p) flag_n_prev <= flag_n;
+  if (!res_n) icr[4] <= 1'b0;
+  else begin
+    if (!flag_n && flag_n_prev) icr[4] <= 1'b1;
+    if (phi2_p) begin
+      flag_n_prev <= flag_n;
+      if (int_reset) icr[4] <= 1'b0;
+    end
+  end
 end
 
 // Port Control Output