From 99df24fee9d1bb5a42c7b4b29e51e4f89db00a50 Mon Sep 17 00:00:00 2001 From: harbaum Date: Tue, 12 Nov 2013 12:19:18 +0000 Subject: [PATCH] Re-enabled CPU type selection --- cores/mist/mist_top.v | 3 +-- cores/mist/video.v | 1 - 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/cores/mist/mist_top.v b/cores/mist/mist_top.v index 6e67719..cfa1a82 100644 --- a/cores/mist/mist_top.v +++ b/cores/mist/mist_top.v @@ -710,8 +710,7 @@ wire address_strobe = cpu_cycle && !tg68_as && !br; // assign tg68_as = ~(!tg68_uds || !tg68_lds); assign tg68_as = ~(tg68_busstate != 2'b01); -TG68KdotC_Kernel tg68k ( -//TG68KdotC_Kernel #(2,2,2,2,2,2) tg68k ( +TG68KdotC_Kernel #(2,2,2,2,2,2) tg68k ( .clk (clk_128 ), .nReset (~reset ), .clkena_in (clkena ), diff --git a/cores/mist/video.v b/cores/mist/video.v index 2d81aa0..ff1db5b 100644 --- a/cores/mist/video.v +++ b/cores/mist/video.v @@ -683,7 +683,6 @@ always @(posedge clk) begin // add line offset at the end of each video line if(me_v && st_h_active && (st_hcnt == t2_h_sync)) vaddr <= vaddr + line_offset; -// vaddr <= vaddr - 23'd4; // XXX // STE vaddr write handling // bus_cycle 6 is in the middle of a cpu cycle