From 9e7eeb4f5dfa123f4821a6055cfde3dfe036d794 Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi Date: Sun, 21 Apr 2019 17:52:18 +0200 Subject: [PATCH] [C64] Fix POT inputs --- cores/c64/rtl/fpga64_sid_iec.vhd | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/cores/c64/rtl/fpga64_sid_iec.vhd b/cores/c64/rtl/fpga64_sid_iec.vhd index b69d531..1d8b61c 100644 --- a/cores/c64/rtl/fpga64_sid_iec.vhd +++ b/cores/c64/rtl/fpga64_sid_iec.vhd @@ -283,7 +283,12 @@ architecture rtl of fpga64_sid_iec is signal ntscMode : std_logic; signal ntscModeInvert : std_logic := '0' ; signal restore_key : std_logic; - + + signal cd4066_sigA : std_logic_vector(7 downto 0); + signal cd4066_sigB : std_logic_vector(7 downto 0); + signal cd4066_sigC : std_logic_vector(7 downto 0); + signal cd4066_sigD : std_logic_vector(7 downto 0); + signal clk_1MHz : std_logic_vector(31 downto 0); signal voice_l : signed(17 downto 0); signal voice_r : signed(17 downto 0); @@ -610,12 +615,13 @@ div1m: process(clk32) -- this process devides 32 MHz to 1MHz (for the SID) sid_do8580_r; -- CD4066 analogue switch - pot_x <= potA_x when cia1_pao(6) = '1' else - potB_x when cia1_pao(7) = '1' else - x"FF"; - pot_y <= potA_y when cia1_pao(6) = '1' else - potB_y when cia1_pao(7) = '1' else - x"FF"; + cd4066_sigA <= x"FF" when cia1_pao(7) = '0' else potB_x; + cd4066_sigB <= x"FF" when cia1_pao(7) = '0' else potB_y; + cd4066_sigC <= x"FF" when cia1_pao(6) = '0' else potA_x; + cd4066_sigD <= x"FF" when cia1_pao(6) = '0' else potA_y; + + pot_x <= cd4066_sigA and cd4066_sigC; + pot_y <= cd4066_sigB and cd4066_sigD; second_sid_en <= '0' when sid_mode(0) = '0' else '1' when cpuAddr(11 downto 8) = x"4" and cpuAddr(5) = '1' else -- D420