diff --git a/cores/gameboy/t80/GBse.vhd b/cores/gameboy/t80/GBse.vhd
index fffaf37..2b6fa6b 100644
--- a/cores/gameboy/t80/GBse.vhd
+++ b/cores/gameboy/t80/GBse.vhd
@@ -93,6 +93,7 @@ entity GBse is
 		RFSH_n          : out std_logic;
 		HALT_n          : out std_logic;
 		BUSAK_n         : out std_logic;
+		STOP            : out std_logic;
 		A               : out std_logic_vector(15 downto 0);
 		DI              : in  std_logic_vector(7 downto 0);
 		DO              : out std_logic_vector(7 downto 0)
@@ -133,6 +134,7 @@ begin
 			Write      => Write,
 			RFSH_n     => RFSH_n,
 			HALT_n     => HALT_n,
+			Stop       => STOP,
 			WAIT_n     => Wait_n,
 			INT_n      => INT_n,
 			NMI_n      => NMI_n,
diff --git a/cores/gameboy/t80/T80.vhd b/cores/gameboy/t80/T80.vhd
index a8ddd9b..4fb4f20 100644
--- a/cores/gameboy/t80/T80.vhd
+++ b/cores/gameboy/t80/T80.vhd
@@ -150,6 +150,7 @@ architecture rtl of T80 is
 
 	-- Help Registers
 	signal TmpAddr              : std_logic_vector(15 downto 0);        -- Temporary address register
+	signal TmpAddr2             : std_logic_vector(15 downto 0);        -- Temporary address register
 	signal IR                   : std_logic_vector(7 downto 0);         -- Instruction register
 	signal ISet                 : std_logic_vector(1 downto 0);         -- Instruction set selector
 	signal RegBusA_r            : std_logic_vector(15 downto 0);
@@ -212,6 +213,7 @@ architecture rtl of T80 is
 	signal Set_BusA_To          : std_logic_vector(3 downto 0);
 	signal ALU_Op               : std_logic_vector(3 downto 0);
 	signal Save_ALU             : std_logic;
+	signal Rot_Akku             : std_logic;
 	signal PreserveC            : std_logic;
 	signal Arith16              : std_logic;
 	signal Set_Addr_To          : std_logic_vector(2 downto 0);
@@ -223,6 +225,8 @@ architecture rtl of T80 is
 	signal LDZ                  : std_logic;
 	signal LDW                  : std_logic;
 	signal LDSPHL               : std_logic;
+	signal LDHLSP               : std_logic;
+	signal ADDSPdd					 : std_logic;
 	signal IORQ_i               : std_logic;
 	signal Special_LD           : std_logic_vector(2 downto 0);
 	signal ExchangeDH           : std_logic;
@@ -280,6 +284,7 @@ begin
 			Set_BusA_To => Set_BusA_To,
 			ALU_Op      => ALU_Op,
 			Save_ALU    => Save_ALU,
+			Rot_Akku    => Rot_Akku,
 			PreserveC   => PreserveC,
 			Arith16     => Arith16,
 			Set_Addr_To => Set_Addr_To,
@@ -292,6 +297,8 @@ begin
 			LDZ         => LDZ,
 			LDW         => LDW,
 			LDSPHL      => LDSPHL,
+			LDHLSP		=> LDHLSP,
+			ADDSPdd		=> ADDSPdd,
 			Special_LD  => Special_LD,
 			ExchangeDH  => ExchangeDH,
 			ExchangeRp  => ExchangeRp,
@@ -331,6 +338,7 @@ begin
 			Arith16 => Arith16_r,
 			Z16     => Z16_r,
 			ALU_Op  => ALU_Op_r,
+			Rot_Akku    => Rot_Akku,
 			IR      => IR(5 downto 0),
 			ISet    => ISet,
 			BusA    => BusA,
@@ -353,6 +361,8 @@ begin
 		ALU_Q;
 
 	process (RESET_n, CLK_n)
+	variable temp_c : unsigned(8 downto 0);
+	variable temp_h : unsigned(4 downto 0);
 	begin
 		if RESET_n = '0' then
 			PC <= (others => '0');  -- Program Counter
@@ -366,7 +376,11 @@ begin
 			DO <= "00000000";
 
 			ACC <= (others => '1');
-			F <= (others => '1');
+			if Mode = 3 then
+				F <= "11110000";
+			else
+				F <= (others => '1');
+			end if;
 			Ap <= (others => '1');
 			Fp <= (others => '1');
 			I <= (others => '0');
@@ -393,6 +407,24 @@ begin
 			Read_To_Reg_r <= "00000";
 
 			MCycles <= MCycles_d;
+			
+			if LDHLSP = '1' and MCycle = "011" and TState = 1 then
+			   temp_c := unsigned('0'&SP(7 downto 0))+unsigned('0'&Save_Mux);
+				temp_h := unsigned('0'&SP(3 downto 0))+unsigned('0'&Save_Mux(3 downto 0));
+				F(Flag_Z) <= '0';	
+				F(Flag_N) <= '0';
+				F(Flag_H) <= temp_h(4);
+				F(Flag_C) <= temp_c(8);
+			end if;
+			
+			if ADDSPdd = '1' and TState = 1 then
+			   temp_c := unsigned('0'&SP(7 downto 0))+unsigned('0'&Save_Mux);
+				temp_h := unsigned('0'&SP(3 downto 0))+unsigned('0'&Save_Mux(3 downto 0));
+				F(Flag_Z) <= '0';	
+				F(Flag_N) <= '0';
+				F(Flag_H) <= temp_h(4);
+				F(Flag_C) <= temp_c(8);
+			end if;
 
       if Mode = 3 then
         IStatus <= "10";
@@ -531,31 +563,54 @@ begin
 
 					Save_ALU_r <= Save_ALU;
 					ALU_Op_r <= ALU_Op;
+					
+					if Mode = 3 then
+						if I_CPL = '1' then
+							-- CPL
+							ACC <= not ACC;
+							F(Flag_H) <= '1';
+							F(Flag_N) <= '1';
+						end if;
+						if I_CCF = '1' then
+							-- CCF
+							F(Flag_C) <= not F(Flag_C);
+							F(Flag_H) <= '0';
+							F(Flag_N) <= '0';
+						end if;
+						if I_SCF = '1' then
+							-- SCF
+							F(Flag_C) <= '1';
+							F(Flag_H) <= '0';
+							F(Flag_N) <= '0';
+						end if;
+					else
+						if I_CPL = '1' then
+							-- CPL
+							ACC <= not ACC;
+							F(Flag_Y) <= not ACC(5);
+							F(Flag_H) <= '1';
+							F(Flag_X) <= not ACC(3);
+							F(Flag_N) <= '1';
+						end if;
+						if I_CCF = '1' then
+							-- CCF
+							F(Flag_C) <= not F(Flag_C);
+							F(Flag_Y) <= ACC(5);
+							F(Flag_H) <=  F(Flag_C);
+							F(Flag_X) <= ACC(3);
+							F(Flag_N) <= '0';
+						end if;
+						if I_SCF = '1' then
+							-- SCF
+							F(Flag_C) <= '1';
+							F(Flag_Y) <= ACC(5);
+							F(Flag_H) <= '0';
+							F(Flag_X) <= ACC(3);
+							F(Flag_N) <= '0';
+						end if;
+					end if;
+
 
-					if I_CPL = '1' then
-						-- CPL
-						ACC <= not ACC;
-						F(Flag_Y) <= not ACC(5);
-						F(Flag_H) <= '1';
-						F(Flag_X) <= not ACC(3);
-						F(Flag_N) <= '1';
-					end if;
-					if I_CCF = '1' then
-						-- CCF
-						F(Flag_C) <= not F(Flag_C);
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= F(Flag_C);
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
-					if I_SCF = '1' then
-						-- SCF
-						F(Flag_C) <= '1';
-						F(Flag_Y) <= ACC(5);
-						F(Flag_H) <= '0';
-						F(Flag_X) <= ACC(3);
-						F(Flag_N) <= '0';
-					end if;
 				end if;
 
 				if TState = 2 and Wait_n = '1' then
@@ -588,6 +643,11 @@ begin
 						end if;
 					end if;
 				end if;
+				
+				if ADDSPdd = '1' and TState = 2 then
+				   TmpAddr<=std_logic_vector(SP);
+					SP <= unsigned(signed(SP)+signed(Save_Mux));
+				end if;
 
 				if LDSPHL = '1' then
 					SP <= unsigned(RegBusC);
@@ -698,7 +758,12 @@ begin
 				when "11001" =>
 					SP(15 downto 8) <= unsigned(Save_Mux);
 				when "11011" =>
-					F <= Save_Mux;
+					if Mode = 3 then
+						F(7 downto 4) <= Save_Mux(7 downto 4);
+						F(3 downto 0) <= "0000"; -- bit 3 to 0 always return 0
+					else
+						F <= Save_Mux;
+					end if;
 				when others =>
 				end case;
 				if XYbit_undoc='1' then
@@ -768,6 +833,8 @@ begin
 			-- EX HL,DL
 			Alternate & "10" when ExchangeDH = '1' and TState = 3 else
 			Alternate & "01" when ExchangeDH = '1' and TState = 4 else
+			-- LDHLSP
+			"010" when LDHLSP = '1' and TState = 4 else
 			-- Bus A / Write
 			RegAddrA_r;
 
@@ -781,7 +848,7 @@ begin
 			signed(RegBusA) + 1;
 
 	process (Save_ALU_r, Auto_Wait_t1, ALU_OP_r, Read_To_Reg_r,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n,LDHLSP)
 	begin
 		RegWEH <= '0';
 		RegWEL <= '0';
@@ -799,6 +866,11 @@ begin
 			RegWEH <= '1';
 			RegWEL <= '1';
 		end if;
+		
+		if LDHLSP = '1' and MCycle = "010" and TState = 4 then
+			RegWEH <= '1';
+			RegWEL <= '1';
+		end if;
 
 		if IncDec_16(2) = '1' and ((TState = 2 and Wait_n = '1' and MCycle /= "001") or (TState = 3 and MCycle = "001")) then
 			case IncDec_16(1 downto 0) is
@@ -810,12 +882,19 @@ begin
 		end if;
 	end process;
 
+	TmpAddr2 <= std_logic_vector(unsigned(signed(SP) + signed(Save_Mux)));
+
 	process (Save_Mux, RegBusB, RegBusA_r, ID16,
-			ExchangeDH, IncDec_16, MCycle, TState, Wait_n)
+			ExchangeDH, IncDec_16, MCycle, TState, Wait_n, LDHLSP, SP, TmpAddr2)
 	begin
 		RegDIH <= Save_Mux;
 		RegDIL <= Save_Mux;
-
+		
+		if LDHLSP = '1' and MCycle = "010" and TState = 4 then
+			RegDIH <= TmpAddr2(15 downto 8);
+			RegDIL <= TmpAddr2(7 downto 0);
+		end if;
+		
 		if ExchangeDH = '1' and TState = 3 then
 			RegDIH <= RegBusB(15 downto 8);
 			RegDIL <= RegBusB(7 downto 0);
@@ -1056,6 +1135,8 @@ begin
 								IntCycle <= '1';
 								IntE_FF1 <= '0';
 								IntE_FF2 <= '0';
+							elsif (Halt_FF = '1' and INT_s = '1' and Mode = 3) then
+								Halt_FF <= '0';
 							end if;
 						else
 							MCycle <= std_logic_vector(unsigned(MCycle) + 1);
diff --git a/cores/gameboy/t80/T80_ALU.vhd b/cores/gameboy/t80/T80_ALU.vhd
index 17b9f0f..811a944 100644
--- a/cores/gameboy/t80/T80_ALU.vhd
+++ b/cores/gameboy/t80/T80_ALU.vhd
@@ -85,6 +85,7 @@ entity T80_ALU is
 		Arith16         : in  std_logic;
 		Z16             : in  std_logic;
 		ALU_Op          : in  std_logic_vector(3 downto 0);
+		Rot_Akku        : in  std_logic;
 		IR              : in  std_logic_vector(5 downto 0);
 		ISet            : in  std_logic_vector(1 downto 0);
 		BusA            : in  std_logic_vector(7 downto 0);
@@ -216,35 +217,64 @@ begin
 			end if;
 		when "1100" =>
 			-- DAA
-			F_Out(Flag_H) <= F_In(Flag_H);
-			F_Out(Flag_C) <= F_In(Flag_C);
-			DAA_Q(7 downto 0) := unsigned(BusA);
-			DAA_Q(8) := '0';
-			if F_In(Flag_N) = '0' then
-				-- After addition
-				-- Alow > 9 or H = 1
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if (DAA_Q(3 downto 0) > 9) then
-						F_Out(Flag_H) <= '1';
-					else
-						F_Out(Flag_H) <= '0';
+			if Mode = 3 then
+				F_Out(Flag_H) <= '0';
+				F_Out(Flag_C) <= F_In(Flag_C);
+				DAA_Q(7 downto 0) := unsigned(BusA);
+				DAA_Q(8) := '0';
+				if F_In(Flag_N) = '0' then
+					-- After addition
+					-- Alow > 9 or H = 1
+					if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+							DAA_Q := DAA_Q + 6;
+					end if;
+					-- new Ahigh > 9 or C = 1
+					if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+						DAA_Q := DAA_Q + 96; -- 0x60
+					end if;
+				else
+					-- After subtraction
+					if F_In(Flag_H) = '1' then
+						DAA_Q := DAA_Q - 6;
+						if F_In(Flag_C) = '0' then
+							DAA_Q(8) := '0';
+						end if;
+					end if;
+					if F_In(Flag_C) = '1' then
+						DAA_Q := DAA_Q - 96; -- 0x60
 					end if;
-					DAA_Q := DAA_Q + 6;
-				end if;
-				-- new Ahigh > 9 or C = 1
-				if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q + 96; -- 0x60
 				end if;
 			else
-				-- After subtraction
-				if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
-					if DAA_Q(3 downto 0) > 5 then
-						F_Out(Flag_H) <= '0';
+				F_Out(Flag_H) <= F_In(Flag_H);
+				F_Out(Flag_C) <= F_In(Flag_C);
+				DAA_Q(7 downto 0) := unsigned(BusA);
+				DAA_Q(8) := '0';
+				if F_In(Flag_N) = '0' then
+					-- After addition
+					-- Alow > 9 or H = 1
+					if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+						if (DAA_Q(3 downto 0) > 9) then
+							F_Out(Flag_H) <= '1';
+						else
+							F_Out(Flag_H) <= '0';
+						end if;
+						DAA_Q := DAA_Q + 6;
+					end if;
+					-- new Ahigh > 9 or C = 1
+					if DAA_Q(8 downto 4) > 9 or F_In(Flag_C) = '1' then
+						DAA_Q := DAA_Q + 96; -- 0x60
+					end if;
+				else
+					-- After subtraction
+					if DAA_Q(3 downto 0) > 9 or F_In(Flag_H) = '1' then
+						if DAA_Q(3 downto 0) > 5 then
+							F_Out(Flag_H) <= '0';
+						end if;
+						DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
+					end if;
+					if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
+						DAA_Q := DAA_Q - 352; -- 0x160
 					end if;
-					DAA_Q(7 downto 0) := DAA_Q(7 downto 0) - 6;
-				end if;
-				if unsigned(BusA) > 153 or F_In(Flag_C) = '1' then
-					DAA_Q := DAA_Q - 352; -- 0x160
 				end if;
 			end if;
 			F_Out(Flag_X) <= DAA_Q(3);
@@ -363,6 +393,9 @@ begin
 				F_Out(Flag_S) <= F_In(Flag_S);
 				F_Out(Flag_Z) <= F_In(Flag_Z);
 			end if;
+			if Mode = 3 and Rot_Akku = '1'  then
+					F_Out(Flag_Z) <= '0';
+			end if; 
 		when others =>
 			null;
 		end case;
diff --git a/cores/gameboy/t80/T80_MCode.vhd b/cores/gameboy/t80/T80_MCode.vhd
index f2b602c..60bfa01 100644
--- a/cores/gameboy/t80/T80_MCode.vhd
+++ b/cores/gameboy/t80/T80_MCode.vhd
@@ -112,6 +112,7 @@ entity T80_MCode is
 		ALU_Op                  : out std_logic_vector(3 downto 0);
 			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
 		Save_ALU                : out std_logic;
+		Rot_Akku                : out std_logic;
 		PreserveC               : out std_logic;
 		Arith16                 : out std_logic;
 		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
@@ -121,9 +122,11 @@ entity T80_MCode is
 		JumpXY                  : out std_logic;
 		Call                    : out std_logic;
 		RstP                    : out std_logic;
-		LDZ                             : out std_logic;
-		LDW                             : out std_logic;
+		LDZ                     : out std_logic;
+		LDW                     : out std_logic;
 		LDSPHL                  : out std_logic;
+		LDHLSP						: out std_logic;
+		ADDSPdd						: out std_logic;
 		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
 		ExchangeDH              : out std_logic;
 		ExchangeRp              : out std_logic;
@@ -184,7 +187,7 @@ architecture rtl of T80_MCode is
 
 begin
 
-	process (IR, ISet, MCycle, F, NMICycle, IntCycle)
+	process (IR, ISet, MCycle, F, NMICycle, IntCycle, XY_State)
 		variable DDD : std_logic_vector(2 downto 0);
 		variable SSS : std_logic_vector(2 downto 0);
 		variable DPair : std_logic_vector(1 downto 0);
@@ -211,6 +214,7 @@ begin
 		Set_BusA_To <= "0000";
 		ALU_Op <= "0" & IR(5 downto 3);
 		Save_ALU <= '0';
+		Rot_Akku <= '0';
 		PreserveC <= '0';
 		Arith16 <= '0';
 		IORQ <= '0';
@@ -223,6 +227,8 @@ begin
 		LDZ <= '0';
 		LDW <= '0';
 		LDSPHL <= '0';
+		LDHLSP <= '0';
+		ADDSPdd <= '0';
 		Special_LD <= "000";
 		ExchangeDH <= '0';
 		ExchangeRp <= '0';
@@ -515,34 +521,66 @@ begin
 			LDSPHL <= '1';
 		when "11000101"|"11010101"|"11100101"|"11110101" =>
 			-- PUSH qq
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				TStates <= "101";
-				IncDec_16 <= "1111";
-				Set_Addr_TO <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "0111";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '0';
-					Set_BusB_To(3) <= '0';
-				end if;
-			when 2 =>
-				IncDec_16 <= "1111";
-				Set_Addr_To <= aSP;
-				if DPAIR = "11" then
-					Set_BusB_To <= "1011";
-				else
-					Set_BusB_To(2 downto 1) <= DPAIR;
-					Set_BusB_To(0) <= '1';
-					Set_BusB_To(3) <= '0';
-				end if;
-				Write <= '1';
-			when 3 =>
-				Write <= '1';
-			when others => null;
-			end case;
+			if Mode = 3 then
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_TO <= aSP;
+					if DPAIR = "11" then
+						Set_BusB_To <= "0111";
+					else
+						Set_BusB_To(2 downto 1) <= DPAIR;
+						Set_BusB_To(0) <= '0';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 3 =>
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					if DPAIR = "11" then
+						Set_BusB_To <= "1011";
+					else
+						Set_BusB_To(2 downto 1) <= DPAIR;
+						Set_BusB_To(0) <= '1';
+						Set_BusB_To(3) <= '0';
+					end if;
+					Write <= '1';
+				when 4 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			else
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					TStates <= "101";
+					IncDec_16 <= "1111";
+					Set_Addr_TO <= aSP;
+					if DPAIR = "11" then
+						Set_BusB_To <= "0111";
+					else
+						Set_BusB_To(2 downto 1) <= DPAIR;
+						Set_BusB_To(0) <= '0';
+						Set_BusB_To(3) <= '0';
+					end if;
+				when 2 =>
+					IncDec_16 <= "1111";
+					Set_Addr_To <= aSP;
+					if DPAIR = "11" then
+						Set_BusB_To <= "1011";
+					else
+						Set_BusB_To(2 downto 1) <= DPAIR;
+						Set_BusB_To(0) <= '1';
+						Set_BusB_To(3) <= '0';
+					end if;
+					Write <= '1';
+				when 3 =>
+					Write <= '1';
+				when others => null;
+				end case;
+			end if;
+
 		when "11000001"|"11010001"|"11100001"|"11110001" =>
 			-- POP qq
 			MCycles <= "011";
@@ -606,7 +644,7 @@ begin
 		when "11011001" =>
 			if Mode = 3 then
 				-- RETI
-				MCycles <= "011";
+				MCycles <= "100";
 				case to_integer(unsigned(MCycle)) is
 				when 1 =>
 					Set_Addr_TO <= aSP;
@@ -851,9 +889,13 @@ begin
 -- 16 BIT ARITHMETIC GROUP
 		when "00001001"|"00011001"|"00101001"|"00111001" =>
 			-- ADD HL,ss
-			MCycles <= "011";
+			if Mode = 3 then
+			  MCycles <= "010";
+			else
+			  MCycles <= "011";
+			end if;
 			case to_integer(unsigned(MCycle)) is
-			when 2 =>
+			when 1 =>
 				NoRead <= '1';
 				ALU_Op <= "0000";
 				Read_To_Reg <= '1';
@@ -868,7 +910,7 @@ begin
 				end case;
 				TStates <= "100";
 				Arith16 <= '1';
-			when 3 =>
+			when 2 =>
 				NoRead <= '1';
 				Read_To_Reg <= '1';
 				Save_ALU <= '1';
@@ -885,14 +927,34 @@ begin
 			end case;
 		when "00000011"|"00010011"|"00100011"|"00110011" =>
 			-- INC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "01";
-			IncDec_16(1 downto 0) <= DPair;
+			if Mode = 3 then
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					IncDec_16(3 downto 2) <= "01";
+					IncDec_16(1 downto 0) <= DPair;
+				when others =>
+				end case;
+			else
+				TStates <= "110";
+				IncDec_16(3 downto 2) <= "01";
+				IncDec_16(1 downto 0) <= DPair;
+			end if;
 		when "00001011"|"00011011"|"00101011"|"00111011" =>
 			-- DEC ss
-			TStates <= "110";
-			IncDec_16(3 downto 2) <= "11";
-			IncDec_16(1 downto 0) <= DPair;
+			if Mode = 3 then
+				MCycles <= "010";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					IncDec_16(3 downto 2) <= "11";
+					IncDec_16(1 downto 0) <= DPair;
+				when others =>
+				end case;
+			else
+				TStates <= "110";
+				IncDec_16(3 downto 2) <= "11";
+				IncDec_16(1 downto 0) <= DPair;
+			end if;
 
 -- ROTATE AND SHIFT GROUP
 		when "00000111"
@@ -906,12 +968,17 @@ begin
 			Set_BusA_To(2 downto 0) <= "111";
 			ALU_Op <= "1000";
 			Read_To_Reg <= '1';
+			Rot_Akku <= '1';
 			Save_ALU <= '1';
 
 -- JUMP GROUP
 		when "11000011" =>
 			-- JP nn
-			MCycles <= "011";
+			if Mode = 3 then
+				MCycles <= "100";
+			else
+				MCycles <= "011";
+			end if;
 			case to_integer(unsigned(MCycle)) is
 			when 2 =>
 				Inc_PC <= '1';
@@ -1108,7 +1175,11 @@ begin
 -- CALL AND RETURN GROUP
 		when "11001101" =>
 			-- CALL nn
-			MCycles <= "101";
+			if Mode = 3 then
+				MCycles <= "110";
+			else
+				MCycles <= "101";
+			end if;
 			case to_integer(unsigned(MCycle)) is
 			when 2 =>
 				Inc_PC <= '1';
@@ -1133,7 +1204,11 @@ begin
 		when "11000100"|"11001100"|"11010100"|"11011100"|"11100100"|"11101100"|"11110100"|"11111100" =>
 			if IR(5) = '0' or Mode /= 3 then
 				-- CALL cc,nn
-				MCycles <= "101";
+				if Mode = 3 then
+					MCycles <= "110";
+				else
+					MCycles <= "101";
+				end if;
 				case to_integer(unsigned(MCycle)) is
 				when 2 =>
 					Inc_PC <= '1';
@@ -1162,19 +1237,36 @@ begin
 			end if;
 		when "11001001" =>
 			-- RET
-			MCycles <= "011";
-			case to_integer(unsigned(MCycle)) is
-			when 1 =>
-				Set_Addr_TO <= aSP;
-			when 2 =>
-				IncDec_16 <= "0111";
-				Set_Addr_To <= aSP;
-				LDZ <= '1';
-			when 3 =>
-				Jump <= '1';
-				IncDec_16 <= "0111";
-			when others => null;
-			end case;
+			if Mode = 3 then
+				MCycles <= "100";
+				case to_integer(unsigned(MCycle)) is
+				when 2 =>
+					Set_Addr_TO <= aSP;
+				when 3 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 4 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+				when others => null;
+				end case;
+			else
+				MCycles <= "011";
+				case to_integer(unsigned(MCycle)) is
+				when 1 =>
+					Set_Addr_TO <= aSP;
+				when 2 =>
+					IncDec_16 <= "0111";
+					Set_Addr_To <= aSP;
+					LDZ <= '1';
+				when 3 =>
+					Jump <= '1';
+					IncDec_16 <= "0111";
+				when others => null;
+				end case;
+			end if;
+
 		when "11000000"|"11001000"|"11010000"|"11011000"|"11100000"|"11101000"|"11110000"|"11111000" =>
 			if IR(5) = '1' and Mode = 3 then
 				case IRB(4 downto 3) is
@@ -1192,22 +1284,13 @@ begin
 					end case;
 				when "01" =>
 					-- ADD SP,n
-					MCycles <= "011";
+					MCycles <= "100";
 					case to_integer(unsigned(MCycle)) is
 					when 2 =>
-						ALU_Op <= "0000";
-						Inc_PC <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						Set_BusA_To <= "1000";
-						Set_BusB_To <= "0110";
+						-- Inc_PC <= '1';
 					when 3 =>
-						NoRead <= '1';
-						Read_To_Reg <= '1';
-						Save_ALU <= '1';
-						ALU_Op <= "0001";
-						Set_BusA_To <= "1001";
-						Set_BusB_To <= "1110";  -- Incorrect unsigned !!!!!!!!!!!!!!!!!!!!!
+					  Inc_PC <= '1';
+					  ADDSPdd <= '1';						
 					when others =>
 					end case;
 				when "10" =>
@@ -1222,51 +1305,68 @@ begin
 					when others => null;
 					end case;
 				when "11" =>
-					-- LD HL,SP+n       -- Not correct !!!!!!!!!!!!!!!!!!!
-					MCycles <= "101";
+					-- LD HL,SP+n
+					MCycles <= "011";
 					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+					  Inc_PC <= '1';
 					when 2 =>
-						Inc_PC <= '1';
-						LDZ <= '1';
+					  LDHLSP <= '1';
+					  Inc_PC <= '1';
 					when 3 =>
-						Set_Addr_To <= aZI;
-						Inc_PC <= '1';
-						LDW <= '1';
-					when 4 =>
-						Set_BusA_To(2 downto 0) <= "101"; -- L
-						Read_To_Reg <= '1';
-						Inc_WZ <= '1';
-						Set_Addr_To <= aZI;
-					when 5 =>
-						Set_BusA_To(2 downto 0) <= "100"; -- H
-						Read_To_Reg <= '1';
+					  LDHLSP <= '1';
 					when others => null;
 					end case;
 				end case;
 			else
 				-- RET cc
-				MCycles <= "011";
-				case to_integer(unsigned(MCycle)) is
-				when 1 =>
-					if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
-						Set_Addr_TO <= aSP;
-					else
-						MCycles <= "001";
-					end if;
-					TStates <= "101";
-				when 2 =>
-					IncDec_16 <= "0111";
-					Set_Addr_To <= aSP;
-					LDZ <= '1';
-				when 3 =>
-					Jump <= '1';
-					IncDec_16 <= "0111";
-				when others => null;
-				end case;
+				if Mode = 3 then
+					MCycles <= "101";
+					case to_integer(unsigned(MCycle)) is
+					when 2 =>
+						if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+							Set_Addr_TO <= aSP;
+						else
+							MCycles <= "010";
+						end if;
+						TStates <= "101";
+					when 3 =>
+						IncDec_16 <= "0111";
+						Set_Addr_To <= aSP;
+						LDZ <= '1';
+					when 4 =>
+						Jump <= '1';
+						IncDec_16 <= "0111";
+					when others => null;
+					end case;
+				else
+					MCycles <= "011";
+					case to_integer(unsigned(MCycle)) is
+					when 1 =>
+						if is_cc_true(F, to_bitvector(IR(5 downto 3))) then
+							Set_Addr_TO <= aSP;
+						else
+							MCycles <= "001";
+						end if;
+						TStates <= "101";
+					when 2 =>
+						IncDec_16 <= "0111";
+						Set_Addr_To <= aSP;
+						LDZ <= '1';
+					when 3 =>
+						Jump <= '1';
+						IncDec_16 <= "0111";
+					when others => null;
+					end case;
+				end if;
 			end if;
 		when "11000111"|"11001111"|"11010111"|"11011111"|"11100111"|"11101111"|"11110111"|"11111111" =>
 			-- RST p
-			MCycles <= "011";
+			if Mode = 3 then
+				MCycles <= "100";
+			else
+				MCycles <= "011";
+			end if;
 			case to_integer(unsigned(MCycle)) is
 			when 1 =>
 				TStates <= "101";
@@ -1537,7 +1637,7 @@ begin
 					when others => null;
 					end case;
 				end if;
-				
+
 			when "10000110"|"10001110"|"10010110"|"10011110"|"10100110"|"10101110"|"10110110"|"10111110" =>
 				-- RES b,(HL)
 				MCycles <= "011";
diff --git a/cores/gameboy/t80/T80_Pack.vhd b/cores/gameboy/t80/T80_Pack.vhd
index 26ff6b2..6bae09f 100644
--- a/cores/gameboy/t80/T80_Pack.vhd
+++ b/cores/gameboy/t80/T80_Pack.vhd
@@ -161,6 +161,7 @@ package T80_Pack is
 		ALU_Op                  : out std_logic_vector(3 downto 0);
 			-- ADD, ADC, SUB, SBC, AND, XOR, OR, CP, ROT, BIT, SET, RES, DAA, RLD, RRD, None
 		Save_ALU                : out std_logic;
+		Rot_Akku                : out std_logic;
 		PreserveC               : out std_logic;
 		Arith16                 : out std_logic;
 		Set_Addr_To             : out std_logic_vector(2 downto 0); -- aNone,aXY,aIOA,aSP,aBC,aDE,aZI
@@ -173,6 +174,8 @@ package T80_Pack is
 		LDZ                     : out std_logic;
 		LDW                     : out std_logic;
 		LDSPHL                  : out std_logic;
+		LDHLSP                  : out std_logic;
+		ADDSPdd						: out std_logic;
 		Special_LD              : out std_logic_vector(2 downto 0); -- A,I;A,R;I,A;R,A;None
 		ExchangeDH              : out std_logic;
 		ExchangeRp              : out std_logic;
@@ -215,6 +218,7 @@ package T80_Pack is
 		Arith16         : in  std_logic;
 		Z16             : in  std_logic;
 		ALU_Op          : in  std_logic_vector(3 downto 0);
+		Rot_Akku        : in  std_logic;
 		IR              : in  std_logic_vector(5 downto 0);
 		ISet            : in  std_logic_vector(1 downto 0);
 		BusA            : in  std_logic_vector(7 downto 0);