From b5883c7c2c941280a4400248a52c2f27db9461b9 Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi Date: Sun, 28 Apr 2019 13:26:17 +0200 Subject: [PATCH 1/2] [Archie] Risc Developments IDE interface --- .../archie/fpga/mist/archimedes_mist_top.qsf | 17 +- cores/archie/fpga/mist/archimedes_mist_top.v | 65 +- cores/archie/fpga/mist/data_io.v | 198 ++++- cores/archie/rtl/archimedes_top.v | 51 +- cores/archie/rtl/ide.sv | 199 +++++ cores/archie/rtl/podules.v | 76 +- cores/archie/rtl/riscdevide_rom.hex | 714 ++++++++++++++++++ 7 files changed, 1267 insertions(+), 53 deletions(-) create mode 100644 cores/archie/rtl/ide.sv create mode 100644 cores/archie/rtl/riscdevide_rom.hex diff --git a/cores/archie/fpga/mist/archimedes_mist_top.qsf b/cores/archie/fpga/mist/archimedes_mist_top.qsf index 2469320..72e217f 100644 --- a/cores/archie/fpga/mist/archimedes_mist_top.qsf +++ b/cores/archie/fpga/mist/archimedes_mist_top.qsf @@ -47,8 +47,8 @@ set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 set_global_assignment -name ERROR_CHECK_FREQUENCY_DIVISOR 1 -set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" -set_global_assignment -name EDA_OUTPUT_DATA_FORMAT "VERILOG HDL" -section_id eda_simulation +set_global_assignment -name EDA_SIMULATION_TOOL "" +set_global_assignment -name EDA_OUTPUT_DATA_FORMAT NONE -section_id eda_simulation set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top @@ -136,7 +136,7 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_* set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to DRAM_* set_global_assignment -name ENABLE_SIGNALTAP OFF -set_global_assignment -name USE_SIGNALTAP_FILE output_files/vidc.stp +set_global_assignment -name USE_SIGNALTAP_FILE output_files/ide.stp set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF set_global_assignment -name ENABLE_NCE_PIN OFF @@ -177,8 +177,9 @@ set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to DRAM_DQ[*] set_global_assignment -name SEED 1 set_global_assignment -name ENABLE_DRC_SETTINGS OFF set_location_assignment PLL_1 -to CLOCKS|altpll_component|auto_generated|pll1 -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT EXTRA +set_global_assignment -name PRE_MAPPING_RESYNTHESIS ON +set_global_assignment -name REMOVE_REDUNDANT_LOGIC_CELLS ON set_global_assignment -name VERILOG_FILE archimedes_mist_top.v set_global_assignment -name SYSTEMVERILOG_FILE rgb2ypbpr.sv set_global_assignment -name VERILOG_FILE scandoubler.v @@ -190,9 +191,10 @@ set_global_assignment -name VERILOG_FILE osd.v set_global_assignment -name VERILOG_FILE sram_line_en.v set_global_assignment -name VERILOG_FILE sram_byte_en.v set_global_assignment -name QIP_FILE clockgen.qip -set_global_assignment -name VERILOG_FILE ../../rtl/fdc1772.v set_global_assignment -name VERILOG_FILE ../../rtl/latches.v +set_global_assignment -name VERILOG_FILE ../../rtl/fdc1772.v set_global_assignment -name VERILOG_FILE ../../rtl/floppy.v +set_global_assignment -name SYSTEMVERILOG_FILE ../../rtl/ide.sv set_global_assignment -name VERILOG_FILE ../../rtl/podules.v set_global_assignment -name VERILOG_FILE ../../rtl/i2cslave/serialInterface.v set_global_assignment -name VERILOG_FILE ../../rtl/i2cslave/registerInterface.v @@ -228,4 +230,5 @@ set_global_assignment -name QIP_FILE pll_reconfig.qip set_global_assignment -name QIP_FILE rom_reconfig_36.qip set_global_assignment -name QIP_FILE pll_vidc.qip set_global_assignment -name SIGNALTAP_FILE output_files/vidc.stp -set_global_assignment -name SIGNALTAP_FILE output_files/sd.stp \ No newline at end of file +set_global_assignment -name SIGNALTAP_FILE output_files/sd.stp +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/cores/archie/fpga/mist/archimedes_mist_top.v b/cores/archie/fpga/mist/archimedes_mist_top.v index 0c0ce92..f2a38ce 100644 --- a/cores/archie/fpga/mist/archimedes_mist_top.v +++ b/cores/archie/fpga/mist/archimedes_mist_top.v @@ -56,6 +56,7 @@ module archimedes_mist_top( input SPI_SCK, input SPI_SS2, // data_io input SPI_SS3, // OSD + input SPI_SS4, // Direct SD input CONF_DATA0 // SPI_SS for user_io ); @@ -340,7 +341,8 @@ wire [8:0] sd_buff_addr; wire [1:0] img_mounted; wire [31:0] img_size; -assign SPI_DO = (CONF_DATA0==0)?user_io_sdo:1'bZ; +// de-multiplex spi outputs from user_io and data_io +assign SPI_DO = (CONF_DATA0==0)?user_io_sdo:(SPI_SS2==0)?data_io_sdo:1'bZ; wire user_io_sdo; user_io user_io( @@ -380,14 +382,34 @@ user_io user_io( .img_size ( img_size ) ); +wire spi_din = SPI_SS4 ? SPI_DI : SPI_DO; + +wire data_io_sdo; data_io # ( .START_ADDR(24'h40_0000) ) DATA_IO ( - .sck ( SPI_SCK ), - .ss ( SPI_SS2 ), - .sdi ( SPI_DI ), + .sck ( SPI_SCK ), + .ss ( SPI_SS2 ), + .ss_sd ( SPI_SS4 ), + .sdi ( spi_din ), + .sdo ( data_io_sdo ), + + .reset ( reset ), + .ide_req ( ide_req ), + .ide_ack ( ide_ack ), + .ide_err ( ide_err ), + .ide_reg_o_adr ( ide_reg_i_adr ), + .ide_reg_o ( ide_reg_i ), + .ide_reg_we ( ide_reg_we ), + .ide_reg_i_adr ( ide_reg_o_adr ), + .ide_reg_i ( ide_reg_o ), + .ide_data_addr ( ide_data_addr ), + .ide_data_o ( ide_data_i ), + .ide_data_i ( ide_data_o ), + .ide_data_rd ( ide_data_rd ), + .ide_data_we ( ide_data_we ), .downloading ( downloading ), - .size ( ), + .size ( ), .index ( dio_index ), // ram interface @@ -413,13 +435,29 @@ wire [1:0] pixbaseclk_select; wire i2c_din, i2c_dout, i2c_clock; +wire ide_req; +wire ide_ack; +wire ide_err; +wire [2:0] ide_reg_o_adr; +wire [7:0] ide_reg_o; +wire ide_reg_we; +wire [2:0] ide_reg_i_adr; +wire [7:0] ide_reg_i; +wire [8:0] ide_data_addr; +wire [7:0] ide_data_o; +wire [7:0] ide_data_i; +wire ide_data_rd; +wire ide_data_we; + +wire reset = ~ram_ready | ~rom_ready; + archimedes_top ARCHIMEDES( .CLKCPU_I ( clk_sys ), .CLKPIX_I ( clk_pix ), // pixel clock for OSD .CEPIX_O ( ce_pix ), - .RESET_I (~ram_ready | ~rom_ready), + .RESET_I ( reset ), .MEM_ACK_I ( core_ack_in ), .MEM_DAT_I ( core_data_in ), @@ -460,6 +498,21 @@ archimedes_top ARCHIMEDES( .sd_dout_strobe ( sd_dout_strobe ), .sd_din_strobe ( sd_din_strobe ), + // IDE controller + .ide_req ( ide_req ), + .ide_ack ( ide_ack ), + .ide_err ( ide_err ), + .ide_reg_o_adr ( ide_reg_o_adr ), + .ide_reg_o ( ide_reg_o ), + .ide_reg_we ( ide_reg_we ), + .ide_reg_i_adr ( ide_reg_i_adr ), + .ide_reg_i ( ide_reg_i ), + .ide_data_addr ( ide_data_addr ), + .ide_data_o ( ide_data_o ), + .ide_data_i ( ide_data_i ), + .ide_data_rd ( ide_data_rd ), + .ide_data_we ( ide_data_we ), + .KBD_OUT_DATA ( kbd_out_data ), .KBD_OUT_STROBE ( kbd_out_strobe ), .KBD_IN_DATA ( kbd_in_data ), diff --git a/cores/archie/fpga/mist/data_io.v b/cores/archie/fpga/mist/data_io.v index c06514a..d1c651a 100644 --- a/cores/archie/fpga/mist/data_io.v +++ b/cores/archie/fpga/mist/data_io.v @@ -2,7 +2,7 @@ // data_io.v // // Data interface for the archimedes core on the MiST board. -// Providing ROM and floppy data up- and download via the MISTs +// Providing ROM and IDE data up- and download via the MISTs // own arm7 cpu. // // http://code.google.com/p/mist-board/ @@ -25,9 +25,27 @@ module data_io #(parameter ADDR_WIDTH=24, START_ADDR = 0) ( // io controller spi interface - input sck, - input ss, - input sdi, + input sck, + input ss, + input ss_sd, + input sdi, + output reg sdo, + + input reset, + input ide_req, + output reg ide_ack, + output reg ide_err, + output reg [2:0] ide_reg_i_adr, + input [7:0] ide_reg_i, + output reg ide_reg_we, + output reg [2:0] ide_reg_o_adr, + output reg [7:0] ide_reg_o, + + output reg [8:0] ide_data_addr, + output reg [7:0] ide_data_o, + input [7:0] ide_data_i, + output reg ide_data_rd, + output reg ide_data_we, output reg downloading, // signal indicating an active download output [ADDR_WIDTH-1:0] size, // number of bytes in input buffer @@ -52,19 +70,28 @@ assign size = addr - START_ADDR; // spi client // ********************************************************************************* -// this core supports only the display related OSD commands -// of the minimig reg [6:0] sbuf; +reg [7:0] cmd; reg [7:0] data; reg [2:0] bit_cnt; -reg [2:0] byte_cnt; +reg [4:0] byte_cnt; + +reg [6:0] sbuf_sd; +reg [2:0] bit_cnt_sd; reg [ADDR_WIDTH-1:0] addr; localparam UIO_FILE_TX = 8'h53; localparam UIO_FILE_TX_DAT = 8'h54; localparam UIO_FILE_INDEX = 8'h55; -// data_io has its own SPI interface to the io controller + +localparam CMD_IDECMD = 8'h04; +localparam CMD_IDEDAT = 8'h08; +localparam CMD_IDE_REGS_RD = 8'h80; +localparam CMD_IDE_REGS_WR = 8'h90; +localparam CMD_IDE_DATA_WR = 8'hA0; +localparam CMD_IDE_DATA_RD = 8'hB0; +localparam CMD_IDE_STATUS_WR = 8'hF0; // SPI bit and byte counters always@(posedge sck or posedge ss) begin @@ -79,6 +106,63 @@ always@(posedge sck or posedge ss) begin end end +reg spi_receiver_strobe_sd_r = 0; +reg spi_transfer_end_sd_r = 1; +reg [7:0] spi_byte_in_sd; + +// direct SD +always@(posedge sck or posedge ss_sd) begin + if(ss_sd == 1) begin + bit_cnt_sd <= 0; + spi_transfer_end_sd_r <= 1; + end else begin + bit_cnt_sd <= bit_cnt_sd + 1'd1; + spi_transfer_end_sd_r <= 0; + if(&bit_cnt_sd) begin + // finished reading a byte, prepare to transfer to clk_sys + spi_byte_in_sd <= { sbuf_sd, sdi}; + spi_receiver_strobe_sd_r <= ~spi_receiver_strobe_sd_r; + end else + sbuf_sd[6:0] <= { sbuf_sd[5:0], sdi }; + end +end + +// SPI transmitter FPGA -> IO +// CMD_IDEDAT is required before the first sector of a write commands +// and just before the _first_ one, even with multiple sector writes. +wire [7:0] cmdcode = write_start ? CMD_IDEDAT : newcmd ? CMD_IDECMD : 8'h0; +wire [4:0] tf_o_pos = byte_cnt - 4'd5; + +// need to know the ATA command sent by Archie for some local processing here +reg [7:0] ide_cmd; + +always@(negedge sck or posedge ss) begin + reg [7:0] dout_r; + + if(ss == 1) begin + sdo <= 1'bZ; + end else begin + + if (&bit_cnt) begin + case(cmd) + CMD_IDE_REGS_RD: + begin + // send task file regs + dout_r <= ide_reg_i; + ide_reg_i_adr <= tf_o_pos[3:1]; + if (tf_o_pos[3:1] == 3'd7) ide_cmd <= ide_reg_i; + end + + CMD_IDE_DATA_RD: dout_r <= ide_data_i; + + default: dout_r <= cmdcode; + + endcase + end + sdo <= (cmd == 0) ? cmdcode[~bit_cnt] : dout_r[~bit_cnt]; + end +end + // SPI receiver IO -> FPGA reg spi_receiver_strobe_r = 0; @@ -90,6 +174,7 @@ always@(posedge sck or posedge ss) begin if(ss == 1) begin spi_transfer_end_r <= 1; + cmd <= 0; end else begin spi_transfer_end_r <= 0; @@ -97,11 +182,16 @@ always@(posedge sck or posedge ss) begin // finished reading a byte, prepare to transfer to clk_sys spi_byte_in <= { sbuf, sdi}; spi_receiver_strobe_r <= ~spi_receiver_strobe_r; + if (!byte_cnt) cmd <= { sbuf, sdi }; end else sbuf[6:0] <= { sbuf[5:0], sdi }; end end +reg newcmd = 0; +reg write_req = 0; +reg write_start = 0; + // Process bytes from SPI at the clk_sys domain always @(posedge clk) begin @@ -110,10 +200,45 @@ always @(posedge clk) begin reg spi_receiver_strobeD; reg spi_transfer_endD; reg [7:0] acmd; - reg [3:0] abyte_cnt; // counts bytes + reg [4:0] abyte_cnt; // counts bytes + + reg spi_receiver_strobe_sd; + reg spi_transfer_end_sd; + reg spi_receiver_strobe_sdD; + reg spi_transfer_end_sdD; + reg [4:0] abyte_cnt_sd; wr <= 0; + // This "state-machine" is messy, but the firmware has to be clean up + // to make it more clear. And that would require changes in Minimig, too. + if (reset) begin + newcmd <= 0; + write_req <= 0; + write_start <= 0; + end + if (ide_req) begin + ide_data_addr <= 0; + ide_err <= 0; + newcmd <= 1; + write_start <= write_req; + end + ide_reg_we <= 0; + ide_ack <= 0; + + ide_data_we <= 0; + if (ide_data_we) begin + ide_data_addr <= ide_data_addr + 1'd1; + newcmd <= 0; + end + + ide_data_rd <= 0; + if (ide_data_rd) begin + ide_data_addr <= ide_data_addr + 1'b1; + write_req <= 0; + write_start <= 0; + end + //synchronize between SPI and sys clock domains spi_receiver_strobeD <= spi_receiver_strobe_r; spi_receiver_strobe <= spi_receiver_strobeD; @@ -132,6 +257,39 @@ always @(posedge clk) begin acmd <= spi_byte_in; end else begin case(acmd) + // IDE commands + CMD_IDE_STATUS_WR: + if (abyte_cnt == 1) begin + // "real" status register handling inside the IDE module, + // since firmware status codes are not real ATA-1 status codes + // (I wonder how it works for Amiga) + if (spi_byte_in[7]) ide_ack <= 1; // IDE_STATUS_END + if (spi_byte_in[4]) newcmd <= 0; // IDE_STATUS_IRQ + if (spi_byte_in[2] || ((ide_cmd == 8'h30 || ide_cmd == 8'hc5) && spi_byte_in[4] && ~spi_byte_in[7])) write_req <= 1; + if (spi_byte_in[1]) ide_err <= 1; // IDE_STATUS_ERR + end + + CMD_IDE_REGS_WR: + begin + ide_reg_o <= spi_byte_in; + if (abyte_cnt == 9) begin ide_reg_o_adr <= 3'd1; ide_reg_we <= 1; end // error + if (abyte_cnt == 11) begin ide_reg_o_adr <= 3'd2; ide_reg_we <= 1; end // sector count + if (abyte_cnt == 13) begin ide_reg_o_adr <= 3'd3; ide_reg_we <= 1; end // sector number + if (abyte_cnt == 15) begin ide_reg_o_adr <= 3'd4; ide_reg_we <= 1; end // cyl low + if (abyte_cnt == 17) begin ide_reg_o_adr <= 3'd5; ide_reg_we <= 1; end // cyl high + if (abyte_cnt == 19) begin ide_reg_o_adr <= 3'd6; ide_reg_we <= 1; end // drive/head + end + + CMD_IDE_DATA_WR: + if (abyte_cnt > 5) begin + ide_data_we <= 1; + ide_data_o <= spi_byte_in; + end + + CMD_IDE_DATA_RD: + if (abyte_cnt > 4) ide_data_rd <= 1; + + // file transfer commands UIO_FILE_TX: begin // prepare @@ -158,6 +316,28 @@ always @(posedge clk) begin endcase; end end + + // direct-sd connection + // synchronize between SPI and sys clock domains + spi_receiver_strobe_sdD <= spi_receiver_strobe_sd_r; + spi_receiver_strobe_sd <= spi_receiver_strobe_sdD; + spi_transfer_end_sdD <= spi_transfer_end_sd_r; + spi_transfer_end_sd <= spi_transfer_end_sdD; + + // strobe is set whenever a valid byte has been received + if (~spi_transfer_end_sdD & spi_transfer_end_sd) begin + abyte_cnt_sd <= 0; + end else if (spi_receiver_strobe_sdD ^ spi_receiver_strobe_sd) begin + + if(~&abyte_cnt_sd) + abyte_cnt_sd <= abyte_cnt_sd + 1'd1; + + if (abyte_cnt_sd == 0 || ide_data_addr != 0) begin // filter spurious byte at the end + ide_data_we <= 1; + ide_data_o <= spi_byte_in_sd; + end + end + end endmodule diff --git a/cores/archie/rtl/archimedes_top.v b/cores/archie/rtl/archimedes_top.v index bf02d73..a6d85b6 100644 --- a/cores/archie/rtl/archimedes_top.v +++ b/cores/archie/rtl/archimedes_top.v @@ -80,6 +80,21 @@ module archimedes_top( input sd_dout_strobe, input sd_din_strobe, + // connection to the IDE controller + output ide_req, // new command request + input ide_err, + input ide_ack, // command finished on the IO controller side + input [2:0] ide_reg_o_adr,// requested task file register index + output [7:0] ide_reg_o, // task file register out + input ide_reg_we, // task file register write strobe from IO controller + input [2:0] ide_reg_i_adr, + input [7:0] ide_reg_i, // task file register input + input [8:0] ide_data_addr, + output [7:0] ide_data_o, + input [7:0] ide_data_i, + input ide_data_rd, + input ide_data_we, + // connection to keyboard controller output [7:0] KBD_OUT_DATA, output KBD_OUT_STROBE, @@ -305,7 +320,10 @@ podules PODULES( .wb_dat_o ( pod_dat_o ), .wb_dat_i ( cpu_dat_o[15:0] ), - .wb_adr ( cpu_address[15:2] ) + .wb_adr ( cpu_address[15:2] ), + + .ide_sel ( ide_sel ), + .ide_din ( ide_dat_o ) ); wire [7:0] floppy_dat_o; @@ -356,6 +374,37 @@ fdc1772 #(.CLK(40000000)) FDC1772 ( .floppy_reset ( floppy_reset ) ); +wire [15:0] ide_dat_o; +wire ide_sel; + +ide IDE ( + + .clk ( CLKCPU_I ), + .reset ( RESET_I ), + + .ide_sel ( ide_sel ), + .ide_we ( cpu_we ), + .ide_reg ( cpu_address[4:2] ), + .ide_dat_o ( ide_dat_o ), + .ide_dat_i ( cpu_dat_o[31:16] ), + + .ide_req ( ide_req ), + .ide_ack ( ide_ack ), + .ide_err ( ide_err ), + + .ide_reg_o_adr ( ide_reg_o_adr ), + .ide_reg_o ( ide_reg_o ), + .ide_reg_we ( ide_reg_we ), + .ide_reg_i_adr ( ide_reg_i_adr ), + .ide_reg_i ( ide_reg_i ), + + .ide_data_addr ( ide_data_addr ), + .ide_data_o ( ide_data_o ), + .ide_data_i ( ide_data_i ), + .ide_data_rd ( ide_data_rd ), + .ide_data_we ( ide_data_we ) +); + wire [7:0] latches_dat_o; wire latches_en = ioc_cs & ioc_select[5] & (ioc_speed == 2'd2); diff --git a/cores/archie/rtl/ide.sv b/cores/archie/rtl/ide.sv new file mode 100644 index 0000000..091a8e0 --- /dev/null +++ b/cores/archie/rtl/ide.sv @@ -0,0 +1,199 @@ +// +// ide.sv +// +// Copyright (c) 2019 György Szombathelyi +// +// This source file is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published +// by the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This source file is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +module ide ( + input clk, // system clock. + input reset, + + input ide_sel, + input ide_we, + input [2:0] ide_reg, + input [15:0] ide_dat_i, + output reg [15:0] ide_dat_o, + + // place any signals that need to be passed up to the top after here. + output reg ide_req, + input ide_err, + input ide_ack, + + input [2:0] ide_reg_o_adr, + output reg [7:0] ide_reg_o, + input ide_reg_we, + input [2:0] ide_reg_i_adr, + input [7:0] ide_reg_i, + + input [8:0] ide_data_addr, + output [7:0] ide_data_o, + input [7:0] ide_data_i, + input ide_data_rd, + input ide_data_we +); + +assign ide_req = ide_cmd_req | ide_sector_req; + +reg [7:0] taskfile[8]; +reg [7:0] status; + +// read from Task File Registers +always @(*) begin + reg [7:0] ide_dat_b; + //cpu read + ide_dat_b = (ide_reg == 3'd7) ? { status[7:1], ide_err } : taskfile[ide_reg]; + ide_dat_o = 16'hFFFF; + if (ide_sel && !ide_we) begin + ide_dat_o = (ide_reg == 3'd0) ? data_out : { ide_dat_b, ide_dat_b }; + end + + // IO controller read + ide_reg_o = taskfile[ide_reg_o_adr]; +end + +reg ide_cmd_req; +// write to Task File Registers +always @(posedge clk) begin + ide_cmd_req <= 0; + // cpu write + if (ide_sel && ide_we) begin + taskfile[ide_reg] <= ide_dat_i[7:0]; + // writing to the command register triggers the IO controller + if (ide_reg == 3'd7) ide_cmd_req <= 1; + end + + // IO controller write + if (ide_reg_we) taskfile[ide_reg_i_adr] <= ide_reg_i; +end + +reg ide_sector_req; + +// status register handling +always @(posedge clk) begin + reg [7:0] sector_count; + + if (reset) begin + status <= 8'h48; + ide_sector_req <= 0; + sector_count <= 8'd1; + end else begin + // write to command register starts the execution + if (ide_sel && ide_we && ide_reg == 3'd7) begin + sector_count <= taskfile[2]; + case (taskfile[7]) + 8'h30, 8'hc5: status <= 8'h08; // request data + default: status <= 8'h80; // busy + endcase + end + + if (ide_ack) begin + case (taskfile[7]) + 8'hec : status <= 8'h08; // ready to transfer + 8'h20, 8'h30, 8'hc4, 8'hc5: ; + default: status <= 8'h40; // ready + endcase + end + + // sector buffer - IO controller side + if ((ide_data_rd | ide_data_we) & ide_data_addr == 9'h1ff) status <= 8'h08; // sector buffer consumed/filled, ready to transfer + if (ide_data_rd | ide_data_we) ide_sector_req <= 0; + + // sector buffer - CPU side + if (ide_sel_d && ~ide_sel && ide_reg == 3'd0 && data_addr == 8'hff) begin + status <= 8'h40; // ready + case (taskfile[7]) + 8'h20, 8'hc4: // reads + begin + sector_count <= sector_count - 1'd1; + if (sector_count != 1) ide_sector_req <= 1; // request the next sector + end + 8'h30, 8'hc5: + begin + ide_sector_req <= 1; // write, signals the write buffer is ready + status <= 8'h80; // busy + end + default: ; + endcase + + end + end +end + +reg [7:0] data_addr; +wire [15:0] data_out; +reg ide_sel_d; + +// read/write data register +always @(posedge clk) begin + ide_sel_d <= ide_sel; + if (ide_sel && ide_we && ide_reg == 3'd7) data_addr <= 0; + if (ide_sel_d && ~ide_sel && ide_reg == 3'd0) data_addr <= data_addr + 1'd1; +end + +// mixed-width sector buffer +ide_dpram ide_databuf ( + .clock ( clk ), + + .address_a ( data_addr ), + .data_a ( ide_dat_i ), + .wren_a ( ide_sel && ide_we && ide_reg == 3'd0 ), + .q_a ( data_out ), + + .address_b ( ide_data_addr ), + .data_b ( ide_data_i ), + .wren_b ( ide_data_we ), + .q_b ( ide_data_o ) +); + +endmodule + + +module ide_dpram +( + input clock, + + input [7:0] address_a, + input [15:0] data_a, + input wren_a, + output reg [15:0] q_a, + + input [8:0] address_b, + input [7:0] data_b, + input wren_b, + output reg [7:0] q_b +); + +reg [1:0][7:0] ram[256]; + +always @(posedge clock) begin + if(wren_a) begin + ram[address_a] <= data_a; + q_a <= data_a; + end else begin + q_a <= ram[address_a]; + end +end + +always @(posedge clock) begin + if(wren_b) begin + ram[address_b[8:1]][address_b[0]] <= data_b; + q_b <= data_b; + end else begin + q_b <= ram[address_b[8:1]][address_b[0]]; + end +end + +endmodule diff --git a/cores/archie/rtl/podules.v b/cores/archie/rtl/podules.v index 5c8d784..d553fbd 100644 --- a/cores/archie/rtl/podules.v +++ b/cores/archie/rtl/podules.v @@ -29,24 +29,26 @@ module podules( - input clkcpu, // system cpu clock. - input clk8m_en, // goes high in sync with 32m clock to give simulated 8mhz - input clk2m_en, // goes high in sync with 32m clock to give simulated 2mhz + input clkcpu, // system cpu clock. + input clk8m_en, // goes high in sync with 32m clock to give simulated 8mhz + input clk2m_en, // goes high in sync with 32m clock to give simulated 2mhz - input rst_i, // reset + input rst_i, // reset - input [1:0] speed_i, // podule access speed. (redundant except for address decode). + input [1:0] speed_i, // podule access speed. (redundant except for address decode). // "wishbone bus" the ack is externally generated currently. - input wb_cyc, - input wb_stb, - input wb_we, + input wb_cyc, + input wb_stb, + input wb_we, - input [15:2] wb_adr, // la - input [15:0] wb_dat_i, // bd - output[15:0] wb_dat_o // bd - + input [15:2] wb_adr, // la + input [15:0] wb_dat_i, // bd + output [15:0] wb_dat_o, // bd + // place any signals that need to be passed up to the top after here. + output ide_sel, + input [15:0] ide_din ); localparam PODULE0 = 2'b00; @@ -54,27 +56,41 @@ localparam PODULE1 = 2'b01; localparam PODULE2 = 2'b10; localparam PODULE3 = 2'b11; -wire [1:0] podule_addr = wb_adr[15:14]; -wire [3:0] podule_select = podule_addr == PODULE0 ? 4'b0001 : - podule_addr == PODULE1 ? 4'b0010 : - podule_addr == PODULE2 ? 4'b0100 : - podule_addr == PODULE3 ? 4'b1000 : 4'd0; +wire [1:0] podule_addr = wb_adr[15:14]; +wire [3:0] podule_select = podule_addr == PODULE0 ? 4'b0001 : + podule_addr == PODULE1 ? 4'b0010 : + podule_addr == PODULE2 ? 4'b0100 : + podule_addr == PODULE3 ? 4'b1000 : 4'd0; -wire [15:0] pod0_dat; -wire [15:0] pod1_dat; -wire [15:0] pod2_dat; -wire [15:0] pod3_dat; - - -always @(posedge clkcpu) begin - - - -end +wire [15:0] pod0_dat; +wire [15:0] pod1_dat; +wire [15:0] pod2_dat; +wire [15:0] pod3_dat; // emulate a simple podule as a test for *PODULES -assign pod0_dat = wb_adr[13:2] == 12'd0 ? {8'd0, 8'b0_1010_000} : 16'hFFFF; - +// assign pod0_dat = wb_adr[13:2] == 12'd0 ? {8'd0, 8'b0_1010_000} : 16'hFFFF; + +// RISC Developments IDE Interface in Podule 0 + +reg [7:0] rd_rom[16384]; +reg [2:0] rd_page; +reg [7:0] rd_rom_q; + +initial begin + $readmemh("riscdevide_rom.hex", rd_rom); + rd_page <= 0; +end + +assign ide_sel = wb_stb && wb_cyc && podule_select[PODULE0] && wb_adr[13:10] == 4'hA; +wire page_sel = wb_stb && wb_cyc && podule_select[PODULE0] && wb_we && wb_adr[13:2] == 12'h800; + +always @(posedge clkcpu) begin + if (page_sel) rd_page <= wb_dat_i[2:0]; + rd_rom_q <= rd_rom[{rd_page, wb_adr[12:2]}]; +end + +assign pod0_dat = ide_sel ? ide_din : {8'd0, rd_rom_q}; + assign wb_dat_o = podule_select[PODULE0] ? pod0_dat : 16'hFFFF; endmodule diff --git a/cores/archie/rtl/riscdevide_rom.hex b/cores/archie/rtl/riscdevide_rom.hex new file mode 100644 index 0000000..86c2557 --- /dev/null +++ b/cores/archie/rtl/riscdevide_rom.hex @@ -0,0 +1,714 @@ +/* http://srecord.sourceforge.net/ */ +@00000000 00 03 00 97 00 23 00 00 00 00 00 00 00 00 00 00 80 D4 00 00 2C 07 00 +@00000017 00 F5 28 00 00 04 07 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +@0000002E 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +@00000045 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +@0000005C 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +@00000073 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +@0000008A 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +@000000A1 00 00 00 00 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FF FF EB 00 00 A0 +@000030F7 E3 3E 80 BD E8 25 44 69 72 20 69 64 65 66 73 3A 3A A4 00 25 42 61 63 +@0000310E 6B 00 3A A4 00 69 64 65 66 73 3A 3A 00 69 64 65 66 73 3A 44 69 73 6D +@00003125 6F 75 6E 74 20 A4 00 2E 24 00 69 64 65 66 73 3A 4E 61 6D 65 44 69 73 +@0000313C 63 20 3A A4 20 00 00 00 01 00 00 00 54 68 69 73 20 64 69 73 63 20 68 +@00003153 61 73 20 61 20 6E 61 6D 65 20 74 68 61 74 20 68 61 73 20 62 65 65 6E +@0000316A 20 73 65 65 6E 20 62 65 66 6F 72 65 2E 20 20 46 6F 72 67 65 74 20 74 +@00003181 68 65 20 6F 6C 64 20 6F 6E 65 3F 00 00 00 00 00 40 2D E9 50 10 8C E2 +@00003198 01 00 A0 E1 94 20 4F E2 9B FF FF EB 29 1E 8C E2 44 24 9F E5 00 20 81 +@000031AF E4 C5 1F 06 EF 00 80 BD 68 00 30 91 E4 03 00 32 E1 03 00 00 0A 00 20 +@000031C6 A0 E3 20 20 81 E5 16 10 81 E2 00 80 FD E8 00 00 E0 E3 3C 00 8C E5 00 +@000031DD 00 A0 E3 00 10 A0 E3 09 00 00 EF 00 50 A0 E1 F8 20 4F E2 29 1E 8C E2 +@000031F4 84 FF FF EB 29 0E 8C E2 05 00 02 EF 3C 00 8C 65 07 00 00 6A 29 2E 8C +@0000320B E2 05 00 A0 E3 0C 00 02 EF 3C 00 8C 65 16 00 4F E2 01 0C 40 E2 05 00 +@00003222 02 EF 3C 00 8C 65 0E 00 A0 E3 05 10 A0 E1 29 00 02 EF 3C 00 8C 65 3C +@00003239 00 9C E5 01 00 70 E3 2B 00 00 1F 29 1E 8C E2 01 00 D1 E4 00 20 A0 E3 +@00003250 00 20 C1 E7 00 80 FD E8 00 40 2D E9 A0 10 8C E2 10 00 81 E5 31 00 A0 +@00003267 E3 14 00 81 E5 00 00 A0 E3 0C 00 81 E5 18 00 81 E5 6D 20 4F E2 01 2C +@0000327E 42 E2 1C 10 81 E2 62 FF FF EB 01 10 41 E2 88 20 8C E2 00 00 D2 E4 20 +@00003295 00 50 E3 8F 20 4F 92 01 2C 42 92 5B FF FF EB 01 10 41 E2 84 20 4F E2 +@000032AC 01 2C 42 E2 57 FF FF EB 01 20 A0 E1 A0 10 8C E2 01 20 42 E0 03 20 82 +@000032C3 E2 03 20 C2 E3 00 20 81 E4 11 00 A0 E3 08 20 9C E5 E7 00 04 EF 00 80 +@000032DA FD E8 00 40 2D E9 04 00 91 E4 00 F1 8F E0 00 80 FD E8 33 00 00 EA 4E +@000032F1 00 00 EA 00 00 00 00 00 00 00 00 1F 00 00 EA FF FF FF EA 4C FF FF EB +@00003308 5C 20 8F E2 00 00 A0 E3 00 10 A0 E3 09 00 00 EF 01 00 2D E9 0E 00 A0 +@0000331F E3 31 10 A0 E3 29 00 00 EF 29 1E 8C E2 36 FF FF EB 29 0E 8C E2 EF 00 +@00003336 04 EF 29 0E 8C E2 05 00 02 EF 03 00 00 7A 03 00 00 EF 04 00 80 E2 02 +@0000334D 00 00 EF 03 00 00 EF 00 00 A0 E3 EF 00 04 EF 02 00 BD E8 0E 00 A0 E3 +@00003364 29 00 00 EF 00 80 FD E8 46 72 65 65 20 3A A4 00 56 65 72 69 66 79 20 +@0000337B 3A A4 00 00 00 2D FF FF EB 18 20 4F E2 DF FF FF EA 01 00 00 00 44 69 +@00003392 73 63 20 6E 61 6D 65 20 6D 75 73 74 20 62 65 20 61 74 20 6C 65 61 73 +@000033A9 74 20 74 77 6F 20 63 68 61 72 61 63 74 65 72 73 20 6C 6F 6E 67 00 00 +@000033C0 88 10 8C E2 94 20 8C E2 00 30 A0 E3 03 00 D1 E7 03 00 C2 E7 01 30 83 +@000033D7 E2 0B 00 53 E3 20 00 50 13 F9 FF FF 8A 03 00 53 E3 64 00 4F 32 2B 00 +@000033EE 00 3F 11 FF FF EB 00 00 30 E3 00 80 FD 18 0F 00 00 EB 50 10 8C E2 DD +@00003405 20 4F E2 02 2C 42 E2 FE FE FF EB 01 10 41 E2 94 20 8C E2 FD FE FF EB +@0000341C 50 00 8C E2 05 00 00 EF 02 FE FF EB 03 FF FF EB 00 80 FD E8 01 FF FF +@00003433 EB 00 00 30 E3 00 00 00 0B 00 80 FD E8 00 40 2D E9 A4 01 9F E5 82 FF +@0000344A FF EB 50 10 8C E2 3D 20 4F E2 03 2C 42 E2 EB FE FF EB 02 10 41 E2 88 +@00003461 20 8C E2 00 00 D2 E4 20 00 50 E3 63 20 4F 92 03 2C 42 92 E6 FE FF EB +@00003478 50 00 8C E2 05 00 00 EF 00 80 FD E8 1F 40 2D E9 03 00 A0 E1 FC 1F 04 +@0000348F EF 02 00 30 E3 1F 80 FD 18 38 00 9C E5 01 00 2D E9 38 30 8C E5 C0 06 +@000034A6 04 EF 38 FF FF EB 0F 00 A0 E1 C1 06 04 EF 00 F0 30 E3 01 00 BD 68 38 +@000034BD 00 8C 65 1F 80 FD 68 01 20 A0 E1 08 10 9D E5 00 00 A0 E3 03 00 81 E5 +@000034D4 CE FE FF EB 01 00 BD E8 38 00 8C E5 1F 40 BD E8 01 40 A0 E3 01 F2 DE +@000034EB E3 00 40 2D E9 01 00 30 E3 04 00 00 0A 02 00 30 E3 1B 00 00 0A 03 00 +@00003502 30 E3 28 00 00 0A 00 80 FD E8 1E 00 2D E9 03 00 A0 E1 50 10 8C E2 C5 +@00003519 1F 06 EF 1E 80 BD 68 02 40 A0 E1 16 10 81 E2 00 00 D1 E4 20 00 50 E3 +@00003530 3A 00 A0 B3 01 00 82 B4 03 10 A0 B1 0A 30 A0 E3 01 00 D1 E4 20 00 50 +@00003547 E3 00 00 A0 93 01 00 C2 E4 01 30 53 E2 00 00 30 13 F8 FF FF 1A 00 00 +@0000355E 30 E3 00 00 A0 13 01 00 C2 14 04 00 42 E0 1E 80 FD E8 0E 00 2D E9 03 +@00003575 00 A0 E1 50 10 8C E2 C5 1F 06 EF 0E 80 BD 68 10 00 91 E5 00 00 82 E4 +@0000358C 03 00 A0 E1 C3 1F 06 EF 0E 80 BD 68 04 00 82 E5 00 10 92 E4 00 10 41 +@000035A3 E0 08 10 82 E5 0E 80 FD E8 00 00 50 E1 00 40 BD E8 01 F2 DE E3 07 40 +@000035BA 2D E9 31 00 A0 E3 DC 10 4F E2 0C 20 A0 E1 01 00 A0 73 00 00 A0 63 4C +@000035D1 00 8C E5 07 80 FD E8 01 40 2D E9 4C 00 9C E5 00 00 50 E3 01 80 FD E8 +@000035E8 31 18 08 00 11 01 00 00 01 04 00 00 AD DE AD DE 31 32 34 00 52 65 6C +@000035FF 65 61 73 65 00 52 49 53 43 20 44 65 76 65 6C 6F 70 6D 65 6E 74 73 20 +@00003616 4C 74 64 20 28 55 4B 29 00 30 00 32 30 2D 4D 61 79 2D 39 32 00 FF FF +@0000362D FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003644 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@0000365B FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003672 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003689 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@000036A0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@000036B7 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@000036CE FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@000036E5 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@000036FC FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003713 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@0000372A FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003741 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003758 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@0000376F FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003786 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@0000379D FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@000037B4 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@000037CB FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@000037E2 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@000037F9 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003810 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003827 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@0000383E FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003855 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@0000386C FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003883 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@0000389A FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@000038B1 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@000038C8 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@000038DF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@000038F6 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@0000390D FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003924 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@0000393B FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003952 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003969 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003980 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003997 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@000039AE FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@000039C5 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@000039DC FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@000039F3 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003A0A FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003A21 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003A38 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003A4F FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003A66 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003A7D FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003A94 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003AAB FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003AC2 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003AD9 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003AF0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003B07 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003B1E FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003B35 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003B4C FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003B63 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003B7A FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003B91 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003BA8 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003BBF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003BD6 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003BED FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003C04 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003C1B FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003C32 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003C49 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003C60 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003C77 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003C8E FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003CA5 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003CBC FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003CD3 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003CEA FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003D01 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003D18 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003D2F FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003D46 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003D5D FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003D74 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003D8B FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003DA2 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003DB9 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003DD0 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003DE7 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003DFE FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003E15 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003E2C FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003E43 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003E5A FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003E71 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003E88 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003E9F FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003EB6 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003ECD FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003EE4 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003EFB FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003F12 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003F29 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003F40 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003F57 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003F6E FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003F85 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003F9C FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003FB3 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003FCA FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003FE1 FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF +@00003FF8 FF FF FF FF FF FF FF FF From 42a828913fd4607257c449946a5700c97212b80b Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi Date: Sat, 2 Nov 2019 18:59:56 +0100 Subject: [PATCH 2/2] Archie: register some SDRAM signals for better timing properties --- cores/archie/rtl/sdram/sdram_top.v | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/cores/archie/rtl/sdram/sdram_top.v b/cores/archie/rtl/sdram/sdram_top.v index 7033bc9..e78083e 100644 --- a/cores/archie/rtl/sdram/sdram_top.v +++ b/cores/archie/rtl/sdram/sdram_top.v @@ -77,6 +77,8 @@ reg [9:0] sd_refresh = 10'd0; reg sd_auto_refresh = 1'b0; reg sd_need_refresh = 1'b0; wire sd_req = wb_stb & wb_cyc & ~wb_ack; +reg sd_req_reg; +reg sd_cache_hit; reg [11:0] sd_active_row[3:0]; reg [3:0] sd_bank_active; wire [1:0] sd_bank = wb_adr[22:21]; @@ -170,6 +172,9 @@ always @(posedge sd_clk) begin sd_word <= sd_word + 1'd1; sd_dat[sd_word[2:1]][{sd_word[0],4'b0000} +:16] <= sd_dq; end + sd_req_reg <= sd_req; + sd_cache_hit <= ~wb_we && sd_last_adr[23:4] == wb_adr[23:4]; + // this is the auto refresh code. // it kicks in so that 8192 auto refreshes are // issued in a 64ms period. Other bus operations @@ -196,7 +201,7 @@ always @(posedge sd_clk) begin default: ; endcase - end else if ((sd_cycle != 0) | (sd_cycle == 0 && sd_req)) begin + end else if ((sd_cycle != 0) | (sd_cycle == 0 && sd_req_reg)) begin // while the cycle is active count. sd_cycle <= sd_cycle + 1'd1; @@ -204,7 +209,7 @@ always @(posedge sd_clk) begin CYCLE_PRECHARGE: begin sd_we <= wb_we; word_index <= 2'b00; - if (~wb_we && sd_last_adr[23:4] == wb_adr[23:4]) begin + if (sd_cache_hit) begin // this word is already in sd_dat, but where? word_index <= wb_adr[3:2] - sd_last_adr[3:2]; sd_done <= ~sd_done; @@ -281,7 +286,7 @@ always @(posedge sd_clk) begin sd_dat[0][15:0] <= sd_dq; sd_word <= 3'b001; end else - sd_cycle <= 5'd0; + sd_cycle <= CYCLE_END; end CYCLE_READ1: if (~sd_we) sd_done <= ~sd_done;