From a994ef500598ac00399efdc62fc44c9dfd23007e Mon Sep 17 00:00:00 2001
From: Gyorgy Szombathelyi <gyurco@freemail.hu>
Date: Sat, 18 Apr 2020 19:35:24 +0200
Subject: [PATCH] PlusToo: update the CPU and some internal stuff

---
 cores/plus_too/TG68K_ALU.vhd                  | 2211 +++++----
 cores/plus_too/TG68K_Pack.vhd                 |  430 +-
 cores/plus_too/TG68KdotC_Kernel.vhd           | 4202 ++++++++++-------
 cores/plus_too/addrController_top.v           |   37 +-
 cores/plus_too/dataController_top.v           |  109 +-
 cores/plus_too/floppy.v                       |   89 +-
 cores/plus_too/floppy_track_encoder.v         |   27 +-
 cores/plus_too/iwm.v                          |   47 +-
 cores/plus_too/ncr5380.v                      |  500 +-
 cores/plus_too/osd.v                          |  182 -
 cores/plus_too/pll.v                          |   16 +-
 cores/plus_too/plusToo_top.qsf                |  584 +--
 cores/plus_too/plusToo_top.sdc                |   30 +-
 .../{plusToo_top.v => plusToo_top.sv}         |  321 +-
 cores/plus_too/ps2.v                          |   35 +-
 cores/plus_too/ps2_kbd.v                      |   90 +-
 cores/plus_too/ps2_mouse.v                    |   66 +-
 cores/plus_too/scc.v                          |  282 +-
 cores/plus_too/scsi.v                         |  738 ++-
 cores/plus_too/sdram.v                        |   59 +-
 cores/plus_too/user_io.v                      |  410 --
 cores/plus_too/via.v                          |   48 +-
 cores/plus_too/videoShifter.v                 |   12 +-
 cores/plus_too/videoTimer.v                   |   59 +-
 24 files changed, 5238 insertions(+), 5346 deletions(-)
 delete mode 100644 cores/plus_too/osd.v
 rename cores/plus_too/{plusToo_top.v => plusToo_top.sv} (65%)
 delete mode 100644 cores/plus_too/user_io.v

diff --git a/cores/plus_too/TG68K_ALU.vhd b/cores/plus_too/TG68K_ALU.vhd
index d0e859d..9ddd1b6 100644
--- a/cores/plus_too/TG68K_ALU.vhd
+++ b/cores/plus_too/TG68K_ALU.vhd
@@ -1,932 +1,1279 @@
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
---                                                                          --
--- Copyright (c) 2009-2011 Tobias Gubener                                   -- 
--- Subdesign fAMpIGA by TobiFlex                                            --
---                                                                          --
--- This source file is free software: you can redistribute it and/or modify --
--- it under the terms of the GNU General Public License as published        --
--- by the Free Software Foundation, either version 3 of the License, or     --
--- (at your option) any later version.                                      --
---                                                                          --
--- This source file is distributed in the hope that it will be useful,      --
--- but WITHOUT ANY WARRANTY; without even the implied warranty of           --
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            --
--- GNU General Public License for more details.                             --
---                                                                          --
--- You should have received a copy of the GNU General Public License        --
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.    --
---                                                                          --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
-library ieee;
-use ieee.std_logic_1164.all;
-use ieee.std_logic_unsigned.all;
-use IEEE.numeric_std.all;
-use work.TG68K_Pack.all;
-
-entity TG68K_ALU is
-generic(
-		MUL_Mode : integer := 0;	--0=>16Bit,  1=>32Bit,  2=>switchable with CPU(1),  3=>no MUL,  
-		DIV_Mode : integer := 0		--0=>16Bit,  1=>32Bit,  2=>switchable with CPU(1),  3=>no DIV,  
-		);
-	   port(clk               	: in std_logic;
-        Reset	         	: in std_logic;
-        clkena_lw         	: in std_logic:='1';
-        execOPC         	: in bit;
-        exe_condition      	: in std_logic;
-        exec_tas		   	: in std_logic;
-        long_start		   	: in bit;
-        movem_presub	   	: in bit;
-        set_stop	   		: in bit;
-        Z_error 	        : in bit;
-        rot_bits 	      	: in std_logic_vector(1 downto 0);
-		exec                : in bit_vector(lastOpcBit downto 0);
-        OP1out          	: in std_logic_vector(31 downto 0);
-        OP2out          	: in std_logic_vector(31 downto 0);
-        reg_QA          	: in std_logic_vector(31 downto 0);
-        reg_QB          	: in std_logic_vector(31 downto 0);
-        opcode          	: in std_logic_vector(15 downto 0);
-        datatype 	      	: in std_logic_vector(1 downto 0);
-        exe_opcode         	: in std_logic_vector(15 downto 0);
-        exe_datatype       	: in std_logic_vector(1 downto 0);
-        sndOPC          	: in std_logic_vector(15 downto 0);
-        last_data_read	 	: in std_logic_vector(15 downto 0);
-        data_read		 	: in std_logic_vector(15 downto 0);
-        FlagsSR          	: in std_logic_vector(7 downto 0);
-		micro_state			: in micro_states;  
-		bf_ext_in       	: in std_logic_vector(7 downto 0);
-		bf_ext_out       	: out std_logic_vector(7 downto 0);
-		bf_shift      	 	: in std_logic_vector(5 downto 0);
-		bf_width        	: in std_logic_vector(5 downto 0);
-		bf_loffset        	: in std_logic_vector(4 downto 0);
-		      
-        set_V_Flag	        : buffer bit;
-        Flags         	 	: buffer std_logic_vector(7 downto 0);
-        c_out         	 	: buffer std_logic_vector(2 downto 0);
-        addsub_q       		: buffer std_logic_vector(31 downto 0);
-        ALUout	        	: out std_logic_vector(31 downto 0)
-        );
-end TG68K_ALU;
-
-architecture logic of TG68K_ALU is
------------------------------------------------------------------------------
------------------------------------------------------------------------------
--- ALU and more
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-    signal OP1in          : std_logic_vector(31 downto 0);
-    signal addsub_a       : std_logic_vector(31 downto 0);
-    signal addsub_b       : std_logic_vector(31 downto 0);
-    signal notaddsub_b    : std_logic_vector(33 downto 0);
-    signal add_result     : std_logic_vector(33 downto 0);
-    signal addsub_ofl     : std_logic_vector(2 downto 0);
-    signal opaddsub	      : bit;
-    signal c_in	          : std_logic_vector(3 downto 0);
-    signal flag_z         : std_logic_vector(2 downto 0);
-	signal set_Flags      : std_logic_vector(3 downto 0);	--NZVC
-	signal CCRin          : std_logic_vector(7 downto 0);
-    
-    signal niba_l		  : std_logic_vector(5 downto 0);
-    signal niba_h		  : std_logic_vector(5 downto 0);
-    signal niba_lc		  : std_logic;
-    signal niba_hc		  : std_logic;
-    signal bcda_lc		  : std_logic;
-    signal bcda_hc		  : std_logic;
-    signal nibs_l		  : std_logic_vector(5 downto 0);
-    signal nibs_h		  : std_logic_vector(5 downto 0);
-    signal nibs_lc		  : std_logic;
-    signal nibs_hc		  : std_logic;
-	
-    signal bcd_a		  : std_logic_vector(8 downto 0);
-    signal bcd_s		  : std_logic_vector(8 downto 0);
-    signal pack_out		  : std_logic_vector(15 downto 0);
-    signal pack_a		  : std_logic_vector(15 downto 0);
-    signal result_mulu    : std_logic_vector(63 downto 0);
-    signal result_div     : std_logic_vector(63 downto 0);
-    signal set_mV_Flag	  : std_logic;
-    signal V_Flag	      : bit;
-    
-	signal rot_rot        : std_logic;
-	signal rot_lsb        : std_logic;
-	signal rot_msb        : std_logic;
-	signal rot_X          : std_logic;
-	signal rot_C          : std_logic;
-    signal rot_out        : std_logic_vector(31 downto 0);
-	signal asl_VFlag      : std_logic;
-    signal bit_bits       : std_logic_vector(1 downto 0);
-    signal bit_number     : std_logic_vector(4 downto 0);
-    signal bits_out       : std_logic_vector(31 downto 0);
-    signal one_bit_in	  : std_logic;
-    signal bchg			  : std_logic;
-    signal bset			  : std_logic;
-    
-    signal mulu_sign	  : std_logic;
-    signal mulu_signext	  : std_logic_vector(16 downto 0);
-    signal muls_msb		  : std_logic;
-    signal mulu_reg       : std_logic_vector(63 downto 0);
-    signal FAsign		  : std_logic;
-    signal faktorA  	  : std_logic_vector(31 downto 0);
-    signal faktorB  	  : std_logic_vector(31 downto 0);
-    
-    signal div_reg        : std_logic_vector(63 downto 0);
-    signal div_quot       : std_logic_vector(63 downto 0);
-    signal div_ovl	      : std_logic;
-    signal div_neg	      : std_logic;
-    signal div_bit	      : std_logic;
-    signal div_sub        : std_logic_vector(32 downto 0);
-    signal div_over       : std_logic_vector(32 downto 0);
-    signal nozero         : std_logic;
-    signal div_qsign	  : std_logic;
-    signal divisor        : std_logic_vector(63 downto 0);
-    signal divs	  		  : std_logic;
-    signal signedOP  	  : std_logic;
-    signal OP1_sign		  : std_logic;
-    signal OP2_sign  	  : std_logic;
-    signal OP2outext      : std_logic_vector(15 downto 0);
-    
-    signal in_offset        : std_logic_vector(5 downto 0);
---    signal in_width         : std_logic_vector(5 downto 0);
-    signal datareg       : std_logic_vector(31 downto 0);
-    signal insert       : std_logic_vector(31 downto 0);
---    signal bf_result        : std_logic_vector(31 downto 0);
---    signal bf_offset        : std_logic_vector(5 downto 0);
---    signal bf_width         : std_logic_vector(5 downto 0);
---    signal bf_firstbit      : std_logic_vector(5 downto 0);
-    signal bf_datareg       : std_logic_vector(31 downto 0);
---    signal bf_out       : std_logic_vector(31 downto 0);
-    signal result           : std_logic_vector(39 downto 0);
-    signal result_tmp           : std_logic_vector(39 downto 0);
-    signal sign             : std_logic_vector(31 downto 0);
-    signal bf_set1          : std_logic_vector(39 downto 0);
-    signal inmux0           : std_logic_vector(39 downto 0);
-    signal inmux1           : std_logic_vector(39 downto 0);
-    signal inmux2           : std_logic_vector(39 downto 0);
-    signal inmux3           : std_logic_vector(31 downto 0);
-    signal copymux0           : std_logic_vector(39 downto 0);
-    signal copymux1           : std_logic_vector(39 downto 0);
-    signal copymux2           : std_logic_vector(39 downto 0);
-    signal copymux3           : std_logic_vector(31 downto 0);
-    signal bf_set2          : std_logic_vector(31 downto 0);
---    signal bf_set3          : std_logic_vector(31 downto 0);
-    signal shift            : std_logic_vector(39 downto 0);
-    signal copy            : std_logic_vector(39 downto 0);
---    signal offset       	: std_logic_vector(5 downto 0);
---    signal width            : std_logic_vector(5 downto 0);
-    signal bf_firstbit      : std_logic_vector(5 downto 0);
-	signal mux     : std_logic_vector(3 downto 0);
-    signal bitnr  : std_logic_vector(4 downto 0);
-    signal mask     : std_logic_vector(31 downto 0);
-    signal bf_bset  : std_logic;
-    signal bf_NFlag  : std_logic;
-    signal bf_bchg  : std_logic;
-    signal bf_ins  : std_logic;
-    signal bf_exts  : std_logic;
-    signal bf_fffo  : std_logic;
-    signal bf_d32  : std_logic;
-    signal bf_s32  : std_logic;
-    signal index  : std_logic_vector(4 downto 0);
---    signal i  : integer range 0 to 31;
---    signal i  : integer range 0 to 31;
---    signal i  : std_logic_vector(5 downto 0);
-BEGIN
------------------------------------------------------------------------------
--- set OP1in
------------------------------------------------------------------------------
-PROCESS (OP2out, reg_QB, opcode, OP1out, OP1in, exe_datatype, addsub_q, execOPC, exec,
-	     pack_out, bcd_a, bcd_s, result_mulu, result_div, exe_condition, bf_shift,
-	     Flags, FlagsSR, bits_out, exec_tas, rot_out, exe_opcode, result, bf_fffo, bf_firstbit, bf_datareg)
-	BEGIN
-		ALUout <= OP1in;
-		ALUout(7) <= OP1in(7) OR exec_tas;
-		IF exec(opcBFwb)='1' THEN
-			ALUout <= result(31 downto 0);
-			IF bf_fffo='1' THEN
-				ALUout <= (OTHERS =>'0');
-				ALUout(5 downto 0) <= bf_firstbit + bf_shift;
-			END IF;
-		END IF;
-		
-		OP1in <= addsub_q;
-		IF exec(opcABCD)='1' THEN	
-			OP1in(7 downto 0) <= bcd_a(7 downto 0);
-		ELSIF exec(opcSBCD)='1' THEN	
-			OP1in(7 downto 0) <= bcd_s(7 downto 0);
-		ELSIF exec(opcMULU)='1' AND MUL_Mode/=3 THEN
-			IF exec(write_lowlong)='1' AND (MUL_Mode=1 OR MUL_Mode=2) THEN
-				OP1in <= result_mulu(31 downto 0);	
-			ELSE	
-				OP1in <= result_mulu(63 downto 32);
-			END IF;		
-		ELSIF exec(opcDIVU)='1' AND DIV_Mode/=3 THEN
-			IF exe_opcode(15)='1' OR DIV_Mode=0 THEN
---			IF exe_opcode(15)='1' THEN
-				OP1in <= result_div(47 downto 32)&result_div(15 downto 0);	
-			ELSE		--64bit
-				IF exec(write_reminder)='1' THEN
-					OP1in <= result_div(63 downto 32);
-				ELSE	
-					OP1in <= result_div(31 downto 0);	
-				END IF;
-			END IF;
-		ELSIF exec(opcOR)='1' THEN
-			OP1in <= OP2out OR OP1out;
-		ELSIF exec(opcAND)='1' THEN
-			OP1in <= OP2out AND OP1out;
-		ELSIF exec(opcScc)='1' THEN
-			OP1in(7 downto 0) <= (others=>exe_condition); 
-		ELSIF exec(opcEOR)='1' THEN
-			OP1in <= OP2out XOR OP1out;
-		ELSIF exec(opcMOVE)='1' OR exec(exg)='1' THEN
---			OP1in <= OP2out(31 downto 8)&(OP2out(7)OR exec_tas)&OP2out(6 downto 0);
-			OP1in <= OP2out;
-		ELSIF exec(opcROT)='1' THEN
-			OP1in <= rot_out;
-		ELSIF exec(opcSWAP)='1' THEN	
-			OP1in <= OP1out(15 downto 0)& OP1out(31 downto 16);
-		ELSIF exec(opcBITS)='1' THEN
-			OP1in <= bits_out;	
-		ELSIF exec(opcBF)='1' THEN
-			OP1in <= bf_datareg;
-		ELSIF exec(opcMOVESR)='1' THEN
-			OP1in(7 downto 0) <= Flags;
-			IF exe_datatype="00" THEN
-				OP1in(15 downto 8) <= "00000000";
-			ELSE	
-				OP1in(15 downto 8) <= FlagsSR;
-			END IF;
-		ELSIF exec(opcPACK)='1' THEN
-			OP1in(15 downto 0) <= pack_out;
-		END IF;
-	END PROCESS;
-	
------------------------------------------------------------------------------
--- addsub
------------------------------------------------------------------------------
-PROCESS (OP1out, OP2out, execOPC, datatype, Flags, long_start, movem_presub, exe_datatype, exec, addsub_a, addsub_b, opaddsub,
-	     notaddsub_b, add_result, c_in, sndOPC)
-	BEGIN
-		addsub_a <= OP1out;
-		IF exec(get_bfoffset)='1' THEN	
-			IF sndOPC(11)='1' THEN
-				addsub_a <= OP1out(31)&OP1out(31)&OP1out(31)&OP1out(31 downto 3);
-			ELSE
-				addsub_a <= "000000000000000000000000000000"&sndOPC(10 downto 9);
-			END IF;	
-		END IF;
-		
-		IF exec(subidx)='1' THEN
-			opaddsub <= '1';
-		ELSE
-			opaddsub <= '0';
-		END IF;
-		
-		c_in(0) <='0';
-		addsub_b <= OP2out;
-		IF execOPC='0' AND exec(OP2out_one)='0' AND exec(get_bfoffset)='0'THEN
-			IF long_start='0' AND datatype="00" AND exec(use_SP)='0' THEN
-				addsub_b <= "00000000000000000000000000000001";
-			ELSIF long_start='0' AND exe_datatype="10" AND (exec(presub) OR exec(postadd) OR movem_presub)='1' THEN
-				IF exec(movem_action)='1' THEN
-					addsub_b <= "00000000000000000000000000000110";
-				ELSE
-					addsub_b <= "00000000000000000000000000000100";
-				END IF;
-			ELSE 
-				addsub_b <= "00000000000000000000000000000010";
-			END IF;
-		ELSE	
-			IF (exec(use_XZFlag)='1' AND Flags(4)='1') OR exec(opcCHK)='1' THEN
-				c_in(0) <= '1';
-			END IF;
-			opaddsub <= exec(addsub);
-		END IF;
-
-		IF opaddsub='0' OR long_start='1' THEN		--ADD
-			notaddsub_b <= '0'&addsub_b&c_in(0);
-		ELSE					--SUB
-			notaddsub_b <= NOT ('0'&addsub_b&c_in(0));
-		END IF;
-		add_result <= (('0'&addsub_a&notaddsub_b(0))+notaddsub_b);
-		c_in(1) <= add_result(9) XOR addsub_a(8) XOR addsub_b(8);
-		c_in(2) <= add_result(17) XOR addsub_a(16) XOR addsub_b(16);
-		c_in(3) <= add_result(33);
-		addsub_q <= add_result(32 downto 1); 
-		addsub_ofl(0) <= (c_in(1) XOR add_result(8) XOR addsub_a(7) XOR addsub_b(7));		--V Byte
-		addsub_ofl(1) <= (c_in(2) XOR add_result(16) XOR addsub_a(15) XOR addsub_b(15));	--V Word
-		addsub_ofl(2) <= (c_in(3) XOR add_result(32) XOR addsub_a(31) XOR addsub_b(31));	--V Long
-		c_out <= c_in(3 downto 1);
-	END PROCESS;
-	
-------------------------------------------------------------------------------
---ALU
-------------------------------------------------------------------------------		
-PROCESS (OP1out, OP2out, pack_a, niba_hc, niba_h, niba_l, niba_lc, nibs_hc, nibs_h, nibs_l, nibs_lc, Flags)
-	BEGIN
-                IF exe_opcode(7 downto 6) = "01" THEN
-                  -- PACK
-                  pack_a <= std_logic_vector(unsigned(OP1out(15 downto 0))+unsigned(OP2out(15 downto 0))); 
-                  pack_out <= "00000000" & pack_a(11 downto 8) & pack_a(3 downto 0);
-                ELSE
-                  -- UNPK
-                  pack_a <= "0000" & OP2out(7 downto 4) & "0000" & OP2out(3 downto 0);
-                  pack_out <= std_logic_vector(unsigned(OP1out(15 downto 0))+unsigned(pack_a)); 
-                END IF;
-  
---BCD_ARITH-------------------------------------------------------------------
-	--ADC
-		bcd_a <= niba_hc&(niba_h(4 downto 1)+('0',niba_hc,niba_hc,'0'))&(niba_l(4 downto 1)+('0',niba_lc,niba_lc,'0'));
-		niba_l <= ('0'&OP1out(3 downto 0)&'1') + ('0'&OP2out(3 downto 0)&Flags(4));
-		niba_lc <= niba_l(5) OR (niba_l(4) AND niba_l(3)) OR (niba_l(4) AND niba_l(2));
-
-		niba_h <= ('0'&OP1out(7 downto 4)&'1') + ('0'&OP2out(7 downto 4)&niba_lc);
-		niba_hc <= niba_h(5) OR (niba_h(4) AND niba_h(3)) OR (niba_h(4) AND niba_h(2));
-	--SBC			
-		bcd_s <= nibs_hc&(nibs_h(4 downto 1)-('0',nibs_hc,nibs_hc,'0'))&(nibs_l(4 downto 1)-('0',nibs_lc,nibs_lc,'0'));
-		nibs_l <= ('0'&OP1out(3 downto 0)&'0') - ('0'&OP2out(3 downto 0)&Flags(4));
-		nibs_lc <= nibs_l(5);
-
-		nibs_h <= ('0'&OP1out(7 downto 4)&'0') - ('0'&OP2out(7 downto 4)&nibs_lc);
-		nibs_hc <= nibs_h(5);
-	END PROCESS;
-			
------------------------------------------------------------------------------
--- Bits
------------------------------------------------------------------------------
-PROCESS (clk, exe_opcode, OP1out, OP2out, one_bit_in, bchg, bset, bit_Number, sndOPC, reg_QB)
-	BEGIN
-		IF rising_edge(clk) THEN		
-	        IF  clkena_lw = '1' THEN
-				bchg <= '0';
-				bset <= '0';
-				CASE opcode(7 downto 6) IS
-					WHEN "01" =>					--bchg
-						bchg <= '1';
-					WHEN "11" =>					--bset
-						bset <= '1';
-					WHEN OTHERS => NULL;			
-				END CASE;
-			END IF;
-		END IF;		
-		
-		IF exe_opcode(8)='0' THEN
-			IF exe_opcode(5 downto 4)="00" THEN
-				bit_number <= sndOPC(4 downto 0);
-			ELSE
-				bit_number <= "00"&sndOPC(2 downto 0);
-			END IF;
-		ELSE
-			IF exe_opcode(5 downto 4)="00" THEN
-				bit_number <= reg_QB(4 downto 0);
-			ELSE
-				bit_number <= "00"&reg_QB(2 downto 0);
-			END IF;
-		END IF;
-						
-		one_bit_in <= OP1out(to_integer(unsigned(bit_Number)));
-		bits_out <= OP1out;
-		bits_out(to_integer(unsigned(bit_Number))) <= (bchg AND NOT one_bit_in) OR bset ;
-	END PROCESS;
-
------------------------------------------------------------------------------
--- Bit Field
------------------------------------------------------------------------------	
-PROCESS (clk, mux, mask, bitnr, bf_ins, bf_bchg, bf_bset, bf_exts, bf_shift, inmux0, inmux1, inmux2, inmux3, bf_set2, OP1out, OP2out, result_tmp, bf_ext_in,
-	     shift, datareg, bf_NFlag, result, reg_QB, sign, bf_d32, bf_s32, copy, bf_loffset, copymux0, copymux1, copymux2, copymux3, bf_width)
-	BEGIN
-		IF rising_edge(clk) THEN		
-	        IF clkena_lw = '1' THEN
-				bf_bset <= '0';
-				bf_bchg <= '0';
-				bf_ins <= '0';
-				bf_exts <= '0';
-				bf_fffo <= '0';
-				bf_d32 <= '0';
-				bf_s32 <= '0';
-				CASE opcode(10 downto 8) IS
-					WHEN "010" => bf_bchg <= '1';				--BFCHG
-					WHEN "011" => bf_exts <= '1';				--BFEXTS
---					WHEN "100" => insert <= (OTHERS =>'0');		--BFCLR
-					WHEN "101" => bf_fffo <= '1';				--BFFFO
-					WHEN "110" => bf_bset <= '1';				--BFSET
-					WHEN "111" => bf_ins <= '1';					--BFINS
-								  bf_s32 <= '1';
-					WHEN OTHERS => NULL;
-				END CASE;	
-				IF opcode(4 downto 3)="00" THEN
-					bf_d32 <= '1';
-				END IF;
-				bf_ext_out <= result(39 downto 32);
-			END IF;
-		END IF;
-		shift <= bf_ext_in&OP2out;
-		IF bf_s32='1' THEN 
-			shift(39 downto 32) <= OP2out(7 downto 0);
-		END IF;
-			
-		IF bf_shift(0)='1' THEN 
-			inmux0 <= shift(0)&shift(39 downto 1);
-		ELSE	
-			inmux0 <= shift;
-		END IF;
-		IF bf_shift(1)='1' THEN 
-			inmux1 <= inmux0(1 downto 0)&inmux0(39 downto 2);
-		ELSE
-			inmux1 <= inmux0;
-		END IF;
-		IF bf_shift(2)='1' THEN 
-			inmux2 <= inmux1(3 downto 0)&inmux1(39 downto 4);
-		ELSE	
-			inmux2 <= inmux1;
-		END IF;
-		IF bf_shift(3)='1' THEN 
-			inmux3 <= inmux2(7 downto 0)&inmux2(31 downto 8);
-		ELSE	
-			inmux3 <= inmux2(31 downto 0);
-		END IF;
-		IF bf_shift(4)='1' THEN 
-			bf_set2(31 downto 0) <= inmux3(15 downto 0)&inmux3(31 downto 16);
-		ELSE	
-			bf_set2(31 downto 0) <= inmux3;
-		END IF;
-				
-		IF bf_loffset(4)='1' THEN 
-			copymux3 <= sign(15 downto 0)&sign(31 downto 16);
-		ELSE	
-			copymux3 <= sign;
-		END IF;
-		IF bf_loffset(3)='1' THEN 
-			copymux2(31 downto 0) <= copymux3(23 downto 0)&copymux3(31 downto 24);
-		ELSE	
-			copymux2(31 downto 0) <= copymux3;
-		END IF;
-		IF bf_d32='1' THEN 
-			copymux2(39 downto 32) <= copymux3(7 downto 0);
-		ELSE	
-			copymux2(39 downto 32) <= "11111111";
-		END IF;
-		IF bf_loffset(2)='1' THEN 
-			copymux1 <= copymux2(35 downto 0)&copymux2(39 downto 36);
-		ELSE	
-			copymux1 <= copymux2;
-		END IF;
-		IF bf_loffset(1)='1' THEN 
-			copymux0 <= copymux1(37 downto 0)&copymux1(39 downto 38);
-		ELSE
-			copymux0 <= copymux1;
-		END IF;
-		IF bf_loffset(0)='1' THEN 
-			copy <= copymux0(38 downto 0)&copymux0(39);
-		ELSE
-			copy <= copymux0;
-		END IF;
-			
-		result_tmp <= bf_ext_in&OP1out;
-		IF bf_ins='1' THEN
-			datareg <= reg_QB;
-		ELSE
-			datareg <= bf_set2;
-		END IF;
-		IF bf_ins='1' THEN
-			result(31 downto 0) <= bf_set2;
-			result(39 downto 32) <= bf_set2(7 downto 0);
-		ELSIF bf_bchg='1' THEN
-			result(31 downto 0) <= NOT OP1out;
-			result(39 downto 32) <= NOT bf_ext_in;
-		ELSE	
-			result <= (OTHERS => '0');
-		END IF;
-		IF bf_bset='1' THEN
-			result <= (OTHERS => '1');
-		END IF;
-		
-		sign <= (OTHERS => '0'); 
-		bf_NFlag <= datareg(to_integer(unsigned(bf_width)));
-		FOR i in 0 to 31 LOOP
-			IF i>bf_width(4 downto 0) THEN
-				datareg(i) <= '0'; 
-				sign(i) <= '1'; 
-			END IF;	
-		END LOOP;
-		
-		FOR i in 0 to 39 LOOP
-			IF copy(i)='1' THEN
-				result(i) <= result_tmp(i);
-			END IF;	
-		END LOOP;
-		
-		IF bf_exts='1' AND bf_NFlag='1' THEN
-			bf_datareg <= datareg OR sign;
-		ELSE	
-			bf_datareg <= datareg;
-		END IF;	
---	bf_datareg <= copy(31 downto 0);
---	result(31 downto 0)<=datareg;
---BFFFO	
-		mask <= datareg;
-		bf_firstbit <= '0'&bitnr;
-		bitnr <= "11111";
-		IF mask(31 downto 28)="0000" THEN
-			IF mask(27 downto 24)="0000" THEN
-				IF mask(23 downto 20)="0000" THEN
-					IF mask(19 downto 16)="0000" THEN
-						bitnr(4) <= '0';
-						IF mask(15 downto 12)="0000" THEN
-							IF mask(11 downto 8)="0000" THEN
-								bitnr(3) <= '0';
-								IF mask(7 downto 4)="0000" THEN
-									bitnr(2) <= '0';
-									mux <= mask(3 downto 0);
-								ELSE
-									mux <= mask(7 downto 4);
-								END IF;
-							ELSE
-								mux <= mask(11 downto 8);
-								bitnr(2) <= '0';
-							END IF;
-						ELSE
-							mux <= mask(15 downto 12);
-						END IF;
-					ELSE
-						mux <= mask(19 downto 16);
-						bitnr(3) <= '0';
-						bitnr(2) <= '0';
-					END IF;
-				ELSE
-					mux <= mask(23 downto 20);
-					bitnr(3) <= '0';
-				END IF;
-			ELSE
-				mux <= mask(27 downto 24);
-				bitnr(2) <= '0';
-			END IF;
-		ELSE
-			mux <= mask(31 downto 28);
-		END IF;
-		
-		IF mux(3 downto 2)="00" THEN
-			bitnr(1) <= '0';
-			IF mux(1)='0' THEN
-				bitnr(0) <= '0';
-			END IF;	
-		ELSE		
-			IF mux(3)='0' THEN
-				bitnr(0) <= '0';
-			END IF;	
-		END  IF;
-	END PROCESS;
-
------------------------------------------------------------------------------
--- Rotation
------------------------------------------------------------------------------
-PROCESS (exe_opcode, OP1out, Flags, rot_bits, rot_msb, rot_lsb, rot_rot, exec)
-	BEGIN
-		CASE exe_opcode(7 downto 6) IS
-			WHEN "00" =>					--Byte
-						rot_rot <= OP1out(7);
-			WHEN "01"|"11" =>				--Word
-						rot_rot <= OP1out(15);
-			WHEN "10" =>					--Long
-						rot_rot <= OP1out(31);
-			WHEN OTHERS => NULL;
-		END CASE;
-	
-		CASE rot_bits IS
-			WHEN "00" =>					--ASL, ASR
-						rot_lsb <= '0';
-						rot_msb <= rot_rot;
-			WHEN "01" =>					--LSL, LSR
-						rot_lsb <= '0';
-						rot_msb <= '0';
-			WHEN "10" =>					--ROXL, ROXR
-						rot_lsb <= Flags(4);
-						rot_msb <= Flags(4);
-			WHEN "11" =>					--ROL, ROR
-						rot_lsb <= rot_rot;
-						rot_msb <= OP1out(0);
-			WHEN OTHERS => NULL;
-		END CASE;
-	
-		IF exec(rot_nop)='1' THEN
-			rot_out <= OP1out;
-			rot_X <= Flags(4);
-			IF rot_bits="10" THEN	--ROXL, ROXR
-				rot_C <= Flags(4);
-			ELSE	
-				rot_C <= '0';
-			END IF;
-		ELSE
-			IF exe_opcode(8)='1' THEN		--left
-				rot_out <= OP1out(30 downto 0)&rot_lsb;
-				rot_X <= rot_rot;
-				rot_C <= rot_rot;
-			ELSE						--right
-				rot_X <= OP1out(0);
-				rot_C <= OP1out(0);
-				rot_out <= rot_msb&OP1out(31 downto 1);
-				CASE exe_opcode(7 downto 6) IS
-					WHEN "00" =>					--Byte
-						rot_out(7) <= rot_msb;
-					WHEN "01"|"11" =>				--Word
-						rot_out(15) <= rot_msb;
-					WHEN OTHERS => NULL;	
-				END CASE;
-			END IF;
-		END IF;
-	END PROCESS;
-		
-------------------------------------------------------------------------------
---CCR op
-------------------------------------------------------------------------------		
-PROCESS (clk, Reset, exe_opcode, exe_datatype, Flags, last_data_read, OP2out, flag_z, OP1IN, c_out, addsub_ofl,
-	     bcd_s, bcd_a, exec)
-	BEGIN
-		IF exec(andiSR)='1' THEN
-			CCRin <= Flags AND last_data_read(7 downto 0);
-		ELSIF exec(eoriSR)='1' THEN
-			CCRin <= Flags XOR last_data_read(7 downto 0);
-		ELSIF exec(oriSR)='1' THEN
-			CCRin <= Flags OR last_data_read(7 downto 0);
-		ELSE	
-			CCRin <= OP2out(7 downto 0);
-		END IF;	
-		
-------------------------------------------------------------------------------
---Flags
-------------------------------------------------------------------------------		
-		flag_z <= "000";
-		IF exec(use_XZFlag)='1' AND flags(2)='0' THEN
-			flag_z <= "000";
-		ELSIF OP1in(7 downto 0)="00000000" THEN
-			flag_z(0) <= '1';
-			IF OP1in(15 downto 8)="00000000" THEN
-				flag_z(1) <= '1';
-				IF OP1in(31 downto 16)="0000000000000000" THEN
-					flag_z(2) <= '1';	
-				END IF;
-			END IF;
-		END IF;
-		
---					--Flags NZVC
-		IF exe_datatype="00" THEN 						--Byte
-			set_flags <= OP1IN(7)&flag_z(0)&addsub_ofl(0)&c_out(0);
-			IF exec(opcABCD)='1' THEN	
-				set_flags(0) <= bcd_a(8);
-			ELSIF exec(opcSBCD)='1' THEN	
-				set_flags(0) <= bcd_s(8);
-			END IF;
-		ELSIF exe_datatype="10" OR exec(opcCPMAW)='1' THEN 						--Long
-			set_flags <= OP1IN(31)&flag_z(2)&addsub_ofl(2)&c_out(2);
-		ELSE 						--Word
-			set_flags <= OP1IN(15)&flag_z(1)&addsub_ofl(1)&c_out(1);
-		END IF;
-		
-		IF rising_edge(clk) THEN		
-	        IF clkena_lw = '1' THEN
-				IF exec(directSR)='1' OR set_stop='1' THEN
-					Flags(7 downto 0) <= data_read(7 downto 0);
-				END IF;	
-				IF exec(directCCR)='1' THEN
-					Flags(7 downto 0) <= data_read(7 downto 0);
-				END IF;	
-				
-				IF exec(opcROT)='1' THEN
-					asl_VFlag <= ((set_flags(3) XOR rot_rot) OR asl_VFlag);	
-				ELSE	
-					asl_VFlag <= '0';
-				END IF;	
-				IF exec(to_CCR)='1' THEN
-					Flags(7 downto 0) <= CCRin(7 downto 0);			--CCR
-				ELSIF Z_error='1' THEN
-					IF exe_opcode(8)='0' THEN
-						Flags(3 downto 0) <= reg_QA(31)&"000";
-					ELSE
-						Flags(3 downto 0) <= "0100";
-					END IF;		
-				ELSIF exec(no_Flags)='0' THEN
-					IF exec(opcADD)='1' THEN
-						Flags(4) <= set_flags(0);
-					ELSIF exec(opcROT)='1' AND rot_bits/="11" AND exec(rot_nop)='0' THEN
-						Flags(4) <= rot_X; 	
-					END IF;
-					
-					IF (exec(opcADD) OR exec(opcCMP))='1' THEN
-						Flags(3 downto 0) <= set_flags;
-					ELSIF exec(opcDIVU)='1' AND DIV_Mode/=3 THEN
-						IF V_Flag='1' THEN	
-							Flags(3 downto 0) <= "1010";
-						ELSE
-							Flags(3 downto 0) <= OP1IN(15)&flag_z(1)&"00";
-						END IF;
-					ELSIF exec(write_reminder)='1' AND MUL_Mode/=3 THEN -- z-flag MULU.l
-						Flags(3) <= set_flags(3);
-						Flags(2) <= set_flags(2) AND Flags(2);
-						Flags(1) <= '0';
-						Flags(0) <= '0';
-					ELSIF exec(write_lowlong)='1' AND (MUL_Mode=1 OR MUL_Mode=2) THEN  -- flag MULU.l
-						Flags(3) <= set_flags(3);
-						Flags(2) <= set_flags(2);
-						Flags(1) <= set_mV_Flag;	--V
-						Flags(0) <= '0';
-					ELSIF exec(opcOR)='1' OR exec(opcAND)='1' OR exec(opcEOR)='1' OR exec(opcMOVE)='1' OR exec(opcMOVEQ)='1' OR exec(opcSWAP)='1' OR exec(opcBF)='1' OR (exec(opcMULU)='1' AND MUL_Mode/=3) THEN
-						Flags(1 downto 0) <= "00";
-						Flags(3 downto 2) <= set_flags(3 downto 2);
-						IF exec(opcBF)='1' THEN
-							Flags(3) <= bf_NFlag;
-						END IF;	
-					ELSIF exec(opcROT)='1' THEN
-						Flags(3 downto 2) <= set_flags(3 downto 2);
-						Flags(0) <= rot_C;
-						IF rot_bits="00" AND ((set_flags(3) XOR rot_rot) OR asl_VFlag)='1' THEN		--ASL/ASR
-							Flags(1) <= '1';
-						ELSE		
-							Flags(1) <= '0';
-						END IF;	
-					ELSIF exec(opcBITS)='1' THEN
-						Flags(2) <= NOT one_bit_in;	
-					ELSIF exec(opcCHK)='1' THEN
-						IF exe_datatype="01" THEN 						--Word
-							Flags(3) <= OP1out(15);
-						ELSE	
-							Flags(3) <= OP1out(31);
-						END IF;	
-						IF OP1out(15 downto 0)=X"0000" AND (exe_datatype="01" OR OP1out(31 downto 16)=X"0000") THEN
-							Flags(2) <='1';
-						ELSE	
-							Flags(2) <='0';
-						END IF;	
-						Flags(1 downto 0) <= "00";
-					END IF;
-				END IF;	
-			END IF;	
-			Flags(7 downto 5) <= "000";
-		END IF;	
-	END PROCESS;
-	
--------------------------------------------------------------------------------
----- MULU/MULS
--------------------------------------------------------------------------------	
-PROCESS (exe_opcode, OP2out, muls_msb, mulu_reg, FAsign, mulu_sign, reg_QA, faktorB, result_mulu, signedOP)
-	BEGIN
-		IF (signedOP='1' AND faktorB(31)='1') OR FAsign='1' THEN
-			muls_msb <= mulu_reg(63);
-		ELSE
-			muls_msb <= '0';
-		END IF;	
-		
-		IF signedOP='1' AND faktorB(31)='1' THEN
-			mulu_sign <= '1';
-		ELSE
-			mulu_sign <= '0';
-		END IF;	
-		
-		IF MUL_Mode=0 THEN	-- 16 Bit
-			result_mulu(63 downto 32) <= muls_msb&mulu_reg(63 downto 33);	
-			result_mulu(15 downto 0) <= 'X'&mulu_reg(15 downto 1);	
-			IF mulu_reg(0)='1' THEN
-				IF FAsign='1' THEN
-					result_mulu(63 downto 47) <= (muls_msb&mulu_reg(63 downto 48)-(mulu_sign&faktorB(31 downto 16)));	
-				ELSE
-					result_mulu(63 downto 47) <= (muls_msb&mulu_reg(63 downto 48)+(mulu_sign&faktorB(31 downto 16)));	
-				END IF;
-			END IF;	
-		ELSE				-- 32 Bit
-			result_mulu <= muls_msb&mulu_reg(63 downto 1);	
-			IF mulu_reg(0)='1' THEN
-				IF FAsign='1' THEN
-					result_mulu(63 downto 31) <= (muls_msb&mulu_reg(63 downto 32)-(mulu_sign&faktorB));	
-				ELSE
-					result_mulu(63 downto 31) <= (muls_msb&mulu_reg(63 downto 32)+(mulu_sign&faktorB));	
-				END IF;
-			END IF;	
-		END IF;
-		IF exe_opcode(15)='1' OR MUL_Mode=0 THEN
-			faktorB(31 downto 16) <= OP2out(15 downto 0);
-			faktorB(15 downto 0) <= (OTHERS=>'0');
-		ELSE	
-			faktorB <= OP2out;
-		END IF;
-		IF (result_mulu(63 downto 32)=X"00000000" AND (signedOP='0' OR result_mulu(31)='0')) OR
-			(result_mulu(63 downto 32)=X"FFFFFFFF" AND signedOP='1' AND result_mulu(31)='1') THEN
-			set_mV_Flag <= '0';
-		ELSE	
-			set_mV_Flag <= '1';
-		END IF;
-	END PROCESS;
-	
-PROCESS (clk)
-	BEGIN
-		IF rising_edge(clk) THEN
-			IF clkena_lw='1' THEN
-				IF micro_state=mul1 THEN
-					mulu_reg(63 downto 32) <= (OTHERS=>'0');
-					IF divs='1' AND ((exe_opcode(15)='1' AND reg_QA(15)='1') OR (exe_opcode(15)='0' AND reg_QA(31)='1')) THEN				--MULS Neg faktor
-						FAsign <= '1';
-						mulu_reg(31 downto 0) <= 0-reg_QA;
-					ELSE
-						FAsign <= '0';
-						mulu_reg(31 downto 0) <= reg_QA;
-					END IF;	
-				ELSIF exec(opcMULU)='0' THEN
-					mulu_reg <= result_mulu;	
-				END IF;
-			END IF;
-		END IF;
-	END PROCESS;
-		
--------------------------------------------------------------------------------
----- DIVU/DIVS
--------------------------------------------------------------------------------
-		
-PROCESS (execOPC, OP1out, OP2out, div_reg, div_neg, div_bit, div_sub, div_quot, OP1_sign, div_over, result_div, reg_QA, opcode, sndOPC, divs, exe_opcode, reg_QB, 
-	     signedOP, nozero, div_qsign, OP2outext)
-	BEGIN
-		divs <= (opcode(15) AND opcode(8)) OR (NOT opcode(15) AND sndOPC(11));
-		divisor(15 downto 0) <= (OTHERS=> '0');
-		divisor(63 downto 32) <= (OTHERS=> divs AND reg_QA(31));
-		IF exe_opcode(15)='1' OR DIV_Mode=0 THEN
-			divisor(47 downto 16) <= reg_QA;
-		ELSE		
-			divisor(31 downto 0) <= reg_QA;
-			IF exe_opcode(14)='1' AND sndOPC(10)='1' THEN
-				divisor(63 downto 32) <= reg_QB;
-			END IF;
-		END IF;
-		IF signedOP='1' OR opcode(15)='0' THEN 
-			OP2outext <= OP2out(31 downto 16);
-		ELSE
-			OP2outext <= (OTHERS=> '0');
-		END IF;
-		IF signedOP='1' AND OP2out(31) ='1' THEN
-			div_sub <= (div_reg(63 downto 31))+('1'&OP2out(31 downto 0));
-		ELSE
-			div_sub <= (div_reg(63 downto 31))-('0'&OP2outext(15 downto 0)&OP2out(15 downto 0));
-		END IF;	
-		IF DIV_Mode=0 THEN
-			div_bit <= div_sub(16);
-		ELSE
-			div_bit <= div_sub(32);
-		END IF;
-		IF div_bit='1' THEN
-			div_quot(63 downto 32) <= div_reg(62 downto 31);	
-		ELSE
-			div_quot(63 downto 32) <= div_sub(31 downto 0);	
-		END IF;	
-		div_quot(31 downto 0) <= div_reg(30 downto 0)&NOT div_bit;
-		
-
-		IF ((nozero='1' AND signedOP='1' AND (OP2out(31) XOR OP1_sign XOR div_neg XOR div_qsign)='1' )	--Overflow DIVS
-			OR (signedOP='0' AND div_over(32)='0')) AND DIV_Mode/=3 THEN	--Overflow DIVU
-			set_V_Flag <= '1';
-		ELSE	
-			set_V_Flag <= '0';
-		END IF;
-	END PROCESS;
-	
-PROCESS (clk)
-	BEGIN
-		IF rising_edge(clk) THEN
-			IF clkena_lw='1' THEN
-				V_Flag <= set_V_Flag;
-				signedOP <= divs;
-				IF micro_state=div1 THEN
-					nozero <= '0';
-					IF divs='1' AND divisor(63)='1' THEN				-- Neg divisor
-						OP1_sign <= '1';
-						div_reg <= 0-divisor;
-					ELSE
-						OP1_sign <= '0';
-						div_reg <= divisor;
-					END IF;	
-				ELSE
-					div_reg <= div_quot;	
-					nozero <= NOT div_bit OR nozero;
-				END IF;
-				IF micro_state=div2 THEN
-					div_qsign <= NOT div_bit;
-					div_neg <= signedOP AND (OP2out(31) XOR OP1_sign);
-					IF DIV_Mode=0 THEN
-						div_over(32 downto 16) <= ('0'&div_reg(47 downto 32))-('0'&OP2out(15 downto 0));
-					ELSE	
-						div_over <= ('0'&div_reg(63 downto 32))-('0'&OP2out);
-					END IF;	
-				END IF;
-				IF exec(write_reminder)='0' THEN
---				IF exec_DIVU='0' THEN
-					IF div_neg='1' THEN
-						result_div(31 downto 0) <= 0-div_quot(31 downto 0);
-					ELSE
-						result_div(31 downto 0) <= div_quot(31 downto 0);
-					END IF;	
-					
-					IF OP1_sign='1' THEN
-						result_div(63 downto 32) <= 0-div_quot(63 downto 32);
-					ELSE
-						result_div(63 downto 32) <= div_quot(63 downto 32);
-					END IF;	
-				END IF;
-			END IF;
-		END IF;
-	END PROCESS;
-END;
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+--                                                                          --
+-- Copyright (c) 2009-2020 Tobias Gubener                                   -- 
+-- Patches by MikeJ, Till Harbaum, Rok Krajnk, ...                          --
+-- Subdesign fAMpIGA by TobiFlex                                            --
+--                                                                          --
+-- This source file is free software: you can redistribute it and/or modify --
+-- it under the terms of the GNU Lesser General Public License as published --
+-- by the Free Software Foundation, either version 3 of the License, or     --
+-- (at your option) any later version.                                      --
+--                                                                          --
+-- This source file is distributed in the hope that it will be useful,      --
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of           --
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            --
+-- GNU General Public License for more details.                             --
+--                                                                          --
+-- You should have received a copy of the GNU General Public License        --
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.    --
+--                                                                          --
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.std_logic_unsigned.all;
+use IEEE.numeric_std.all;
+use work.TG68K_Pack.all;
+
+entity TG68K_ALU is
+generic(
+		MUL_Mode : integer;			--0=>16Bit,	1=>32Bit,	2=>switchable with CPU(1),	3=>no MUL,  
+		MUL_Hardware : integer;		--0=>no,		1=>yes,  
+		DIV_Mode : integer;			--0=>16Bit,	1=>32Bit,	2=>switchable with CPU(1),	3=>no DIV,  
+		BarrelShifter :integer		--0=>no,		1=>yes,		2=>switchable with CPU(1)  
+		);
+	port(clk						: in std_logic;
+		Reset						: in std_logic;
+		clkena_lw				: in std_logic:='1';
+		CPU						: in std_logic_vector(1 downto 0):="00";  -- 00->68000  01->68010  11->68020(only some parts - yet)
+		execOPC					: in bit;
+		decodeOPC				: in bit;
+		exe_condition			: in std_logic;
+		exec_tas					: in std_logic;
+		long_start				: in bit;
+		non_aligned				: in std_logic;
+		movem_presub			: in bit;
+		set_stop					: in bit;
+		Z_error 					: in bit;
+		rot_bits					: in std_logic_vector(1 downto 0);
+		exec						: in bit_vector(lastOpcBit downto 0);
+		OP1out					: in std_logic_vector(31 downto 0);
+		OP2out					: in std_logic_vector(31 downto 0);
+		reg_QA					: in std_logic_vector(31 downto 0);
+		reg_QB					: in std_logic_vector(31 downto 0);
+		opcode					: in std_logic_vector(15 downto 0);
+		exe_opcode				: in std_logic_vector(15 downto 0);
+		exe_datatype			: in std_logic_vector(1 downto 0);
+		sndOPC					: in std_logic_vector(15 downto 0);
+		last_data_read			: in std_logic_vector(15 downto 0);
+		data_read				: in std_logic_vector(15 downto 0);
+		FlagsSR					: in std_logic_vector(7 downto 0);
+		micro_state				: in micro_states;  
+		bf_ext_in				: in std_logic_vector(7 downto 0);
+		bf_ext_out				: out std_logic_vector(7 downto 0);
+		bf_shift					: in std_logic_vector(5 downto 0);
+		bf_width					: in std_logic_vector(5 downto 0);
+		bf_ffo_offset			: in std_logic_vector(31 downto 0);
+		bf_loffset				: in std_logic_vector(4 downto 0);
+
+		set_V_Flag				: buffer bit;
+		Flags						: buffer std_logic_vector(7 downto 0);
+		c_out						: buffer std_logic_vector(2 downto 0);
+		addsub_q					: buffer std_logic_vector(31 downto 0);
+		ALUout					: out std_logic_vector(31 downto 0)
+	);
+end TG68K_ALU;
+
+architecture logic of TG68K_ALU is
+-----------------------------------------------------------------------------
+-----------------------------------------------------------------------------
+-- ALU and more
+-----------------------------------------------------------------------------
+-----------------------------------------------------------------------------
+	signal OP1in				: std_logic_vector(31 downto 0);
+	signal addsub_a			: std_logic_vector(31 downto 0);
+	signal addsub_b			: std_logic_vector(31 downto 0);
+	signal notaddsub_b		: std_logic_vector(33 downto 0);
+	signal add_result			: std_logic_vector(33 downto 0);
+	signal addsub_ofl			: std_logic_vector(2 downto 0);
+	signal opaddsub			: bit;
+	signal c_in					: std_logic_vector(3 downto 0);
+	signal flag_z				: std_logic_vector(2 downto 0);
+	signal set_Flags			: std_logic_vector(3 downto 0);	--NZVC
+	signal CCRin				: std_logic_vector(7 downto 0);
+	signal last_Flags1		: std_logic_vector(3 downto 0);	--NZVC
+    
+--BCD
+	signal bcd_pur				: std_logic_vector(9 downto 0);
+	signal bcd_kor				: std_logic_vector(8 downto 0);
+	signal halve_carry		: std_logic;
+	signal Vflag_a				: std_logic;
+	signal bcd_a_carry		: std_logic;
+	signal bcd_a				: std_logic_vector(8 downto 0);
+	signal result_mulu		: std_logic_vector(127 downto 0);
+	signal result_div			: std_logic_vector(63 downto 0);
+	signal result_div_pre	: std_logic_vector(31 downto 0);
+	signal set_mV_Flag		: std_logic;
+	signal V_Flag				: bit;
+	
+	signal rot_rot				: std_logic;
+	signal rot_lsb				: std_logic;
+	signal rot_msb				: std_logic;
+	signal rot_X				: std_logic;
+	signal rot_C				: std_logic;
+	signal rot_out				: std_logic_vector(31 downto 0);
+	signal asl_VFlag			: std_logic;
+	signal bit_bits			: std_logic_vector(1 downto 0);
+	signal bit_number			: std_logic_vector(4 downto 0);
+	signal bits_out			: std_logic_vector(31 downto 0);
+	signal one_bit_in			: std_logic;
+	signal bchg					: std_logic;
+	signal bset					: std_logic;
+	
+	signal mulu_sign			: std_logic;
+	signal mulu_signext		: std_logic_vector(16 downto 0);
+	signal muls_msb			: std_logic;
+	signal mulu_reg			: std_logic_vector(63 downto 0);
+	signal FAsign				: std_logic;
+	signal faktorA				: std_logic_vector(31 downto 0);
+	signal faktorB				: std_logic_vector(31 downto 0);
+	
+	signal div_reg				: std_logic_vector(63 downto 0);
+	signal div_quot			: std_logic_vector(63 downto 0);
+	signal div_ovl				: std_logic;
+	signal div_neg				: std_logic;
+	signal div_bit				: std_logic;
+	signal div_sub				: std_logic_vector(32 downto 0);
+	signal div_over			: std_logic_vector(32 downto 0);
+	signal nozero				: std_logic;
+	signal div_qsign			: std_logic;
+	signal dividend			: std_logic_vector(63 downto 0);
+	signal divs					: std_logic;
+	signal signedOP			: std_logic;
+	signal OP1_sign			: std_logic;
+	signal OP2_sign			: std_logic;
+	signal OP2outext			: std_logic_vector(15 downto 0);
+
+	signal in_offset			: std_logic_vector(5 downto 0);
+	signal datareg				: std_logic_vector(31 downto 0);
+	signal insert				: std_logic_vector(31 downto 0);
+	signal bf_datareg			: std_logic_vector(31 downto 0);
+	signal result				: std_logic_vector(39 downto 0);
+	signal result_tmp			: std_logic_vector(39 downto 0);
+	signal unshifted_bitmask: std_logic_vector(31 downto 0);
+	signal bf_set1				: std_logic_vector(39 downto 0);
+	signal inmux0				: std_logic_vector(39 downto 0);
+	signal inmux1				: std_logic_vector(39 downto 0);
+	signal inmux2				: std_logic_vector(39 downto 0);
+	signal inmux3				: std_logic_vector(31 downto 0);
+	signal shifted_bitmask	: std_logic_vector(39 downto 0);
+	signal bitmaskmux0		: std_logic_vector(37 downto 0);
+	signal bitmaskmux1		: std_logic_vector(35 downto 0);
+	signal bitmaskmux2		: std_logic_vector(31 downto 0);
+	signal bitmaskmux3		: std_logic_vector(31 downto 0);
+	signal bf_set2				: std_logic_vector(31 downto 0);
+	signal shift				: std_logic_vector(39 downto 0);
+	signal bf_firstbit		: std_logic_vector(5 downto 0);
+	signal mux					: std_logic_vector(3 downto 0);
+	signal bitnr				: std_logic_vector(4 downto 0);
+	signal mask					: std_logic_vector(31 downto 0);
+	signal mask_not_zero		: std_logic;
+	signal bf_bset				: std_logic;
+	signal bf_NFlag			: std_logic;
+	signal bf_bchg				: std_logic;
+	signal bf_ins				: std_logic;
+	signal bf_exts				: std_logic;
+	signal bf_fffo				: std_logic;
+	signal bf_d32				: std_logic;
+	signal bf_s32				: std_logic;
+	signal index				: std_logic_vector(4 downto 0);
+--	signal i						: integer range 0 to 31;
+--	signal i						: integer range 0 to 31;
+--	signal i						: std_logic_vector(5 downto 0);
+
+	signal hot_msb				: std_logic_vector(33 downto 0);
+	signal vector				: std_logic_vector(32 downto 0);
+	signal result_bs			: std_logic_vector(65 downto 0);
+	signal bit_nr				: std_logic_vector(5 downto 0);
+	signal bit_msb				: std_logic_vector(5 downto 0);
+	signal bs_shift			: std_logic_vector(5 downto 0);
+	signal bs_shift_mod		: std_logic_vector(5 downto 0);
+	signal asl_over			: std_logic_vector(32 downto 0);
+	signal asl_over_xor		: std_logic_vector(32 downto 0);
+	signal asr_sign			: std_logic_vector(32 downto 0);
+	signal msb					: std_logic;  
+	signal ring					: std_logic_vector(5 downto 0);
+	signal ALU					: std_logic_vector(31 downto 0);
+	signal BSout				: std_logic_vector(31 downto 0);
+	signal bs_V					: std_logic;  
+	signal bs_C					: std_logic;  
+	signal bs_X					: std_logic;  
+
+
+BEGIN
+-----------------------------------------------------------------------------
+-- set OP1in
+-----------------------------------------------------------------------------
+PROCESS (OP2out, reg_QB, opcode, OP1out, OP1in, exe_datatype, addsub_q, execOPC, exec,
+			bcd_a, result_mulu, result_div, exe_condition, bf_shift, bf_ffo_offset, mulu_reg, BSout,
+			Flags, FlagsSR, bits_out, exec_tas, rot_out, exe_opcode, result, bf_fffo, bf_firstbit, bf_datareg)
+	BEGIN
+		ALUout <= OP1in;
+		ALUout(7) <= OP1in(7) OR exec_tas;
+		IF exec(opcBFwb)='1' THEN
+			ALUout <= result(31 downto 0);
+			IF bf_fffo='1' THEN
+				ALUout <= bf_ffo_offset - bf_firstbit;
+			END IF;
+		END IF;
+		
+		OP1in <= addsub_q;
+		IF exec(opcABCD)='1' OR exec(opcSBCD)='1' THEN	
+			OP1in(7 downto 0) <= bcd_a(7 downto 0);
+		ELSIF exec(opcMULU)='1' AND MUL_Mode/=3 THEN
+			IF MUL_Hardware=0 THEN
+				IF exec(write_lowlong)='1' AND (MUL_Mode=1 OR MUL_Mode=2) THEN
+					OP1in <= result_mulu(31 downto 0);	
+				ELSE	
+					OP1in <= result_mulu(63 downto 32);
+				END IF;		
+			ELSE
+				IF exec(write_lowlong)='1' THEN --AND (MUL_Mode=1 OR MUL_Mode=2) THEN
+					OP1in <= result_mulu(31 downto 0);	
+				ELSE	
+--					OP1in <= result_mulu(63 downto 32);
+					OP1in <= mulu_reg(31 downto 0);
+				END IF;
+			END IF;
+		ELSIF exec(opcDIVU)='1' AND DIV_Mode/=3 THEN
+			IF exe_opcode(15)='1' OR DIV_Mode=0 THEN
+--			IF exe_opcode(15)='1' THEN
+				OP1in <= result_div(47 downto 32)&result_div(15 downto 0);	--word 
+			ELSE		--64bit
+				IF exec(write_reminder)='1' THEN
+					OP1in <= result_div(63 downto 32);
+				ELSE	
+					OP1in <= result_div(31 downto 0);	
+				END IF;
+			END IF;
+		ELSIF exec(opcOR)='1' THEN
+			OP1in <= OP2out OR OP1out;
+		ELSIF exec(opcAND)='1' THEN
+			OP1in <= OP2out AND OP1out;
+		ELSIF exec(opcScc)='1' THEN
+			OP1in(7 downto 0) <= (others=>exe_condition); 
+		ELSIF exec(opcEOR)='1' THEN
+			OP1in <= OP2out XOR OP1out;
+--		ELSIF exec(alu_move)='1' OR exec(exg)='1' THEN
+		ELSIF exec(alu_move)='1' THEN
+--			OP1in <= OP2out(31 downto 8)&(OP2out(7)OR exec_tas)&OP2out(6 downto 0);
+			OP1in <= OP2out;
+		ELSIF exec(opcROT)='1' THEN
+			OP1in <= rot_out;
+		ELSIF exec(exec_BS)='1' THEN
+			OP1in <= BSout;
+		ELSIF exec(opcSWAP)='1' THEN	
+			OP1in <= OP1out(15 downto 0)& OP1out(31 downto 16);
+		ELSIF exec(opcBITS)='1' THEN
+			OP1in <= bits_out;	
+		ELSIF exec(opcBF)='1' THEN
+			OP1in <= bf_datareg;		--new bitfieldvector for bfins - for others the old bitfieldvector
+		ELSIF exec(opcMOVESR)='1' THEN
+			OP1in(7 downto 0) <= Flags;
+			IF exe_opcode(9)='1' THEN
+				OP1in(15 downto 8) <= "00000000";
+			ELSE	
+				OP1in(15 downto 8) <= FlagsSR;
+			END IF;
+		ELSIF exec(opcPACK)='1' THEN	
+			OP1in(7 downto 0) <= addsub_q(11 downto 8) & addsub_q(3 downto 0);
+		END IF;
+	END PROCESS;
+	
+-----------------------------------------------------------------------------
+-- addsub
+-----------------------------------------------------------------------------
+PROCESS (OP1out, OP2out, execOPC, Flags, long_start, movem_presub, exe_datatype, exec, addsub_a, addsub_b, opaddsub,
+	     notaddsub_b, add_result, c_in, sndOPC, non_aligned)
+	BEGIN
+		addsub_a <= OP1out;
+		IF exec(get_bfoffset)='1' THEN	
+			IF sndOPC(11)='1' THEN
+				addsub_a <= OP1out(31)&OP1out(31)&OP1out(31)&OP1out(31 downto 3);
+			ELSE
+				addsub_a <= "000000000000000000000000000000"&sndOPC(10 downto 9);
+			END IF;	
+		END IF;
+		
+		IF exec(subidx)='1' THEN
+			opaddsub <= '1';
+		ELSE
+			opaddsub <= '0';
+		END IF;
+		
+		c_in(0) <='0';
+		addsub_b <= OP2out;
+		IF exec(opcUNPACK)='1' THEN
+			addsub_b(15 downto 0) <= "0000" & OP2out(7 downto 4) & "0000" & OP2out(3 downto 0);
+		ELSIF execOPC='0' AND exec(OP2out_one)='0' AND exec(get_bfoffset)='0'THEN
+			IF long_start='0' AND exe_datatype="00" AND exec(use_SP)='0' THEN
+				addsub_b <= "00000000000000000000000000000001";
+			ELSIF long_start='0' AND exe_datatype="10" AND (exec(presub) OR exec(postadd) OR movem_presub)='1' THEN
+				IF exec(movem_action)='1' THEN
+					addsub_b <= "00000000000000000000000000000110";
+				ELSE
+					addsub_b <= "00000000000000000000000000000100";
+				END IF;
+			ELSE 
+				addsub_b <= "00000000000000000000000000000010";
+			END IF;
+		ELSE	
+			IF (exec(use_XZFlag)='1' AND Flags(4)='1') OR exec(opcCHK)='1' THEN 
+				c_in(0) <= '1';
+			END IF;
+			opaddsub <= exec(addsub);
+		END IF;
+
+		-- patch for un-aligned movem --mikej
+		if (exec(movem_action) = '1') then
+		  if (movem_presub = '0') then -- up
+			if (non_aligned = '1') and (long_start = '0') then -- hold
+			  addsub_b <= (others => '0');
+			end if;
+		  else
+			if (non_aligned = '1') and (long_start = '0') then
+			  if (exe_datatype = "10") then
+				addsub_b <= "00000000000000000000000000001000";
+			  else
+				addsub_b <= "00000000000000000000000000000100";
+			  end if;
+			end if;
+		  end if;
+		end if;
+
+		IF opaddsub='0' OR long_start='1' THEN		--ADD
+			notaddsub_b <= '0'&addsub_b&c_in(0);
+		ELSE					--SUB
+			notaddsub_b <= NOT ('0'&addsub_b&c_in(0));
+		END IF;
+		add_result <= (('0'&addsub_a&notaddsub_b(0))+notaddsub_b);
+		c_in(1) <= add_result(9) XOR addsub_a(8) XOR addsub_b(8);
+		c_in(2) <= add_result(17) XOR addsub_a(16) XOR addsub_b(16);
+		c_in(3) <= add_result(33);
+		addsub_q <= add_result(32 downto 1); 
+		addsub_ofl(0) <= (c_in(1) XOR add_result(8) XOR addsub_a(7) XOR addsub_b(7));		--V Byte
+		addsub_ofl(1) <= (c_in(2) XOR add_result(16) XOR addsub_a(15) XOR addsub_b(15));	--V Word
+		addsub_ofl(2) <= (c_in(3) XOR add_result(32) XOR addsub_a(31) XOR addsub_b(31));	--V Long
+		c_out <= c_in(3 downto 1);
+	END PROCESS;
+	
+------------------------------------------------------------------------------
+--ALU
+------------------------------------------------------------------------------		
+PROCESS (OP1out, OP2out, CPU, exec, add_result, bcd_pur, bcd_a, bcd_kor, halve_carry, c_in)
+	BEGIN
+--BCD_ARITH-------------------------------------------------------------------
+--04.04.2017 by Tobiflex - BCD handling with all undefined behavior!
+		bcd_pur <= c_in(1)&add_result(8 downto 0);
+		bcd_kor <= "000000000";
+		halve_carry <= OP1out(4) XOR OP2out(4) XOR bcd_pur(5); 
+		IF halve_carry='1' THEN
+			bcd_kor(3 downto 0) <= "0110"; --  -6
+		END IF;
+		IF bcd_pur(9)='1' THEN
+			bcd_kor(7 downto 4) <= "0110"; --  -60
+		END IF;
+		IF exec(opcABCD)='1' THEN	
+			Vflag_a <= NOT bcd_pur(8) AND bcd_a(7); 
+--			bcd_pur <= ('0'&OP1out(7 downto 0)&'1') + ('0'&OP2out(7 downto 0)&Flags(4));
+			bcd_a <= bcd_pur(9 downto 1) + bcd_kor;
+			IF (bcd_pur(4) AND (bcd_pur(3) OR bcd_pur(2)))='1' THEN
+				bcd_kor(3 downto 0) <= "0110"; --  +6
+			END IF;
+			IF (bcd_pur(8) AND (bcd_pur(7) OR bcd_pur(6) OR (bcd_pur(5) AND bcd_pur(4) AND (bcd_pur(3) OR bcd_pur(2)))))='1' THEN
+				bcd_kor(7 downto 4) <= "0110"; --  +60 
+			END IF;
+		ELSE --opcSBCD	
+			Vflag_a <= bcd_pur(8) AND NOT bcd_a(7); 
+--			bcd_pur <= ('0'&OP1out(7 downto 0)&'0') - ('0'&OP2out(7 downto 0)&Flags(4));
+			bcd_a <= bcd_pur(9 downto 1) - bcd_kor;
+		END IF;
+		IF cpu(1)='1' THEN
+			Vflag_a <= '0'; --68020
+		END IF;
+		bcd_a_carry <= bcd_pur(9) OR bcd_a(8);
+	END PROCESS;
+			
+-----------------------------------------------------------------------------
+-- Bits
+-----------------------------------------------------------------------------
+PROCESS (clk, exe_opcode, OP1out, OP2out, reg_QB, one_bit_in, bchg, bset, bit_Number, sndOPC)
+	BEGIN
+		IF rising_edge(clk) THEN		
+	        IF  clkena_lw = '1' THEN
+				bchg <= '0';
+				bset <= '0';
+				CASE opcode(7 downto 6) IS
+					WHEN "01" =>					--bchg
+						bchg <= '1';
+					WHEN "11" =>					--bset
+						bset <= '1';
+					WHEN OTHERS => NULL;			
+				END CASE;
+			END IF;
+		END IF;		
+		
+		IF exe_opcode(8)='0' THEN
+			IF exe_opcode(5 downto 4)="00" THEN
+				bit_number <= sndOPC(4 downto 0);
+			ELSE
+				bit_number <= "00"&sndOPC(2 downto 0);
+			END IF;
+		ELSE
+			IF exe_opcode(5 downto 4)="00" THEN
+				bit_number <= reg_QB(4 downto 0);
+			ELSE
+				bit_number <= "00"&reg_QB(2 downto 0);
+			END IF;
+		END IF;
+						
+		one_bit_in <= OP1out(conv_integer(bit_Number));
+		bits_out <= OP1out;
+		bits_out(conv_integer(bit_Number)) <= (bchg AND NOT one_bit_in) OR bset ;
+	END PROCESS;
+
+-----------------------------------------------------------------------------
+-- Bit Field
+-----------------------------------------------------------------------------	
+
+PROCESS (clk, mux, mask, bitnr, bf_ins, bf_bchg, bf_bset, bf_exts, bf_shift, inmux0, inmux1, inmux2, inmux3, bf_set2, OP1out, OP2out, 
+			result_tmp, bf_ext_in, mask_not_zero, exec, shift, datareg, bf_NFlag, result, reg_QB, unshifted_bitmask, bf_d32, bf_s32, 
+			shifted_bitmask, bf_loffset, bitmaskmux0, bitmaskmux1, bitmaskmux2, bitmaskmux3, bf_width)
+	BEGIN
+		IF rising_edge(clk) THEN		
+			IF clkena_lw = '1' THEN
+				bf_bset <= '0';
+				bf_bchg <= '0';
+				bf_ins <= '0';
+				bf_exts <= '0';
+				bf_fffo <= '0';
+				bf_d32 <= '0';
+				bf_s32 <= '0';
+--		000-bftst, 001-bfextu, 010-bfchg, 011-bfexts, 100-bfclr, 101-bfff0, 110-bfset, 111-bfins	
+				IF opcode(5 downto 4) ="00" THEN
+					  bf_s32 <= '1';
+				END IF;
+				CASE opcode(10 downto 8) IS
+					WHEN "010" => bf_bchg <= '1';					--BFCHG
+					WHEN "011" => bf_exts <= '1';					--BFEXTS
+--					WHEN "100" => insert <= (OTHERS =>'0');	--BFCLR
+					WHEN "101" => bf_fffo <= '1';					--BFFFO
+					WHEN "110" => bf_bset <= '1';					--BFSET
+					WHEN "111" => bf_ins <= '1';					--BFINS
+									  bf_s32 <= '1';
+					WHEN OTHERS => NULL;
+				END CASE;
+				IF opcode(4 downto 3)="00" THEN
+					bf_d32 <= '1';
+				END IF;
+				bf_ext_out <= result(39 downto 32);
+			END IF;
+		END IF;
+		
+		IF bf_ins='1' THEN
+			datareg <= reg_QB;
+		ELSE
+			datareg <= bf_set2;
+		END IF;
+		
+		
+-- create bitmask for operation
+-- unshifted bitmask '0' => bit is in the Bitfieldvector
+--					 '1' => bit isn't in the Bitfieldvector
+-- Example bf_with=11    => "11111111 11111111 11111000 00000000"
+-- datareg 
+		unshifted_bitmask <= (OTHERS => '0'); 
+		FOR i in 0 to 31 LOOP
+			IF i>bf_width(4 downto 0) THEN
+				datareg(i) <= '0'; 
+				unshifted_bitmask(i) <= '1'; 			 
+			END IF;	
+		END LOOP;
+		
+		bf_NFlag <= datareg(conv_integer(bf_width));
+		IF bf_exts='1' AND bf_NFlag='1' THEN
+			bf_datareg <= datareg OR unshifted_bitmask;
+		ELSE	
+			bf_datareg <= datareg;
+		END IF;	
+		
+-- shift bitmask for operation
+		IF bf_loffset(4)='1' THEN 
+			bitmaskmux3 <= unshifted_bitmask(15 downto 0)&unshifted_bitmask(31 downto 16);
+		ELSE	
+			bitmaskmux3 <= unshifted_bitmask;
+		END IF;
+		IF bf_loffset(3)='1' THEN 
+			bitmaskmux2(31 downto 0) <= bitmaskmux3(23 downto 0)&bitmaskmux3(31 downto 24);
+		ELSE	
+			bitmaskmux2(31 downto 0) <= bitmaskmux3;
+		END IF;
+		IF bf_loffset(2)='1' THEN 
+			bitmaskmux1 <= bitmaskmux2&"1111";
+			IF bf_d32='1' THEN 
+				bitmaskmux1(3 downto 0) <= bitmaskmux2(31 downto 28);
+			END IF;
+		ELSE	
+			bitmaskmux1 <= "1111"&bitmaskmux2;
+		END IF;
+		IF bf_loffset(1)='1' THEN 
+			bitmaskmux0 <= bitmaskmux1&"11";
+			IF bf_d32='1' THEN 
+				bitmaskmux0(1 downto 0) <= bitmaskmux1(31 downto 30);
+			END IF;
+		ELSE
+			bitmaskmux0 <= "11"&bitmaskmux1;
+		END IF;
+		IF bf_loffset(0)='1' THEN 
+			shifted_bitmask <= '1'&bitmaskmux0&'1';
+			IF bf_d32='1' THEN 
+				shifted_bitmask(0) <= bitmaskmux0(31);
+			END IF;
+		ELSE
+			shifted_bitmask <= "11"&bitmaskmux0;
+		END IF;
+		
+		
+-- shift for ins 
+		shift <= bf_ext_in&OP2out;
+		IF bf_s32='1' THEN 
+			shift(39 downto 32) <= OP2out(7 downto 0);
+		END IF;
+			
+		IF bf_shift(0)='1' THEN 
+			inmux0 <= shift(0)&shift(39 downto 1);
+		ELSE	
+			inmux0 <= shift;
+		END IF;
+		IF bf_shift(1)='1' THEN 
+			inmux1 <= inmux0(1 downto 0)&inmux0(39 downto 2);
+		ELSE
+			inmux1 <= inmux0;
+		END IF;
+		IF bf_shift(2)='1' THEN 
+			inmux2 <= inmux1(3 downto 0)&inmux1(39 downto 4);
+		ELSE	
+			inmux2 <= inmux1;
+		END IF;
+		IF bf_shift(3)='1' THEN 
+			inmux3 <= inmux2(7 downto 0)&inmux2(31 downto 8);
+		ELSE	
+			inmux3 <= inmux2(31 downto 0);
+		END IF;
+		IF bf_shift(4)='1' THEN 
+			bf_set2(31 downto 0) <= inmux3(15 downto 0)&inmux3(31 downto 16);
+		ELSE	
+			bf_set2(31 downto 0) <= inmux3;
+		END IF;
+		
+		IF bf_ins='1' THEN
+			result(31 downto 0) <= bf_set2;
+			result(39 downto 32) <= bf_set2(7 downto 0);
+		ELSIF bf_bchg='1' THEN
+			result(31 downto 0) <= NOT OP2out;
+			result(39 downto 32) <= NOT bf_ext_in;
+		ELSE	
+			result <= (OTHERS => '0');
+		END IF;
+		IF bf_bset='1' THEN
+			result <= (OTHERS => '1');
+		END IF;
+-- 		
+		IF bf_ins='1' THEN
+			result_tmp <= bf_ext_in&OP1out;
+		ELSE	
+			result_tmp <= bf_ext_in&OP2out;
+		END IF;
+		FOR i in 0 to 39 LOOP
+			IF shifted_bitmask(i)='1' THEN	
+				result(i) <= result_tmp(i);   --restore old data
+			END IF;	
+		END LOOP;
+		
+--BFFFO	
+		mask <= datareg;
+		bf_firstbit <= ('0'&bitnr)+mask_not_zero;
+		bitnr <= "11111";
+		mask_not_zero <= '1'; 
+		IF mask(31 downto 28)="0000" THEN
+			IF mask(27 downto 24)="0000" THEN
+				IF mask(23 downto 20)="0000" THEN
+					IF mask(19 downto 16)="0000" THEN
+						bitnr(4) <= '0';
+						IF mask(15 downto 12)="0000" THEN
+							IF mask(11 downto 8)="0000" THEN
+								bitnr(3) <= '0';
+								IF mask(7 downto 4)="0000" THEN
+									bitnr(2) <= '0';
+									mux <= mask(3 downto 0);
+								ELSE
+									mux <= mask(7 downto 4);
+								END IF;
+							ELSE
+								mux <= mask(11 downto 8);
+								bitnr(2) <= '0';
+							END IF;
+						ELSE
+							mux <= mask(15 downto 12);
+						END IF;
+					ELSE
+						mux <= mask(19 downto 16);
+						bitnr(3) <= '0';
+						bitnr(2) <= '0';
+					END IF;
+				ELSE
+					mux <= mask(23 downto 20);
+					bitnr(3) <= '0';
+				END IF;
+			ELSE
+				mux <= mask(27 downto 24);
+				bitnr(2) <= '0';
+			END IF;
+		ELSE
+			mux <= mask(31 downto 28);
+		END IF;
+		
+		IF mux(3 downto 2)="00" THEN
+			bitnr(1) <= '0';
+			IF mux(1)='0' THEN
+				bitnr(0) <= '0';
+				IF mux(0)='0' THEN
+					mask_not_zero <= '0'; 
+				END IF;	
+			END IF;	
+		ELSE		
+			IF mux(3)='0' THEN
+				bitnr(0) <= '0';
+			END IF;	
+		END  IF;
+	END PROCESS;
+
+-----------------------------------------------------------------------------
+-- Rotation
+-----------------------------------------------------------------------------
+PROCESS (exe_opcode, OP1out, Flags, rot_bits, rot_msb, rot_lsb, rot_rot, exec, BSout)
+	BEGIN
+		CASE exe_opcode(7 downto 6) IS
+			WHEN "00" =>					--Byte
+						rot_rot <= OP1out(7);
+			WHEN "01"|"11" =>				--Word
+						rot_rot <= OP1out(15);
+			WHEN "10" =>					--Long
+						rot_rot <= OP1out(31);
+			WHEN OTHERS => NULL;
+		END CASE;
+	
+		CASE rot_bits IS
+			WHEN "00" =>					--ASL, ASR
+						rot_lsb <= '0';
+						rot_msb <= rot_rot;
+			WHEN "01" =>					--LSL, LSR
+						rot_lsb <= '0';
+						rot_msb <= '0';
+			WHEN "10" =>					--ROXL, ROXR
+						rot_lsb <= Flags(4);
+						rot_msb <= Flags(4);
+			WHEN "11" =>					--ROL, ROR
+						rot_lsb <= rot_rot;
+						rot_msb <= OP1out(0);
+			WHEN OTHERS => NULL;
+		END CASE;
+	
+		IF exec(rot_nop)='1' THEN
+			rot_out <= OP1out;
+			rot_X <= Flags(4);
+			IF rot_bits="10" THEN	--ROXL, ROXR
+				rot_C <= Flags(4);
+			ELSE	
+				rot_C <= '0';
+			END IF;
+		ELSE
+			IF exe_opcode(8)='1' THEN		--left
+				rot_out <= OP1out(30 downto 0)&rot_lsb;
+				rot_X <= rot_rot;
+				rot_C <= rot_rot;
+			ELSE						--right
+				rot_X <= OP1out(0);
+				rot_C <= OP1out(0);
+				rot_out <= rot_msb&OP1out(31 downto 1);
+				CASE exe_opcode(7 downto 6) IS
+					WHEN "00" =>					--Byte
+						rot_out(7) <= rot_msb;
+					WHEN "01"|"11" =>				--Word
+						rot_out(15) <= rot_msb;
+					WHEN OTHERS => NULL;	
+				END CASE;
+			END IF;
+			IF BarrelShifter/=0 THEN
+			   rot_out <= BSout;
+			END IF;
+		END IF;
+	END PROCESS;
+		
+-----------------------------------------------------------------------------
+-- Barrel Shifter
+-----------------------------------------------------------------------------	
+process (OP1out, OP2out, opcode, bit_nr, bit_msb, bs_shift, bs_shift_mod, ring, result_bs, exe_opcode, vector, 
+         rot_bits, Flags, bs_C, msb, hot_msb, asl_over, asl_over_xor, ALU, asr_sign, exec)
+	begin
+		ring <= "100000";
+		IF rot_bits="10" THEN --ROX L/R
+			CASE exe_opcode(7 downto 6) IS
+				WHEN "00" =>					--Byte
+							ring <= "001001";
+				WHEN "01"|"11" =>				--Word
+							ring <= "010001";
+				WHEN "10" =>					--Long
+							ring <= "100001";
+				WHEN OTHERS => NULL;
+			END CASE;
+		ELSE
+			CASE exe_opcode(7 downto 6) IS
+				WHEN "00" =>					--Byte
+							ring <= "001000";
+				WHEN "01"|"11" =>				--Word
+							ring <= "010000";
+				WHEN "10" =>					--Long
+							ring <= "100000";
+				WHEN OTHERS => NULL;
+			END CASE;
+		END IF;	
+		
+		IF exe_opcode(7 downto 6)="11" OR exec(exec_BS)='0' THEN
+			bs_shift <="000001";
+		ELSIF exe_opcode(5)='1' THEN
+			bs_shift <= OP2out(5 downto 0);
+		ELSE
+			bs_shift(2 downto 0) <= exe_opcode(11 downto 9);
+			IF exe_opcode(11 downto 9)="000" THEN
+				bs_shift(5 downto 3) <="001";
+			ELSE
+				bs_shift(5 downto 3) <="000";
+			END IF;
+		END IF;
+
+-- calc V-Flag by ASL		
+		bit_msb <= "000000";
+		hot_msb <= (OTHERS =>'0');
+		hot_msb(conv_integer(bit_msb)) <= '1';
+		IF bs_shift < ring THEN
+			bit_msb <= ring-bs_shift;
+		END IF;
+		asl_over_xor <= (('0'&vector(30 downto 0)) XOR ('0'&vector(31 downto 1)))&msb;
+		CASE exe_opcode(7 downto 6) IS
+			WHEN "00" =>					--Byte
+				asl_over_xor(8) <= '0';
+			WHEN "01"|"11" =>				--Word
+				asl_over_xor(16) <= '0';
+			WHEN OTHERS => NULL;
+		END CASE;
+		asl_over <= asl_over_xor - ('0'&hot_msb(31 downto 0));	
+		bs_V <= '0';
+		IF rot_bits="00" AND exe_opcode(8)='1' THEN --ASL
+			bs_V <= not asl_over(32);
+		END IF;
+		
+		bs_X <= bs_C;
+		IF exe_opcode(8)='0' THEN --right shift
+			bs_C <= result_bs(31);
+		ELSE                  --left shift
+			CASE exe_opcode(7 downto 6) IS
+				WHEN "00" =>					--Byte
+					bs_C <= result_bs(8);
+				WHEN "01"|"11" =>				--Word
+					bs_C <= result_bs(16);
+				WHEN "10" =>					--Long
+					bs_C <= result_bs(32);
+				WHEN OTHERS => NULL;
+			END CASE;
+		END IF;
+		
+		ALU <= (others=>'-');
+		IF rot_bits="11" THEN --RO L/R
+			bs_X <= Flags(4);
+			CASE exe_opcode(7 downto 6) IS
+				WHEN "00" =>					--Byte
+					ALU(7 downto 0) <= result_bs(7 downto 0) OR result_bs(15 downto 8);
+					bs_C <= ALU(7);
+				WHEN "01"|"11" =>				--Word
+					ALU(15 downto 0) <= result_bs(15 downto 0) OR result_bs(31 downto 16);
+					bs_C <= ALU(15);
+				WHEN "10" =>					--Long
+					ALU <= result_bs(31 downto 0) OR result_bs(63 downto 32);
+					bs_C <= ALU(31);
+				WHEN OTHERS => NULL;
+			END CASE;
+			IF exe_opcode(8)='1' THEN --left shift
+				bs_C <= ALU(0);
+			END IF;
+		ELSIF rot_bits="10" THEN --ROX L/R
+			CASE exe_opcode(7 downto 6) IS
+				WHEN "00" =>					--Byte
+					ALU(7 downto 0) <= result_bs(7 downto 0) OR result_bs(16 downto 9);
+					bs_C <= result_bs(8) OR result_bs(17);
+				WHEN "01"|"11" =>				--Word
+					ALU(15 downto 0) <= result_bs(15 downto 0) OR result_bs(32 downto 17);
+					bs_C <= result_bs(16) OR result_bs(33);
+				WHEN "10" =>					--Long
+					ALU <= result_bs(31 downto 0) OR result_bs(64 downto 33);
+					bs_C <= result_bs(32) OR result_bs(65);
+				WHEN OTHERS => NULL;
+			END CASE;
+		ELSE
+			IF exe_opcode(8)='0' THEN --right shift
+				ALU <= result_bs(63 downto 32);
+			ELSE                  --left shift
+				ALU <= result_bs(31 downto 0);
+			END IF;
+		END IF;
+		
+		IF(bs_shift = "000000") THEN
+			IF rot_bits="10" THEN --ROX L/R
+				bs_C <= Flags(4);
+			ELSE
+				bs_C <= '0';
+			END IF;
+			bs_X <= Flags(4);
+			bs_V <= '0';
+		END IF;
+
+-- calc shift count		
+		bs_shift_mod <= std_logic_vector(unsigned(bs_shift) rem unsigned(ring)); 
+		bit_nr <= bs_shift_mod(5 downto 0);
+		IF exe_opcode(8)='0' THEN  --right shift
+			bit_nr <= ring-bs_shift_mod;
+		END IF;
+		IF rot_bits(1)='0' THEN --only shift
+			IF exe_opcode(8)='0' THEN  --right shift
+				bit_nr <= 32-bs_shift_mod;
+			END IF;
+			IF bs_shift = ring THEN
+				IF exe_opcode(8)='0' THEN  --right shift
+					bit_nr <= 32-ring;
+				ELSE	
+					bit_nr <= ring;
+				END IF;
+			END IF;
+			IF bs_shift > ring THEN
+				IF exe_opcode(8)='0' THEN  --right shift
+					bit_nr <= "000000";
+					bs_C <= '0';
+				ELSE	
+					bit_nr <= ring+1;
+				END IF;
+			END IF;
+		END IF;
+		
+-- calc ASR sign		
+		BSout <= ALU;
+		asr_sign <= (OTHERS =>'0');	
+		asr_sign(32 downto 1) <= asr_sign(31 downto 0) OR hot_msb(31 downto 0);	
+		IF rot_bits="00" AND exe_opcode(8)='0' AND msb='1' THEN --ASR
+			BSout <= ALU or asr_sign(32 downto 1);
+			IF bs_shift > ring THEN
+				bs_C <= '1';
+			END IF;
+		END IF;
+
+		vector(32 downto 0) <= '0'&OP1out;
+		CASE exe_opcode(7 downto 6) IS
+			WHEN "00" =>					--Byte
+				msb <= OP1out(7);
+				vector(31 downto 8) <= X"000000";
+				BSout(31 downto 8) <= X"000000";
+				IF rot_bits="10" THEN --ROX L/R
+					vector(8) <= Flags(4);
+				END IF;
+			WHEN "01"|"11" =>				--Word
+				msb <= OP1out(15);
+				vector(31 downto 16) <= X"0000";
+				BSout(31 downto 16) <= X"0000";
+				IF rot_bits="10" THEN --ROX L/R
+					vector(16) <= Flags(4);
+				END IF;
+			WHEN "10" =>					--Long
+				msb <= OP1out(31);
+				IF rot_bits="10" THEN --ROX L/R
+					vector(32) <= Flags(4);
+				END IF;
+			WHEN OTHERS => NULL;
+		END CASE;
+		result_bs <= std_logic_vector(unsigned('0'&X"00000000"&vector) sll to_integer(unsigned(bit_nr(5 downto 0)))); 
+
+  end process;
+
+  
+------------------------------------------------------------------------------
+--CCR op
+------------------------------------------------------------------------------		
+PROCESS (clk, Reset, exe_opcode, exe_datatype, Flags, last_data_read, OP2out, flag_z, OP1IN, c_out, addsub_ofl,
+	     bcd_a, bcd_a_carry, Vflag_a, exec)
+	BEGIN
+		IF exec(andiSR)='1' THEN
+			CCRin <= Flags AND last_data_read(7 downto 0);
+		ELSIF exec(eoriSR)='1' THEN
+			CCRin <= Flags XOR last_data_read(7 downto 0);
+		ELSIF exec(oriSR)='1' THEN
+			CCRin <= Flags OR last_data_read(7 downto 0);
+		ELSE	
+			CCRin <= OP2out(7 downto 0);
+		END IF;	
+		
+------------------------------------------------------------------------------
+--Flags
+------------------------------------------------------------------------------		
+		flag_z <= "000";
+		IF exec(use_XZFlag)='1' AND flags(2)='0' THEN
+			flag_z <= "000";
+		ELSIF OP1in(7 downto 0)="00000000" THEN
+			flag_z(0) <= '1';
+			IF OP1in(15 downto 8)="00000000" THEN
+				flag_z(1) <= '1';
+				IF OP1in(31 downto 16)="0000000000000000" THEN
+					flag_z(2) <= '1';	
+				END IF;
+			END IF;
+		END IF;
+		
+--					--Flags NZVC
+		IF exe_datatype="00" THEN 						--Byte
+			set_flags <= OP1IN(7)&flag_z(0)&addsub_ofl(0)&c_out(0);
+			IF exec(opcABCD)='1' OR exec(opcSBCD)='1' THEN	
+				set_flags(0) <= bcd_a_carry;
+				set_flags(1) <= Vflag_a;
+			END IF;
+		ELSIF exe_datatype="10" OR exec(opcCPMAW)='1' THEN 						--Long
+			set_flags <= OP1IN(31)&flag_z(2)&addsub_ofl(2)&c_out(2);
+		ELSE 						--Word
+			set_flags <= OP1IN(15)&flag_z(1)&addsub_ofl(1)&c_out(1);
+		END IF;
+		
+		IF rising_edge(clk) THEN		
+			IF Reset='1' THEN
+				Flags(7 downto 0) <= "00000000"; 
+			ELSIF clkena_lw = '1' THEN
+				IF exec(directSR)='1' OR set_stop='1' THEN
+					Flags(7 downto 0) <= data_read(7 downto 0);
+				END IF;	
+				IF exec(directCCR)='1' THEN
+					Flags(7 downto 0) <= data_read(7 downto 0);
+				END IF;	
+				
+				IF exec(opcROT)='1' AND decodeOPC='0' THEN
+					asl_VFlag <= ((set_flags(3) XOR rot_rot) OR asl_VFlag);	
+				ELSE	
+					asl_VFlag <= '0';
+				END IF;	
+				IF exec(to_CCR)='1' THEN
+					Flags(7 downto 0) <= CCRin(7 downto 0);			--CCR
+				ELSIF Z_error='1' THEN
+					IF exe_opcode(8)='0' THEN
+--						Flags(3 downto 0) <= reg_QA(31)&"000";
+						Flags(3 downto 0) <= '0'&NOT reg_QA(31)&"00";
+					ELSE
+						Flags(3 downto 0) <= "0100";
+					END IF;		
+				ELSIF exec(no_Flags)='0' THEN
+					last_Flags1 <= Flags(3 downto 0);
+					IF exec(opcADD)='1' THEN
+						Flags(4) <= set_flags(0);
+					ELSIF exec(opcROT)='1' AND rot_bits/="11" AND exec(rot_nop)='0' THEN
+						Flags(4) <= rot_X; 	
+					ELSIF exec(exec_BS)='1' THEN
+						Flags(4) <= BS_X; 	
+					END IF;
+					
+					IF (exec(opcCMP) OR exec(alu_setFlags))='1' THEN
+						Flags(3 downto 0) <= set_flags;
+					ELSIF exec(opcDIVU)='1' AND DIV_Mode/=3 THEN
+						IF V_Flag='1' THEN	
+							Flags(3 downto 0) <= "1010";
+						ELSIF exe_opcode(15)='1' OR DIV_Mode=0 THEN
+							Flags(3 downto 0) <= OP1IN(15)&flag_z(1)&"00";
+						ELSE
+							Flags(3 downto 0) <= OP1IN(31)&flag_z(2)&"00";
+						END IF;
+					ELSIF exec(write_reminder)='1' AND MUL_Mode/=3 THEN -- z-flag MULU.l
+						Flags(3) <= set_flags(3);
+						Flags(2) <= set_flags(2) AND Flags(2);
+						Flags(1) <= '0';
+						Flags(0) <= '0';
+					ELSIF exec(write_lowlong)='1' AND (MUL_Mode=1 OR MUL_Mode=2) THEN  -- flag MULU.l
+						Flags(3) <= set_flags(3);
+						Flags(2) <= set_flags(2);
+						Flags(1) <= set_mV_Flag;	--V
+						Flags(0) <= '0';
+					ELSIF exec(opcOR)='1' OR exec(opcAND)='1' OR exec(opcEOR)='1' OR exec(opcMOVE)='1' OR exec(opcMOVEQ)='1' OR exec(opcSWAP)='1' OR exec(opcBF)='1' OR (exec(opcMULU)='1' AND MUL_Mode/=3) THEN
+						Flags(1 downto 0) <= "00";
+						Flags(3 downto 2) <= set_flags(3 downto 2);
+						IF exec(opcBF)='1' THEN
+							Flags(3) <= bf_NFlag;
+						END IF;	
+					ELSIF exec(opcROT)='1' THEN
+						Flags(3 downto 2) <= set_flags(3 downto 2);
+						Flags(0) <= rot_C;
+						IF rot_bits="00" AND ((set_flags(3) XOR rot_rot) OR asl_VFlag)='1' THEN		--ASL/ASR
+							Flags(1) <= '1';
+						ELSE		
+							Flags(1) <= '0';
+						END IF;	
+					ELSIF exec(exec_BS)='1' THEN
+						Flags(3 downto 2) <= set_flags(3 downto 2);
+						Flags(0) <= BS_C;
+						Flags(1) <= BS_V;
+					ELSIF exec(opcBITS)='1' THEN
+						Flags(2) <= NOT one_bit_in;	
+					ELSIF exec(opcCHK2)='1' THEN
+						Flags(0) <= '0';
+						Flags(2) <= Flags(2) OR set_flags(2);
+----lower bound first
+						IF last_Flags1(0)='0' THEN			--unsigned OP
+							Flags(0) <= Flags(0) OR (NOT set_flags(0) AND NOT set_flags(2));
+						ELSE										--signed OP
+							Flags(0) <= (Flags(3) AND NOT Flags(1)) OR (NOT Flags(3) AND Flags(1)) OR																				--LT
+										   (set_flags(3) AND set_flags(1) AND NOT set_flags(2)) OR (NOT set_flags(3) AND NOT set_flags(1) AND NOT set_flags(2));	--GT
+						END IF;
+					ELSIF exec(opcCHK)='1' THEN
+						IF exe_datatype="01" THEN 						--Word
+							Flags(3) <= OP1out(15);
+						ELSE	
+							Flags(3) <= OP1out(31);
+						END IF;	
+						IF OP1out(15 downto 0)=X"0000" AND (exe_datatype="01" OR OP1out(31 downto 16)=X"0000") THEN
+							Flags(2) <='1';
+						ELSE	
+							Flags(2) <='0';
+						END IF;	
+						Flags(1) <= '0';
+						Flags(0) <= '0';
+					END IF;
+				END IF;	
+			END IF;	
+			Flags(7 downto 5) <= "000";
+		END IF;	
+	END PROCESS;
+	
+---------------------------------------------------------------------------------
+------ MULU/MULS
+---------------------------------------------------------------------------------	
+PROCESS (exe_opcode, OP2out, muls_msb, mulu_reg, FAsign, mulu_sign, reg_QA, faktorA, faktorB, result_mulu, signedOP)
+--PROCESS (exec, reg_QA, OP2out, faktorA, faktorB, signedOP)
+	BEGIN
+	IF MUL_Hardware=1 THEN
+--		IF exe_opcode(15)='1' OR MUL_Mode=0 THEN	-- 16 Bit
+		IF MUL_Mode=0 THEN	-- 16 Bit
+			IF signedOP='1' AND reg_QA(15)='1' THEN
+				faktorA <= X"FFFFFFFF";
+			ELSE	
+				faktorA <= X"00000000";
+			END IF;
+			IF signedOP='1' AND OP2out(15)='1' THEN
+				faktorB <= X"FFFFFFFF";
+			ELSE	
+				faktorB <= X"00000000";
+			END IF;
+			result_mulu(63 downto 0) <= (faktorA(15 downto 0) & reg_QA(15 downto 0)) * (faktorB(15 downto 0) & OP2out(15 downto 0));
+		ELSE
+			IF exe_opcode(15)='1' THEN	-- 16 Bit
+				IF signedOP='1' AND reg_QA(15)='1' THEN
+					faktorA <= X"FFFFFFFF";
+				ELSE	
+					faktorA <= X"00000000";
+				END IF;
+				IF signedOP='1' AND OP2out(15)='1' THEN
+					faktorB <= X"FFFFFFFF";
+				ELSE	
+					faktorB <= X"00000000";
+				END IF;
+			ELSE	
+				faktorA(15 downto 0) <= reg_QA(31 downto 16);
+				faktorB(15 downto 0) <= OP2out(31 downto 16);
+				IF signedOP='1' AND reg_QA(31)='1' THEN
+					faktorA(31 downto 16) <= X"FFFF";
+				ELSE	
+					faktorA(31 downto 16) <= X"0000";
+				END IF;
+				IF signedOP='1' AND OP2out(31)='1' THEN
+					faktorB(31 downto 16) <= X"FFFF";
+				ELSE	
+					faktorB(31 downto 16) <= X"0000";
+				END IF;
+			END IF;
+			result_mulu(127 downto 0) <= (faktorA(31 downto 16) & faktorA(31 downto 0) & reg_QA(15 downto 0)) * (faktorB(31 downto 16) & faktorB(31 downto 0) & OP2out(15 downto 0));
+		END IF;
+--	END PROCESS;
+-------------------------------------------------------------------------------
+---- MULU/MULS
+-------------------------------------------------------------------------------	
+--PROCESS (exe_opcode, OP2out, muls_msb, mulu_reg, FAsign, mulu_sign, reg_QA, faktorB, result_mulu, signedOP)
+--	BEGIN
+	ELSE
+		IF (signedOP='1' AND faktorB(31)='1') OR FAsign='1' THEN
+			muls_msb <= mulu_reg(63);
+		ELSE
+			muls_msb <= '0';
+		END IF;	
+		
+		IF signedOP='1' AND faktorB(31)='1' THEN
+			mulu_sign <= '1';
+		ELSE
+			mulu_sign <= '0';
+		END IF;	
+		
+		IF MUL_Mode=0 THEN	-- 16 Bit
+			result_mulu(63 downto 32) <= muls_msb&mulu_reg(63 downto 33);	
+			result_mulu(15 downto 0) <= 'X'&mulu_reg(15 downto 1);	
+			IF mulu_reg(0)='1' THEN
+				IF FAsign='1' THEN
+					result_mulu(63 downto 47) <= (muls_msb&mulu_reg(63 downto 48)-(mulu_sign&faktorB(31 downto 16)));	
+				ELSE
+					result_mulu(63 downto 47) <= (muls_msb&mulu_reg(63 downto 48)+(mulu_sign&faktorB(31 downto 16)));	
+				END IF;
+			END IF;	
+		ELSE				-- 32 Bit
+			result_mulu(63 downto 0) <= muls_msb&mulu_reg(63 downto 1);	
+			IF mulu_reg(0)='1' THEN
+				IF FAsign='1' THEN
+					result_mulu(63 downto 31) <= (muls_msb&mulu_reg(63 downto 32)-(mulu_sign&faktorB));	
+				ELSE
+					result_mulu(63 downto 31) <= (muls_msb&mulu_reg(63 downto 32)+(mulu_sign&faktorB));	
+				END IF;
+			END IF;	
+		END IF;
+		IF exe_opcode(15)='1' OR MUL_Mode=0 THEN
+			faktorB(31 downto 16) <= OP2out(15 downto 0);
+			faktorB(15 downto 0) <= (OTHERS=>'0');
+		ELSE	
+			faktorB <= OP2out;
+		END IF;
+	END IF;
+		IF (result_mulu(63 downto 32)=X"00000000" AND (signedOP='0' OR result_mulu(31)='0')) OR
+			(result_mulu(63 downto 32)=X"FFFFFFFF" AND signedOP='1' AND result_mulu(31)='1') THEN
+			set_mV_Flag <= '0';
+		ELSE	
+			set_mV_Flag <= '1';
+		END IF;
+	END PROCESS;
+	
+PROCESS (clk)
+	BEGIN
+		IF rising_edge(clk) THEN
+			IF clkena_lw='1' THEN
+				IF MUL_Hardware=0 THEN
+					IF micro_state=mul1 THEN
+						mulu_reg(63 downto 32) <= (OTHERS=>'0');
+						IF divs='1' AND ((exe_opcode(15)='1' AND reg_QA(15)='1') OR (exe_opcode(15)='0' AND reg_QA(31)='1')) THEN				--MULS Neg faktor
+							FAsign <= '1';
+							mulu_reg(31 downto 0) <= 0-reg_QA;
+						ELSE
+							FAsign <= '0';
+							mulu_reg(31 downto 0) <= reg_QA;
+						END IF;	
+					ELSIF exec(opcMULU)='0' THEN
+						mulu_reg <= result_mulu(63 downto 0);	
+					END IF;
+				ELSE	
+					mulu_reg(31 downto 0) <= result_mulu(63 downto 32);
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+		
+-------------------------------------------------------------------------------
+---- DIVU/DIVS
+-------------------------------------------------------------------------------
+		
+PROCESS (execOPC, OP1out, OP2out, div_reg, div_neg, div_bit, div_sub, div_quot, OP1_sign, div_over, result_div, reg_QA, opcode, sndOPC, divs, exe_opcode, reg_QB, 
+	     signedOP, nozero, div_qsign, OP2outext, result_div_pre)
+	BEGIN
+		divs <= (opcode(15) AND opcode(8)) OR (NOT opcode(15) AND sndOPC(11));
+		dividend(15 downto 0) <= (OTHERS=> '0');
+		dividend(63 downto 32) <= (OTHERS=> divs AND reg_QA(31));
+		IF exe_opcode(15)='1' OR DIV_Mode=0 THEN --DIV.W
+			dividend(47 downto 16) <= reg_QA;
+			div_qsign <= result_div_pre(15);
+		ELSE												  --DIV.l
+			dividend(31 downto 0) <= reg_QA;
+			IF exe_opcode(14)='1' AND sndOPC(10)='1' THEN
+				dividend(63 downto 32) <= reg_QB;
+			END IF;
+			div_qsign <= result_div_pre(31);
+		END IF;
+		IF signedOP='1' OR opcode(15)='0' THEN 
+			OP2outext <= OP2out(31 downto 16);
+		ELSE
+			OP2outext <= (OTHERS=> '0');
+		END IF;
+		IF signedOP='1' AND OP2out(31) ='1' THEN
+			div_sub <= (div_reg(63 downto 31))+('1'&OP2out(31 downto 0));
+		ELSE
+			div_sub <= (div_reg(63 downto 31))-('0'&OP2outext(15 downto 0)&OP2out(15 downto 0));
+		END IF;	
+		IF DIV_Mode=0 THEN
+			div_bit <= div_sub(16);
+		ELSE
+			div_bit <= div_sub(32);
+		END IF;
+		IF div_bit='1' THEN
+			div_quot(63 downto 32) <= div_reg(62 downto 31);	
+		ELSE
+			div_quot(63 downto 32) <= div_sub(31 downto 0);	
+		END IF;	
+		div_quot(31 downto 0) <= div_reg(30 downto 0)&NOT div_bit;
+		
+		IF div_neg='1' THEN
+			result_div_pre(31 downto 0) <= 0-div_quot(31 downto 0);
+
+		ELSE
+			result_div_pre(31 downto 0) <= div_quot(31 downto 0);
+		END IF;	
+		
+		IF (((nozero='1' OR div_bit='0') AND signedOP='1' AND (OP2out(31) XOR OP1_sign XOR div_qsign)='1' )	--Overflow DIVS
+			OR (signedOP='0' AND div_over(32)='0')) AND DIV_Mode/=3 THEN	--Overflow DIVU
+			set_V_Flag <= '1';
+		ELSE	
+			set_V_Flag <= '0';
+		END IF;
+	END PROCESS;
+	
+PROCESS (clk)
+	BEGIN
+		IF rising_edge(clk) THEN
+			IF clkena_lw='1' THEN
+				V_Flag <= set_V_Flag;
+				signedOP <= divs;
+				IF micro_state=div1 THEN
+					nozero <= '0';
+					IF divs='1' AND dividend(63)='1' THEN				-- Neg dividend
+						OP1_sign <= '1';
+						div_reg <= 0-dividend;
+					ELSE
+						OP1_sign <= '0';
+						div_reg <= dividend;
+					END IF;	
+				ELSE
+					div_reg <= div_quot;	
+					nozero <= NOT div_bit OR nozero;
+				END IF;
+				IF micro_state=div2 THEN
+					div_neg <= signedOP AND (OP2out(31) XOR OP1_sign);
+					IF DIV_Mode=0 THEN
+						div_over(32 downto 16) <= ('0'&div_reg(47 downto 32))-('0'&OP2out(15 downto 0));
+					ELSE	
+						div_over <= ('0'&div_reg(63 downto 32))-('0'&OP2out);
+					END IF;	
+				END IF;
+				IF exec(write_reminder)='0' THEN
+					result_div(31 downto 0) <= result_div_pre;
+					IF OP1_sign='1' THEN
+						result_div(63 downto 32) <= 0-div_quot(63 downto 32);
+					ELSE
+						result_div(63 downto 32) <= div_quot(63 downto 32);
+					END IF;	
+				END IF;
+			END IF;
+		END IF;
+	END PROCESS;
+END;
diff --git a/cores/plus_too/TG68K_Pack.vhd b/cores/plus_too/TG68K_Pack.vhd
index fd3c8f4..1d5eb5d 100644
--- a/cores/plus_too/TG68K_Pack.vhd
+++ b/cores/plus_too/TG68K_Pack.vhd
@@ -1,250 +1,180 @@
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
---                                                                          --
--- Copyright (c) 2009-2013 Tobias Gubener                                   --
--- Subdesign fAMpIGA by TobiFlex                                            --
---                                                                          --
--- This source file is free software: you can redistribute it and/or modify --
--- it under the terms of the GNU General Public License as published        --
--- by the Free Software Foundation, either version 3 of the License, or     --
--- (at your option) any later version.                                      --
---                                                                          --
--- This source file is distributed in the hope that it will be useful,      --
--- but WITHOUT ANY WARRANTY; without even the implied warranty of           --
--- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            --
--- GNU General Public License for more details.                             --
---                                                                          --
--- You should have received a copy of the GNU General Public License        --
--- along with this program.  If not, see <http://www.gnu.org/licenses/>.    --
---                                                                          --
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-library IEEE;
-use IEEE.std_logic_1164.all;
-
-package TG68K_Pack is
-
-	type micro_states is (idle, nop, ld_nn, st_nn, ld_dAn1, ld_AnXn1, ld_AnXn2, st_dAn1, ld_AnXnbd1, ld_AnXnbd2, ld_AnXnbd3,
-						  ld_229_1, ld_229_2, ld_229_3, ld_229_4, st_229_1, st_229_2, st_229_3, st_229_4,
-						  st_AnXn1, st_AnXn2, bra1, bsr1, bsr2, nopnop, dbcc1, movem1, movem2, movem3,
-						  andi, op_AxAy, cmpm, link1, link2, unlink1, unlink2, int1, int2, int3, int4, rte1, rte2, rte3, trap0, trap1, trap2, trap3,
-						  trap4, trap5, trap6, movec1, movep1, movep2, movep3, movep4, movep5, rota1, bf1,
-						  mul1, mul2, mul_end1,  mul_end2, div1, div2, div3, div4, div_end1, div_end2, pack1, pack2, pack3);
-
-	constant opcMOVE        : integer := 0; --
-	constant opcMOVEQ       : integer := 1; --
-	constant opcMOVESR      : integer := 2; --
-	constant opcADD         : integer := 3; --
-	constant opcADDQ        : integer := 4; --
-	constant opcOR          : integer := 5; --
-	constant opcAND         : integer := 6; --
-	constant opcEOR         : integer := 7;     --
-	constant opcCMP         : integer := 8; --
-	constant opcROT         : integer := 9; --
-	constant opcCPMAW       : integer := 10;
-	constant opcEXT         : integer := 11; --
-	constant opcABCD        : integer := 12; --
-	constant opcSBCD        : integer := 13; --
-	constant opcBITS        : integer := 14; --
-	constant opcSWAP        : integer := 15; --
-	constant opcScc         : integer := 16; --
-	constant andiSR         : integer := 17; --
-	constant eoriSR         : integer := 18; --
-	constant oriSR          : integer := 19; --
-	constant opcMULU        : integer := 20; --
-	constant opcDIVU        : integer := 21; --
-	constant dispouter      : integer := 22; --
-	constant rot_nop        : integer := 23; --
-	constant ld_rot_cnt     : integer := 24; --
-	constant writePC_add    : integer := 25; --
-	constant ea_data_OP1    : integer := 26; --
-	constant ea_data_OP2    : integer := 27; --
-	constant use_XZFlag     : integer := 28; --
-	constant get_bfoffset   : integer := 29; --
-	constant save_memaddr   : integer := 30; --
-	constant opcCHK         : integer := 31; --
-	constant movec_rd       : integer := 32; --
-	constant movec_wr       : integer := 33; --
-	constant Regwrena       : integer := 34; --
-	constant update_FC      : integer := 35; --
-	constant linksp         : integer := 36; --
-	constant movepl         : integer := 37; --
-	constant update_ld      : integer := 38; --
-	constant OP1addr        : integer := 39; --
-	constant write_reg      : integer := 40; --
-	constant changeMode     : integer := 41; --
-	constant ea_build       : integer := 42; --
-	constant trap_chk       : integer := 43; --
-	constant store_ea_data  : integer := 44; --
-	constant addrlong       : integer := 45; --
-	constant postadd        : integer := 46; --
-	constant presub         : integer := 47; --
-	constant subidx         : integer := 48; --
-	constant no_Flags       : integer := 49; --
-	constant use_SP         : integer := 50; --
-	constant to_CCR         : integer := 51; --
-	constant to_SR          : integer := 52; --
-	constant OP2out_one     : integer := 53; --
-	constant OP1out_zero    : integer := 54; --
-	constant mem_addsub     : integer := 55; --
-	constant addsub         : integer := 56; --
-	constant directPC       : integer := 57; --
-	constant direct_delta   : integer := 58; --
-	constant directSR       : integer := 59; --
-	constant directCCR      : integer := 60; --
-	constant exg            : integer := 61; --
-	constant get_ea_now     : integer := 62; --
-	constant ea_to_pc       : integer := 63; --
-	constant hold_dwr       : integer := 64; --
-	constant to_USP         : integer := 65; --
-	constant from_USP       : integer := 66; --
-	constant write_lowlong  : integer := 67; --
-	constant write_reminder : integer := 68; --
-	constant movem_action   : integer := 69; --
-	constant briefext       : integer := 70; --
-	constant get_2ndOPC     : integer := 71; --
-	constant mem_byte       : integer := 72; --
-	constant longaktion     : integer := 73; --
-	constant opcRESET       : integer := 74; --
-	constant opcBF          : integer := 75; --
-	constant opcBFwb        : integer := 76; --
-	constant s2nd_hbits     : integer := 77; --
-  constant opcPACK        : integer := 77; --
--- constant s2nd_hbits     : integer := 77; --
-
-
---      constant    : integer := 75; --
---      constant         : integer := 76; --
---      constant         : integer := 7; --
---      constant         : integer := 7; --
---      constant         : integer := 7; --
-
-	constant lastOpcBit     : integer := 77;
-
-	type rTG68K_opc is record
-	   opcMOVE        : bit;
-	   opcMOVEQ       : bit;
-	   opcMOVESR      : bit;
-	   opcADD         : bit;
-	   opcADDQ        : bit;
-	   opcOR          : bit;
-	   opcAND         : bit;
-	   opcEOR         : bit;
-	   opcCMP         : bit;
-	   opcROT         : bit;
-	   opcCPMAW       : bit;
-	   opcEXT         : bit;
-	   opcABCD        : bit;
-	   opcSBCD        : bit;
-	   opcBITS        : bit;
-	   opcSWAP        : bit;
-	   opcScc         : bit;
-	   andiSR         : bit;
-	   eoriSR         : bit;
-	   oriSR          : bit;
-	   opcMULU        : bit;
-	   opcDIVU        : bit;
-	   dispouter      : bit;
-	   rot_nop        : bit;
-	   ld_rot_cnt     : bit;
-	   writePC_add    : bit;
-	   ea_data_OP1    : bit;
-	   ea_data_OP2    : bit;
-	   use_XZFlag     : bit;
-	   get_bfoffset   : bit;
-	   save_memaddr   : bit;
-	   opcCHK         : bit;
-	   movec_rd       : bit;
-	   movec_wr       : bit;
-	   Regwrena       : bit;
-	   update_FC      : bit;
-	   linksp         : bit;
-	   movepl         : bit;
-	   update_ld      : bit;
-	   OP1addr        : bit;
-	   write_reg      : bit;
-	   changeMode     : bit;
-	   ea_build       : bit;
-	   trap_chk       : bit;
-	   store_ea_data  : bit;
-	   addrlong       : bit;
-	   postadd        : bit;
-	   presub         : bit;
-	   subidx         : bit;
-	   no_Flags       : bit;
-	   use_SP         : bit;
-	   to_CCR         : bit;
-	   to_SR          : bit;
-	   OP2out_one     : bit;
-	   OP1out_zero    : bit;
-	   mem_addsub     : bit;
-	   addsub         : bit;
-	   directPC       : bit;
-	   direct_delta   : bit;
-	   directSR       : bit;
-	   directCCR      : bit;
-	   exg            : bit;
-	   get_ea_now     : bit;
-	   ea_to_pc       : bit;
-	   hold_dwr       : bit;
-	   to_USP         : bit;
-	   from_USP       : bit;
-	   write_lowlong  : bit;
-	   write_reminder : bit;
-	   movem_action   : bit;
-	   briefext       : bit;
-	   get_2ndOPC     : bit;
-	   mem_byte       : bit;
-	   longaktion     : bit;
-	   opcRESET       : bit;
-	   opcBF          : bit;
-	   opcBFwb        : bit;
-	   s2nd_hbits     : bit;
-	end record;
-
-	component TG68K_ALU
-	generic(
-		MUL_Mode : integer := 0;           --0=>16Bit,  1=>32Bit,  2=>switchable with CPU(1),  3=>no MUL,
-		DIV_Mode : integer := 0            --0=>16Bit,  1=>32Bit,  2=>switchable with CPU(1),  3=>no DIV,
-		);
-	port(
-		clk                     : in std_logic;
-		Reset                   : in std_logic;
-		clkena_lw               : in std_logic:='1';
-		execOPC                 : in bit;
-		exe_condition           : in std_logic;
-		exec_tas                        : in std_logic;
-		long_start                      : in bit;
-		movem_presub            : in bit;
-		set_stop                        : in bit;
-		Z_error                 : in bit;
-		rot_bits                : in std_logic_vector(1 downto 0);
-		exec                : in bit_vector(lastOpcBit downto 0);
-		OP1out                  : in std_logic_vector(31 downto 0);
-		OP2out                  : in std_logic_vector(31 downto 0);
-		reg_QA                  : in std_logic_vector(31 downto 0);
-		reg_QB                  : in std_logic_vector(31 downto 0);
-		opcode                  : in std_logic_vector(15 downto 0);
-		datatype                : in std_logic_vector(1 downto 0);
-		exe_opcode              : in std_logic_vector(15 downto 0);
-		exe_datatype            : in std_logic_vector(1 downto 0);
-		sndOPC                  : in std_logic_vector(15 downto 0);
-		last_data_read          : in std_logic_vector(15 downto 0);
-		data_read                       : in std_logic_vector(15 downto 0);
-		FlagsSR                 : in std_logic_vector(7 downto 0);
-		micro_state                     : in micro_states;
-		bf_ext_in               : in std_logic_vector(7 downto 0);
-		bf_ext_out              : out std_logic_vector(7 downto 0);
-		bf_shift                : in std_logic_vector(5 downto 0);
-		bf_width                : in std_logic_vector(5 downto 0);
-		bf_loffset              : in std_logic_vector(4 downto 0);
-
-		set_V_Flag              : buffer bit;
-		Flags                   : buffer std_logic_vector(7 downto 0);
-		c_out                   : buffer std_logic_vector(2 downto 0);
-		addsub_q                : buffer std_logic_vector(31 downto 0);
-		ALUout                  : out std_logic_vector(31 downto 0)
-	);
-	end component;
-
-end;
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+--                                                                          --
+-- Copyright (c) 2009-2020 Tobias Gubener                                   -- 
+-- Patches by MikeJ, Till Harbaum, Rok Krajnk, ...                          --
+-- Subdesign fAMpIGA by TobiFlex                                            --
+--                                                                          --
+-- This source file is free software: you can redistribute it and/or modify --
+-- it under the terms of the GNU Lesser General Public License as published --
+-- by the Free Software Foundation, either version 3 of the License, or     --
+-- (at your option) any later version.                                      --
+--                                                                          --
+-- This source file is distributed in the hope that it will be useful,      --
+-- but WITHOUT ANY WARRANTY; without even the implied warranty of           --
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the            --
+-- GNU General Public License for more details.                             --
+--                                                                          --
+-- You should have received a copy of the GNU General Public License        --
+-- along with this program.  If not, see <http://www.gnu.org/licenses/>.    --
+--                                                                          --
+------------------------------------------------------------------------------
+------------------------------------------------------------------------------
+library IEEE;
+use IEEE.std_logic_1164.all;
+
+package TG68K_Pack is
+
+	type micro_states is (idle, nop, ld_nn, st_nn, ld_dAn1, ld_AnXn1, ld_AnXn2, st_dAn1, ld_AnXnbd1, ld_AnXnbd2, ld_AnXnbd3,
+						  ld_229_1, ld_229_2, ld_229_3, ld_229_4, st_229_1, st_229_2, st_229_3, st_229_4,   
+						  st_AnXn1, st_AnXn2, bra1, bsr1, bsr2, nopnop, dbcc1, movem1, movem2, movem3, 
+						  andi, pack1, pack2, pack3, op_AxAy, cmpm, link1, link2, unlink1, unlink2, int1, int2, int3, int4, rte1, rte2, rte3, 
+						  rte4, rte5, rtd1, rtd2, trap00, trap0, trap1, trap2, trap3, cas1, cas2, cas21, cas22, cas23, cas24,
+						  cas25, cas26, cas27, cas28, chk20, chk21, chk22, chk23, chk24,
+						  trap4, trap5, trap6, movec1, movep1, movep2, movep3, movep4, movep5, rota1, bf1, 
+						  mul1, mul2, mul_end1,  mul_end2, div1, div2, div3, div4, div_end1, div_end2);
+	
+	constant opcMOVE				: integer := 0; --
+	constant opcMOVEQ				: integer := 1; --
+	constant opcMOVESR			: integer := 2; --
+	constant opcADD				: integer := 3; --
+	constant opcADDQ				: integer := 4; --
+	constant opcOR					: integer := 5; --
+	constant opcAND				: integer := 6; --
+	constant opcEOR				: integer := 7; --
+	constant opcCMP				: integer := 8; --
+	constant opcROT				: integer := 9; --
+	constant opcCPMAW				: integer := 10;
+	constant opcEXT				: integer := 11; --
+	constant opcABCD				: integer := 12; --
+	constant opcSBCD				: integer := 13; --
+	constant opcBITS				: integer := 14; --
+	constant opcSWAP				: integer := 15; --
+	constant opcScc				: integer := 16; --
+	constant andiSR				: integer := 17; --
+	constant eoriSR				: integer := 18; --
+	constant oriSR					: integer := 19; --
+	constant opcMULU				: integer := 20; --
+	constant opcDIVU				: integer := 21; --
+	constant dispouter			: integer := 22; --
+	constant rot_nop				: integer := 23; --
+	constant ld_rot_cnt			: integer := 24; --
+	constant writePC_add			: integer := 25; --
+	constant ea_data_OP1			: integer := 26; --
+	constant ea_data_OP2			: integer := 27; --
+	constant use_XZFlag			: integer := 28; --
+	constant get_bfoffset		: integer := 29; --
+	constant save_memaddr		: integer := 30; --
+	constant opcCHK				: integer := 31; --
+	constant movec_rd				: integer := 32; --
+	constant movec_wr				: integer := 33; --
+	constant Regwrena				: integer := 34; --
+	constant update_FC			: integer := 35; --
+	constant linksp				: integer := 36; --
+	constant movepl				: integer := 37; --
+	constant update_ld			: integer := 38; --
+	constant OP1addr				: integer := 39; --
+	constant write_reg			: integer := 40; --
+	constant changeMode			: integer := 41; --
+	constant ea_build				: integer := 42; --
+	constant trap_chk				: integer := 43; --
+	constant store_ea_data		: integer := 44; --
+	constant addrlong				: integer := 45; --
+	constant postadd				: integer := 46; --
+	constant presub				: integer := 47; --
+	constant subidx				: integer := 48; --
+	constant no_Flags				: integer := 49; --
+	constant use_SP				: integer := 50; --
+	constant to_CCR				: integer := 51; --
+	constant to_SR					: integer := 52; --
+	constant OP2out_one			: integer := 53; --
+	constant OP1out_zero			: integer := 54; --
+	constant mem_addsub			: integer := 55; --
+	constant addsub				: integer := 56; --
+	constant directPC				: integer := 57; --
+	constant direct_delta		: integer := 58; --
+	constant directSR				: integer := 59; --
+	constant directCCR			: integer := 60; --
+	constant exg					: integer := 61; --
+	constant get_ea_now			: integer := 62; --
+	constant ea_to_pc				: integer := 63; --
+	constant hold_dwr				: integer := 64; --
+	constant to_USP				: integer := 65; --
+	constant from_USP				: integer := 66; --
+	constant write_lowlong		: integer := 67; --
+	constant write_reminder		: integer := 68; --
+	constant movem_action		: integer := 69; --
+	constant briefext				: integer := 70; --
+	constant get_2ndOPC			: integer := 71; --
+	constant mem_byte				: integer := 72; --
+	constant longaktion			: integer := 73; --
+	constant opcRESET				: integer := 74; --
+	constant opcBF					: integer := 75; --
+	constant opcBFwb				: integer := 76; --
+	constant opcPACK				: integer := 77; --
+	constant opcUNPACK			: integer := 78; --
+	constant hold_ea_data		: integer := 79; --
+	constant store_ea_packdata	: integer := 80; --
+	constant exec_BS				: integer := 81; --
+	constant hold_OP2				: integer := 82; --
+	constant restore_ADDR		: integer := 83; --
+	constant alu_exec				: integer := 84; --
+	constant alu_move				: integer := 85; --
+	constant alu_setFlags		: integer := 86; --
+	constant opcCHK2				: integer := 87; --
+	constant opcEXTB				: integer := 88; --
+
+	constant lastOpcBit			: integer := 88;
+
+	component TG68K_ALU
+	generic(
+		MUL_Mode :integer;			--0=>16Bit,		1=>32Bit,	2=>switchable with CPU(1),		3=>no MUL,  
+		MUL_Hardware :integer;		--0=>no,			1=>yes,  
+		DIV_Mode :integer;			--0=>16Bit,		1=>32Bit,	2=>switchable with CPU(1),		3=>no DIV,  
+		BarrelShifter :integer		--0=>no,			1=>yes,		2=>switchable with CPU(1)  
+		);
+	port(
+		clk						: in std_logic;
+		Reset						: in std_logic;
+		CPU						: in std_logic_vector(1 downto 0):="00";  -- 00->68000  01->68010  11->68020(only some parts - yet)
+		clkena_lw				: in std_logic:='1';
+		execOPC					: in bit;
+		decodeOPC				: in bit;
+		exe_condition			: in std_logic;
+		exec_tas					: in std_logic;
+		long_start				: in bit;
+		non_aligned				: in  std_logic;
+		movem_presub			: in bit;
+		set_stop					: in bit;
+		Z_error					: in bit;
+		rot_bits					: in std_logic_vector(1 downto 0);
+		exec						: in bit_vector(lastOpcBit downto 0);
+		OP1out					: in std_logic_vector(31 downto 0);
+		OP2out					: in std_logic_vector(31 downto 0);
+		reg_QA					: in std_logic_vector(31 downto 0);
+		reg_QB					: in std_logic_vector(31 downto 0);
+		opcode					: in std_logic_vector(15 downto 0);
+--		datatype					: in std_logic_vector(1 downto 0);
+		exe_opcode				: in std_logic_vector(15 downto 0);
+		exe_datatype			: in std_logic_vector(1 downto 0);
+		sndOPC					: in std_logic_vector(15 downto 0);
+		last_data_read			: in std_logic_vector(15 downto 0);
+		data_read				: in std_logic_vector(15 downto 0);
+		FlagsSR					: in std_logic_vector(7 downto 0);
+		micro_state				: in micro_states;  
+		bf_ext_in				: in std_logic_vector(7 downto 0);
+		bf_ext_out				: out std_logic_vector(7 downto 0);
+		bf_shift					: in std_logic_vector(5 downto 0);
+		bf_width					: in std_logic_vector(5 downto 0);
+		bf_ffo_offset			: in std_logic_vector(31 downto 0);
+		bf_loffset				: in std_logic_vector(4 downto 0);
+
+		set_V_Flag				: buffer bit;
+		Flags						: buffer std_logic_vector(7 downto 0);
+		c_out						: buffer std_logic_vector(2 downto 0);
+		addsub_q					: buffer std_logic_vector(31 downto 0);
+		ALUout					: out std_logic_vector(31 downto 0)
+	);
+	end component;
+
+end;
\ No newline at end of file
diff --git a/cores/plus_too/TG68KdotC_Kernel.vhd b/cores/plus_too/TG68KdotC_Kernel.vhd
index 72f9d44..6bfcb01 100644
--- a/cores/plus_too/TG68KdotC_Kernel.vhd
+++ b/cores/plus_too/TG68KdotC_Kernel.vhd
@@ -1,12 +1,12 @@
 ------------------------------------------------------------------------------
 ------------------------------------------------------------------------------
 --                                                                          --
--- Copyright (c) 2009-2013 Tobias Gubener                                   --
--- Patches by MikeJ, Till Harbaum, Rok Krajnk, ...                          --
+-- Copyright (c) 2009-2020 Tobias Gubener                                   -- 
+-- Patches by MikeJ, Till Harbaum, Rok Krajnk, ...                          --
 -- Subdesign fAMpIGA by TobiFlex                                            --
 --                                                                          --
 -- This source file is free software: you can redistribute it and/or modify --
--- it under the terms of the GNU General Public License as published        --
+-- it under the terms of the GNU Lesser General Public License as published --
 -- by the Free Software Foundation, either version 3 of the License, or     --
 -- (at your option) any later version.                                      --
 --                                                                          --
@@ -19,28 +19,72 @@
 -- along with this program.  If not, see <http://www.gnu.org/licenses/>.    --
 --                                                                          --
 ------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-
--- optimize Register file
-
--- to do 68010:
+------------------------------------------------------------------------------
+
+-- 17.03.2020 TG bugfix move data to (extended address)
+-- 13.03.2020 TG bugfix extended addess mode - thanks Adam Polkosnik
+-- 15.02.2020 TG bugfix DIVS.W with result $8000
+-- 08.01.2020 TH fix the byte-mirroring
+-- 25.11.2019 TG bugfix ILLEGAL.B handling
+-- 24.11.2019 TG next try CMP2 and CHK2.l
+-- 24.11.2019 retrofun(RF) commit ILLEGAL.B handling 
+-- 18.11.2019 TG insert CMP2 and CHK2.l
+-- 17.11.2019 TG insert CAS and CAS2
+-- 10.11.2019 TG insert TRAPcc
+-- 08.11.2019 TG bugfix movem in 68020 mode
+-- 06.11.2019 TG bugfix CHK
+-- 06.11.2019 TG bugfix flags and stackframe DIVU
+-- 04.11.2019 TG insert RTE from TH
+-- 03.11.2019 TG insert TrapV from TH 
+-- 03.11.2019 TG bugfix MUL 64Bit 
+-- 03.11.2019 TG rework barrel shifter - some other tweaks
+-- 02.11.2019 TG bugfig N-Flag and Z-Flag for DIV
+-- 30.10.2019 TG bugfix RTR in 68020-mode
+-- 30.10.2019 TG bugfix BFINS again
+-- 19.10.2019 TG insert some bugfixes from apolkosnik
+-- 05.12.2018 TG insert RTD opcode
+-- 03.12.2018 TG insert barrel shifter
+-- 01.11.2017 TG bugfix V-Flag for ASL/ASR - thanks Peter Graf
+-- 29.05.2017 TG decode 0x4AFB as illegal, needed for QL BKP - thanks Peter Graf
+-- 21.05.2017 TG insert generic for hardware multiplier for MULU & MULS
+-- 04.04.2017 TG change GPL to LGPL
+-- 04.04.2017 TG BCD handling with all undefined behavior! 
+-- 02.04.2017 TG bugfix Bitfield Opcodes 
+-- 19.03.2017 TG insert PACK/UNPACK  
+-- 19.03.2017 TG bugfix CMPI ...(PC) - thanks Till Harbaum
+--     ???    MJ bugfix non_aligned movem access
+-- add berr handling 10.03.2013 - needed for ATARI Core
+
+-- bugfix session 07/08.Feb.2013
+-- movem ,-(an)
+-- movem (an)+,          - thanks  Gerhard Suttner
+-- btst dn,#data         - thanks  Peter Graf
+-- movep                 - thanks  Till Harbaum
+-- IPL vector            - thanks  Till Harbaum
+--  
+
+-- optimize Register file
+
+-- to do 68010:
 -- (MOVEC)
 -- BKPT
--- RTD
 -- MOVES
 --
 -- to do 68020:
 -- (CALLM)
 -- (RETM)
 
--- CAS, CAS2
+-- bugfix CHK2, CMP2
+-- rework barrel shifter 
 -- CHK2
 -- CMP2
 -- cpXXX Coprozessor stuff
--- TRAPcc
 
--- done 020:
--- PACK, UNPK
+-- done 020:
+-- CAS, CAS2
+-- TRAPcc
+-- PACK
+-- UNPK
 -- Bitfields
 -- address modes
 -- long bra
@@ -56,323 +100,362 @@ use work.TG68K_Pack.all;
 
 entity TG68KdotC_Kernel is
 	generic(
-		SR_Read        : integer := 0; --0=>user,   1=>privileged,      2=>switchable with CPU(0)
-		VBR_Stackframe : integer := 0; --0=>no,     1=>yes/extended,    2=>switchable with CPU(0)
-		extAddr_Mode   : integer := 0; --0=>no,     1=>yes,             2=>switchable with CPU(1)
-		MUL_Mode       : integer := 0; --0=>16Bit,  1=>32Bit,           2=>switchable with CPU(1),  3=>no MUL,
-		DIV_Mode       : integer := 0; --0=>16Bit,  1=>32Bit,           2=>switchable with CPU(1),  3=>no DIV,
-		BitField       : integer := 0  --0=>no,     1=>yes,             2=>switchable with CPU(1)
+		SR_Read : integer:= 2;				--0=>user,		1=>privileged,		2=>switchable with CPU(0)
+		VBR_Stackframe : integer:= 2;		--0=>no,			1=>yes/extended,	2=>switchable with CPU(0)
+		extAddr_Mode : integer:= 2;		--0=>no,			1=>yes,				2=>switchable with CPU(1)
+		MUL_Mode : integer := 2;			--0=>16Bit,		1=>32Bit,			2=>switchable with CPU(1),  3=>no MUL,  
+		DIV_Mode : integer := 2;			--0=>16Bit,		1=>32Bit,			2=>switchable with CPU(1),  3=>no DIV,  
+		BitField : integer := 2;			--0=>no,			1=>yes,				2=>switchable with CPU(1) 
+		
+		BarrelShifter : integer := 1;		--0=>no,			1=>yes,				2=>switchable with CPU(1)  
+		MUL_Hardware : integer := 1		--0=>no,			1=>yes,  
 		);
-   port(clk                     : in std_logic;
-		nReset                  : in std_logic;                 --low active
-		clkena_in               : in std_logic:='1';
-		data_in                 : in std_logic_vector(15 downto 0);
-		IPL                     : in std_logic_vector(2 downto 0):="111";
-		IPL_autovector          : in std_logic:='0';
-                berr			: in std_logic:='0';			  -- only 68000 Stackpointer dummy
-		CPU                     : in std_logic_vector(1 downto 0):="00";  -- 00->68000  01->68010  11->68020(only some parts - yet)
-		addr                    : buffer std_logic_vector(31 downto 0);
-		data_write              : out std_logic_vector(15 downto 0);
-		nWr                     : out std_logic;
-		nUDS                    : out std_logic;
-		nLDS                    : out std_logic;
-		busstate                : out std_logic_vector(1 downto 0);     -- 00-> fetch code 10->read data 11->write data 01->no memaccess
-		nResetOut               : out std_logic;
-		FC                      : out std_logic_vector(2 downto 0);
-		clr_berr	  	: out std_logic;
+	port(clk						: in std_logic;
+		nReset					: in std_logic;			--low active
+		clkena_in				: in std_logic:='1';
+		data_in					: in std_logic_vector(15 downto 0);
+		IPL						: in std_logic_vector(2 downto 0):="111";
+		IPL_autovector			: in std_logic:='0';
+		berr						: in std_logic:='0';					-- only 68000 Stackpointer dummy
+		CPU						: in std_logic_vector(1 downto 0):="00";  -- 00->68000  01->68010  11->68020(only some parts - yet)
+		addr_out					: out std_logic_vector(31 downto 0);
+		data_write				: out std_logic_vector(15 downto 0);
+		nWr						: out std_logic;
+		nUDS						: out std_logic;
+		nLDS						: out std_logic;
+		busstate					: out std_logic_vector(1 downto 0);	-- 00-> fetch code 10->read data 11->write data 01->no memaccess
+		nResetOut				: out std_logic;
+		FC							: out std_logic_vector(2 downto 0);
+		clr_berr					: out std_logic;
 -- for debug
-		skipFetch               : out std_logic;
-		regin                   : buffer std_logic_vector(31 downto 0);
-                CACR_out                : buffer std_logic_vector(3 downto 0);
-                VBR_out                 : buffer std_logic_vector(31 downto 0)
+		skipFetch				: out std_logic;
+		regin_out				: out std_logic_vector(31 downto 0);
+		CACR_out					: out std_logic_vector( 3 downto 0);
+		VBR_out					: out std_logic_vector(31 downto 0)
 		);
 end TG68KdotC_Kernel;
 
---nBS : std_logic_vector(3 downto 0); -- nBS0 is 31..24 3 is 7..0, active LOW
---SIZ : std_logic_vector(1 downto 0);
---ACK for 16/32 bit transfer?
 architecture logic of TG68KdotC_Kernel is
 
 
-	signal syncReset            : std_logic_vector(3 downto 0);
-	signal Reset                : std_logic;
-	signal clkena_lw            : std_logic;
-	signal TG68_PC              : std_logic_vector(31 downto 0);
-	signal tmp_TG68_PC          : std_logic_vector(31 downto 0);
-	signal TG68_PC_add          : std_logic_vector(31 downto 0);
-	signal PC_dataa             : std_logic_vector(31 downto 0);
-	signal PC_datab             : std_logic_vector(31 downto 0);
-	signal memaddr              : std_logic_vector(31 downto 0);
-	signal state                : std_logic_vector(1 downto 0);
-	signal datatype             : std_logic_vector(1 downto 0);
-	signal set_datatype         : std_logic_vector(1 downto 0);
-	signal exe_datatype         : std_logic_vector(1 downto 0);
-	signal setstate             : std_logic_vector(1 downto 0);
+	signal use_VBR_Stackframe	: std_logic;
+
+	signal syncReset			: std_logic_vector(3 downto 0);
+	signal Reset				: std_logic;
+	signal clkena_lw			: std_logic;
+	signal TG68_PC				: std_logic_vector(31 downto 0);
+	signal tmp_TG68_PC		: std_logic_vector(31 downto 0);
+	signal TG68_PC_add		: std_logic_vector(31 downto 0);
+	signal PC_dataa			: std_logic_vector(31 downto 0);
+	signal PC_datab			: std_logic_vector(31 downto 0);
+	signal memaddr				: std_logic_vector(31 downto 0);
+	signal state				: std_logic_vector(1 downto 0);
+	signal datatype			: std_logic_vector(1 downto 0);
+	signal set_datatype		: std_logic_vector(1 downto 0);
+	signal exe_datatype		: std_logic_vector(1 downto 0);
+	signal setstate			: std_logic_vector(1 downto 0);
+	signal setaddrvalue		: std_logic;
+	signal addrvalue			: std_logic;
 
-	signal opcode               : std_logic_vector(15 downto 0);
-	signal exe_opcode           : std_logic_vector(15 downto 0);
-	signal sndOPC               : std_logic_vector(15 downto 0);
+	signal opcode				: std_logic_vector(15 downto 0);
+	signal exe_opcode			: std_logic_vector(15 downto 0);
+	signal sndOPC				: std_logic_vector(15 downto 0);
 
-	signal last_opc_read        : std_logic_vector(15 downto 0);
-	signal registerin           : std_logic_vector(31 downto 0);
-	signal reg_QA               : std_logic_vector(31 downto 0);
-	signal reg_QB               : std_logic_vector(31 downto 0);
-	signal Wwrena,Lwrena        : bit;
-	signal Bwrena               : bit;
-	signal Regwrena_now         : bit;
-	signal rf_dest_addr         : std_logic_vector(3 downto 0);
-	signal rf_source_addr       : std_logic_vector(3 downto 0);
-	signal rf_source_addrd      : std_logic_vector(3 downto 0);
-
-	type regfile_t is array(0 to 15) of std_logic_vector(31 downto 0);
-	signal regfile              : regfile_t := (others => (others =>'0')); -- mikej stops sim X issues;
-	signal RDindex_A            : integer range 0 to 15;
-	signal RDindex_B            : integer range 0 to 15;
-	signal WR_AReg              : std_logic;
+	signal exe_pc				: std_logic_vector(31 downto 0);--TH
+	signal last_opc_pc		: std_logic_vector(31 downto 0);--TH
+	signal last_opc_read		: std_logic_vector(15 downto 0);
+	signal registerin			: std_logic_vector(31 downto 0);
+	signal reg_QA				: std_logic_vector(31 downto 0);
+	signal reg_QB				: std_logic_vector(31 downto 0);
+	signal Wwrena,Lwrena		: bit;
+	signal Bwrena				: bit;
+	signal Regwrena_now		: bit;
+	signal rf_dest_addr		: std_logic_vector(3 downto 0);
+	signal rf_source_addr	: std_logic_vector(3 downto 0);
+	signal rf_source_addrd	: std_logic_vector(3 downto 0);
+   
+	signal regin				: std_logic_vector(31 downto 0);
+	type   regfile_t is array(0 to 15) of std_logic_vector(31 downto 0);
+	signal regfile				: regfile_t := (OTHERS => (OTHERS => '0')); -- mikej stops sim X issues;
+	signal RDindex_A			: integer range 0 to 15;
+	signal RDindex_B			: integer range 0 to 15;
+	signal WR_AReg				: std_logic;
 
 
-	signal memaddr_reg          : std_logic_vector(31 downto 0);
-	signal memaddr_delta        : std_logic_vector(31 downto 0);
-	signal use_base             : bit;
+	signal addr					: std_logic_vector(31 downto 0);
+	signal memaddr_reg		: std_logic_vector(31 downto 0);
+	signal memaddr_delta		: std_logic_vector(31 downto 0);
+	signal use_base			: bit;
+	
+	signal ea_data				: std_logic_vector(31 downto 0);
+	signal OP1out				: std_logic_vector(31 downto 0);
+	signal OP2out				: std_logic_vector(31 downto 0);
+	signal OP1outbrief		: std_logic_vector(15 downto 0);
+	signal OP1in				: std_logic_vector(31 downto 0);
+	signal ALUout	: std_logic_vector(31 downto 0);
+	signal data_write_tmp	: std_logic_vector(31 downto 0);
+	signal data_write_muxin	: std_logic_vector(31 downto 0);
+	signal data_write_mux	: std_logic_vector(47 downto 0);
+	signal nextpass			: bit;
+	signal setnextpass		: bit;
+	signal setdispbyte		: bit;
+	signal setdisp				: bit;
+	signal regdirectsource	:bit;		-- checken !!!
+	signal addsub_q			: std_logic_vector(31 downto 0);
+	signal briefdata			: std_logic_vector(31 downto 0);
+	signal c_out				: std_logic_vector(2 downto 0);
 
-	signal ea_data              : std_logic_vector(31 downto 0);
-	signal OP1out               : std_logic_vector(31 downto 0);
-	signal OP2out               : std_logic_vector(31 downto 0);
-	signal OP1outbrief          : std_logic_vector(15 downto 0);
-	signal OP1in                : std_logic_vector(31 downto 0);
-	signal ALUout               : std_logic_vector(31 downto 0);
-	signal data_write_i         : std_logic_vector(15 downto 0);
-	signal data_write_tmp       : std_logic_vector(31 downto 0);
-	signal data_write_muxin     : std_logic_vector(31 downto 0);
-	signal data_write_mux       : std_logic_vector(47 downto 0);
-	signal nextpass             : bit;
-	signal setnextpass          : bit;
-	signal setdispbyte          : bit;
-	signal setdisp              : bit;
-	signal regdirectsource      : bit;         -- checken !!!
-	signal addsub_q             : std_logic_vector(31 downto 0);
-	signal briefdata            : std_logic_vector(31 downto 0);
---   signal c_in                  : std_logic_vector(3 downto 0);
-	signal c_out                : std_logic_vector(2 downto 0);
+	signal mem_address		: std_logic_vector(31 downto 0);
+	signal memaddr_a			: std_logic_vector(31 downto 0);
 
-	signal mem_address          : std_logic_vector(31 downto 0);
-	signal memaddr_a            : std_logic_vector(31 downto 0);
+	signal TG68_PC_brw		: bit;
+	signal TG68_PC_word		: bit;
+	signal getbrief			: bit;
+	signal brief				: std_logic_vector(15 downto 0);
+	signal data_is_source	: bit;
+	signal store_in_tmp		: bit;
+	signal write_back			: bit;
+	signal exec_write_back	: bit;
+	signal setstackaddr		: bit;
+	signal writePC				: bit;
+	signal writePCbig			: bit;
+	signal set_writePCbig	: bit;
+	signal setopcode			: bit;
+	signal decodeOPC			: bit;
+	signal execOPC				: bit;
+	signal execOPC_ALU		: bit;
+	signal setexecOPC			: bit;
+	signal endOPC				: bit;
+	signal setendOPC			: bit;
+	signal Flags				: std_logic_vector(7 downto 0);	-- ...XNZVC
+	signal FlagsSR				: std_logic_vector(7 downto 0);	-- T.S.0III
+	signal SRin					: std_logic_vector(7 downto 0);
+	signal exec_DIRECT		: bit;
+	signal exec_tas			: std_logic;
+	signal set_exec_tas		: std_logic;
 
-	signal TG68_PC_brw          : bit;
-	signal TG68_PC_word         : bit;
-	signal getbrief             : bit;
-	signal brief                : std_logic_vector(15 downto 0);
-	signal dest_areg            : std_logic;
-	signal source_areg          : std_logic;
-	signal data_is_source       : bit;
-	signal store_in_tmp         : bit;
-	signal write_back           : bit;
-	signal exec_write_back      : bit;
-	signal setstackaddr         : bit;
-	signal writePC              : bit;
-	signal writePCbig           : bit;
-	signal set_writePCbig       : bit;
-	signal setopcode            : bit;
-	signal decodeOPC            : bit;
-	signal execOPC              : bit;
-	signal setexecOPC           : bit;
-	signal endOPC               : bit;
-	signal setendOPC            : bit;
-	signal Flags                : std_logic_vector(7 downto 0);       -- ...XNZVC
-	signal FlagsSR              : std_logic_vector(7 downto 0);       -- T.S..III
-	signal SRin                 : std_logic_vector(7 downto 0);
-	signal exec_DIRECT          : bit;
-	signal exec_tas             : std_logic;
-	signal set_exec_tas         : std_logic;
+	signal exe_condition		: std_logic;
+	signal ea_only				: bit;
+	signal source_areg		: std_logic;
+	signal source_lowbits	: bit;
+	signal source_LDRLbits 	: bit;
+	signal source_LDRMbits 	: bit;
+	signal source_2ndHbits	: bit;
+	signal source_2ndMbits	: bit;
+	signal source_2ndLbits	: bit;
+	signal dest_areg			: std_logic;
+	signal dest_LDRareg		: std_logic;
+	signal dest_LDRHbits		: bit;
+	signal dest_LDRLbits		: bit;
+	signal dest_2ndHbits		: bit;
+	signal dest_2ndLbits		: bit;
+	signal dest_hbits			: bit;
+	signal rot_bits			: std_logic_vector(1 downto 0);
+	signal set_rot_bits		: std_logic_vector(1 downto 0);
+	signal rot_cnt				: std_logic_vector(5 downto 0);
+	signal set_rot_cnt		: std_logic_vector(5 downto 0);
+	signal movem_actiond		: bit;
+	signal movem_regaddr		: std_logic_vector(3 downto 0);
+	signal movem_mux			: std_logic_vector(3 downto 0);
+	signal movem_presub		: bit;
+	signal movem_run			: bit;
+	signal ea_calc_b			: std_logic_vector(31 downto 0);
+	signal set_direct_data	: bit;
+	signal use_direct_data	: bit;
+	signal direct_data		: bit;
 
-	signal exe_condition        : std_logic;
-	signal ea_only              : bit;
-	signal source_lowbits       : bit;
-	signal source_2ndHbits      : bit;
-	signal source_2ndLbits      : bit;
-	signal dest_2ndHbits        : bit;
-	signal dest_hbits           : bit;
-	signal rot_bits             : std_logic_vector(1 downto 0);
-	signal set_rot_bits         : std_logic_vector(1 downto 0);
-	signal rot_cnt              : std_logic_vector(5 downto 0);
-	signal set_rot_cnt          : std_logic_vector(5 downto 0);
-	signal movem_actiond        : bit;
-	signal movem_regaddr        : std_logic_vector(3 downto 0);
-	signal movem_mux            : std_logic_vector(3 downto 0);
-	signal movem_presub         : bit;
-	signal movem_run            : bit;
-	signal ea_calc_b            : std_logic_vector(31 downto 0);
-	signal set_direct_data      : bit;
-	signal use_direct_data      : bit;
-	signal direct_data          : bit;
+	signal set_V_Flag			: bit;
+	signal set_vectoraddr	: bit;
+	signal writeSR				: bit;
+	signal trap_berr			: bit;
+	signal trap_illegal		: bit;
+	signal trap_addr_error	: bit;
+	signal trap_priv			: bit;
+	signal trap_trace			: bit;
+	signal trap_1010			: bit;
+	signal trap_1111			: bit;
+	signal trap_trap			: bit;
+	signal trap_trapv			: bit;
+	signal trap_interrupt	: bit;
+	signal trapmake			: bit;
+	signal trapd				: bit;
+	signal trap_SR				: std_logic_vector(7 downto 0);
+	signal make_trace			: std_logic;
+	signal make_berr			: std_logic;
+	signal useStackframe2	: std_logic;
+	
+	signal set_stop			: bit;
+	signal stop					: bit;
+	signal trap_vector		: std_logic_vector(31 downto 0);
+	signal trap_vector_vbr	: std_logic_vector(31 downto 0);
+	signal USP					: std_logic_vector(31 downto 0);
+--	signal illegal_write_mode	: bit;
+--	signal illegal_read_mode	: bit;
+--	signal illegal_byteaddr		: bit;
 
-	signal set_V_Flag           : bit;
-	signal set_vectoraddr       : bit;
-	signal writeSR              : bit;
-	signal trap_berr            : bit;
-	signal trap_illegal         : bit;
-	signal trap_addr_error      : bit;
-	signal trap_priv            : bit;
-	signal trap_trace           : bit;
-	signal trap_1010            : bit;
-	signal trap_1111            : bit;
-	signal trap_trap            : bit;
-	signal trap_trapv           : bit;
-	signal trap_interrupt       : bit;
-	signal trapmake             : bit;
-	signal trapd                : bit;
-	signal trap_SR              : std_logic_vector(7 downto 0);
-	signal make_trace           : std_logic;
-	signal make_berr     		 : std_logic;
+	signal IPL_nr				: std_logic_vector(2 downto 0);
+	signal rIPL_nr				: std_logic_vector(2 downto 0);
+	signal IPL_vec				: std_logic_vector(7 downto 0);
+	signal interrupt			: bit;
+	signal setinterrupt		: bit;
+	signal SVmode				: std_logic;
+	signal preSVmode			: std_logic;
+	signal Suppress_Base		: bit;
+	signal set_Suppress_Base: bit;
+	signal set_Z_error 		: bit;
+	signal Z_error 			: bit;
+	signal ea_build_now		: bit;	
+	signal build_logical		: bit;	
+	signal build_bcd			: bit;	
+	
+	signal data_read			: std_logic_vector(31 downto 0);
+	signal bf_ext_in			: std_logic_vector(7 downto 0);
+	signal bf_ext_out			: std_logic_vector(7 downto 0);
+--	signal byte					: bit;
+	signal long_start			: bit;
+	signal long_start_alu	: bit;
+	signal non_aligned		: std_logic;
+	signal long_done			: bit;
+	signal memmask				: std_logic_vector(5 downto 0);
+	signal set_memmask		: std_logic_vector(5 downto 0);
+	signal memread				: std_logic_vector(3 downto 0);
+	signal wbmemmask			: std_logic_vector(5 downto 0);
+	signal memmaskmux			: std_logic_vector(5 downto 0);
+	signal oddout				: std_logic;
+	signal set_oddout			: std_logic;
+	signal PCbase				: std_logic;
+	signal set_PCbase			: std_logic;
+		 
+	signal last_data_read	: std_logic_vector(31 downto 0);
+	signal last_data_in		: std_logic_vector(31 downto 0);
 
-	signal set_stop             : bit;
-	signal stop                 : bit;
-	signal trap_vector          : std_logic_vector(31 downto 0);
-	signal trap_vector_vbr      : std_logic_vector(31 downto 0);
-	signal USP                  : std_logic_vector(31 downto 0);
-	signal illegal_write_mode   : bit;
-	signal illegal_read_mode    : bit;
-	signal illegal_byteaddr     : bit;
+	signal bf_offset			: std_logic_vector(5 downto 0);
+	signal bf_width			: std_logic_vector(5 downto 0);
+	signal bf_bhits			: std_logic_vector(5 downto 0);
+	signal bf_shift			: std_logic_vector(5 downto 0);
+	signal alu_width			: std_logic_vector(5 downto 0);
+	signal alu_bf_shift		: std_logic_vector(5 downto 0);
+	signal bf_loffset			: std_logic_vector(5 downto 0);
+	signal bf_full_offset	: std_logic_vector(31 downto 0);
+	signal alu_bf_ffo_offset: std_logic_vector(31 downto 0);
+	signal alu_bf_loffset	: std_logic_vector(5 downto 0);
 
-	signal IPL_nr               : std_logic_vector(2 downto 0);
-	signal rIPL_nr              : std_logic_vector(2 downto 0);
-	signal IPL_vec              : std_logic_vector(7 downto 0);
-	signal interrupt            : bit;
-	signal setinterrupt         : bit;
-	signal SVmode               : std_logic;
-	signal preSVmode            : std_logic;
-	signal Suppress_Base        : bit;
-	signal set_Suppress_Base    : bit;
-	signal set_Z_error          : bit;
-	signal Z_error              : bit;
-	signal ea_build_now         : bit;
-	signal build_logical        : bit;
-	signal build_bcd            : bit;
+	signal movec_data			: std_logic_vector(31 downto 0);
+	signal VBR					: std_logic_vector(31 downto 0);
+	signal CACR					: std_logic_vector(3 downto 0);
+	signal DFC					: std_logic_vector(2 downto 0);
+	signal SFC					: std_logic_vector(2 downto 0);
+	
 
-	signal data_read            : std_logic_vector(31 downto 0);
-	signal bf_ext_in            : std_logic_vector(7 downto 0);
-	signal bf_ext_out           : std_logic_vector(7 downto 0);
-	signal byte                 : bit;
-	signal long_start           : bit;
-	signal long_start_alu       : bit;
-	signal long_done            : bit;
-	signal memmask              : std_logic_vector(5 downto 0);
-	signal set_memmask          : std_logic_vector(5 downto 0);
-	signal memread              : std_logic_vector(3 downto 0);
-	signal wbmemmask            : std_logic_vector(5 downto 0);
-	signal memmaskmux           : std_logic_vector(5 downto 0);
-	signal oddout               : std_logic;
-	signal set_oddout           : std_logic;
-	signal PCbase               : std_logic;
-	signal set_PCbase           : std_logic;
+	signal set					: bit_vector(lastOpcBit downto 0);
+	signal set_exec			: bit_vector(lastOpcBit downto 0);
+	signal exec					: bit_vector(lastOpcBit downto 0);
 
-	signal last_data_read       : std_logic_vector(31 downto 0);
-	signal last_data_in         : std_logic_vector(31 downto 0);
-
-	signal bf_offset            : std_logic_vector(5 downto 0);
-	signal bf_width             : std_logic_vector(5 downto 0);
-	signal bf_bhits             : std_logic_vector(5 downto 0);
-	signal bf_shift             : std_logic_vector(5 downto 0);
-	signal alu_width            : std_logic_vector(5 downto 0);
-	signal alu_bf_shift         : std_logic_vector(5 downto 0);
-	signal bf_loffset           : std_logic_vector(5 downto 0);
-	signal alu_bf_loffset       : std_logic_vector(5 downto 0);
-
-	signal movec_data           : std_logic_vector(31 downto 0);
-	signal VBR                  : std_logic_vector(31 downto 0);
-	signal CACR                 : std_logic_vector(3 downto 0);
-	signal DFC                  : std_logic_vector(2 downto 0);
-	signal SFC                  : std_logic_vector(2 downto 0);
+	signal micro_state		: micro_states;
+	signal next_micro_state	: micro_states;
+	
 
 
-	signal set                  : bit_vector(lastOpcBit downto 0);
-	signal set_exec             : bit_vector(lastOpcBit downto 0);
-	signal exec                 : bit_vector(lastOpcBit downto 0);
-	signal exec_d               : rTG68K_opc;
+BEGIN  
 
-	signal micro_state          : micro_states;
-	signal next_micro_state     : micro_states;
-
-BEGIN
-ALU: TG68K_ALU
+ALU: TG68K_ALU   
 	generic map(
-		MUL_Mode => MUL_Mode,           --0=>16Bit,  1=>32Bit,  2=>switchable with CPU(1),  3=>no MUL,
-		DIV_Mode => DIV_Mode            --0=>16Bit,  1=>32Bit,  2=>switchable with CPU(1),  3=>no DIV,
+		MUL_Mode => MUL_Mode,				--0=>16Bit,	1=>32Bit,	2=>switchable with CPU(1),		3=>no MUL,
+		MUL_Hardware => MUL_Hardware,		--0=>no,		1=>yes,
+		DIV_Mode => DIV_Mode,				--0=>16Bit,	1=>32Bit,	2=>switchable with CPU(1),		3=>no DIV,
+		BarrelShifter => BarrelShifter	--0=>no,		1=>yes,		2=>switchable with CPU(1)  
 		)
 	port map(
-		clk            => clk,                            --: in std_logic;
-		Reset          => Reset,                          --: in std_logic;
-		clkena_lw      => clkena_lw,                      --: in std_logic:='1';
-		execOPC        => execOPC,                        --: in bit;
-		exe_condition  => exe_condition,                  --: in std_logic;
-		exec_tas       => exec_tas,                       --: in std_logic;
-		long_start     => long_start_alu,                 --: in bit;
-		movem_presub   => movem_presub,                   --: in bit;
-		set_stop       => set_stop,                       --: in bit;
-		Z_error        => Z_error,                        --: in bit;
-		rot_bits       => rot_bits,                       --: in std_logic_vector(1 downto 0);
-		exec           => exec,                           --: in bit_vector(lastOpcBit downto 0);
-		OP1out         => OP1out,                         --: in std_logic_vector(31 downto 0);
-		OP2out         => OP2out,                         --: in std_logic_vector(31 downto 0);
-		reg_QA         => reg_QA,                         --: in std_logic_vector(31 downto 0);
-		reg_QB         => reg_QB,                         --: in std_logic_vector(31 downto 0);
-		opcode         => opcode,                         --: in std_logic_vector(15 downto 0);
-		datatype       => datatype,                       --: in std_logic_vector(1 downto 0);
-		exe_opcode     => exe_opcode,                     --: in std_logic_vector(15 downto 0);
-		exe_datatype   => exe_datatype,                   --: in std_logic_vector(1 downto 0);
-		sndOPC         => sndOPC,                         --: in std_logic_vector(15 downto 0);
-		last_data_read => last_data_read(15 downto 0),    --: in std_logic_vector(31 downto 0);
-		data_read      => data_read(15 downto 0),         --: in std_logic_vector(31 downto 0);
-		FlagsSR        => FlagsSR,                        --: in std_logic_vector(7 downto 0);
-		micro_state    => micro_state,                    --: in micro_states;
-		bf_ext_in      => bf_ext_in,
-		bf_ext_out     => bf_ext_out,
-		bf_shift       => alu_bf_shift,
-		bf_width       => alu_width,
-		bf_loffset     => alu_bf_loffset(4 downto 0),
-		set_V_Flag     => set_V_Flag,                     --: buffer bit;
-		Flags          => Flags,                          --: buffer std_logic_vector(8 downto 0);
-		c_out          => c_out,                          --: buffer std_logic_vector(2 downto 0);
-		addsub_q       => addsub_q,                       --: buffer std_logic_vector(31 downto 0);
-		ALUout         => ALUout                          --: buffer std_logic_vector(31 downto 0)
+		clk => clk,								--: in std_logic;
+		Reset => Reset,						--: in std_logic;
+		CPU => CPU,								--: in std_logic_vector(1 downto 0):="00";  -- 00->68000  01->68010  11->68020(only some parts - yet)
+		clkena_lw => clkena_lw,				--: in std_logic:='1';
+		execOPC => execOPC_ALU,				--: in bit;
+		decodeOPC => decodeOPC,				--: in bit;
+		exe_condition => exe_condition,	--: in std_logic;
+		exec_tas => exec_tas,				--: in std_logic;
+		long_start => long_start_alu,		--: in bit;
+		non_aligned => non_aligned,
+		movem_presub => movem_presub,		--: in bit;
+		set_stop => set_stop,				--: in bit;
+		Z_error => Z_error,					--: in bit;
+
+		rot_bits => rot_bits,				--: in std_logic_vector(1 downto 0);
+		exec => exec,							--: in bit_vector(lastOpcBit downto 0);
+		OP1out => OP1out,						--: in std_logic_vector(31 downto 0);
+		OP2out => OP2out,						--: in std_logic_vector(31 downto 0);
+		reg_QA => reg_QA,						--: in std_logic_vector(31 downto 0);
+		reg_QB => reg_QB,						--: in std_logic_vector(31 downto 0);
+		opcode => opcode,						--: in std_logic_vector(15 downto 0);
+		exe_opcode => exe_opcode,			--: in std_logic_vector(15 downto 0);
+		exe_datatype => exe_datatype,		--: in std_logic_vector(1 downto 0);
+		sndOPC => sndOPC,						--: in std_logic_vector(15 downto 0);
+		last_data_read => last_data_read(15 downto 0),	--: in std_logic_vector(31 downto 0);
+		data_read => data_read(15 downto 0),		 		--: in std_logic_vector(31 downto 0);
+		FlagsSR => FlagsSR,					--: in std_logic_vector(7 downto 0);
+		micro_state => micro_state,		--: in micro_states;  
+		bf_ext_in => bf_ext_in,
+		bf_ext_out => bf_ext_out,
+		bf_shift => alu_bf_shift,
+		bf_width => alu_width,
+		bf_ffo_offset => alu_bf_ffo_offset,
+		bf_loffset => alu_bf_loffset(4 downto 0),
+
+		set_V_Flag => set_V_Flag,			--: buffer bit;
+		Flags => Flags,					 	--: buffer std_logic_vector(8 downto 0);
+		c_out => c_out,					 	--: buffer std_logic_vector(2 downto 0);
+		addsub_q => addsub_q,				--: buffer std_logic_vector(31 downto 0);
+		ALUout => ALUout						--: buffer std_logic_vector(31 downto 0)
 	);
 
-	long_start_alu <= to_bit(NOT memmaskmux(3));
+	long_start_alu <= to_bit(NOT memmaskmux(3));
+	execOPC_ALU <= execOPC OR exec(alu_exec);
+	process (memmaskmux)
+	begin
+		non_aligned <= '0';
+		if (memmaskmux(5 downto 4) = "01") or (memmaskmux(5 downto 4) = "10") then
+			non_aligned <= '1';
+		end if;
+	end process;
 -----------------------------------------------------------------------------
 -- Bus control
 -----------------------------------------------------------------------------
+   regin_out <= regin;
+
+
 	nWr <= '0' WHEN state="11" ELSE '1';
 	busstate <= state;
-	nResetOut <= '0' WHEN exec(opcRESET)='1' ELSE '1';
-
-	-- does shift for byte access. Note active low me
-	-- should produce address error on 68000
-	memmaskmux <= memmask WHEN addr(0)='1' ELSE memmask(4 downto 0)&'1';
-
+	nResetOut <= '0' WHEN exec(opcRESET)='1' ELSE '1';
+	
+	-- does shift for byte access. note active low me
+	-- should produce address error on 68000
+	memmaskmux <= memmask when addr(0) = '1' else memmask(4 downto 0) & '1';
 	nUDS <= memmaskmux(5);
 	nLDS <= memmaskmux(4);
-	
-	-- drive output data, output bytes on both half-words during byte write
-	data_write( 7 downto 0) <= data_write_i( 7 downto 0) WHEN memmaskmux(4)='0' ELSE data_write_i(15 downto 8);
-	data_write(15 downto 8) <= data_write_i(15 downto 8) WHEN memmaskmux(5)='0' ELSE data_write_i( 7 downto 0);
-	
-	clkena_lw <= '1' WHEN clkena_in='1' AND memmaskmux(3)='1' ELSE '0'; -- step
+	clkena_lw <= '1' WHEN clkena_in='1' AND memmaskmux(3)='1' ELSE '0';
 	clr_berr <= '1' WHEN setopcode='1' AND trap_berr='1' ELSE '0';
-
+	
 	PROCESS (clk, nReset)
 	BEGIN
 		IF nReset='0' THEN
 			syncReset <= "0000";
-			Reset <= '1';
-		ELSIF rising_edge(clk) THEN
+			Reset <= '1'; 
+	  	ELSIF rising_edge(clk) THEN
 			IF clkena_in='1' THEN
 				syncReset <= syncReset(2 downto 0)&'1';
-				Reset <= NOT syncReset(3);
+				Reset <= NOT syncReset(3);	
 			END IF;
 		END IF;
-	END PROCESS;
-
-PROCESS (clk, long_done, last_data_in, data_in, byte, addr, long_start, memmaskmux, memread, memmask, data_read)
+		IF rising_edge(clk) THEN
+			IF VBR_Stackframe=1 or (cpu(0)='1' and VBR_Stackframe=2) THEN
+				use_VBR_Stackframe<='1';
+			ELSE
+				use_VBR_Stackframe<='0';
+			END IF;
+		END IF;
+	END PROCESS;
+			
+PROCESS (clk, long_done, last_data_in, data_in, addr, long_start, memmaskmux, memread, memmask, data_read)
 	BEGIN
 		IF memmaskmux(4)='0' THEN
 			data_read <= last_data_in(15 downto 0)&data_in;
@@ -381,20 +464,20 @@ PROCESS (clk, long_done, last_data_in, data_in, byte, addr, long_start, memmaskm
 		END IF;
 		IF memread(0)='1' OR (memread(1 downto 0)="10" AND memmaskmux(4)='1')THEN
 			data_read(31 downto 16) <= (OTHERS=>data_read(15));
-		END IF;
-
-		IF rising_edge(clk) THEN
+		END IF;	
+		
+		IF rising_edge(clk) THEN	
 			IF clkena_lw='1' AND state="10" THEN
 				IF memmaskmux(4)='0' THEN
 					bf_ext_in <= last_data_in(23 downto 16);
 				ELSE
 					bf_ext_in <= last_data_in(31 downto 24);
 				END IF;
-			END IF;
+			END IF;	
 			IF Reset='1' THEN
 				last_data_read <= (OTHERS => '0');
 			ELSIF clkena_in='1' THEN
-				IF state="00" OR exec(update_ld)='1' THEN
+				IF state="00" OR exec(update_ld)='1' THEN 
 					last_data_read <= data_read;
 					IF state(1)='0' AND memmask(1)='0' THEN
 						last_data_read(31 downto 16) <= last_opc_read;
@@ -403,170 +486,191 @@ PROCESS (clk, long_done, last_data_in, data_in, byte, addr, long_start, memmaskm
 					END IF;
 				END IF;
 				last_data_in <= last_data_in(15 downto 0)&data_in(15 downto 0);
-
+				
 			END IF;
 		END IF;
 				long_start <= to_bit(NOT memmask(1));
 				long_done <= to_bit(NOT memread(1));
 	END PROCESS;
-
-PROCESS (byte, long_start, reg_QB, data_write_tmp, exec, data_read, data_write_mux, memmaskmux, bf_ext_out,
+	
+PROCESS (long_start, reg_QB, data_write_tmp, exec, data_read, data_write_mux, memmaskmux, bf_ext_out, 
 		 data_write_muxin, memmask, oddout, addr)
 	BEGIN
 		IF exec(write_reg)='1' THEN
 			data_write_muxin <= reg_QB;
 		ELSE
 			data_write_muxin <= data_write_tmp;
-		END IF;
-
-		IF BitField=0 THEN
-			IF oddout=addr(0) THEN
-				data_write_mux <= "XXXXXXXX"&"XXXXXXXX"&data_write_muxin;
-			ELSE
-				data_write_mux <= "XXXXXXXX"&data_write_muxin&"XXXXXXXX";
-			END IF;
-		ELSE
-			IF oddout=addr(0) THEN
-				data_write_mux <= "XXXXXXXX"&bf_ext_out&data_write_muxin;
-			ELSE
-				data_write_mux <= bf_ext_out&data_write_muxin&"XXXXXXXX";
-			END IF;
-		END IF;
-
-		IF memmaskmux(1)='0' THEN
-			data_write_i <= data_write_mux(47 downto 32);
-		ELSIF memmaskmux(3)='0' THEN
-			data_write_i <= data_write_mux(31 downto 16);
-		ELSE
-			data_write_i <= data_write_mux(15 downto 0);
-		END IF;
-		IF exec(mem_byte)='1' THEN      --movep
-			data_write_i(7 downto 0) <= data_write_tmp(15 downto 8);
+		END IF;
+		
+		IF BitField=0 THEN
+			IF oddout=addr(0) THEN
+				data_write_mux <= "--------"&"--------"&data_write_muxin;
+			ELSE
+				data_write_mux <= "--------"&data_write_muxin&"--------";
+			END IF;
+		ELSE
+			IF oddout=addr(0) THEN
+				data_write_mux <= "--------"&bf_ext_out&data_write_muxin;
+			ELSE
+				data_write_mux <= bf_ext_out&data_write_muxin&"--------";
+			END IF;
+		END IF;
+		
+		IF memmaskmux(1)='0' THEN
+			data_write <= data_write_mux(47 downto 32);
+		ELSIF memmaskmux(3)='0' THEN	
+			data_write <= data_write_mux(31 downto 16);
+		ELSE
+-- a single byte shows up on both bus halfs
+			IF memmaskmux(5 downto 4) = "10" THEN
+				data_write <= data_write_mux(7 downto 0) & data_write_mux(7 downto 0);
+			ELSIF memmaskmux(5 downto 4) = "01" THEN
+				data_write <= data_write_mux(15 downto 8) & data_write_mux(15 downto 8);
+			ELSE
+				data_write <= data_write_mux(15 downto 0);
+			END IF;
+		END IF;
+		IF exec(mem_byte)='1' THEN	--movep
+			data_write(7 downto 0) <= data_write_tmp(15 downto 8);
 		END IF;
 	END PROCESS;
-
------------------------------------------------------------------------------
--- Registerfile
------------------------------------------------------------------------------
-PROCESS (clk, regfile, RDindex_A, RDindex_B, exec)
-	BEGIN
-		reg_QA <= regfile(RDindex_A);
-		reg_QB <= regfile(RDindex_B);
-		IF rising_edge(clk) THEN
-			IF clkena_lw='1' THEN
-				rf_source_addrd <= rf_source_addr;
-				WR_AReg <= rf_dest_addr(3);
-				RDindex_A <= conv_integer(rf_dest_addr(3 downto 0));
-				RDindex_B <= conv_integer(rf_source_addr(3 downto 0));
-				IF Wwrena='1' THEN
-					regfile(RDindex_A) <= regin;
-				END IF;
-
-				IF exec(to_USP)='1' THEN
-					USP <= reg_QA;
-				END IF;
-			END IF;
-		END IF;
-	END PROCESS;
-
------------------------------------------------------------------------------
--- Write Reg
------------------------------------------------------------------------------
-PROCESS (OP1in, reg_QA, Regwrena_now, Bwrena, Lwrena, exe_datatype, WR_AReg, movem_actiond, exec, ALUout, memaddr, memaddr_a, ea_only, USP, movec_data)
-	BEGIN
-		regin <= ALUout;
-		IF exec(save_memaddr)='1' THEN
-			regin <= memaddr;
-		ELSIF exec(get_ea_now)='1' AND ea_only='1' THEN
-			regin <= memaddr_a;
-		ELSIF exec(from_USP)='1' THEN
-			regin <= USP;
-		ELSIF exec(movec_rd)='1' THEN
-			regin <= movec_data;
-		END IF;
-
-		IF Bwrena='1' THEN
-			regin(15 downto 8) <= reg_QA(15 downto 8);
-		END IF;
-		IF Lwrena='0' THEN
-			regin(31 downto 16) <= reg_QA(31 downto 16);
-		END IF;
-
-		Bwrena <= '0';
-		Wwrena <= '0';
-		Lwrena <= '0';
-		IF exec(presub)='1' OR exec(postadd)='1' OR exec(changeMode)='1' THEN           -- -(An)+
-			Wwrena <= '1';
-			Lwrena <= '1';
-		ELSIF Regwrena_now='1' THEN             --dbcc
-			Wwrena <= '1';
-		ELSIF exec(Regwrena)='1' THEN           --read (mem)
-			Wwrena <= '1';
-			CASE exe_datatype IS
-				WHEN "00" =>            --BYTE
-					Bwrena <= '1';
-				WHEN "01" =>            --WORD
-					IF WR_AReg='1' OR movem_actiond='1' THEN
-						Lwrena <='1';
-					END IF;
-				WHEN OTHERS =>          --LONG
-					Lwrena <= '1';
-			END CASE;
-		END IF;
-	END PROCESS;
-
+	
+-----------------------------------------------------------------------------
+-- Registerfile
+-----------------------------------------------------------------------------
+PROCESS (clk, regfile, RDindex_A, RDindex_B, exec)
+	BEGIN
+		reg_QA <= regfile(RDindex_A);
+		reg_QB <= regfile(RDindex_B);
+		IF rising_edge(clk) THEN
+		    IF clkena_lw='1' THEN
+				rf_source_addrd <= rf_source_addr;
+				WR_AReg <= rf_dest_addr(3);
+				RDindex_A <= conv_integer(rf_dest_addr(3 downto 0));
+				RDindex_B <= conv_integer(rf_source_addr(3 downto 0));
+				IF Wwrena='1' THEN
+					regfile(RDindex_A) <= regin;
+				END IF;
+				
+				IF exec(to_USP)='1' THEN
+					USP <= reg_QA;
+				END IF;	
+			END IF;
+		END IF;
+	END PROCESS;
+
+-----------------------------------------------------------------------------
+-- Write Reg
+-----------------------------------------------------------------------------
+PROCESS (OP1in, reg_QA, Regwrena_now, Bwrena, Lwrena, exe_datatype, WR_AReg, movem_actiond, exec, ALUout, memaddr, memaddr_a, ea_only, USP, movec_data)
+	BEGIN
+		regin <= ALUout;
+		IF exec(save_memaddr)='1' THEN
+			regin <= memaddr;	
+		ELSIF exec(get_ea_now)='1' AND ea_only='1' THEN
+			regin <= memaddr_a;	
+		ELSIF exec(from_USP)='1' THEN
+			regin <= USP;	
+		ELSIF exec(movec_rd)='1' THEN
+			regin <= movec_data;
+		END IF;
+		
+		IF Bwrena='1' THEN
+			regin(15 downto 8) <= reg_QA(15 downto 8);
+		END IF;
+		IF Lwrena='0' THEN
+			regin(31 downto 16) <= reg_QA(31 downto 16);
+		END IF;
+
+		Bwrena <= '0';
+		Wwrena <= '0';
+		Lwrena <= '0';
+		IF exec(presub)='1' OR exec(postadd)='1' OR exec(changeMode)='1' THEN		-- -(An)+
+			Wwrena <= '1';
+			Lwrena <= '1';
+		ELSIF Regwrena_now='1' THEN		--dbcc	
+			Wwrena <= '1';
+		ELSIF exec(Regwrena)='1' THEN		--read (mem)
+			Wwrena <= '1';
+			CASE exe_datatype IS
+				WHEN "00" =>		--BYTE
+					Bwrena <= '1';
+				WHEN "01" =>		--WORD
+					IF WR_AReg='1' OR movem_actiond='1' THEN
+						Lwrena <='1';
+					END IF;
+				WHEN OTHERS =>		--LONG
+					Lwrena <= '1';
+			END CASE;
+		END IF;	
+	END PROCESS;
+	
 -----------------------------------------------------------------------------
 -- set dest regaddr
 -----------------------------------------------------------------------------
-PROCESS (opcode, rf_source_addrd, brief, setstackaddr, dest_hbits, dest_areg, data_is_source, sndOPC, exec, set, dest_2ndHbits)
+PROCESS (opcode, rf_source_addrd, brief, setstackaddr, dest_hbits, dest_areg, dest_LDRareg, data_is_source, sndOPC, exec, set, dest_2ndHbits, dest_2ndLbits, dest_LDRHbits, dest_LDRLbits, last_data_read)
 	BEGIN
 		IF exec(movem_action) ='1' THEN
 			rf_dest_addr <= rf_source_addrd;
 		ELSIF set(briefext)='1' THEN
 			rf_dest_addr <= brief(15 downto 12);
-		ELSIF set(get_bfoffset)='1' THEN
-			rf_dest_addr <= sndOPC(9 downto 6);
+		ELSIF set(get_bfoffset)='1' THEN
+--			IF opcode(15 downto 12)="1110" THEN
+				rf_dest_addr <= '0'&sndOPC(8 downto 6);
+--			ELSE
+--				rf_dest_addr <= sndOPC(9 downto 6);
+--			END IF;
 		ELSIF dest_2ndHbits='1' THEN
-			rf_dest_addr <= sndOPC(15 downto 12);
-		ELSIF set(write_reminder)='1' THEN
-			rf_dest_addr <= sndOPC(3 downto 0);
-		ELSIF setstackaddr='1' THEN
+			rf_dest_addr <= dest_LDRareg&sndOPC(14 downto 12);
+		ELSIF dest_LDRHbits='1' THEN
+			rf_dest_addr <= last_data_read(15 downto 12);
+		ELSIF dest_LDRLbits='1' THEN
+			rf_dest_addr <= '0'&last_data_read(2 downto 0);
+		ELSIF dest_2ndLbits='1' THEN
+			rf_dest_addr <= '0'&sndOPC(2 downto 0);
+		ELSIF setstackaddr='1' THEN	
 			rf_dest_addr <= "1111";
-		ELSIF dest_hbits='1' THEN
+		ELSIF dest_hbits='1' THEN	
 			rf_dest_addr <= dest_areg&opcode(11 downto 9);
 		ELSE
-			IF opcode(5 downto 3)="000" OR data_is_source='1' THEN
+			IF opcode(5 downto 3)="000" OR data_is_source='1' THEN 			
 				rf_dest_addr <= dest_areg&opcode(2 downto 0);
 			ELSE
 				rf_dest_addr <= '1'&opcode(2 downto 0);
 			END IF;
-		END IF;
+		END IF;	
 	END PROCESS;
-
+	
 -----------------------------------------------------------------------------
 -- set source regaddr
 -----------------------------------------------------------------------------
-PROCESS (opcode, movem_presub, movem_regaddr, source_lowbits, source_areg, sndOPC, exec, set, source_2ndLbits, source_2ndHbits)
+PROCESS (opcode, movem_presub, movem_regaddr, source_lowbits, source_areg, sndOPC, exec, set, source_2ndLbits, source_2ndHbits, 	source_LDRLbits, source_LDRMbits, last_data_read, source_2ndMbits)
 	BEGIN
 		IF exec(movem_action)='1' OR set(movem_action) ='1' THEN
 			IF movem_presub='1' THEN
 				rf_source_addr <= movem_regaddr XOR "1111";
 			ELSE
 				rf_source_addr <= movem_regaddr;
-			END IF;
+			END IF; 
 		ELSIF source_2ndLbits='1' THEN
-			rf_source_addr <= sndOPC(3 downto 0);
+			rf_source_addr <= '0'&sndOPC(2 downto 0);
 		ELSIF source_2ndHbits='1' THEN
-			rf_source_addr <= sndOPC(15 downto 12);
+			rf_source_addr <= '0'&sndOPC(14 downto 12);
+		ELSIF source_2ndMbits='1' THEN
+			rf_source_addr <= '0'&sndOPC(8 downto 6);
+		ELSIF source_LDRLbits='1' THEN
+			rf_source_addr <= '0'&last_data_read(2 downto 0);
+		ELSIF source_LDRMbits='1' THEN
+			rf_source_addr <= '0'&last_data_read(8 downto 6);
 		ELSIF source_lowbits='1' THEN
 			rf_source_addr <= source_areg&opcode(2 downto 0);
 		ELSIF exec(linksp)='1' THEN
 			rf_source_addr <= "1111";
 		ELSE
 			rf_source_addr <= source_areg&opcode(11 downto 9);
-		END IF;
+		END IF;	
 	END PROCESS;
-
+	
 -----------------------------------------------------------------------------
 -- set OP1out
 -----------------------------------------------------------------------------
@@ -574,34 +678,28 @@ PROCESS (reg_QA, store_in_tmp, ea_data, long_start, addr, exec, memmaskmux)
 	BEGIN
 		OP1out <= reg_QA;
 		IF exec(OP1out_zero)='1' THEN
-			OP1out <= (OTHERS => '0');
+			OP1out <= (OTHERS => '0');	
 		ELSIF exec(ea_data_OP1)='1' AND store_in_tmp='1' THEN
 			OP1out <= ea_data;
-   ELSIF exec(opcPACK)='1' THEN
-     OP1out <= data_write_tmp; 
-		ELSIF exec(movem_action)='1' OR memmaskmux(3)='0' OR exec(OP1addr)='1' THEN
+		ELSIF exec(movem_action)='1' OR memmaskmux(3)='0' OR exec(OP1addr)='1' THEN 
 			OP1out <= addr;
 		END IF;
 	END PROCESS;
-
+	
 -----------------------------------------------------------------------------
 -- set OP2out
 -----------------------------------------------------------------------------
-PROCESS (OP2out, reg_QB, exe_opcode, exe_datatype, execOPC, exec, use_direct_data,
-		 store_in_tmp, data_write_tmp, ea_data)
+PROCESS (OP2out, reg_QB, exe_opcode, exe_datatype, execOPC, exec, use_direct_data, 
+	     store_in_tmp, data_write_tmp, ea_data)
 	BEGIN
 		OP2out(15 downto 0) <= reg_QB(15 downto 0);
 		OP2out(31 downto 16) <= (OTHERS => OP2out(15));
 		IF exec(OP2out_one)='1' THEN
 			OP2out(15 downto 0) <= "1111111111111111";
-		ELSIF exec(opcEXT)='1' THEN
-			IF exe_opcode(6)='0' OR exe_opcode(8)='1' THEN      --ext.w
-				OP2out(15 downto 8) <= (OTHERS => OP2out(7));
-			END IF;
- 		ELSIF (use_direct_data='1' AND exec(opcPACK)='0') OR (exec(exg)='1' AND execOPC='1') OR exec(get_bfoffset)='1' THEN	
-			OP2out <= data_write_tmp;
+		ELSIF use_direct_data='1' OR (exec(exg)='1' AND execOPC='1') OR exec(get_bfoffset)='1' THEN	
+			OP2out <= data_write_tmp;	
 		ELSIF (exec(ea_data_OP1)='0' AND store_in_tmp='1') OR exec(ea_data_OP2)='1' THEN
-			OP2out <= ea_data;
+			OP2out <= ea_data;	
 		ELSIF exec(opcMOVEQ)='1' THEN
 			OP2out(7 downto 0) <= exe_opcode(7 downto 0);
 			OP2out(15 downto 8) <= (OTHERS => exe_opcode(7));
@@ -613,84 +711,95 @@ PROCESS (OP2out, reg_QB, exe_opcode, exe_datatype, execOPC, exec, use_direct_dat
 				OP2out(3) <='0';
 			END IF;
 			OP2out(15 downto 4) <= (OTHERS => '0');
-		ELSIF exe_datatype="10" THEN
+		ELSIF exe_datatype="10" AND exec(opcEXT)='0'  THEN 
 			OP2out(31 downto 16) <= reg_QB(31 downto 16);
 		END IF;
+		IF exec(opcEXTB)='1' THEN
+			OP2out(31 downto 8) <= (OTHERS => OP2out(7));		
+		END IF;
 	END PROCESS;
-
+	
 
 -----------------------------------------------------------------------------
 -- handle EA_data, data_write
 -----------------------------------------------------------------------------
 PROCESS (clk)
 	BEGIN
-		IF rising_edge(clk) THEN
+     	IF rising_edge(clk) THEN
 			IF Reset = '1' THEN
 				store_in_tmp <='0';
-				exec_write_back <= '0';
 				direct_data <= '0';
 				use_direct_data <= '0';
 				Z_error <= '0';
 			ELSIF clkena_lw='1' THEN
+				useStackframe2<='0';
 				direct_data <= '0';
-				IF state="11" THEN
-					exec_write_back <= '0';
-				ELSIF setstate="10" AND write_back='1' THEN
-					exec_write_back <= '1';
+				IF exec(hold_OP2)='1' THEN
+					use_direct_data <= '1';
 				END IF;
-
-
 				IF set_direct_data='1' THEN
-					direct_data <= '1';
-          IF set_exec(opcPACK)='1' THEN
-            use_direct_data <= '0';
-          ELSE
-					  use_direct_data <= '1';
-          END IF;
-				ELSIF endOPC='1' THEN
+					direct_data <= '1';
+					use_direct_data <= '1';
+				ELSIF endOPC='1' OR set(ea_data_OP2)='1' THEN	
 					use_direct_data <= '0';
-				END IF;
+				END IF;	
 				exec_DIRECT <= set_exec(opcMOVE);
-
+				
 				IF endOPC='1' THEN
 					store_in_tmp <='0';
 					Z_error <= '0';
 				ELSE
 					IF set_Z_error='1'  THEN
 						Z_error <= '1';
-					END IF;
+					END IF;	
 					IF set_exec(opcMOVE)='1' AND state="11" THEN
 						use_direct_data <= '1';
 					END IF;
 
-					IF state="10" THEN
-						store_in_tmp <= '1';
+					IF state="10" OR exec(store_ea_packdata)='1' THEN
+						store_in_tmp <= '1'; 
 					END IF;
 					IF direct_data='1' AND state="00" THEN
-						store_in_tmp <= '1';
-					END IF;
-				END IF;
-				IF state="10" THEN
+						store_in_tmp <= '1'; 
+					END IF;	
+				END IF;
+				
+				IF state="10" AND exec(hold_ea_data)='0' THEN
 					ea_data <= data_read;
-				ELSIF exec(get_2ndOPC)='1' OR set_PCbase='1' THEN --TH cmpi (d16,PC) fix
+				ELSIF exec(get_2ndOPC)='1' THEN
 					ea_data <= addr;
 				ELSIF exec(store_ea_data)='1' OR (direct_data='1' AND state="00") THEN
 					ea_data <= last_data_read;
-				END IF;
-
+				END IF;	
+				
 				IF writePC='1' THEN
 					data_write_tmp <= TG68_PC;
 				ELSIF exec(writePC_add)='1' THEN
 					data_write_tmp <= TG68_PC_add;
-				ELSIF micro_state=trap0 THEN
-					data_write_tmp(15 downto 0) <= trap_vector(15 downto 0);
-				ELSIF exec(hold_dwr)='1' THEN
+-- paste and copy form TH	---------	
+				elsif micro_state=trap00 THEN
+					data_write_tmp <= exe_pc; --TH
+					useStackframe2<='1';
+				elsif micro_state = trap0 then
+		  -- this is only active for 010+ since in 000 writePC is
+		  -- true in state trap0
+--					if trap_trace='1' or set_exec(opcTRAPV)='1' or Z_error='1' then
+					IF	useStackframe2='1' THEN
+						-- stack frame format #2
+						data_write_tmp(15 downto 0) <= "0010" & trap_vector(11 downto 0); --TH
+					else
+						data_write_tmp(15 downto 0) <= "0000" & trap_vector(11 downto 0);
+					end if;
+------------------------------------
+--				ELSIF micro_state=trap0 THEN	
+--					data_write_tmp(15 downto 0) <= trap_vector(15 downto 0);
+				ELSIF exec(hold_dwr)='1' THEN	
 					data_write_tmp <= data_write_tmp;
-				ELSIF exec(exg)='1' THEN
+				ELSIF exec(exg)='1' THEN	
 					data_write_tmp <= OP1out;
-				ELSIF exec(get_ea_now)='1' AND ea_only='1' THEN         -- ist for pea
+				ELSIF exec(get_ea_now)='1' AND ea_only='1' THEN		-- ist for pea
 					data_write_tmp <= addr;
-				ELSIF execOPC='1' or micro_state=pack2 THEN
+				ELSIF execOPC='1' THEN
 					data_write_tmp <= ALUout;
 				ELSIF (exec_DIRECT='1' AND state="10") THEN
 					data_write_tmp <= data_read;
@@ -703,13 +812,13 @@ PROCESS (clk)
 					data_write_tmp <= last_data_read;
 				ELSIF writeSR='1'THEN
 					data_write_tmp(15 downto 0) <= trap_SR(7 downto 0)& Flags(7 downto 0);
-				ELSE
+				ELSE	
 					data_write_tmp <= OP2out;
 				END IF;
-			END IF;
-		END IF;
+			END IF;	
+		END IF;	
 	END PROCESS;
-
+	
 -----------------------------------------------------------------------------
 -- brief
 -----------------------------------------------------------------------------
@@ -722,7 +831,7 @@ PROCESS (brief, OP1out, OP1outbrief, cpu)
 		END IF;
 		briefdata <= OP1outbrief&OP1out(15 downto 0);
 		IF extAddr_Mode=1 OR (cpu(1)='1' AND extAddr_Mode=2) THEN
-			CASE brief(10 downto 9) IS -- mikej SCALE factor
+			CASE brief(10 downto 9) IS
 				WHEN "00" => briefdata <= OP1outbrief&OP1out(15 downto 0);
 				WHEN "01" => briefdata <= OP1outbrief(14 downto 0)&OP1out(15 downto 0)&'0';
 				WHEN "10" => briefdata <= OP1outbrief(13 downto 0)&OP1out(15 downto 0)&"00";
@@ -733,60 +842,59 @@ PROCESS (brief, OP1out, OP1outbrief, cpu)
 	END PROCESS;
 
 -----------------------------------------------------------------------------
--- MEM_IO
+-- MEM_IO 
 -----------------------------------------------------------------------------
-PROCESS (clk, setdisp, memaddr_a, briefdata, memaddr_delta, setdispbyte, datatype, interrupt, rIPL_nr, IPL_vec,
-		 memaddr_reg, reg_QA, use_base, VBR, last_data_read, trap_vector, exec, set, cpu)
+PROCESS (clk, setdisp, memaddr_a, briefdata, memaddr_delta, setdispbyte, datatype, interrupt, rIPL_nr, IPL_vec,
+         memaddr_reg, reg_QA, use_base, VBR, last_data_read, trap_vector, exec, set, cpu, use_VBR_Stackframe)
 	BEGIN
-
+		
 		IF rising_edge(clk) THEN
-			IF clkena_lw='1' THEN
-				trap_vector(31 downto 8) <= (others => '0');
+			IF clkena_lw='1' THEN
+				trap_vector(31 downto 10) <= (others => '0');
 				IF trap_berr='1' THEN
-					trap_vector(7 downto 0) <= X"08";
+					trap_vector(9 downto 0) <= "00" & X"08";
 				END IF;	
 				IF trap_addr_error='1' THEN
-					trap_vector(7 downto 0) <= X"0C";
-				END IF;
+					trap_vector(9 downto 0) <= "00" & X"0C";
+				END IF;	
 				IF trap_illegal='1' THEN
-					trap_vector(7 downto 0) <= X"10";
-				END IF;
-				IF z_error='1' THEN
-					trap_vector(7 downto 0) <= X"14";
-				END IF;
+					trap_vector(9 downto 0) <= "00" & X"10";
+				END IF;	
+				IF set_Z_error='1' THEN
+					trap_vector(9 downto 0) <= "00" & X"14";
+				END IF;	
 				IF exec(trap_chk)='1' THEN
-					trap_vector(7 downto 0) <= X"18";
-				END IF;
+					trap_vector(9 downto 0) <= "00" & X"18";
+				END IF;	
 				IF trap_trapv='1' THEN
-					trap_vector(7 downto 0) <= X"1C";
-				END IF;
+					trap_vector(9 downto 0) <= "00" & X"1C";
+				END IF;	
 				IF trap_priv='1' THEN
-					trap_vector(7 downto 0) <= X"20";
-				END IF;
+					trap_vector(9 downto 0) <= "00" & X"20";
+				END IF;	
 				IF trap_trace='1' THEN
-					trap_vector(7 downto 0) <= X"24";
-				END IF;
+					trap_vector(9 downto 0) <= "00" & X"24";
+				END IF;	
 				IF trap_1010='1' THEN
-					trap_vector(7 downto 0) <= X"28";
-				END IF;
+					trap_vector(9 downto 0) <= "00" & X"28";
+				END IF;	
 				IF trap_1111='1' THEN
-					trap_vector(7 downto 0) <= X"2C";
-				END IF;
+					trap_vector(9 downto 0) <= "00" & X"2C";
+				END IF;	
 				IF trap_trap='1' THEN
-					trap_vector(7 downto 0) <= "10"&opcode(3 downto 0)&"00";
-				END IF;
-				IF trap_interrupt='1' THEN
-					trap_vector(9 downto 0) <= IPL_vec & "00";   --TH
-				END IF;
-								-- TH TODO: non-autovector IRQs
+					trap_vector(9 downto 0) <= "0010" & opcode(3 downto 0) & "00";
+				END IF;	
+				IF trap_interrupt='1' or set_vectoraddr = '1' THEN
+					trap_vector(9 downto 0) <= IPL_vec & "00";      --TH
+				END IF;	
 			END IF;
 		END IF;
-		IF VBR_Stackframe=0 OR (cpu(0)='0' AND VBR_Stackframe=2) THEN
-			trap_vector_vbr <= trap_vector;
-		ELSE
+		IF use_VBR_Stackframe='1' THEN
 			trap_vector_vbr <= trap_vector+VBR;
-		END IF;
-
+		ELSE		
+			trap_vector_vbr <= trap_vector;
+		END IF;		
+		
 		memaddr_a(4 downto 0) <= "00000";
 		memaddr_a(7 downto 5) <= (OTHERS=>memaddr_a(4));
 		memaddr_a(15 downto 8) <= (OTHERS=>memaddr_a(7));
@@ -798,36 +906,28 @@ PROCESS (clk, setdisp, memaddr_a, briefdata, memaddr_delta, setdispbyte, datatyp
 				memaddr_a(7 downto 0) <= last_data_read(7 downto 0);
 			ELSE
 				memaddr_a <= last_data_read;
-			END IF;
+			END IF;	 
 		ELSIF set(presub)='1' THEN
-			IF set(longaktion)='1' THEN
+			IF set(longaktion)='1' THEN	
 				memaddr_a(4 downto 0) <= "11100";
 			ELSIF datatype="00" AND set(use_SP)='0' THEN
 				memaddr_a(4 downto 0) <= "11111";
 			ELSE
 				memaddr_a(4 downto 0) <= "11110";
-			END IF;
+			END IF;	
 		ELSIF interrupt='1' THEN
-			memaddr_a(4 downto 0) <= '1'&rIPL_nr&'0';
-		END IF;
-
+			memaddr_a(4 downto 0) <= '1'&rIPL_nr&'0';	
+		END IF;	 
+		
 		IF rising_edge(clk) THEN
 			IF clkena_in='1' THEN
 				IF exec(get_2ndOPC)='1' OR (state="10" AND memread(0)='1') THEN
 					tmp_TG68_PC <= addr;
 				END IF;
-				use_base <= '0';
-
-				IF memmaskmux(3)='0' THEN
-					  memaddr_delta <= addsub_q;
-				ELSIF exec(mem_addsub)='1' THEN
-					-- note, this should give an exception for 68000
-					if exec(movem_action) = '1' and memmaskmux(3) = '1' and (memmaskmux(5 downto 4) = "10" or memmaskmux(5 downto 4) = "01") and (movem_presub = '0') then
-					  memaddr_delta <= addr; -- hold for non-aligned case, only when incrementing
-					else
-					  memaddr_delta <= addsub_q;
-					end if;
-				ELSIF state="01" AND exec_write_back='1' THEN
+				use_base <= '0'; 
+				IF memmaskmux(3)='0' OR exec(mem_addsub)='1' THEN
+					memaddr_delta <= addsub_q;	
+				ELSIF set(restore_ADDR)='1' THEN			
 					memaddr_delta <= tmp_TG68_PC;
 				ELSIF exec(direct_delta)='1' THEN
 					memaddr_delta <= data_read;
@@ -835,46 +935,51 @@ PROCESS (clk, setdisp, memaddr_a, briefdata, memaddr_delta, setdispbyte, datatyp
 					memaddr_delta <= addr;
 				ELSIF set(addrlong)='1' THEN
 					memaddr_delta <= last_data_read;
-				ELSIF setstate="00" THEN
+				ELSIF setstate="00" THEN	
 					memaddr_delta <= TG68_PC_add;
 				ELSIF exec(dispouter)='1' THEN
 					memaddr_delta <= ea_data+memaddr_a;
-				ELSIF set_vectoraddr='1' THEN
+				ELSIF set_vectoraddr='1' THEN	
 					memaddr_delta <= trap_vector_vbr;
-				ELSE
+				ELSE 
 					memaddr_delta <= memaddr_a;
 					IF interrupt='0' AND Suppress_Base='0' THEN
---                                      IF interrupt='0' AND Suppress_Base='0' AND setstate(1)='1' THEN
+--					IF interrupt='0' AND Suppress_Base='0' AND setstate(1)='1' THEN
 						use_base <= '1';
+					END IF;	
+				END IF;
+					
+		-- only used for movem address update
+--					IF (long_done='0' AND state(1)='1') OR movem_presub='0' THEN
+					if ((memread(0) = '1') and state(1) = '1') or movem_presub = '0' then -- fix for unaligned movem mikej
+						memaddr <= addr;
 					END IF;
-				END IF;
-
-				IF (long_done='0' AND state(1)='1') OR movem_presub='0' THEN
-				  memaddr <= addr;
-				END IF;
 			END IF;
 		END IF;
-		-- if access done, and not aligned, don't increment
+
+		-- if access done, and not aligned, don't increment
 		addr <= memaddr_reg+memaddr_delta;
+		addr_out <= memaddr_reg + memaddr_delta;
+
 		IF use_base='0' THEN
 			memaddr_reg <= (others=>'0');
-		ELSE
+		ELSE	
 			memaddr_reg <= reg_QA;
-		END IF;
-	END PROCESS;
-
+		END IF;	
+    END PROCESS;
+    
 -----------------------------------------------------------------------------
 -- PC Calc + fetch opcode
 -----------------------------------------------------------------------------
-PROCESS (clk, IPL, setstate, state, exec_write_back, set_direct_data, next_micro_state, stop, make_trace, make_berr, IPL_nr, FlagsSR, set_rot_cnt, opcode, writePCbig, set_exec, exec,
-		 PC_dataa, PC_datab, setnextpass, last_data_read, TG68_PC_brw, TG68_PC_word, Z_error, trap_trap, trap_trapv, interrupt, tmp_TG68_PC, TG68_PC)
+PROCESS (clk, IPL, setstate, addrvalue, state, exec_write_back, set_direct_data, next_micro_state, stop, make_trace, make_berr, IPL_nr, FlagsSR, set_rot_cnt, opcode, writePCbig, set_exec, exec,
+        PC_dataa, PC_datab, setnextpass, last_data_read, TG68_PC_brw, TG68_PC_word, Z_error, trap_trap, trap_trapv, interrupt, tmp_TG68_PC, TG68_PC)
 	BEGIN
-
+	
 		PC_dataa <= TG68_PC;
 		IF TG68_PC_brw = '1' THEN
 			PC_dataa <= tmp_TG68_PC;
 		END IF;
-
+		
 		PC_datab(2 downto 0) <= (others => '0');
 		PC_datab(3) <= PC_datab(2);
 		PC_datab(7 downto 4) <= (others => PC_datab(3));
@@ -887,16 +992,16 @@ PROCESS (clk, IPL, setstate, state, exec_write_back, set_direct_data, next_micro
 			IF writePCbig='1' THEN
 				PC_datab(3) <= '1';
 				PC_datab(1) <= '1';
-			ELSE
+			ELSE	
 				PC_datab(2) <= '1';
 			END IF;
-			IF trap_trap='1' OR trap_trapv='1' OR exec(trap_chk)='1' OR Z_error='1' THEN
+			IF trap_trap='1' OR trap_trapv='1' OR exec(trap_chk)='1' OR Z_error='1' THEN 
 				PC_datab(1) <= '1';
 			END IF;
 		ELSIF state="00" THEN
 			PC_datab(1) <= '1';
-		END IF;
-		IF TG68_PC_brw = '1' THEN
+		END IF;	
+		IF TG68_PC_brw = '1' THEN	
 			IF TG68_PC_word='1' THEN
 				PC_datab <= last_data_read;
 			ELSE
@@ -905,131 +1010,149 @@ PROCESS (clk, IPL, setstate, state, exec_write_back, set_direct_data, next_micro
 		END IF;
 
 		TG68_PC_add <= PC_dataa+PC_datab;
-
+		
 		setopcode <= '0';
 		setendOPC <= '0';
 		setinterrupt <= '0';
 		IF setstate="00" AND next_micro_state=idle AND setnextpass='0' AND (exec_write_back='0' OR state="11") AND set_rot_cnt="000001" AND set_exec(opcCHK)='0'THEN
 			setendOPC <= '1';
-			IF FlagsSR(2 downto 0)<IPL_nr OR IPL_nr="111"  OR make_trace='1'  OR make_berr='1' THEN
+			IF FlagsSR(2 downto 0)<IPL_nr OR IPL_nr="111"  OR make_trace='1' OR make_berr='1' THEN
 				setinterrupt <= '1';
 			ELSIF stop='0' THEN
 				setopcode <= '1';
 			END IF;
-		END IF;
+		END IF;	
 		setexecOPC <= '0';
-		IF setstate="00" AND next_micro_state=idle AND set_direct_data='0' AND (exec_write_back='0' OR state="10") THEN
+		IF setstate="00" AND next_micro_state=idle AND set_direct_data='0' AND (exec_write_back='0' OR (state="10" AND addrvalue='0')) THEN
 			setexecOPC <= '1';
 		END IF;
-
+		
 		IPL_nr <= NOT IPL;
 		IF rising_edge(clk) THEN
 			IF Reset = '1' THEN
-				state <= "01";
-				opcode <= X"2E79";                                      --move $0,a7
+				state <= "01";
+				addrvalue <= '0';
+				opcode <= X"2E79"; 					--move $0,a7
 				trap_interrupt <= '0';
 				interrupt <= '0';
-				last_opc_read  <= X"4EF9";                      --jmp nn.l
+				last_opc_read  <= X"4EF9";			--jmp nn.l
 				TG68_PC <= X"00000004";
 				decodeOPC <= '0';
 				endOPC <= '0';
 				TG68_PC_word <= '0';
 				execOPC <= '0';
+--				execOPC_ALU <= '0';
 				stop <= '0';
 				rot_cnt <="000001";
-				byte <= '0';
---                              IPL_nr <= "000";
+--				byte <= '0';
+--				IPL_nr <= "000";
 				trap_trace <= '0';
-                                trap_berr <= '0';
+				trap_berr <= '0';
 				writePCbig <= '0';
---                              recall_last <= '0';
-				Suppress_Base <= '0';
+--				recall_last <= '0';
+				Suppress_Base <= '0'; 
+				make_berr <= '0';
 				memmask <= "111111";
+				exec_write_back <= '0';
 			ELSE
---                              IPL_nr <= NOT IPL;
+--				IPL_nr <= NOT IPL;
 				IF clkena_in='1' THEN
-					-- MIKEJ
-					memmask <= memmask(3 downto 0) & "11";
-					memread <= memread(1 downto 0) & memmaskmux(5 downto 4);
---                                      IF wbmemmask(5 downto 4)="11" THEN
---                                              wbmemmask <= memmask;
---                                      END IF;
+					memmask <= memmask(3 downto 0)&"11";
+					memread <= memread(1 downto 0)&memmaskmux(5 downto 4);
+--					IF wbmemmask(5 downto 4)="11" THEN	
+--						wbmemmask <= memmask;
+--					END IF;
 					IF exec(directPC)='1' THEN
 						TG68_PC <= data_read;
 					ELSIF exec(ea_to_pc)='1' THEN
 						TG68_PC <= addr;
-					ELSIF (state ="00" OR TG68_PC_brw = '1') AND stop='0'  THEN
+					ELSIF (state ="00" OR TG68_PC_brw = '1') AND stop='0'  THEN				
 						TG68_PC <= TG68_PC_add;
-					END IF;
-				END IF;
+					END IF;	
+				END IF;	
 				IF clkena_lw='1' THEN
 					interrupt <= setinterrupt;
 					decodeOPC <= setopcode;
 					endOPC <= setendOPC;
-					execOPC <= setexecOPC;
-
+					execOPC <= setexecOPC;
+--					IF setexecOPC='1' OR set(alu_exec)='1' THEN
+--						execOPC_ALU <= '1';
+--					ELSE
+--						execOPC_ALU <= '0';
+--					END IF;
+					
 					exe_datatype <= set_datatype;
 					exe_opcode <= opcode;
-                                        
+
 					if(trap_berr='0') then
-						make_berr <= (berr OR make_berr);
-					else
-						make_berr <= '0';
-					end if;
-                                                                   
+						make_berr <= (berr OR make_berr);
+					else
+						make_berr <= '0';
+					end if;
+						
 					stop <= set_stop OR (stop AND NOT setinterrupt);
 					IF setinterrupt='1' THEN
-						make_berr <= '0';
-						trap_berr <= '0';
+						trap_interrupt <= '0';
+						trap_trace <= '0';
+--						TG68_PC_word <= '0';
+						make_berr <= '0';
+						trap_berr <= '0';
 						IF make_trace='1' THEN
 							trap_trace <= '1';
-						ELSIF make_berr='1' THEN
-							trap_berr <= '1';
-						ELSE
-							rIPL_nr <= IPL_nr;
-							IPL_vec <= "00011"&IPL_nr;            --    TH
+						ELSIF make_berr='1' THEN
+							trap_berr <= '1';
+						ELSE	
+							rIPL_nr <= IPL_nr;
+							IPL_vec <= "00011"&IPL_nr;            --	TH		
 							trap_interrupt <= '1';
 						END IF;
-					END IF;
-					IF micro_state=trap0 AND IPL_autovector='0' THEN
-						IPL_vec <= last_data_read(7 downto 0);    --    TH
-					END IF;
-					IF state="00" THEN
+					END IF;	
+					IF micro_state=trap0 AND IPL_autovector='0' THEN 			
+						IPL_vec <= last_data_read(7 downto 0);    --	TH
+					END IF;	
+					IF state="00" THEN				
 						last_opc_read <= data_read(15 downto 0);
-					END IF;
+						last_opc_pc <= tg68_pc;--TH
+					END IF;	
 					IF setopcode='1' THEN
 						trap_interrupt <= '0';
 						trap_trace <= '0';
 						TG68_PC_word <= '0';
-                                                trap_berr <= '0';
+						trap_berr <= '0';
 					ELSIF opcode(7 downto 0)="00000000" OR opcode(7 downto 0)="11111111" OR data_is_source='1' THEN
 						TG68_PC_word <= '1';
-					END IF;
-
+					END IF;	
+					
 					IF exec(get_bfoffset)='1' THEN
 						alu_width <= bf_width;
 						alu_bf_shift <= bf_shift;
 						alu_bf_loffset <= bf_loffset;
+						alu_bf_ffo_offset <= bf_full_offset+bf_width+1;
 					END IF;
-					byte <= '0';
 					memread <= "1111";
 					FC(1) <= NOT setstate(1) OR (PCbase AND NOT setstate(0));
 					FC(0) <= setstate(1) AND (NOT PCbase OR setstate(0));
 					IF interrupt='1' THEN
 						FC(1 downto 0) <= "11";
-					END IF;
-					IF (state="10" AND write_back='1' AND setstate/="10") OR set_rot_cnt/="000001" OR (stop='1' AND interrupt='0') OR set_exec(opcCHK)='1' THEN
+					END IF;	
+					
+					IF state="11" THEN
+						exec_write_back <= '0';
+					ELSIF setstate="10" AND setaddrvalue='0' AND write_back='1' THEN
+						exec_write_back <= '1';
+					END IF;	
+					IF (state="10" AND addrvalue='0' AND write_back='1' AND setstate/="10") OR set_rot_cnt/="000001" OR (stop='1' AND interrupt='0') OR set_exec(opcCHK)='1' THEN
 						state <= "01";
-						memmask <= "111111";
+						memmask <= "111111";
+						addrvalue <= '0';
 					ELSIF execOPC='1' AND exec_write_back='1' THEN
 						state <= "11";
 						FC(1 downto 0) <= "01";
 						memmask <= wbmemmask;
-						IF datatype="00" THEN
-							byte <= '1';
-						END IF;
-					ELSE
-						state <= setstate;
+						addrvalue <= '0';
+					ELSE	
+						state <= setstate;
+						addrvalue <= setaddrvalue; 
 						IF setstate="01" THEN
 							memmask <= "111111";
 							wbmemmask <= "111111";
@@ -1041,37 +1164,35 @@ PROCESS (clk, IPL, setstate, state, exec_write_back, set_direct_data, next_micro
 							memmask <= "100001";
 							wbmemmask <= "100001";
 							oddout <= '0';
-						ELSIF set_datatype="00" AND setstate(1)='1' THEN
+--						ELSIF set_datatype="00" AND setstate(1)='1' AND setaddrvalue='0' THEN	
+						ELSIF set_datatype="00" AND setstate(1)='1' THEN	
 							memmask <= "101111";
-							wbmemmask <= "101111";
-							IF set(mem_byte)='1' THEN
-								oddout <= '0';
+							wbmemmask <= "101111";
+							IF set(mem_byte)='1' THEN
+								oddout <= '0';
 							ELSE
 								oddout <= '1';
-							END IF;
-						ELSE
+							END IF;	
+						ELSE	
 							memmask <= "100111";
 							wbmemmask <= "100111";
 							oddout <= '0';
-						END IF;
+						END IF;	
 					END IF;
 
 					IF decodeOPC='1' THEN
 						rot_bits <= set_rot_bits;
 						writePCbig <= '0';
-					ELSE
-						writePCbig <= set_writePCbig OR writePCbig;
+					ELSE	
+						writePCbig <= set_writePCbig OR writePCbig; 
 					END IF;
 					IF decodeOPC='1' OR exec(ld_rot_cnt)='1' OR rot_cnt/="000001" THEN
 						rot_cnt <= set_rot_cnt;
 					END IF;
-					IF setstate(1)='1' AND set_datatype="00" THEN
-						byte <= '1';
-					END IF;
-
+					
 					IF set_Suppress_Base='1' THEN
 						Suppress_Base <= '1';
-					ELSIF setstate(1)='1' OR (ea_only='1' AND set(get_ea_now)='1') THEN
+					ELSIF setstate(1)='1' OR (ea_only='1' AND set(get_ea_now)='1') THEN	
 						Suppress_Base <= '0';
 					END IF;
 					IF getbrief='1' THEN
@@ -1080,33 +1201,34 @@ PROCESS (clk, IPL, setstate, state, exec_write_back, set_direct_data, next_micro
 						ELSE
 							brief <= data_read(15 downto 0);
 						END IF;
-					END IF;
-
+					END IF;	
+					
 					IF setopcode='1' AND berr='0' THEN
 						IF state="00" THEN
 							opcode <= data_read(15 downto 0);
+							exe_pc <= tg68_pc;--TH
 						ELSE
 							opcode <= last_opc_read(15 downto 0);
+							exe_pc <= last_opc_pc;--TH
 						END IF;
 						nextpass <= '0';
-					ELSIF setinterrupt='1' THEN
-						opcode(15 downto 12) <= X"7";           --moveq
-						opcode(8 downto 6) <= "001";            --word
-						nextpass <= '0';
+					ELSIF setinterrupt='1' OR setopcode='1' THEN
+						opcode <= X"4E71";		--nop
+						nextpass <= '0';
 					ELSE
---                                              IF setnextpass='1' OR (regdirectsource='1' AND state="00") THEN
+--						IF setnextpass='1' OR (regdirectsource='1' AND state="00") THEN
 						IF setnextpass='1' OR regdirectsource='1' THEN
-							nextpass <= '1';
+							nextpass <= '1';	
 						END IF;
-					END IF;
+					END IF;
 
 					IF decodeOPC='1' OR interrupt='1' THEN
 						trap_SR <= FlagsSR;
 					END IF;
-				END IF;
-			END IF;
-		END IF;
-
+				END IF;	
+			END IF;	
+		END IF;	
+	
 		IF rising_edge(clk) THEN
 			IF Reset = '1' THEN
 				PCbase <= '1';
@@ -1114,48 +1236,60 @@ PROCESS (clk, IPL, setstate, state, exec_write_back, set_direct_data, next_micro
 				PCbase <= set_PCbase OR PCbase;
 				IF setexecOPC='1' OR (state(1)='1' AND movem_run='0') THEN
 					PCbase <= '0';
-				END IF;
-			END IF;
+				END IF;	
+			END IF;	
 			IF clkena_lw='1' THEN
 				exec <= set;
+				exec(alu_move) <= set(opcMOVE) OR set(alu_move);
+				exec(alu_setFlags) <= set(opcADD) OR set(alu_setFlags);
 				exec_tas <= '0';
 				exec(subidx) <= set(presub) or set(subidx);
 				IF setexecOPC='1' THEN
-					exec <= set_exec OR set;
+					exec <= set_exec OR set;
+					exec(alu_move) <= set_exec(opcMOVE) OR set(opcMOVE) OR set(alu_move);
+					exec(alu_setFlags) <= set_exec(opcADD) OR set(opcADD) OR set(alu_setFlags);
 					exec_tas <= set_exec_tas;
-				END IF;
+				END IF;	
 				exec(get_2ndOPC) <= set(get_2ndOPC) OR setopcode;
-			END IF;
-		END IF;
+			END IF;	
+		END IF;	
 	END PROCESS;
-
+	
 ------------------------------------------------------------------------------
 --prepare Bitfield Parameters
-------------------------------------------------------------------------------
+------------------------------------------------------------------------------		
 PROCESS (clk, Reset, sndOPC, reg_QA, reg_QB, bf_width, bf_offset, bf_bhits, opcode, setstate, bf_shift)
 	BEGIN
 		IF sndOPC(11)='1' THEN
 			bf_offset <= '0'&reg_QA(4 downto 0);
 		ELSE
 			bf_offset <= '0'&sndOPC(10 downto 6);
-		END IF;
-
+		END IF;	
+		IF sndOPC(11)='1' THEN
+			bf_full_offset <= reg_QA;
+		ELSE
+			bf_full_offset <= (others => '0');
+			bf_full_offset(4 downto 0) <= sndOPC(10 downto 6);
+		END IF;	
+		
 		bf_width(5) <= '0';
 		IF sndOPC(5)='1' THEN
 			bf_width(4 downto 0) <= reg_QB(4 downto 0)-1;
 		ELSE
 			bf_width(4 downto 0) <= sndOPC(4 downto 0)-1;
-		END IF;
+		END IF;	
 		bf_bhits <= bf_width+bf_offset;
 		set_oddout <= NOT bf_bhits(3);
-
+		
+
+-- bf_loffset is used for the shifted_bitmask
 		IF opcode(10 downto 8)="111" THEN --INS
 			bf_loffset <= 32-bf_shift;
 		ELSE
 			bf_loffset <= bf_shift;
 		END IF;
 		bf_loffset(5) <= '0';
-
+		
 		IF opcode(4 downto 3)="00" THEN
 			IF opcode(10 downto 8)="111" THEN --INS
 				bf_shift <= bf_bhits+1;
@@ -1164,34 +1298,35 @@ PROCESS (clk, Reset, sndOPC, reg_QA, reg_QB, bf_width, bf_offset, bf_bhits, opco
 			END IF;
 			bf_shift(5) <= '0';
 		ELSE
-			IF opcode(10 downto 8)="111" THEN --INS
-				bf_shift <= "011"&("001"+bf_bhits(2 downto 0));
+			IF opcode(10 downto 8)="111" THEN --INS
+				bf_shift <= "011001"+("000"&bf_bhits(2 downto 0));
+				bf_shift(5) <= '0';
 			ELSE
 				bf_shift <= "000"&("111"-bf_bhits(2 downto 0));
 			END IF;
 			bf_offset(4 downto 3) <= "00";
 		END IF;
-
-			CASE bf_bhits(5 downto 3) IS
-				WHEN "000" =>
-					set_memmask <= "101111";
-				WHEN "001" =>
-					set_memmask <= "100111";
-				WHEN "010" =>
-					set_memmask <= "100011";
-				WHEN "011" =>
-					set_memmask <= "100001";
-				WHEN OTHERS =>
-					set_memmask <= "100000";
-			END CASE;
-			IF setstate="00" THEN
+		
+		CASE bf_bhits(5 downto 3) IS
+			WHEN "000" =>
+				set_memmask <= "101111";
+			WHEN "001" =>
 				set_memmask <= "100111";
-			END IF;
-	END PROCESS;
-
+			WHEN "010" =>
+				set_memmask <= "100011";
+			WHEN "011" =>
+				set_memmask <= "100001";
+			WHEN OTHERS =>
+				set_memmask <= "100000";
+		END CASE;	
+		IF setstate="00" THEN
+			set_memmask <= "100111";
+		END IF;
+	END PROCESS;		
+	
 ------------------------------------------------------------------------------
 --SR op
-------------------------------------------------------------------------------
+------------------------------------------------------------------------------		
 PROCESS (clk, Reset, FlagsSR, last_data_read, OP2out, exec)
 	BEGIN
 		IF exec(andiSR)='1' THEN
@@ -1200,27 +1335,26 @@ PROCESS (clk, Reset, FlagsSR, last_data_read, OP2out, exec)
 			SRin <= FlagsSR XOR last_data_read(15 downto 8);
 		ELSIF exec(oriSR)='1' THEN
 			SRin <= FlagsSR OR last_data_read(15 downto 8);
-		ELSE
+		ELSE	
 			SRin <= OP2out(15 downto 8);
-		END IF;
-
+		END IF;	
+		
 		IF rising_edge(clk) THEN
 			IF Reset='1' THEN
-				FlagsSR(5) <= '1';
 				FC(2) <= '1';
 				SVmode <= '1';
 				preSVmode <= '1';
-				FlagsSR(2 downto 0) <= "111";
+				FlagsSR <= "00100111";
 				make_trace <= '0';
 			ELSIF clkena_lw = '1' THEN
 				IF setopcode='1' THEN
 					make_trace <= FlagsSR(7);
 					IF set(changeMode)='1' THEN
-						SVmode <= NOT SVmode;
+						SVmode <= NOT SVmode; 
 					ELSE
 						SVmode <= preSVmode;
-					END IF;
-				END IF;
+					END IF;	
+				END IF;	
 				IF set(changeMode)='1' THEN
 					preSVmode <= NOT preSVmode;
 					FlagsSR(5) <= NOT preSVmode;
@@ -1234,23 +1368,26 @@ PROCESS (clk, Reset, FlagsSR, last_data_read, OP2out, exec)
 				END IF;
 				IF exec(directSR)='1' OR set_stop='1' THEN
 					FlagsSR <= data_read(15 downto 8);
-				END IF;
+				END IF;	
 				IF interrupt='1' AND trap_interrupt='1' THEN
 					FlagsSR(2 downto 0) <=rIPL_nr;
-				END IF;
---                              IF exec(to_CCR)='1' AND exec(to_SR)='1' THEN
+				END IF;	
 				IF exec(to_SR)='1' THEN
-					FlagsSR(7 downto 0) <= SRin;        --SR
+					FlagsSR(7 downto 0) <= SRin;	--SR
 					FC(2) <= SRin(5);
---                              END IF;
 				ELSIF exec(update_FC)='1' THEN
 					FC(2) <= FlagsSR(5);
 				END IF;
 				IF interrupt='1' THEN
 					FC(2) <= '1';
+				END IF;	
+				IF cpu(1)='0' THEN
+					FlagsSR(4) <= '0';
+					FlagsSR(6) <= '0';
 				END IF;
+				FlagsSR(3) <= '0';
 			END IF;
-		END IF;
+		END IF;	
 	END PROCESS;
 
 -----------------------------------------------------------------------------
@@ -1258,12 +1395,13 @@ PROCESS (clk, Reset, FlagsSR, last_data_read, OP2out, exec)
 -----------------------------------------------------------------------------
 PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state, decodeOPC, state, setexecOPC, Flags, FlagsSR, direct_data, build_logical,
 		 build_bcd, set_Z_error, trapd, movem_run, last_data_read, set, set_V_Flag, z_error, trap_trace, trap_interrupt,
-		 SVmode, preSVmode, stop, long_done, ea_only, setstate, execOPC, exec_write_back, exe_datatype,
-		 datatype, interrupt, c_out, trapmake, rot_cnt, brief, addr,
+		 SVmode, preSVmode, stop, long_done, ea_only, setstate, addrvalue, execOPC, exec_write_back, exe_datatype,
+		 datatype, interrupt, c_out, trapmake, rot_cnt, brief, addr, trap_trapv, last_data_in, use_VBR_Stackframe,
 		 long_start, set_datatype, sndOPC, set_exec, exec, ea_build_now, reg_QA, reg_QB, make_berr, trap_berr)
 	BEGIN
-		TG68_PC_brw <= '0';
-		setstate <= "00";
+		TG68_PC_brw <= '0';	
+		setstate <= "00";
+		setaddrvalue <= '0';
 		Regwrena_now <= '0';
 		movem_presub <= '0';
 		setnextpass <= '0';
@@ -1271,20 +1409,28 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 		setdisp <= '0';
 		setdispbyte <= '0';
 		getbrief <= '0';
-		dest_areg <= '0';
+		dest_LDRareg <= '0';
+		dest_areg <= '0';
 		source_areg <= '0';
 		data_is_source <= '0';
 		write_back <= '0';
 		setstackaddr <= '0';
 		writePC <= '0';
 		ea_build_now <= '0';
-		set_rot_bits <= "XX";
+--		set_rot_bits <= "00";
+		set_rot_bits <= opcode(4 downto 3);
 		set_rot_cnt <= "000001";
 		dest_hbits <= '0';
-		source_lowbits <= '0';
+		source_lowbits <= '0';
+		source_LDRLbits <= '0';
+		source_LDRMbits <= '0';
 		source_2ndHbits <= '0';
+		source_2ndMbits <= '0';
 		source_2ndLbits <= '0';
+		dest_LDRHbits <= '0';
+		dest_LDRLbits <= '0';
 		dest_2ndHbits <= '0';
+		dest_2ndLbits <= '0';
 		ea_only <= '0';
 		set_direct_data <= '0';
 		set_exec_tas <= '0';
@@ -1299,9 +1445,9 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 		set_vectoraddr <='0';
 		writeSR <= '0';
 		set_stop <= '0';
-		illegal_write_mode <= '0';
-		illegal_read_mode <= '0';
-		illegal_byteaddr <= '0';
+--		illegal_write_mode <= '0';
+--		illegal_read_mode <= '0';
+--		illegal_byteaddr <= '0';
 		set_Z_error <= '0';
 
 		next_micro_state <= idle;
@@ -1309,80 +1455,102 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 		build_bcd <= '0';
 		skipFetch <= make_berr;
 		set_writePCbig <= '0';
---              set_recall_last <= '0';
+--		set_recall_last <= '0';
 		set_Suppress_Base <= '0';
 		set_PCbase <= '0';
-
+						
 		IF rot_cnt/="000001" THEN
 			set_rot_cnt <= rot_cnt-1;
-		END IF;
+		END IF;	
 		set_datatype <= datatype;
-
+		
 		set <= (OTHERS=>'0');
 		set_exec <= (OTHERS=>'0');
 		set(update_ld) <= '0';
---              odd_start <= '0';
+--		odd_start <= '0';
 ------------------------------------------------------------------------------
 --Sourcepass
-------------------------------------------------------------------------------
+------------------------------------------------------------------------------		
 		CASE opcode(7 downto 6) IS
-			WHEN "00" => datatype <= "00";              --Byte
-			WHEN "01" => datatype <= "01";              --Word
-			WHEN OTHERS => datatype <= "10";    --Long
+			WHEN "00" => datatype <= "00";		--Byte
+			WHEN "01" => datatype <= "01";		--Word
+			WHEN OTHERS => datatype <= "10";	--Long
 		END CASE;
-
-		IF trapmake='1' AND trapd='0' THEN
-			next_micro_state <= trap0;
-			IF VBR_Stackframe=0 OR (cpu(0)='0' AND VBR_Stackframe=2) THEN
+
+		IF execOPC='1' AND exec_write_back='1' THEN
+			set(restore_ADDR) <= '1';
+		END IF;
+		
+		IF interrupt='1' AND trap_berr='1' THEN
+			next_micro_state <= trap0;
+			IF preSVmode='0' THEN
+				set(changeMode) <= '1';
+			END IF;
+			setstate <= "01";
+		END IF;	
+		IF trapmake='1' AND trapd='0' THEN
+--			IF use_VBR_Stackframe='1' AND (trap_trapv='1' OR set_Z_error='1' OR exec(opcCHK)='1') THEN
+			IF use_VBR_Stackframe='1' AND (trap_trapv='1' OR set_Z_error='1' OR exec(trap_chk)='1') THEN
+				next_micro_state <= trap00;
+			else
+				next_micro_state <= trap0;
+			end if;
+			IF use_VBR_Stackframe='0' THEN
 				set(writePC_add) <= '1';
---                              set_datatype <= "10";
+--				set_datatype <= "10";
 			END IF;
 			IF preSVmode='0' THEN
 				set(changeMode) <= '1';
 			END IF;
 			setstate <= "01";
-		END IF;
-		IF interrupt='1' AND trap_berr='1' THEN
-			next_micro_state <= trap0;
-			IF preSVmode='0' THEN
-				set(changeMode) <= '1';
-			END IF;
-			setstate <= "01";
 		END IF;	
 		IF micro_state=int1 OR (interrupt='1' AND trap_trace='1') THEN
-			next_micro_state <= trap0;
---                      IF cpu(0)='0' THEN
---                              set_datatype <= "10";
---                      END IF;
+-- paste and copy form TH	---------	
+			if trap_trace='1' AND use_VBR_Stackframe='1' then
+				next_micro_state <= trap00;  --TH
+			else
+				next_micro_state <= trap0;
+			end if;
+------------------------------------
+--			next_micro_state <= trap0;
+--			IF cpu(0)='0' THEN
+--				set_datatype <= "10";
+--			END IF;
 			IF preSVmode='0' THEN
 				set(changeMode) <= '1';
 			END IF;
 			setstate <= "01";
-		END IF;
-
+		END IF;	
+	if micro_state = int1 or (interrupt = '1' and trap_trace = '1') then
+	  if preSVmode = '0' then
+		set(changeMode) <= '1';
+	  end if;
+	  setstate <= "01";
+	end if;
+		
 		IF setexecOPC='1' AND FlagsSR(5)/=preSVmode THEN
 			set(changeMode) <= '1';
---                      setstate <= "01";
---                      next_micro_state <= nop;
+--			setstate <= "01";
+--			next_micro_state <= nop;
 		END IF;
 
 		IF interrupt='1' AND trap_interrupt='1'THEN
---                      skipFetch <= '1';
+--			skipFetch <= '1';
 			next_micro_state <= int1;
 			set(update_ld) <= '1';
 			setstate <= "10";
 		END IF;
-
-		IF set(changeMode)='1' THEN
+			
+		IF set(changeMode)='1' THEN		
 			set(to_USP) <= '1';
 			set(from_USP) <= '1';
 			setstackaddr <='1';
 		END IF;
-
+			
 		IF ea_only='0' AND set(get_ea_now)='1' THEN
 			setstate <= "10";
---                      set_recall_last <= '1';
---                      set(update_ld) <= '0';
+--			set_recall_last <= '1';
+--			set(update_ld) <= '0';
 		END IF;
 
 		IF setstate(1)='1' AND set_datatype(1)='1' THEN
@@ -1390,46 +1558,46 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 		END IF;
 
 		IF (ea_build_now='1' AND decodeOPC='1') OR exec(ea_build)='1' THEN
-			CASE opcode(5 downto 3) IS          --source
-				WHEN "010"|"011"|"100" =>                                               -- -(An)+
+			CASE opcode(5 downto 3) IS		--source
+				WHEN "010"|"011"|"100" =>						-- -(An)+
 					set(get_ea_now) <='1';
 					setnextpass <= '1';
-					IF opcode(3)='1' THEN       --(An)+
+					IF opcode(3)='1' THEN	--(An)+
 						set(postadd) <= '1';
 						IF opcode(2 downto 0)="111" THEN
 							set(use_SP) <= '1';
 						END IF;
-					END IF;
-					IF opcode(5)='1' THEN       -- -(An)
-						set(presub) <= '1';
+					END IF;	 	
+					IF opcode(5)='1' THEN	-- -(An)
+						set(presub) <= '1'; 					
 						IF opcode(2 downto 0)="111" THEN
 							set(use_SP) <= '1';
 						END IF;
-					END IF;
-				WHEN "101" =>                           --(d16,An)
+					END IF;	 	
+				WHEN "101" =>				--(d16,An)
 					next_micro_state <= ld_dAn1;
-				WHEN "110" =>                           --(d8,An,Xn)
+				WHEN "110" =>				--(d8,An,Xn)
 					next_micro_state <= ld_AnXn1;
 					getbrief <='1';
 				WHEN "111" =>
 					CASE opcode(2 downto 0) IS
-						WHEN "000" =>                           --(xxxx).w
+						WHEN "000" =>				--(xxxx).w
 							next_micro_state <= ld_nn;
-						WHEN "001" =>                           --(xxxx).l
+						WHEN "001" =>				--(xxxx).l
 							set(longaktion) <= '1';
 							next_micro_state <= ld_nn;
-						WHEN "010" =>                           --(d16,PC)
+						WHEN "010" =>				--(d16,PC)
 							next_micro_state <= ld_dAn1;
 							set(dispouter) <= '1';
 							set_Suppress_Base <= '1';
 							set_PCbase <= '1';
-						WHEN "011" =>                           --(d8,PC,Xn)
+						WHEN "011" =>				--(d8,PC,Xn)
 							next_micro_state <= ld_AnXn1;
 							getbrief <= '1';
 							set(dispouter) <= '1';
 							set_Suppress_Base <= '1';
 							set_PCbase <= '1';
-						WHEN "100" =>                           --#data
+						WHEN "100" =>				--#data
 							setnextpass <= '1';
 							set_direct_data <= '1';
 							IF datatype="10" THEN
@@ -1441,14 +1609,14 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 			END CASE;
 		END IF;
 ------------------------------------------------------------------------------
---prepere opcode
+--prepare opcode
 ------------------------------------------------------------------------------
 		CASE opcode(15 downto 12) IS
 -- 0000 ----------------------------------------------------------------------------
 			WHEN "0000" =>
 			IF opcode(8)='1' AND opcode(5 downto 3)="001" THEN --movep
-				datatype <= "00";                               --Byte
-				set(use_SP) <= '1';             --addr+2
+				datatype <= "00";				--Byte
+				set(use_SP) <= '1';		--addr+2
 				set(no_Flags) <='1';
 				IF opcode(7)='0' THEN  --to register
 					set_exec(Regwrena) <= '1';
@@ -1460,7 +1628,7 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 						set(movepl) <= '1';
 					END IF;
 					IF opcode(7)='0' THEN
-						set_direct_data <= '1';         -- to register
+						set_direct_data <= '1';		-- to register
 					END IF;
 					next_micro_state <= movep1;
 				END IF;
@@ -1468,190 +1636,320 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 					dest_hbits <='1';
 				END IF;
 			ELSE
-				IF opcode(8)='1' OR opcode(11 downto 9)="100" THEN              --Bits
-					set_exec(opcBITS) <= '1';
-					set_exec(ea_data_OP1) <= '1';
-					IF opcode(7 downto 6)/="00" THEN
-						IF opcode(5 downto 4)="00" THEN
-							set_exec(Regwrena) <= '1';
-						END IF;
-						write_back <= '1';
-					END IF;
-					IF opcode(5 downto 4)="00" THEN
-						datatype <= "10";                       --Long
-					ELSE
-						datatype <= "00";                       --Byte
-					END IF;
-					IF opcode(8)='0' THEN
-						IF decodeOPC='1' THEN
-							next_micro_state <= nop;
-							set(get_2ndOPC) <= '1';
-							set(ea_build) <= '1';
-						END IF;
-					ELSE
-						ea_build_now <= '1';
-					END IF;
-				ELSIF opcode(11 downto 9)="111" THEN            --MOVES not in 68000
-					trap_illegal <= '1';
---                                      trap_addr_error <= '1';
-					trapmake <= '1';
-				ELSE                                                            --andi, ...xxxi
-					IF opcode(11 downto 9)="000" THEN   --ORI
-						set_exec(opcOR) <= '1';
-					END IF;
-					IF opcode(11 downto 9)="001" THEN   --ANDI
-						set_exec(opcAND) <= '1';
-					END IF;
-					IF opcode(11 downto 9)="010" OR opcode(11 downto 9)="011" THEN      --SUBI, ADDI
-						set_exec(opcADD) <= '1';
-					END IF;
-					IF opcode(11 downto 9)="101" THEN   --EORI
-						set_exec(opcEOR) <= '1';
-					END IF;
-					IF opcode(11 downto 9)="110" THEN   --CMPI
-						set_exec(opcCMP) <= '1';
-					END IF;
-					IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (set_exec(opcAND) OR set_exec(opcOR) OR set_exec(opcEOR))='1' THEN             --SR
-						IF decodeOPC='1' AND SVmode='0' AND opcode(6)='1' THEN  --SR
-							trap_priv <= '1';
-							trapmake <= '1';
-						ELSE
-							set(no_Flags) <= '1';
-							IF decodeOPC='1' THEN
-								IF opcode(6)='1' THEN
-									set(to_SR) <= '1';
-								END IF;
-								set(to_CCR) <= '1';
-								set(andiSR) <= set_exec(opcAND);
-								set(eoriSR) <= set_exec(opcEOR);
-								set(oriSR) <= set_exec(opcOR);
-								setstate <= "01";
-								next_micro_state <= nopnop;
-							END IF;
-						END IF;
-					ELSE
-						IF decodeOPC='1' THEN
-							next_micro_state <= andi;
-							set(ea_build) <= '1';
-							set_direct_data <= '1';
-							IF datatype="10" THEN
-								set(longaktion) <= '1';
-							END IF;
-						END IF;
-						IF opcode(5 downto 4)/="00" THEN
-							set_exec(ea_data_OP1) <= '1';
-						END IF;
-						IF opcode(11 downto 9)/="110" THEN      --CMPI
+				IF opcode(8)='1' OR opcode(11 downto 9)="100" THEN		--Bits
+					IF opcode(5 downto 3)/="001" AND --ea An illegal mode
+					   (opcode(8 downto 3)/="000111" OR opcode(2)='0') AND --BTST bit number static illegal modes
+					   (opcode(8 downto 2)/="1001111" OR opcode(1 downto 0)="00") AND --BTST bit number dynamic illegal modes
+					   (opcode(7 downto 6)="00" OR opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00") THEN --BCHG, BCLR, BSET illegal modes
+						set_exec(opcBITS) <= '1';
+						set_exec(ea_data_OP1) <= '1';
+						IF opcode(7 downto 6)/="00" THEN
 							IF opcode(5 downto 4)="00" THEN
 								set_exec(Regwrena) <= '1';
 							END IF;
 							write_back <= '1';
 						END IF;
-						IF opcode(10 downto 9)="10" THEN        --CMPI, SUBI
-							set(addsub) <= '1';
+						IF opcode(5 downto 4)="00" THEN
+							datatype <= "10";			--Long
+						ELSE
+							datatype <= "00";			--Byte
 						END IF;
+						IF opcode(8)='0' THEN
+							IF decodeOPC='1' THEN
+								next_micro_state <= nop;
+								set(get_2ndOPC) <= '1';
+								set(ea_build) <= '1';
+							END IF;
+						ELSE
+							ea_build_now <= '1';
+						END IF;
+					ELSE
+						trap_illegal <= '1';
+						trapmake <= '1';
+					END IF;
+				ELSIF opcode(8 downto 6)="011" THEN			--CAS/CAS2/CMP2/CHK2
+					IF cpu(1)='1' THEN
+						IF opcode(11)='1' THEN					--CAS/CAS2
+							IF (opcode(10 downto 9)/="00" AND --CAS illegal size
+							   opcode(5 downto 4)/="00" AND (opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00")) OR --ea illegal modes
+							   (opcode(10)='1' AND opcode(5 downto 0)="111100") THEN --CAS2
+								CASE opcode(10 downto 9) IS
+									WHEN "01" => datatype <= "00";		--Byte
+									WHEN "10" => datatype <= "01";		--Word
+									WHEN OTHERS => datatype <= "10";	--Long
+								END CASE;
+								IF opcode(10)='1' AND opcode(5 downto 0)="111100" THEN --CAS2
+									IF decodeOPC='1' THEN
+										set(get_2ndOPC) <= '1';
+										next_micro_state <= cas21;
+									END IF;
+								ELSE											--CAS
+									IF decodeOPC='1' THEN
+										next_micro_state <= nop;
+										set(get_2ndOPC) <= '1';
+										set(ea_build) <= '1';
+									END IF;
+									IF micro_state=idle AND nextpass='1' THEN
+										source_2ndLbits <= '1';
+										set(ea_data_OP1) <= '1';
+										set(addsub) <= '1';
+										set(alu_exec) <= '1';
+										set(alu_setFlags) <= '1';
+										setstate <= "01";
+										next_micro_state <= cas1;
+									END IF;
+								END IF;
+							ELSE
+								trap_illegal <= '1';
+								trapmake <= '1';
+							END IF;
+						ELSE				--CMP2/CHK2
+							IF opcode(10 downto 9)/="11" AND --illegal size
+							   opcode(5 downto 4)/="00" AND opcode(5 downto 3)/="011" AND opcode(5 downto 3)/="100" AND opcode(5 downto 2)/="1111" THEN --ea illegal modes
+								set(trap_chk) <= '1';
+								datatype <= opcode(10 downto 9);
+								IF decodeOPC='1' THEN
+									next_micro_state <= nop;
+									set(get_2ndOPC) <= '1';
+									set(ea_build) <= '1';
+								END IF;
+								IF set(get_ea_now)='1' THEN
+									set(mem_addsub) <= '1';
+									set(OP1addr) <= '1';
+								END IF;
+								IF micro_state=idle AND nextpass='1' THEN
+									setstate <= "10";
+									set(hold_OP2) <='1';
+									next_micro_state <= chk20;
+								END IF;
+							ELSE
+								trap_illegal <= '1';
+								trapmake <= '1';
+							END IF;
+						END IF;
+					ELSE
+						trap_illegal <= '1';
+						trapmake <= '1';
+					END IF;
+				ELSIF opcode(11 downto 9)="111" THEN		--MOVES not in 68000
+					IF cpu(0)='1' AND opcode(7 downto 6)/="11" AND opcode(5 downto 4)/="00" AND (opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00") THEN
+						IF SVmode='1' THEN
+							--TODO: implement MOVES
+							trap_illegal <= '1';
+							trapmake <= '1';
+						ELSE
+							trap_priv <= '1';
+							trapmake <= '1';
+						END IF;
+					ELSE
+						trap_illegal <= '1';
+						trapmake <= '1';
+					END IF;
+				ELSE								--andi, ...xxxi
+					IF opcode(7 downto 6)/="11" AND opcode(5 downto 3)/="001" THEN --ea An illegal mode
+						IF opcode(11 downto 9)="000" THEN	--ORI
+							IF opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00" OR opcode(2 downto 0)="100" THEN
+								set_exec(opcOR) <= '1';
+							ELSE
+								trap_illegal <= '1';
+								trapmake <= '1';
+							END IF;
+						END IF;
+						IF opcode(11 downto 9)="001" THEN	--ANDI
+							IF opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00" OR opcode(2 downto 0)="100" THEN
+								set_exec(opcAND) <= '1';
+							ELSE
+								trap_illegal <= '1';
+								trapmake <= '1';
+							END IF;
+						END IF;
+						IF opcode(11 downto 9)="010" OR opcode(11 downto 9)="011" THEN	--SUBI, ADDI
+							IF opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00" THEN
+								set_exec(opcADD) <= '1';
+							ELSE
+								trap_illegal <= '1';
+								trapmake <= '1';
+							END IF;
+						END IF;
+						IF opcode(11 downto 9)="101" THEN	--EORI
+							IF opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00" OR opcode(2 downto 0)="100" THEN
+								set_exec(opcEOR) <= '1';
+							ELSE
+								trap_illegal <= '1';
+								trapmake <= '1';
+							END IF;
+						END IF;
+						IF opcode(11 downto 9)="110" THEN	--CMPI
+							IF opcode(5 downto 3)/="111" OR opcode(2)='0' THEN
+								set_exec(opcCMP) <= '1';
+							ELSE
+								trap_illegal <= '1';
+								trapmake <= '1';
+							END IF;
+						END IF;
+						IF (set_exec(opcor) OR set_exec(opcand) OR set_exec(opcADD) OR set_exec(opcEor) OR set_exec(opcCMP))='1' THEN
+							IF opcode(7)='0' AND opcode(5 downto 0)="111100" AND (set_exec(opcAND) OR set_exec(opcOR) OR set_exec(opcEOR))='1' THEN		--SR
+								IF decodeOPC='1' AND SVmode='0' AND opcode(6)='1' THEN  --SR
+									trap_priv <= '1';
+									trapmake <= '1';
+								ELSE
+									set(no_Flags) <= '1';
+									IF decodeOPC='1' THEN
+										IF opcode(6)='1' THEN
+											set(to_SR) <= '1';
+										END IF;
+										set(to_CCR) <= '1';
+										set(andiSR) <= set_exec(opcAND);
+										set(eoriSR) <= set_exec(opcEOR);
+										set(oriSR) <= set_exec(opcOR);
+										setstate <= "01";
+										next_micro_state <= nopnop;
+									END IF;
+								END IF;
+							ELSIF opcode(7)='0' OR opcode(5 downto 0)/="111100" OR (set_exec(opcand) OR set_exec(opcor) OR set_exec(opcEor))='0' THEN
+								IF decodeOPC='1' THEN
+									next_micro_state <= andi;
+									set(get_2ndOPC) <='1';
+									set(ea_build) <= '1';
+									set_direct_data <= '1';
+									IF datatype="10" THEN
+										set(longaktion) <= '1';
+									END IF;
+								END IF;
+								IF opcode(5 downto 4)/="00" THEN
+									set_exec(ea_data_OP1) <= '1';
+								END IF;
+								IF opcode(11 downto 9)/="110" THEN	--CMPI
+									IF opcode(5 downto 4)="00" THEN
+										set_exec(Regwrena) <= '1';
+									END IF;
+									write_back <= '1';
+								END IF;
+								IF opcode(10 downto 9)="10" THEN	--CMPI, SUBI
+									set(addsub) <= '1';
+								END IF;
+							ELSE
+								trap_illegal <= '1';
+								trapmake <= '1';
+							END IF;
+						ELSE
+							trap_illegal <= '1';
+							trapmake <= '1';
+						END IF;
+					ELSE
+						trap_illegal <= '1';
+						trapmake <= '1';
 					END IF;
 				END IF;
 			END IF;
-
+				
 -- 0001, 0010, 0011 -----------------------------------------------------------------
-			WHEN "0001"|"0010"|"0011" =>                                --move.b, move.l, move.w
-				set_exec(opcMOVE) <= '1';
-				ea_build_now <= '1';
-				IF opcode(8 downto 6)="001" THEN
-					set(no_Flags) <= '1';
-				END IF;
-				IF opcode(5 downto 4)="00" THEN --Dn, An
-					IF opcode(8 downto 7)="00" THEN
-						set_exec(Regwrena) <= '1';
+			WHEN "0001"|"0010"|"0011" =>				--move.b, move.l, move.w
+				IF ((opcode(11 downto 10)="00" OR opcode(8 downto 6)/="111") AND --illegal dest ea
+				   (opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00") AND --illegal src ea
+				   (opcode(13)='1' OR (opcode(8 downto 6)/="001" AND opcode(5 downto 3)/="001"))) THEN --byte src address reg direct, byte movea
+					set_exec(opcMOVE) <= '1';
+					ea_build_now <= '1';
+					IF opcode(8 downto 6)="001" THEN
+						set(no_Flags) <= '1';
 					END IF;
-				END IF;
-				CASE opcode(13 downto 12) IS
-					WHEN "01" => datatype <= "00";              --Byte
-					WHEN "10" => datatype <= "10";              --Long
-					WHEN OTHERS => datatype <= "01";    --Word
-				END CASE;
-				source_lowbits <= '1';                                  -- Dn=>  An=>
-				IF opcode(3)='1' THEN
-					source_areg <= '1';
-				END IF;
-
-				IF nextpass='1' OR opcode(5 downto 4)="00" THEN
-					dest_hbits <= '1';
-					IF opcode(8 downto 6)/="000" THEN
-						dest_areg <= '1';
+					IF opcode(5 downto 4)="00" THEN	--Dn, An
+						IF opcode(8 downto 7)="00" THEN
+							set_exec(Regwrena) <= '1';
+						END IF;
 					END IF;
-				END IF;
---                              IF setstate="10" THEN
---                                      set(update_ld) <= '0';
---                              END IF;
---
-				IF micro_state=idle AND (nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1')) THEN
-					CASE opcode(8 downto 6) IS          --destination
-						WHEN "000"|"001" =>                                             --Dn,An
-								set_exec(Regwrena) <= '1';
-						WHEN "010"|"011"|"100" =>                                       --destination -(an)+
-							IF opcode(6)='1' THEN       --(An)+
-								set(postadd) <= '1';
-								IF opcode(11 downto 9)="111" THEN
-									set(use_SP) <= '1';
-								END IF;
-							END IF;
-							IF opcode(8)='1' THEN       -- -(An)
-								set(presub) <= '1';
-								IF opcode(11 downto 9)="111" THEN
-									set(use_SP) <= '1';
-								END IF;
-							END IF;
-							setstate <= "11";
-							next_micro_state <= nop;
-							IF nextpass='0' THEN
-								set(write_reg) <= '1';
-							END IF;
-						WHEN "101" =>                           --(d16,An)
-							next_micro_state <= st_dAn1;
---                                                      getbrief <= '1';
-						WHEN "110" =>                           --(d8,An,Xn)
-							next_micro_state <= st_AnXn1;
-							getbrief <= '1';
-						WHEN "111" =>
-							CASE opcode(11 downto 9) IS
-								WHEN "000" =>                           --(xxxx).w
-									next_micro_state <= st_nn;
-								WHEN "001" =>                           --(xxxx).l
-									set(longaktion) <= '1';
-									next_micro_state <= st_nn;
-								WHEN OTHERS => NULL;
-							END CASE;
-						WHEN OTHERS => NULL;
+					CASE opcode(13 downto 12) IS
+						WHEN "01" => datatype <= "00";		--Byte
+						WHEN "10" => datatype <= "10";		--Long
+						WHEN OTHERS => datatype <= "01";	--Word
 					END CASE;
+					source_lowbits <= '1';					-- Dn=>  An=>
+					IF opcode(3)='1' THEN
+						source_areg <= '1';
+					END IF;
+
+					IF nextpass='1' OR opcode(5 downto 4)="00" THEN
+						dest_hbits <= '1';
+						IF opcode(8 downto 6)/="000" THEN
+							dest_areg <= '1';
+						END IF;
+					END IF;
+
+					IF micro_state=idle AND (nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1')) THEN
+						CASE opcode(8 downto 6) IS		--destination
+							WHEN "000"|"001" =>						--Dn,An
+									set_exec(Regwrena) <= '1';
+							WHEN "010"|"011"|"100" =>					--destination -(an)+
+								IF opcode(6)='1' THEN	--(An)+
+									set(postadd) <= '1';
+									IF opcode(11 downto 9)="111" THEN
+										set(use_SP) <= '1';
+									END IF;
+								END IF;
+								IF opcode(8)='1' THEN	-- -(An)
+									set(presub) <= '1';
+									IF opcode(11 downto 9)="111" THEN
+										set(use_SP) <= '1';
+									END IF;
+								END IF;
+								setstate <= "11";
+								next_micro_state <= nop;
+								IF nextpass='0' THEN
+									set(write_reg) <= '1';
+								END IF;
+							WHEN "101" =>				--(d16,An)
+								next_micro_state <= st_dAn1;
+--								getbrief <= '1';
+							WHEN "110" =>				--(d8,An,Xn)
+								next_micro_state <= st_AnXn1;
+								getbrief <= '1';
+							WHEN "111" =>
+								CASE opcode(11 downto 9) IS
+									WHEN "000" =>				--(xxxx).w
+										next_micro_state <= st_nn;
+									WHEN "001" =>				--(xxxx).l
+										set(longaktion) <= '1';
+										next_micro_state <= st_nn;
+									WHEN OTHERS => NULL;
+								END CASE;
+							WHEN OTHERS => NULL;
+						END CASE;
+					END IF;
+				ELSE
+					trap_illegal <= '1';
+					trapmake <= '1';
 				END IF;
----- 0100 ----------------------------------------------------------------------------
-			WHEN "0100" =>                              --rts_group
-				IF opcode(8)='1' THEN           --lea
-					IF opcode(6)='1' THEN               --lea
-						IF opcode(7)='1' THEN
-							source_lowbits <= '1';
---                                                      IF opcode(5 downto 3)="000" AND opcode(10)='0' THEN             --ext
-							IF opcode(5 downto 4)="00" THEN             --extb.l
+---- 0100 ----------------------------------------------------------------------------		
+			WHEN "0100" =>				--rts_group
+				IF opcode(8)='1' THEN		--lea, extb.l, chk
+					IF opcode(6)='1' THEN		--lea, extb.l
+						IF opcode(11 downto 9)="100" AND opcode(5 downto 3)="000" THEN --extb.l
+							IF opcode(7)='1' AND cpu(1)='1' THEN
+								source_lowbits <= '1';
 								set_exec(opcEXT) <= '1';
+								set_exec(opcEXTB) <= '1';
 								set_exec(opcMOVE) <= '1';
 								set_exec(Regwrena) <= '1';
---                                                              IF opcode(6)='0' THEN
---                                                                      datatype <= "01";               --WORD
---                                                              END IF;
 							ELSE
+								trap_illegal <= '1';
+								trapmake <= '1';
+							END IF;
+						ELSE
+							IF opcode(7)='1' AND
+							   (opcode(5)='1' OR opcode(4 downto 3)="10") AND
+							   opcode(5 downto 3)/="100" AND opcode(5 downto 2)/="1111" THEN --ea illegal opcodes
+								source_lowbits <= '1';
 								source_areg <= '1';
 								ea_only <= '1';
 								set_exec(Regwrena) <= '1';
 								set_exec(opcMOVE) <='1';
 								set(no_Flags) <='1';
-								IF opcode(5 downto 3)="010" THEN        --lea (Am),An
+								IF opcode(5 downto 3)="010" THEN  	--lea (Am),An
 									dest_areg <= '1';
 									dest_hbits <= '1';
 								ELSE
 									ea_build_now <= '1';
-								END IF;
+								END IF;	
 								IF set(get_ea_now)='1' THEN
 									setstate <= "01";
 									set_direct_data <= '1';
@@ -1660,210 +1958,288 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 									dest_areg <= '1';
 									dest_hbits <= '1';
 								END IF;
+							ELSE
+								trap_illegal <='1';
+								trapmake <='1';
+							END IF;
+						END IF;
+					ELSE								--chk
+						IF opcode(5 downto 3)/="001" AND --ea An illegal mode
+						   (opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00") THEN --ea illegal modes
+							IF opcode(7)='1' THEN
+								datatype <= "01";	--Word
+								set(trap_chk) <= '1';
+								IF (c_out(1)='0' OR OP1out(15)='1' OR OP2out(15)='1') AND exec(opcCHK)='1' THEN
+									trapmake <= '1';
+								END IF;
+							ELSIF cpu(1)='1' THEN   --chk long for 68020
+								datatype <= "10";	--Long
+								set(trap_chk) <= '1';
+								IF (c_out(2)='0' OR OP1out(31)='1' OR OP2out(31)='1') AND exec(opcCHK)='1' THEN
+									trapmake <= '1';
+								END IF;
+							ELSE
+								trap_illegal <= '1';		-- chk long for 68020
+								trapmake <= '1';
+							END IF;
+							IF opcode(7)='1' OR cpu(1)='1' THEN
+								IF (nextpass='1' OR opcode(5 downto 4)="00") AND exec(opcCHK)='0' AND micro_state=idle THEN
+									set_exec(opcCHK) <= '1';
+								END IF;
+								ea_build_now <= '1';
+								set(addsub) <= '1';
+								IF setexecOPC='1' THEN
+									dest_hbits <= '1';
+									source_lowbits <='1';
+								END IF;
 							END IF;
 						ELSE
 							trap_illegal <= '1';
 							trapmake <= '1';
 						END IF;
-					ELSE                                                                --chk
-						IF opcode(7)='1' THEN
-							datatype <= "01";   --Word
-								set(trap_chk) <= '1';
-							IF (c_out(1)='0' OR OP1out(15)='1' OR OP2out(15)='1') AND exec(opcCHK)='1' THEN
-								trapmake <= '1';
-							END IF;
-						ELSIF cpu(1)='1' THEN   --chk long for 68020
-							datatype <= "10";   --Long
-								set(trap_chk) <= '1';
-							IF (c_out(2)='1' OR OP1out(31)='1' OR OP2out(31)='1') AND exec(opcCHK)='1' THEN
-								trapmake <= '1';
-							END IF;
-						ELSE
-							trap_illegal <= '1';                -- chk long for 68020
-							trapmake <= '1';
-						END IF;
-						IF opcode(7)='1' OR cpu(1)='1' THEN
-							IF (nextpass='1' OR opcode(5 downto 4)="00") AND exec(opcCHK)='0' AND micro_state=idle THEN
-								set_exec(opcCHK) <= '1';
-							END IF;
-							ea_build_now <= '1';
-							set(addsub) <= '1';
-							IF setexecOPC='1' THEN
-								dest_hbits <= '1';
-								source_lowbits <='1';
-							END IF;
-						END IF;
 					END IF;
 				ELSE
 					CASE opcode(11 downto 9) IS
 						WHEN "000"=>
-							IF opcode(7 downto 6)="11" THEN                                     --move from SR
-								IF SR_Read=0 OR (cpu(0)='0' AND SR_Read=2) OR SVmode='1'  THEN
---                                                              IF SVmode='1'  THEN
-									ea_build_now <= '1';
-									set_exec(opcMOVESR) <= '1';
-									datatype <= "01";
-									write_back <='1';                                                   -- im 68000 wird auch erst gelesen
-									IF cpu(0)='1' AND state="10" THEN
-										skipFetch <= '1';
+							IF (opcode(5 downto 3)/="001" AND --ea An illegal mode
+							   (opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00")) THEN --ea illegal modes
+								IF opcode(7 downto 6)="11" THEN					--move from SR
+									IF SR_Read=0 OR (cpu(0)='0' AND SR_Read=2) OR SVmode='1'  THEN
+										ea_build_now <= '1';
+										set_exec(opcMOVESR) <= '1';
+										datatype <= "01";
+										write_back <='1';							-- im 68000 wird auch erst gelesen
+										IF cpu(0)='1' AND state="10" AND addrvalue='0' THEN
+											skipFetch <= '1';
+										END IF;
+										IF opcode(5 downto 4)="00" THEN
+											set_exec(Regwrena) <= '1';
+										END IF;
+									ELSE
+										trap_priv <= '1';
+										trapmake <= '1';
 									END IF;
+								ELSE									--negx
+									ea_build_now <= '1';
+									set_exec(use_XZFlag) <= '1';
+									write_back <='1';
+									set_exec(opcADD) <= '1';
+									set(addsub) <= '1';
+									source_lowbits <= '1';
 									IF opcode(5 downto 4)="00" THEN
 										set_exec(Regwrena) <= '1';
 									END IF;
-								ELSE
-									trap_priv <= '1';
-									trapmake <= '1';
-								END IF;
-							ELSE                                                                        --negx
-								ea_build_now <= '1';
-								set_exec(use_XZFlag) <= '1';
-								write_back <='1';
-								set_exec(opcADD) <= '1';
-								set(addsub) <= '1';
-								source_lowbits <= '1';
-								IF opcode(5 downto 4)="00" THEN
-									set_exec(Regwrena) <= '1';
-								END IF;
-								IF setexecOPC='1' THEN
-									set(OP1out_zero) <= '1';
+									IF setexecOPC='1' THEN
+										set(OP1out_zero) <= '1';
+									END IF;
 								END IF;
+							ELSE
+								trap_illegal <= '1';
+								trapmake <= '1';
 							END IF;
 						WHEN "001"=>
-							IF opcode(7 downto 6)="11" THEN                                     --move from CCR 68010
-								IF SR_Read=1 OR (cpu(0)='1' AND SR_Read=2) THEN
+							IF (opcode(5 downto 3)/="001" AND --ea An illegal mode
+							   (opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00")) THEN --ea illegal modes
+								IF opcode(7 downto 6)="11" THEN					--move from CCR 68010
+									IF SR_Read=1 OR (cpu(0)='1' AND SR_Read=2) THEN
+										ea_build_now <= '1';
+										set_exec(opcMOVESR) <= '1';
+										datatype <= "01";
+										write_back <='1';							-- im 68000 wird auch erst gelesen
+--										IF state="10" THEN
+--											skipFetch <= '1';
+--										END IF;
+										IF opcode(5 downto 4)="00" THEN
+											set_exec(Regwrena) <= '1';
+										END IF;
+									ELSE
+										trap_illegal <= '1';
+										trapmake <= '1';
+									END IF;
+								ELSE											--clr
 									ea_build_now <= '1';
-									set_exec(opcMOVESR) <= '1';
-									datatype <= "00";
-									write_back <='1';                                                   -- im 68000 wird auch erst gelesen
+									write_back <='1';
+									set_exec(opcAND) <= '1';
+								IF cpu(0)='1' AND state="10" AND addrvalue='0' THEN
+									skipFetch <= '1';
+								END IF;
+									IF setexecOPC='1' THEN
+										set(OP1out_zero) <= '1';
+									END IF;
 									IF opcode(5 downto 4)="00" THEN
 										set_exec(Regwrena) <= '1';
 									END IF;
+								END IF;
+							ELSE
+								trap_illegal <= '1';
+								trapmake <= '1';
+							END IF;
+						WHEN "010"=>
+							IF opcode(7 downto 6)="11" THEN					--move to CCR
+								IF opcode(5 downto 3)/="001" AND --ea An illegal mode
+								   (opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00") THEN --ea illegal modes
+									ea_build_now <= '1';
+									datatype <= "01";
+									source_lowbits <= '1';
+									IF (decodeOPC='1' AND opcode(5 downto 4)="00") OR (state="10" AND addrvalue='0') OR direct_data='1' THEN
+										set(to_CCR) <= '1';
+									END IF;
 								ELSE
 									trap_illegal <= '1';
 									trapmake <= '1';
 								END IF;
-							ELSE                                                                                        --clr
-								ea_build_now <= '1';
-								write_back <='1';
-								set_exec(opcAND) <= '1';
-							IF cpu(0)='1' AND state="10" THEN
-								skipFetch <= '1';
-							END IF;
-								IF setexecOPC='1' THEN
-									set(OP1out_zero) <= '1';
-								END IF;
-								IF opcode(5 downto 4)="00" THEN
-									set_exec(Regwrena) <= '1';
-								END IF;
-							END IF;
-						WHEN "010"=>
-							ea_build_now <= '1';
-							IF opcode(7 downto 6)="11" THEN                                     --move to CCR
-								datatype <= "01";
-								source_lowbits <= '1';
-								IF (decodeOPC='1' AND opcode(5 downto 4)="00") OR state="10" OR direct_data='1' THEN
-									set(to_CCR) <= '1';
-								END IF;
-							ELSE                                                                                        --neg
-								write_back <='1';
-								set_exec(opcADD) <= '1';
-								set(addsub) <= '1';
-								source_lowbits <= '1';
-								IF opcode(5 downto 4)="00" THEN
-									set_exec(Regwrena) <= '1';
-								END IF;
-								IF setexecOPC='1' THEN
-									set(OP1out_zero) <= '1';
-								END IF;
-							END IF;
-						WHEN "011"=>                                                                            --not, move toSR
-							IF opcode(7 downto 6)="11" THEN                                     --move to SR
-								IF SVmode='1' THEN
+							ELSE											--neg
+								IF (opcode(5 downto 3)/="001" AND --ea An illegal mode
+								   (opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00")) THEN --ea illegal modes
 									ea_build_now <= '1';
-									datatype <= "01";
+									write_back <='1';
+									set_exec(opcADD) <= '1';
+									set(addsub) <= '1';
 									source_lowbits <= '1';
-									IF (decodeOPC='1' AND opcode(5 downto 4)="00") OR state="10" OR direct_data='1' THEN
-										set(to_SR) <= '1';
-										set(to_CCR) <= '1';
+									IF opcode(5 downto 4)="00" THEN
+										set_exec(Regwrena) <= '1';
 									END IF;
-									IF exec(to_SR)='1' OR (decodeOPC='1' AND opcode(5 downto 4)="00") OR state="10" OR direct_data='1' THEN
-										setstate <="01";
+									IF setexecOPC='1' THEN
+										set(OP1out_zero) <= '1';
 									END IF;
 								ELSE
-									trap_priv <= '1';
+									trap_illegal <= '1';
 									trapmake <= '1';
 								END IF;
-							ELSE                                                                                        --not
-								ea_build_now <= '1';
-								write_back <='1';
-								set_exec(opcEOR) <= '1';
-								set_exec(ea_data_OP1) <= '1';
-								IF opcode(5 downto 3)="000" THEN
-									set_exec(Regwrena) <= '1';
+							END IF;
+						WHEN "011"=>										--not, move toSR
+							IF opcode(7 downto 6)="11" THEN					--move to SR
+								IF opcode(5 downto 3)/="001" AND --ea An illegal mode
+								   (opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00") THEN --ea illegal modes
+									IF SVmode='1' THEN
+										ea_build_now <= '1';
+										datatype <= "01";
+										source_lowbits <= '1';
+										IF (decodeOPC='1' AND opcode(5 downto 4)="00") OR (state="10" AND addrvalue='0') OR direct_data='1' THEN
+											set(to_SR) <= '1';
+											set(to_CCR) <= '1';
+										END IF;
+										IF exec(to_SR)='1' OR (decodeOPC='1' AND opcode(5 downto 4)="00") OR (state="10" AND addrvalue='0') OR direct_data='1' THEN
+											setstate <="01";
+										END IF;
+									ELSE
+										trap_priv <= '1';
+										trapmake <= '1';
+									END IF;
+								ELSE
+									trap_illegal <= '1';
+									trapmake <= '1';
 								END IF;
-								IF setexecOPC='1' THEN
-									set(OP2out_one) <= '1';
+							ELSE											--not
+								IF opcode(5 downto 3)/="001" AND --ea An illegal mode
+								   (opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00") THEN --ea illegal modes
+									ea_build_now <= '1';
+									write_back <='1';
+									set_exec(opcEOR) <= '1';
+									set_exec(ea_data_OP1) <= '1';
+									IF opcode(5 downto 3)="000" THEN
+										set_exec(Regwrena) <= '1';
+									END IF;
+									IF setexecOPC='1' THEN
+										set(OP2out_one) <= '1';
+									END IF;
+								ELSE
+									trap_illegal <= '1';
+									trapmake <= '1';
 								END IF;
 							END IF;
 						WHEN "100"|"110"=>
-							IF opcode(7)='1' THEN                       --movem, ext
-								IF opcode(5 downto 3)="000" AND opcode(10)='0' THEN             --ext
+							IF opcode(7)='1' THEN			--movem, ext
+								IF opcode(5 downto 3)="000" AND opcode(10)='0' THEN		--ext
 									source_lowbits <= '1';
 									set_exec(opcEXT) <= '1';
 									set_exec(opcMOVE) <= '1';
-									set_exec(Regwrena) <= '1';
+									set_exec(Regwrena) <= '1';	
 									IF opcode(6)='0' THEN
-										datatype <= "01";               --WORD
+										datatype <= "01";		--WORD
+										set_exec(opcEXTB) <= '1';
 									END IF;
-								ELSE                                                                                                    --movem
---                                                              IF opcode(11 downto 7)="10001" OR opcode(11 downto 7)="11001" THEN      --MOVEM
-									ea_only <= '1';
-									set(no_Flags) <= '1';
-									IF opcode(6)='0' THEN
-										datatype <= "01";               --Word transfer
+								ELSE													--movem
+--								IF opcode(11 downto 7)="10001" OR opcode(11 downto 7)="11001" THEN	--MOVEM
+									IF (opcode(10)='1' OR ((opcode(5)='1' OR opcode(4 downto 3)="10") AND
+									   (opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00"))) AND
+									   (opcode(10)='0' OR (opcode(5 downto 4)/="00" AND
+									   opcode(5 downto 3)/="100" AND
+									   opcode(5 downto 2)/="1111")) THEN --ea illegal modes
+										ea_only <= '1';
+										set(no_Flags) <= '1';
+										IF opcode(6)='0' THEN
+											datatype <= "01";		--Word transfer
+										END IF;
+										IF (opcode(5 downto 3)="100" OR opcode(5 downto 3)="011") AND state="01" THEN	-- -(An), (An)+
+											set_exec(save_memaddr) <= '1';
+											set_exec(Regwrena) <= '1';
+										END IF;
+										IF opcode(5 downto 3)="100" THEN	-- -(An)
+											movem_presub <= '1';
+											set(subidx) <= '1';
+										END IF;
+										IF state="10" AND addrvalue='0' THEN
+											set(Regwrena) <= '1';
+											set(opcMOVE) <= '1';
+										END IF;
+										IF decodeOPC='1' THEN
+											set(get_2ndOPC) <='1';
+											IF opcode(5 downto 3)="010" OR opcode(5 downto 3)="011" OR opcode(5 downto 3)="100" THEN
+												next_micro_state <= movem1;
+											ELSE
+												next_micro_state <= nop;
+												set(ea_build) <= '1';
+											END IF;
+										END IF;
+										IF set(get_ea_now)='1' THEN
+											IF movem_run='1' THEN
+												set(movem_action) <= '1';
+												IF opcode(10)='0' THEN
+													setstate <="11";
+													set(write_reg) <= '1';
+												ELSE
+													setstate <="10";
+												END IF;
+												next_micro_state <= movem2;
+												set(mem_addsub) <= '1';
+											ELSE
+												setstate <="01";
+											END IF;
+										END IF;
+									ELSE
+										trap_illegal <= '1';
+										trapmake <= '1';
 									END IF;
-									IF (opcode(5 downto 3)="100" OR opcode(5 downto 3)="011") AND state="01" THEN       -- -(An), (An)+
-										set_exec(save_memaddr) <= '1';
-										set_exec(Regwrena) <= '1';
-									END IF;
-									IF opcode(5 downto 3)="100" THEN    -- -(An)
-										movem_presub <= '1';
-										set(subidx) <= '1';
-									END IF;
-									IF state="10" THEN
-										set(Regwrena) <= '1';
-										set(opcMOVE) <= '1';
-									END IF;
-									IF decodeOPC='1' THEN
-										set(get_2ndOPC) <='1';
-										IF opcode(5 downto 3)="010" OR opcode(5 downto 3)="011" OR opcode(5 downto 3)="100" THEN
-											next_micro_state <= movem1;
-										ELSE
+								END IF;	
+							ELSE
+								IF opcode(10)='1' THEN						--MUL.L, DIV.L 68020
+	 --FPGA Multiplier for long							
+									IF opcode(8 downto 7)="00" AND opcode(5 downto 3)/="001" AND (opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00") AND--ea An illegal mode
+									   MUL_Hardware=1 AND (opcode(6)='0' AND (MUL_Mode=1 OR (cpu(1)='1' AND MUL_Mode=2))) THEN
+										IF decodeOPC='1' THEN
 											next_micro_state <= nop;
+											set(get_2ndOPC) <= '1';
 											set(ea_build) <= '1';
 										END IF;
-									END IF;
-									IF set(get_ea_now)='1' THEN
-										IF movem_run='1' THEN
-											set(movem_action) <= '1';
-											IF opcode(10)='0' THEN
-												setstate <="11";
-												set(write_reg) <= '1';
-											ELSE
-												setstate <="10";
+										IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND exec(ea_build)='1') THEN
+											dest_2ndHbits <= '1';
+											datatype <= "10";
+											set(opcMULU) <= '1';
+											set(write_lowlong) <= '1';
+											IF sndOPC(10)='1' THEN
+												setstate <="01";
+												next_micro_state <= mul_end2;
 											END IF;
-											next_micro_state <= movem2;
-											set(mem_addsub) <= '1';
-										ELSE
-											setstate <="01";
+											set(Regwrena) <= '1';
 										END IF;
-									END IF;
-								END IF;
-							ELSE
-								IF opcode(10)='1' THEN                                          --MUL.L, DIV.L 68020
---                                                                      IF cpu(1)='1' THEN
-									IF (opcode(6)='1' AND (DIV_Mode=1 OR (cpu(1)='1' AND DIV_Mode=2))) OR
-									   (opcode(6)='0' AND (MUL_Mode=1 OR (cpu(1)='1' AND MUL_Mode=2))) THEN
+										source_lowbits <='1';
+										datatype <= "10";
+
+	 --no FPGA Multiplier
+									ELSIF opcode(8 downto 7)="00" AND opcode(5 downto 3)/="001" AND (opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00") AND --ea An illegal mode
+									   ((opcode(6)='1' AND (DIV_Mode=1 OR (cpu(1)='1' AND DIV_Mode=2))) OR
+									   (opcode(6)='0' AND (MUL_Mode=1 OR (cpu(1)='1' AND MUL_Mode=2)))) THEN
 										IF decodeOPC='1' THEN
 											next_micro_state <= nop;
 											set(get_2ndOPC) <= '1';
@@ -1875,16 +2251,13 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 											source_2ndLbits <= '1';
 											IF opcode(6)='1' THEN
 												next_micro_state <= div1;
-											ELSE
+											ELSE	
 												next_micro_state <= mul1;
 												set(ld_rot_cnt) <= '1';
 											END IF;
 										END IF;
-										IF z_error='0' AND set_V_Flag='0' AND set(opcDIVU)='1' THEN
-											set(Regwrena) <= '1';
-										END IF;
 										source_lowbits <='1';
-										IF nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
+										IF nextpass='1' OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN	
 											dest_hbits <= '1';
 										END IF;
 										datatype <= "10";
@@ -1892,32 +2265,40 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 										trap_illegal <= '1';
 										trapmake <= '1';
 									END IF;
-
-								ELSE                                                    --pea, swap
+					
+								ELSE							--pea, swap
 									IF opcode(6)='1' THEN
 										datatype <= "10";
-										IF opcode(5 downto 3)="000" THEN                --swap
+										IF opcode(5 downto 3)="000" THEN 		--swap
 											set_exec(opcSWAP) <= '1';
-											set_exec(Regwrena) <= '1';
-										ELSIF opcode(5 downto 3)="001" THEN             --bkpt
-
-										ELSE                                                                    --pea
-											ea_only <= '1';
-											ea_build_now <= '1';
-											IF nextpass='1' AND micro_state=idle THEN
-												set(presub) <= '1';
-												setstackaddr <='1';
-												setstate <="11";
-												next_micro_state <= nop;
-											END IF;
-											IF set(get_ea_now)='1' THEN
-												setstate <="01";
+											set_exec(Regwrena) <= '1';	
+										ELSIF opcode(5 downto 3)="001" THEN 		--bkpt
+											trap_illegal <= '1';
+											trapmake <= '1';
+										ELSE									--pea
+											IF (opcode(5)='1' OR opcode(4 downto 3)="10") AND
+											   opcode(5 downto 3)/="100" AND
+											   opcode(5 downto 2)/="1111" THEN --ea illegal modes
+												ea_only <= '1';
+												ea_build_now <= '1';
+												IF nextpass='1' AND micro_state=idle THEN
+													set(presub) <= '1';
+													setstackaddr <='1';
+													setstate <="11";
+													next_micro_state <= nop;
+												END IF;
+												IF set(get_ea_now)='1' THEN
+													setstate <="01";
+												END IF;
+											ELSE
+												trap_illegal <= '1';
+												trapmake <= '1';
 											END IF;
 										END IF;
 									ELSE
 										IF opcode(5 downto 3)="001" THEN --link.l
 											datatype <= "10";
-											set_exec(opcADD) <= '1';                                            --for displacement
+											set_exec(opcADD) <= '1';						--for displacement
 											set_exec(Regwrena) <= '1';
 											set(no_Flags) <= '1';
 											IF decodeOPC='1' THEN
@@ -1931,102 +2312,126 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 												source_areg <= '1';
 												set(store_ea_data) <= '1';
 											END IF;
-										ELSE                                            --nbcd
-											ea_build_now <= '1';
-											set_exec(use_XZFlag) <= '1';
-											write_back <='1';
-											set_exec(opcADD) <= '1';
-											set_exec(opcSBCD) <= '1';
-											source_lowbits <= '1';
-											IF opcode(5 downto 4)="00" THEN
-												set_exec(Regwrena) <= '1';
+										ELSE						--nbcd
+											IF opcode(5 downto 3)/="001" AND --ea An illegal mode
+											   (opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00") THEN --ea illegal modes
+												ea_build_now <= '1';
+												set_exec(use_XZFlag) <= '1';
+												write_back <='1';
+												set_exec(opcADD) <= '1';
+												set_exec(opcSBCD) <= '1';
+												set(addsub) <= '1';
+												source_lowbits <= '1';
+												IF opcode(5 downto 4)="00" THEN
+													set_exec(Regwrena) <= '1';
+												END IF;
+												IF setexecOPC='1' THEN
+													set(OP1out_zero) <= '1';
+												END IF;
+											ELSE
+												trap_illegal <= '1';
+												trapmake <= '1';
 											END IF;
-											IF setexecOPC='1' THEN
-												set(OP1out_zero) <= '1';
-											END IF;
-										END IF;
+										END IF;	
 									END IF;
 								END IF;
 							END IF;
---
-						WHEN "101"=>                                            --tst, tas  4aFC - illegal
-							IF opcode(7 downto 2)="111111" THEN   --illegal
+--0x4AXX							
+						WHEN "101"=>						--tst, tas  4aFC - illegal
+--							IF opcode(7 downto 2)="111111" THEN   --illegal
+							IF opcode(7 downto 3)="11111" AND opcode(2 downto 1)/="00" THEN   --0x4AFC illegal  --0x4AFB BKP Sinclair QL
 								trap_illegal <= '1';
 								trapmake <= '1';
 							ELSE
-								ea_build_now <= '1';
-								IF setexecOPC='1' THEN
-									source_lowbits <= '1';
-									IF opcode(3)='1' THEN                       --MC68020...
-										source_areg <= '1';
+								IF (opcode(7 downto 6)/="11" OR --tas
+								   (opcode(5 downto 3)/="001" AND --ea An illegal mode
+								   (opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00"))) AND --ea illegal modes
+								   ((opcode(7 downto 6)/="00" OR (opcode(5 downto 3)/="001")) AND
+								   (opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00")) THEN
+									ea_build_now <= '1';
+									IF setexecOPC='1' THEN
+										source_lowbits <= '1';
+										IF opcode(3)='1' THEN			--MC68020...
+											source_areg <= '1';
+										END IF;
 									END IF;
-								END IF;
-								set_exec(opcMOVE) <= '1';
-								IF opcode(7 downto 6)="11" THEN         --tas
-									set_exec_tas <= '1';
-									write_back <= '1';
-									datatype <= "00";                           --Byte
-									IF opcode(5 downto 4)="00" THEN
-										set_exec(Regwrena) <= '1';
+									set_exec(opcMOVE) <= '1';
+									IF opcode(7 downto 6)="11" THEN		--tas
+										set_exec_tas <= '1';
+										write_back <= '1';
+										datatype <= "00";				--Byte
+										IF opcode(5 downto 4)="00" THEN
+											set_exec(Regwrena) <= '1';
+										END IF;
 									END IF;
+								ELSE
+									trap_illegal <= '1';
+									trapmake <= '1';
 								END IF;
 							END IF;
-----                                            WHEN "110"=>
-						WHEN "111"=>                                    --4EXX
+----						WHEN "110"=>
+						WHEN "111"=>					--4EXX
 --
---                                                                                      ea_only <= '1';
---                                                                                      ea_build_now <= '1';
---                                                                                      IF nextpass='1' AND micro_state=idle THEN
---                                                                                              set(presub) <= '1';
---                                                                                              setstackaddr <='1';
---                                                                                              set(mem_addsub) <= '1';
---                                                                                              setstate <="11";
---                                                                                              next_micro_state <= nop;
---                                                                                      END IF;
---                                                                                      IF set(get_ea_now)='1' THEN
---                                                                                              setstate <="01";
---                                                                                      END IF;
---
-
-
-
-							IF opcode(7)='1' THEN               --jsr, jmp
-								datatype <= "10";
-								ea_only <= '1';
-								ea_build_now <= '1';
-								IF exec(ea_to_pc)='1' THEN
-									next_micro_state <= nop;
-								END IF;
-								IF nextpass='1' AND micro_state=idle AND opcode(6)='0' THEN
-									set(presub) <= '1';
-									setstackaddr <='1';
-									setstate <="11";
-									next_micro_state <= nopnop;
-								END IF;
--- achtung buggefahr
-								IF micro_state=ld_AnXn1 AND brief(8)='0'THEN                    --JMP/JSR n(Ax,Dn)
-									skipFetch <= '1';
-								END IF;
-								IF state="00" THEN
-									writePC <= '1';
-								END IF;
-								set(hold_dwr) <= '1';
-								IF set(get_ea_now)='1' THEN                                     --jsr
-									IF exec(longaktion)='0' OR long_done='1' THEN
+--											ea_only <= '1';
+--											ea_build_now <= '1';
+--											IF nextpass='1' AND micro_state=idle THEN
+--												set(presub) <= '1';
+--												setstackaddr <='1';
+--												set(mem_addsub) <= '1';
+--												setstate <="11";
+--												next_micro_state <= nop;
+--											END IF;
+--											IF set(get_ea_now)='1' THEN
+--												setstate <="01";
+--											END IF;
+--								
+								
+								
+								
+							IF opcode(7)='1' THEN		--jsr, jmp
+								IF (opcode(5)='1' OR opcode(4 downto 3)="10") AND
+								   opcode(5 downto 3)/="100" AND opcode(5 downto 2)/="1111" THEN --ea illegal modes
+									datatype <= "10";
+									ea_only <= '1';
+									ea_build_now <= '1';
+									IF exec(ea_to_pc)='1' THEN
+										next_micro_state <= nop;
+									END IF;
+									IF nextpass='1' AND micro_state=idle AND opcode(6)='0' THEN
+										set(presub) <= '1';
+										setstackaddr <='1';
+										setstate <="11";
+										next_micro_state <= nopnop;
+									END IF;
+								
+									IF micro_state=ld_AnXn1 AND brief(8)='0'THEN			--JMP/JSR n(Ax,Dn)
 										skipFetch <= '1';
 									END IF;
-									setstate <="01";
-									set(ea_to_pc) <= '1';
+									IF state="00" THEN
+										writePC <= '1';
+									END IF;
+									set(hold_dwr) <= '1';
+									IF set(get_ea_now)='1' THEN					--jsr
+										IF exec(longaktion)='0' OR long_done='1' THEN
+											skipFetch <= '1';
+										END IF;
+										setstate <="01";
+										set(ea_to_pc) <= '1';
+									END IF;
+								ELSE
+									trap_illegal <= '1';
+									trapmake <= '1';
 								END IF;
-							ELSE                                                --
+							ELSE						--
 								CASE opcode(6 downto 0) IS
-									WHEN "1000000"|"1000001"|"1000010"|"1000011"|"1000100"|"1000101"|"1000110"|"1000111"|               --trap
-										 "1001000"|"1001001"|"1001010"|"1001011"|"1001100"|"1001101"|"1001110"|"1001111" =>             --trap
+									WHEN "1000000"|"1000001"|"1000010"|"1000011"|"1000100"|"1000101"|"1000110"|"1000111"|		--trap
+									     "1001000"|"1001001"|"1001010"|"1001011"|"1001100"|"1001101"|"1001110"|"1001111" =>		--trap
 											trap_trap <='1';
 											trapmake <= '1';
-									WHEN "1010000"|"1010001"|"1010010"|"1010011"|"1010100"|"1010101"|"1010110"|"1010111"=>              --link
+									
+									WHEN "1010000"|"1010001"|"1010010"|"1010011"|"1010100"|"1010101"|"1010110"|"1010111"=> 		--link word
 										datatype <= "10";
-										set_exec(opcADD) <= '1';                                                --for displacement
+										set_exec(opcADD) <= '1';						--for displacement
 										set_exec(Regwrena) <= '1';
 										set(no_Flags) <= '1';
 										IF decodeOPC='1' THEN
@@ -2038,11 +2443,11 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 											source_areg <= '1';
 											set(store_ea_data) <= '1';
 										END IF;
-
-									WHEN "1011000"|"1011001"|"1011010"|"1011011"|"1011100"|"1011101"|"1011110"|"1011111" =>             --unlink
+									
+									WHEN "1011000"|"1011001"|"1011010"|"1011011"|"1011100"|"1011101"|"1011110"|"1011111" =>		--unlink
 										datatype <= "10";
 										set_exec(Regwrena) <= '1';
-										set_exec(opcMOVE) <= '1';
+										set_exec(opcMOVE) <= '1';						
 										set(no_Flags) <= '1';
 										IF decodeOPC='1' THEN
 											setstate <= "01";
@@ -2053,10 +2458,10 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 											source_lowbits <= '1';
 											source_areg <= '1';
 										END IF;
-
-									WHEN "1100000"|"1100001"|"1100010"|"1100011"|"1100100"|"1100101"|"1100110"|"1100111" =>             --move An,USP
+									
+									WHEN "1100000"|"1100001"|"1100010"|"1100011"|"1100100"|"1100101"|"1100110"|"1100111" =>		--move An,USP
 										IF SVmode='1' THEN
---                                                                                      set(no_Flags) <= '1';
+--											set(no_Flags) <= '1';
 											set(to_USP) <= '1';
 											source_lowbits <= '1';
 											source_areg <= '1';
@@ -2065,9 +2470,10 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 											trap_priv <= '1';
 											trapmake <= '1';
 										END IF;
-									WHEN "1101000"|"1101001"|"1101010"|"1101011"|"1101100"|"1101101"|"1101110"|"1101111" =>             --move USP,An
+									
+									WHEN "1101000"|"1101001"|"1101010"|"1101011"|"1101100"|"1101101"|"1101110"|"1101111" =>		--move USP,An
 										IF SVmode='1' THEN
---                                                                                      set(no_Flags) <= '1';
+--											set(no_Flags) <= '1';
 											set(from_USP) <= '1';
 											datatype <= "10";
 											set_exec(Regwrena) <= '1';
@@ -2075,37 +2481,37 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 											trap_priv <= '1';
 											trapmake <= '1';
 										END IF;
-
-									WHEN "1110000" =>                                   --reset
+									
+									WHEN "1110000" =>					--reset
 										IF SVmode='0' THEN
 											trap_priv <= '1';
 											trapmake <= '1';
 										ELSE
 											set(opcRESET) <= '1';
 											IF decodeOPC='1' THEN
-												set(ld_rot_cnt) <= '1';
+												set(ld_rot_cnt) <= '1'; 
 												set_rot_cnt <= "000000";
 											END IF;
 										END IF;
-
-									WHEN "1110001" =>                                   --nop
-
-									WHEN "1110010" =>                                   --stop
+										
+									WHEN "1110001" =>					--nop
+									
+									WHEN "1110010" =>					--stop
 										IF SVmode='0' THEN
 											trap_priv <= '1';
 											trapmake <= '1';
 										ELSE
 											IF decodeOPC='1' THEN
 												setnextpass <= '1';
-												set_stop <= '1';
+												set_stop <= '1';	
 											END IF;
 											IF stop='1' THEN
 												skipFetch <= '1';
-											END IF;
-
+											END IF;		
+											
 										END IF;
-
-									WHEN "1110011"|"1110111" =>                                                                         --rte/rtr
+									
+									WHEN "1110011"|"1110111" =>  									--rte/rtr
 										IF SVmode='1' OR opcode(2)='1' THEN
 											IF decodeOPC='1' THEN
 												setstate <= "10";
@@ -2113,8 +2519,8 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 												setstackaddr <= '1';
 												IF opcode(2)='1' THEN
 													set(directCCR) <= '1';
-												ELSE
-													set(directSR) <= '1';
+												ELSE	
+													set(directSR) <= '1';	
 												END IF;
 												next_micro_state <= rte1;
 											END IF;
@@ -2122,8 +2528,8 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 											trap_priv <= '1';
 											trapmake <= '1';
 										END IF;
-
-									WHEN "1110101" =>                                                                   --rts
+										
+									WHEN "1110100" =>  									--rtd
 										datatype <= "10";
 										IF decodeOPC='1' THEN
 											setstate <= "10";
@@ -2131,27 +2537,40 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 											setstackaddr <= '1';
 											set(direct_delta) <= '1';
 											set(directPC) <= '1';
+											set_direct_data <= '1';
+											next_micro_state <= rtd1;
+										END IF;
+										
+										
+									WHEN "1110101" =>  									--rts
+										datatype <= "10";
+										IF decodeOPC='1' THEN
+											setstate <= "10";
+											set(postadd) <= '1';
+											setstackaddr <= '1';
+											set(direct_delta) <= '1';	
+											set(directPC) <= '1';
 											next_micro_state <= nopnop;
 										END IF;
-
-									WHEN "1110110" =>                                                                   --trapv
+										
+									WHEN "1110110" =>  									--trapv
 										IF decodeOPC='1' THEN
 											setstate <= "01";
-										END IF;
+										END IF;	
 										IF Flags(1)='1' AND state="01" THEN
 											trap_trapv <= '1';
 											trapmake <= '1';
 										END IF;
-
-									WHEN "1111010"|"1111011" =>                                                                         --movec
-										IF VBR_Stackframe=0 OR (cpu(0)='0' AND VBR_Stackframe=2) THEN
+										
+									WHEN "1111010"|"1111011" =>  									--movec
+										IF cpu="00" THEN
 											trap_illegal <= '1';
 											trapmake <= '1';
 										ELSIF SVmode='0' THEN
 											trap_priv <= '1';
 											trapmake <= '1';
 										ELSE
-											datatype <= "10";   --Long
+											datatype <= "10";	--Long
 											IF last_data_read(11 downto 0)=X"800" THEN
 												set(from_USP) <= '1';
 												IF opcode(0)='1' THEN
@@ -2160,7 +2579,7 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 											END IF;
 											IF opcode(0)='0' THEN
 												set_exec(movec_rd) <= '1';
-											ELSE
+											ELSE		
 												set_exec(movec_wr) <= '1';
 											END IF;
 											IF decodeOPC='1' THEN
@@ -2168,19 +2587,18 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 												getbrief <='1';
 											END IF;
 										END IF;
-
-									WHEN OTHERS =>
+									
+									WHEN OTHERS =>	
 										trap_illegal <= '1';
 										trapmake <= '1';
-								END CASE;
+								END CASE;	
 							END IF;
 						WHEN OTHERS => NULL;
 					END CASE;
-				END IF;
---
+				END IF;	
+--					
 ---- 0101 ----------------------------------------------------------------------------
-			WHEN "0101" =>                                                              --subq, addq
-
+			WHEN "0101" => 								--subq, addq
 					IF opcode(7 downto 6)="11" THEN --dbcc
 						IF opcode(5 downto 3)="001" THEN --dbcc
 							IF decodeOPC='1' THEN
@@ -2188,41 +2606,69 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 								set(OP2out_one) <= '1';
 								data_is_source <= '1';
 							END IF;
-						ELSE                            --Scc
-							datatype <= "00";                   --Byte
+						ELSIF opcode(5 downto 3)="111" AND (opcode(2 downto 1)="01" OR opcode(2 downto 0)="100") THEN	--trapcc
+							IF cpu(1)='1' THEN							-- only 68020+
+								IF opcode(2 downto 1)="01" THEN
+									IF decodeOPC='1' THEN
+										IF opcode(0)='1' THEN			--long
+											set(longaktion) <= '1';
+										END IF;
+										next_micro_state <= nop;
+									END IF;
+								ELSE
+									IF decodeOPC='1' THEN
+										setstate <= "01";
+									END IF;
+								END IF;
+								IF exe_condition='1' AND decodeOPC='0' THEN
+									trap_trapv <= '1';
+									trapmake <= '1';
+								END IF;
+							ELSE
+								trap_illegal <= '1';
+								trapmake <= '1';
+							END IF;
+						ELSE				--Scc
+							datatype <= "00";			--Byte
 							ea_build_now <= '1';
 							write_back <= '1';
 							set_exec(opcScc) <= '1';
-							IF cpu(0)='1' AND state="10" THEN
+							IF cpu(0)='1' AND state="10" AND addrvalue='0' THEN
 								skipFetch <= '1';
 							END IF;
 							IF opcode(5 downto 4)="00" THEN
 								set_exec(Regwrena) <= '1';
 							END IF;
 						END IF;
-					ELSE                                        --addq, subq
-						ea_build_now <= '1';
-						IF opcode(5 downto 3)="001" THEN
-							set(no_Flags) <= '1';
-						END IF;
-						IF opcode(8)='1' THEN
-							set(addsub) <= '1';
-						END IF;
-						write_back <= '1';
-						set_exec(opcADDQ) <= '1';
-						set_exec(opcADD) <= '1';
-						set_exec(ea_data_OP1) <= '1';
-						IF opcode(5 downto 4)="00" THEN
-							set_exec(Regwrena) <= '1';
+					ELSE					--addq, subq
+						IF opcode(7 downto 3)/="00001" AND
+						   (opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00") THEN --ea illegal modes
+							ea_build_now <= '1';
+							IF opcode(5 downto 3)="001" THEN
+								set(no_Flags) <= '1';
+							END IF;
+							IF opcode(8)='1' THEN
+								set(addsub) <= '1';
+							END IF;
+							write_back <= '1';
+							set_exec(opcADDQ) <= '1';
+							set_exec(opcADD) <= '1';
+							set_exec(ea_data_OP1) <= '1';
+							IF opcode(5 downto 4)="00" THEN
+								set_exec(Regwrena) <= '1';
+							END IF;
+						ELSE
+							trap_illegal <= '1';
+							trapmake <= '1';
 						END IF;
 					END IF;
---
----- 0110 ----------------------------------------------------------------------------
-			WHEN "0110" =>                              --bra,bsr,bcc
+--				
+---- 0110 ----------------------------------------------------------------------------		
+			WHEN "0110" =>				--bra,bsr,bcc
 				datatype <= "10";
-
+				
 				IF micro_state=idle THEN
-					IF opcode(11 downto 8)="0001" THEN          --bsr
+					IF opcode(11 downto 8)="0001" THEN		--bsr
 						set(presub) <= '1';
 						setstackaddr <='1';
 						IF opcode(7 downto 0)="11111111" THEN
@@ -2230,12 +2676,12 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 							set(longaktion) <= '1';
 						ELSIF opcode(7 downto 0)="00000000" THEN
 							next_micro_state <= bsr2;
-						ELSE
+						ELSE	
 							next_micro_state <= bsr1;
 							setstate <= "11";
 							writePC <= '1';
 						END IF;
-					ELSE                                                                        --bra
+					ELSE									--bra
 						IF opcode(7 downto 0)="11111111" THEN
 							next_micro_state <= bra1;
 							set(longaktion) <= '1';
@@ -2246,28 +2692,27 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 							next_micro_state <= bra1;
 						END IF;
 					END IF;
+				END IF;	
+				
+-- 0111 ----------------------------------------------------------------------------		
+			WHEN "0111" =>				--moveq
+				IF opcode(8)='0' THEN
+					datatype <= "10";		--Long
+					set_exec(Regwrena) <= '1';
+					set_exec(opcMOVEQ) <= '1';
+					set_exec(opcMOVE) <= '1';
+					dest_hbits <= '1';
+				ELSE
+					trap_illegal <= '1';
+					trapmake <= '1';
 				END IF;
-
--- 0111 ----------------------------------------------------------------------------
-			WHEN "0111" =>                              --moveq
---                              IF opcode(8)='0' THEN   -- Cloanto's Amiga Forver ROMs have mangled movq instructions with a 1 here...
-					IF trap_interrupt='0' AND trap_trace='0' THEN
-						datatype <= "10";               --Long
-						set_exec(Regwrena) <= '1';
-						set_exec(opcMOVEQ) <= '1';
-						set_exec(opcMOVE) <= '1';
-						dest_hbits <= '1';
-					END IF;
---                              ELSE
---                                      trap_illegal <= '1';
---                                      trapmake <= '1';
---                              END IF;
-
----- 1000 ----------------------------------------------------------------------------
-			WHEN "1000" =>                                                              --or
-				IF opcode(7 downto 6)="11" THEN --divu, divs
-					IF DIV_Mode/=3 THEN
-						IF opcode(5 downto 4)="00" THEN --Dn, An
+				
+---- 1000 ----------------------------------------------------------------------------		
+			WHEN "1000" => 								--or	
+				IF opcode(7 downto 6)="11" THEN	--divu, divs
+					IF DIV_Mode/=3 AND
+					   opcode(5 downto 3)/="001" AND (opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00") THEN --ea illegal modes
+						IF opcode(5 downto 4)="00" THEN	--Dn, An
 							regdirectsource <= '1';
 						END IF;
 						IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
@@ -2287,123 +2732,132 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 						trap_illegal <= '1';
 						trapmake <= '1';
 					END IF;
-
-				ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN    --sbcd, pack , unpack
-					IF opcode(7 downto 6)="00" THEN     --sbcd
+				ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN	--sbcd, pack , unpack
+					IF opcode(7 downto 6)="00" THEN	--sbcd
 						build_bcd <= '1';
 						set_exec(opcADD) <= '1';
 						set_exec(opcSBCD) <= '1';
-         ELSIF cpu(1)='1' AND (opcode(7 downto 6)="01" OR opcode(7 downto 6)="10") THEN  --pack, unpack
-           datatype <= "01";   --Word
-           set_exec(opcPACK) <= '1';
-           set(no_Flags) <= '1';  -- this command modifies no flags
-
-           -- immediate value is kept in op1
-           -- source value is in op2
-           
-           -- xyz
-           if opcode(3)='0' then -- R/M bit = 0 -> Dy->Dy, 1 -(Ax),-(Ay)
-             dest_hbits <='1';      -- dest register is encoded in bits 9-11
-             source_lowbits <= '1'; -- source register is encoded in bits 0-2
-
-             set_exec(Regwrena) <= '1';    -- write result into register
-             set_exec(ea_data_OP1) <= '1'; -- immediate value goes into op2
-             set(hold_dwr) <= '1';
-
-             -- pack writes a byte only
-             IF opcode(7 downto 6) = "01" THEN
-               datatype <= "00";    --Byte
-             ELSE
-               datatype <= "01";    --Word
-             END IF;
-  
-             IF decodeOPC='1' THEN
-               next_micro_state <= nop;
-               set_direct_data <= '1';
-             END IF;
-           else 
-             set_exec(ea_data_OP1) <= '1';
-             source_lowbits <= '1'; -- source register is encoded in bits 0-2
-             
-             IF decodeOPC='1' THEN
-               -- first step: read source value
-               IF opcode(7 downto 6) = "10" THEN -- UNPK reads a byte
-                 datatype <= "00"; -- Byte
-               END IF;
-                set_direct_data <= '1';
-                setstate <= "10";
-                set(update_ld) <= '1';
-                set(presub) <= '1';
-                next_micro_state <= pack1;
-                dest_areg <= '1'; --???
-              end IF;
-           end IF;
-         ELSE
+						set(addsub) <= '1';
+					ELSIF opcode(7 downto 6)="01" OR opcode(7 downto 6)="10" THEN	--pack , unpack
+						set_exec(ea_data_OP1) <= '1';
+						set(no_Flags) <= '1';
+						source_lowbits <='1';
+						IF opcode(7 downto 6) = "01" THEN	--pack
+							set_exec(opcPACK) <= '1';
+							datatype <= "01";				--Word
+						ELSE								--unpk
+							set_exec(opcUNPACK) <= '1';
+							datatype <= "00";				--Byte
+						END IF;
+						IF opcode(3)='0' THEN
+							IF opcode(7 downto 6) = "01" THEN	--pack
+								set_datatype <= "00";		--Byte
+							ELSE								--unpk
+								set_datatype <= "01";		--Word
+							END IF;
+							set_exec(Regwrena) <= '1';
+							dest_hbits <= '1';
+							IF decodeOPC='1' THEN
+								next_micro_state <= nop;
+--								set_direct_data <= '1';
+								set(store_ea_packdata) <= '1';
+								set(store_ea_data) <= '1';
+							END IF;
+						ELSE				-- pack -(Ax),-(Ay)
+							write_back <= '1';
+							IF decodeOPC='1' THEN
+								next_micro_state <= pack1;
+								set_direct_data <= '1';
+							END IF;
+						END IF;
+					ELSE
 						trap_illegal <= '1';
 						trapmake <= '1';
 					END IF;
-				ELSE                                                                    --or
-					set_exec(opcOR) <= '1';
-					build_logical <= '1';
-				END IF;
-
----- 1001, 1101 -----------------------------------------------------------------------
-			WHEN "1001"|"1101" =>                                               --sub, add
-				set_exec(opcADD) <= '1';
-				ea_build_now <= '1';
-				IF opcode(14)='0' THEN
-					set(addsub) <= '1';
-				END IF;
-				IF opcode(7 downto 6)="11" THEN --      --adda, suba
-					IF opcode(8)='0' THEN       --adda.w, suba.w
-						datatype <= "01";       --Word
-					END IF;
-					set_exec(Regwrena) <= '1';
-					source_lowbits <='1';
-					IF opcode(3)='1' THEN
-						source_areg <= '1';
-					END IF;
-					set(no_Flags) <= '1';
-					IF setexecOPC='1' THEN
-						dest_areg <='1';
-						dest_hbits <= '1';
-					END IF;
-				ELSE
-					IF opcode(8)='1' AND opcode(5 downto 4)="00" THEN           --addx, subx
-						build_bcd <= '1';
-					ELSE                                                        --sub, add
+				ELSE									--or
+					IF opcode(7 downto 6)/="11" AND --illegal opmode
+					   ((opcode(8)='0' AND opcode(5 downto 3)/="001" AND (opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00")) OR --illegal src ea
+					   (opcode(8)='1' AND opcode(5 downto 4)/="00" AND (opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00"))) THEN --illegal dst ea
+						set_exec(opcOR) <= '1';
 						build_logical <= '1';
+					ELSE
+						trap_illegal <= '1';
+						trapmake <= '1';
 					END IF;
 				END IF;
-
---
----- 1010 ----------------------------------------------------------------------------
-			WHEN "1010" =>                                                      --Trap 1010
-				trap_1010 <= '1';
-				trapmake <= '1';
----- 1011 ----------------------------------------------------------------------------
-			WHEN "1011" =>                                                      --eor, cmp
-				ea_build_now <= '1';
-				IF opcode(7 downto 6)="11" THEN --CMPA
-					IF opcode(8)='0' THEN       --cmpa.w
-						datatype <= "01";       --Word
-						set_exec(opcCPMAW) <= '1';
+				
+---- 1001, 1101 -----------------------------------------------------------------------		
+			WHEN "1001"|"1101" => 						--sub, add
+				IF opcode(8 downto 3)/="000001" AND --byte src address reg direct
+				   (((opcode(8)='0' OR opcode(7 downto 6)="11") AND (opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00")) OR --illegal src ea
+				   (opcode(8)='1' AND (opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00"))) THEN --illegal dst ea
+					set_exec(opcADD) <= '1';
+					ea_build_now <= '1';
+					IF opcode(14)='0' THEN
+						set(addsub) <= '1';
 					END IF;
-					set_exec(opcCMP) <= '1';
-					IF setexecOPC='1' THEN
+					IF opcode(7 downto 6)="11" THEN	--	--adda, suba
+						IF opcode(8)='0' THEN	--adda.w, suba.w
+							datatype <= "01";	--Word
+						END IF;
+						set_exec(Regwrena) <= '1';
 						source_lowbits <='1';
 						IF opcode(3)='1' THEN
 							source_areg <= '1';
 						END IF;
-						dest_areg <='1';
-						dest_hbits <= '1';
+						set(no_Flags) <= '1';
+						IF setexecOPC='1' THEN
+							dest_areg <='1';
+							dest_hbits <= '1';
+						END IF;
+					ELSE
+						IF opcode(8)='1' AND opcode(5 downto 4)="00" THEN		--addx, subx
+							build_bcd <= '1';
+						ELSE							--sub, add
+							build_logical <= '1';
+						END IF;
 					END IF;
-					set(addsub) <= '1';
 				ELSE
+						trap_illegal <= '1';
+						trapmake <= '1';
+				END IF;
+--				
+---- 1010 ----------------------------------------------------------------------------		
+			WHEN "1010" => 							--Trap 1010
+				trap_1010 <= '1';
+				trapmake <= '1';
+---- 1011 ----------------------------------------------------------------------------		
+			WHEN "1011" => 							--eor, cmp
+				IF opcode(7 downto 6)="11" THEN	--CMPA
+					IF opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00" THEN --illegal src ea
+						ea_build_now <= '1';
+						IF opcode(8)='0' THEN	--cmpa.w
+							datatype <= "01";	--Word
+							set_exec(opcCPMAW) <= '1';
+						END IF;
+						set_exec(opcCMP) <= '1';
+						IF setexecOPC='1' THEN
+							source_lowbits <='1';
+							IF opcode(3)='1' THEN
+								source_areg <= '1';
+							END IF;
+							dest_areg <='1';
+							dest_hbits <= '1';
+						END IF;
+						set(addsub) <= '1';
+					ELSE
+						trap_illegal <= '1';
+						trapmake <= '1';
+					END IF;
+				ELSE	--cmpm, eor, cmp
 					IF opcode(8)='1' THEN
-						IF opcode(5 downto 3)="001" THEN                --cmpm
+						IF opcode(5 downto 3)="001" THEN		--cmpm
+							ea_build_now <= '1';
 							set_exec(opcCMP) <= '1';
 							IF decodeOPC='1' THEN
+								IF opcode(2 downto 0)="111" THEN
+									set(use_SP) <= '1';
+								END IF;
 								setstate <= "10";
 								set(update_ld) <= '1';
 								set(postadd) <= '1';
@@ -2411,28 +2865,47 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 							END IF;
 							set_exec(ea_data_OP1) <= '1';
 							set(addsub) <= '1';
-						ELSE                                            --EOR
-							build_logical <= '1';
-							set_exec(opcEOR) <= '1';
+						ELSE						--EOR
+							IF opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00" THEN --illegal dst ea
+								ea_build_now <= '1';
+								build_logical <= '1';
+								set_exec(opcEOR) <= '1';
+							ELSE
+								trap_illegal <= '1';
+								trapmake <= '1';
+							END IF;
+						END IF;
+					ELSE							--CMP
+						IF opcode(8 downto 3)/="000001" AND --byte src address reg direct
+						   (opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00") THEN --illegal src ea
+							ea_build_now <= '1';
+							build_logical <= '1';
+							set_exec(opcCMP) <= '1';
+							set(addsub) <= '1';
+						ELSE
+							trap_illegal <= '1';
+							trapmake <= '1';
 						END IF;
-					ELSE                                                        --CMP
-						build_logical <= '1';
-						set_exec(opcCMP) <= '1';
-						set(addsub) <= '1';
 					END IF;
 				END IF;
---
----- 1100 ----------------------------------------------------------------------------
-			WHEN "1100" =>                                                              --and, exg
-				IF opcode(7 downto 6)="11" THEN --mulu, muls
-					IF MUL_Mode/=3 THEN
-						IF opcode(5 downto 4)="00" THEN --Dn, An
+--				
+---- 1100 ----------------------------------------------------------------------------		
+			WHEN "1100" => 								--and, exg
+				IF opcode(7 downto 6)="11" THEN	--mulu, muls
+					IF MUL_Mode/=3 AND
+					   opcode(5 downto 3)/="001" AND (opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00") THEN --ea illegal modes
+						IF opcode(5 downto 4)="00" THEN	--Dn, An
 							regdirectsource <= '1';
 						END IF;
-						IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN
-							setstate <="01";
-							set(ld_rot_cnt) <= '1';
-							next_micro_state <= mul1;
+						IF (micro_state=idle AND nextpass='1') OR (opcode(5 downto 4)="00" AND decodeOPC='1') THEN	
+							IF MUL_Hardware=0 THEN
+								setstate <="01";
+								set(ld_rot_cnt) <= '1';
+								next_micro_state <= mul1;
+							ELSE
+								set_exec(write_lowlong) <= '1';
+								set_exec(opcMULU) <= '1';
+							END IF;
 						END IF;
 						ea_build_now <= '1';
 						set_exec(Regwrena) <= '1';
@@ -2441,47 +2914,75 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 							dest_hbits <= '1';
 						END IF;
 						datatype <= "01";
+						IF setexecOPC='1' THEN
+							datatype <= "10";
+						END IF;
 					ELSE
 						trap_illegal <= '1';
 						trapmake <= '1';
 					END IF;
-
-				ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN    --exg, abcd
-					IF opcode(7 downto 6)="00" THEN     --abcd
+				ELSIF opcode(8)='1' AND opcode(5 downto 4)="00" THEN	--exg, abcd
+					IF opcode(7 downto 6)="00" THEN	--abcd
 						build_bcd <= '1';
 						set_exec(opcADD) <= '1';
 						set_exec(opcABCD) <= '1';
-					ELSE                                                                        --exg
-						datatype <= "10";
-						set(Regwrena) <= '1';
-						set(exg) <= '1';
-						IF opcode(6)='1' AND opcode(3)='1' THEN
-							dest_areg <= '1';
-							source_areg <= '1';
-						END IF;
-						IF decodeOPC='1' THEN
-							setstate <= "01";
+					ELSE									--exg
+						IF opcode(7 downto 4)="0100" OR opcode(7 downto 3)="10001" THEN
+							datatype <= "10";
+							set(Regwrena) <= '1';
+							set(exg) <= '1';
+							set(alu_move) <= '1';
+							IF opcode(6)='1' AND opcode(3)='1' THEN
+								dest_areg <= '1';
+								source_areg <= '1';
+							END IF;
+							IF decodeOPC='1' THEN
+								setstate <= "01";
+							ELSE
+								dest_hbits <= '1';
+							END IF;
 						ELSE
-							dest_hbits <= '1';
+							trap_illegal <= '1';
+							trapmake <= '1';
 						END IF;
 					END IF;
-				ELSE                                                                    --and
-					set_exec(opcAND) <= '1';
-					build_logical <= '1';
+				ELSE									--and
+					IF opcode(7 downto 6)/="11" AND --illegal opmode
+					   ((opcode(8)='0' AND opcode(5 downto 3)/="001" AND (opcode(5 downto 2)/="1111" OR opcode(1 downto 0)="00")) OR --illegal src ea
+					   (opcode(8)='1' AND opcode(5 downto 4)/="00" AND (opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00"))) THEN --illegal dst ea
+						set_exec(opcAND) <= '1';
+						build_logical <= '1';
+					ELSE
+						trap_illegal <= '1';
+						trapmake <= '1';
+					END IF;
 				END IF;
---
----- 1110 ----------------------------------------------------------------------------
-			WHEN "1110" =>                                                              --rotation / bitfield
+--				
+---- 1110 ----------------------------------------------------------------------------		
+			WHEN "1110" => 								--rotation / bitfield
 				IF opcode(7 downto 6)="11" THEN
 					IF opcode(11)='0' THEN
-						set_exec(opcROT) <= '1';
-						ea_build_now <= '1';
-						datatype <= "01";
-						set_rot_bits <= opcode(10 downto 9);
-						set_exec(ea_data_OP1) <= '1';
-						write_back <= '1';
-					ELSE                --bitfield
-						IF BitField=0 OR (cpu(1)='0' AND BitField=2) THEN
+					   IF (opcode(5 downto 4)/="00" AND (opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00")) THEN --ea illegal modes
+							IF BarrelShifter=0 THEN
+								set_exec(opcROT) <= '1';
+							ELSE
+								set_exec(exec_BS) <='1';
+							END IF;
+							ea_build_now <= '1';
+							datatype <= "01";
+							set_rot_bits <= opcode(10 downto 9);
+							set_exec(ea_data_OP1) <= '1';
+							write_back <= '1';
+						ELSE
+							trap_illegal <= '1';
+							trapmake <= '1';
+						END IF;
+					ELSE		--bitfield
+						IF BitField=0 OR (cpu(1)='0' AND BitField=2) OR
+						   ((opcode(10 downto 9)="11" OR opcode(10 downto 8)="010" OR opcode(10 downto 8)="100") AND
+						   (opcode(5 downto 3)="001" OR opcode(5 downto 3)="011" OR opcode(5 downto 3)="100" OR (opcode(5 downto 3)="111" AND opcode(2 downto 1)/="00"))) OR
+						   ((opcode(10 downto 9)="00" OR opcode(10 downto 8)="011" OR opcode(10 downto 8)="101") AND
+						   (opcode(5 downto 3)="001" OR opcode(5 downto 3)="011" OR opcode(5 downto 3)="100" OR opcode(5 downto 2)="1111")) THEN
 							trap_illegal <= '1';
 							trapmake <= '1';
 						ELSE
@@ -2491,26 +2992,24 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 								set(ea_build) <= '1';
 							END IF;
 							set_exec(opcBF) <= '1';
+--		000-bftst, 001-bfextu, 010-bfchg, 011-bfexts, 100-bfclr, 101-bfff0, 110-bfset, 111-bfins								
 							IF opcode(10)='1' OR opcode(8)='0' THEN
-								set_exec(opcBFwb) <= '1';
-                                                                IF opcode(10 downto 8)/="111" THEN -- bfins
-                                                                  set_exec(ea_data_OP2) <= '1'; -- for the flags
-                                                                END IF;
+								set_exec(opcBFwb) <= '1';			--'1' for tst,chg,clr,ffo,set,ins    --'0' for extu,exts
+							END IF;
+							IF opcode(10 downto 8)="111" THEN	--BFINS
 								set_exec(ea_data_OP1) <= '1';
 							END IF;
-
-                                                        -- BFCHG, BFCLR, BFSET, BFINS
 							IF opcode(10 downto 8)="010" OR opcode(10 downto 8)="100" OR opcode(10 downto 8)="110" OR opcode(10 downto 8)="111" THEN
 								write_back <= '1';
 							END IF;
 							ea_only <= '1';
-                                                        -- BFEXTU, BFEXTS, BFFFO
 							IF opcode(10 downto 8)="001" OR opcode(10 downto 8)="011" OR opcode(10 downto 8)="101" THEN
 								set_exec(Regwrena) <= '1';
 							END IF;
-                                                        -- register destination
 							IF opcode(4 downto 3)="00" THEN
-								set_exec(Regwrena) <= '1';
+								IF opcode(10 downto 8)/="000" THEN
+									set_exec(Regwrena) <= '1';
+								END IF;
 								IF exec(ea_build)='1' THEN
 									dest_2ndHbits <= '1';
 									source_2ndLbits <= '1';
@@ -2529,45 +3028,122 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 								set(mem_addsub) <='1';
 								next_micro_state <= bf1;
 							END IF;
-
--- BFINS  D1,D0         s2ndHbits <<D1 -> D0
--- BFEXT  D0,D1         sLbits    >>D0 -> D1 d2ndHbits
--- BFINS  D1,(A0)       s2ndHbits <<D1 -> (A0)
--- BFEXT  (A0),D1               >>(A0) -> D1 d2ndHbits
 							IF setexecOPC='1' THEN
-								IF opcode(10 downto 8)="111" THEN       --BFINS
+								IF opcode(10 downto 8)="111" THEN	--BFINS
 									source_2ndHbits <= '1';
-								ELSIF opcode(10 downto 8)="001" or opcode(10 downto 8)="011" THEN	--BFEXT
+								ELSE
 									source_lowbits <= '1';
+								END IF;
+								IF opcode(10 downto 8)="001" OR opcode(10 downto 8)="011" OR opcode(10 downto 8)="101" THEN	--BFEXT, BFFFO
 									dest_2ndHbits <= '1';
 								END IF;
 							END IF;
 						END IF;
 					END IF;
 				ELSE
-					set_exec(opcROT) <= '1';
-					set_rot_bits <= opcode(4 downto 3);
 					data_is_source <= '1';
-					set_exec(Regwrena) <= '1';
-					IF decodeOPC='1' THEN
-						IF opcode(5)='1' THEN
-							next_micro_state <= rota1;
-							set(ld_rot_cnt) <= '1';
-							setstate <= "01";
-						ELSE
-							set_rot_cnt(2 downto 0) <= opcode(11 downto 9);
-							IF opcode(11 downto 9)="000" THEN
-								set_rot_cnt(3) <='1';
+					IF BarrelShifter=0 OR (cpu(1)='0' AND BarrelShifter=2) THEN
+						set_exec(opcROT) <= '1';
+						set_rot_bits <= opcode(4 downto 3);
+						set_exec(Regwrena) <= '1';
+						IF decodeOPC='1' THEN
+							IF opcode(5)='1' THEN
+								next_micro_state <= rota1;
+								set(ld_rot_cnt) <= '1';
+								setstate <= "01";
 							ELSE
-								set_rot_cnt(3) <='0';
+								set_rot_cnt(2 downto 0) <= opcode(11 downto 9);
+								IF opcode(11 downto 9)="000" THEN
+									set_rot_cnt(3) <='1';
+								ELSE
+									set_rot_cnt(3) <='0';
+								END IF;
 							END IF;
 						END IF;
+					ELSE
+						set_exec(exec_BS) <='1';
+						set_rot_bits <= opcode(4 downto 3);
+						set_exec(Regwrena) <= '1';
 					END IF;
 				END IF;
---
-----      ----------------------------------------------------------------------------
+--				
+---- 1111 ----------------------------------------------------------------------------		
+			WHEN "1111" =>
+				IF cpu(1)='1' AND opcode(8 downto 6)="100" THEN --cpSAVE
+					IF opcode(5 downto 4)/="00" AND opcode(5 downto 3)/="011" AND
+					   (opcode(5 downto 3)/="111" OR opcode(2 downto 1)="00") THEN --ea illegal modes
+						IF opcode(11 downto 9)/="000" THEN
+							IF SVmode='1' THEN
+								IF opcode(5)='0' AND opcode(5 downto 4)/="01" THEN
+									--never reached according to cputest?!
+									--cpSAVE not implemented
+									trap_illegal <= '1';
+									trapmake <= '1';
+								ELSE
+									trap_1111 <= '1';
+									trapmake <= '1';
+								END IF;
+							ELSE
+								trap_priv <= '1';
+								trapmake <= '1';
+							END IF;
+						ELSE
+							IF SVmode='1' THEN
+								trap_1111 <= '1';
+								trapmake <= '1';
+							ELSE
+								trap_priv <= '1';
+								trapmake <= '1';
+							END IF;
+						END IF;
+					ELSE
+						trap_1111 <= '1';
+						trapmake <= '1';
+					END IF;
+				ELSIF cpu(1)='1' AND opcode(8 downto 6)="101" THEN --cpRESTORE
+					IF opcode(5 downto 4)/="00" AND opcode(5 downto 3)/="100" AND
+					   (opcode(5 downto 3)/="111" OR (opcode(2 downto 1)/="11" AND
+					   opcode(2 downto 0)/="101")) THEN --ea illegal modes
+						IF opcode(5 downto 1)/="11110" THEN
+							IF opcode(11 downto 9)="001" OR opcode(11 downto 9)="010" THEN
+								IF SVmode='1' THEN
+									IF opcode(5 downto 3)="101" THEN
+										--cpRESTORE not implemented
+										trap_illegal <= '1';
+										trapmake <= '1';
+									ELSE
+										trap_1111 <= '1';
+										trapmake <= '1';
+									END IF;
+								ELSE
+									trap_priv <= '1';
+									trapmake <= '1';
+								END IF;
+							ELSE
+								IF SVmode='1' THEN
+									trap_1111 <= '1';
+									trapmake <= '1';
+								ELSE
+									trap_priv <= '1';
+									trapmake <= '1';
+								END IF;
+							END IF;
+						ELSE
+							trap_1111 <= '1';
+							trapmake <= '1';
+						END IF;
+					ELSE
+						trap_1111 <= '1';
+						trapmake <= '1';
+					END IF;
+				ELSE
+					trap_1111 <= '1';
+					trapmake <= '1';
+				END IF;
+--							
+----      ----------------------------------------------------------------------------		
 			WHEN OTHERS =>
-				trap_1111 <= '1';
+				trap_illegal <= '1';
 				trapmake <= '1';
 
 		END CASE;
@@ -2575,7 +3151,7 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 -- use for AND, OR, EOR, CMP
 		IF build_logical='1' THEN
 			ea_build_now <= '1';
-			IF set_exec(opcCMP)='0' AND (opcode(8)='0' OR opcode(5 downto 4)="00" ) THEN
+			IF set_exec(opcCMP)='0' AND (opcode(8)='0' OR opcode(5 downto 4)="00" ) THEN					
 				set_exec(Regwrena) <= '1';
 			END IF;
 			IF opcode(8)='1' THEN
@@ -2583,7 +3159,7 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 				set_exec(ea_data_OP1) <= '1';
 			ELSE
 				source_lowbits <='1';
-				IF opcode(3)='1' THEN           --use for cmp
+				IF opcode(3)='1' THEN		--use for cmp
 					source_areg <= '1';
 				END IF;
 				IF setexecOPC='1' THEN
@@ -2591,7 +3167,7 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 				END IF;
 			END IF;
 		END IF;
-
+		
 -- use for ABCD, SBCD
 		IF build_bcd='1' THEN
 			set_exec(use_XZFlag) <= '1';
@@ -2600,33 +3176,36 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 			source_lowbits <='1';
 			IF opcode(3)='1' THEN
 				IF decodeOPC='1' THEN
+					IF opcode(2 downto 0)="111" THEN
+						set(use_SP) <= '1';
+					END IF;
 					setstate <= "10";
 					set(update_ld) <= '1';
 					set(presub) <= '1';
 					next_micro_state <= op_AxAy;
-					dest_areg <= '1';                           --???
+					dest_areg <= '1';				--???
 				END IF;
 			ELSE
 				dest_hbits <= '1';
 				set_exec(Regwrena) <= '1';
 			END IF;
 		END IF;
+		
 
-
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-		IF set_Z_error='1'  THEN                -- divu by zero
-			trapmake <= '1';                    --wichtig for USP
+------------------------------------------------------------------------------		
+------------------------------------------------------------------------------		
+		IF set_Z_error='1'  THEN		-- divu by zero
+			trapmake <= '1';			--wichtig for USP
 			IF trapd='0' THEN
 				writePC <= '1';
-			END IF;
-		END IF;
-
+			END IF;			
+		END IF;	
+		
 -----------------------------------------------------------------------------
 -- execute microcode
 -----------------------------------------------------------------------------
 		IF rising_edge(clk) THEN
-			IF Reset='1' THEN
+	        IF Reset='1' THEN
 				micro_state <= ld_nn;
 			ELSIF clkena_lw='1' THEN
 				trapd <= trapmake;
@@ -2635,31 +3214,30 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 		END IF;
 
 			CASE micro_state IS
-				WHEN ld_nn =>           -- (nnnn).w/l=>
+				WHEN ld_nn =>		-- (nnnn).w/l=>
 					set(get_ea_now) <='1';
 					setnextpass <= '1';
 					set(addrlong) <= '1';
-
-				WHEN st_nn =>           -- =>(nnnn).w/l
+					
+				WHEN st_nn =>		-- =>(nnnn).w/l
 					setstate <= "11";
 					set(addrlong) <= '1';
 					next_micro_state <= nop;
-
-				WHEN ld_dAn1 =>         -- d(An)=>, --d(PC)=>
+					
+				WHEN ld_dAn1 =>		-- d(An)=>, --d(PC)=>
 					set(get_ea_now) <='1';
-					setdisp <= '1';             --word
+					setdisp <= '1';		--word
 					setnextpass <= '1';
-
-				WHEN ld_AnXn1 =>                -- d(An,Xn)=>, --d(PC,Xn)=>
+					
+				WHEN ld_AnXn1 =>		-- d(An,Xn)=>, --d(PC,Xn)=>
 					IF brief(8)='0' OR extAddr_Mode=0 OR (cpu(1)='0' AND extAddr_Mode=2) THEN
-						-- mikej brief extension word only
-						setdisp <= '1';         --byte
+						setdisp <= '1';		--byte	
 						setdispbyte <= '1';
 						setstate <= "01";
 						set(briefext) <= '1';
 						next_micro_state <= ld_AnXn2;
-					ELSE
-						IF brief(7)='1'THEN             --suppress Base
+					ELSE	
+						IF brief(7)='1'THEN		--suppress Base
 							set_suppress_base <= '1';
 						ELSIF exec(dispouter)='1' THEN
 							set(dispouter) <= '1';
@@ -2673,46 +3251,48 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 						END IF;
 						next_micro_state <= ld_229_1;
 					END IF;
-
+					
 				WHEN ld_AnXn2 =>
 					set(get_ea_now) <='1';
-					setdisp <= '1';             --brief
+					setdisp <= '1';		--brief
 					setnextpass <= '1';
-
--------------------------------------------------------------------------------------
-
-				WHEN ld_229_1 =>                -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
+					
+-------------------------------------------------------------------------------------					
+					
+				WHEN ld_229_1 =>		-- (bd,An,Xn)=>, --(bd,PC,Xn)=>
 					IF brief(5)='1' THEN    --Base Displacement
-						setdisp <= '1';         --add last_data_read
+						setdisp <= '1';		--add last_data_read
 					END IF;
 					IF brief(6)='0' AND brief(2)='0' THEN --Preindex or Index
 						set(briefext) <= '1';
 						setstate <= "01";
 						IF brief(1 downto 0)="00" THEN
 							next_micro_state <= ld_AnXn2;
-						ELSE
+						ELSE	
 							next_micro_state <= ld_229_2;
-						END IF;
+						END IF;	
 					ELSE
 						IF brief(1 downto 0)="00" THEN
 							set(get_ea_now) <='1';
 							setnextpass <= '1';
 						ELSE
-							setstate <= "10";
+							setstate <= "10";
+							setaddrvalue <= '1';
 							set(longaktion) <= '1';
 							next_micro_state <= ld_229_3;
 						END IF;
 					END IF;
-
-				WHEN ld_229_2 =>                -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
-					setdisp <= '1';             -- add Index
+					
+				WHEN ld_229_2 =>		-- (bd,An,Xn)=>, --(bd,PC,Xn)=>
+					setdisp <= '1';		-- add Index
 					setstate <= "10";
+					setaddrvalue <= '1';
 					set(longaktion) <= '1';
 					next_micro_state <= ld_229_3;
-
-				WHEN ld_229_3 =>                -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
+				
+				WHEN ld_229_3 =>		-- (bd,An,Xn)=>, --(bd,PC,Xn)=>
 					set_suppress_base <= '1';
-					set(dispouter) <= '1';
+					set(dispouter) <= '1'; 	
 					IF brief(1)='0' THEN --NULL Outer Displacement
 						setstate <= "01";
 					ELSE  --WORD Outer Displacement
@@ -2721,10 +3301,10 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 						END IF;
 					END IF;
 					next_micro_state <= ld_229_4;
-
-				WHEN ld_229_4 =>                -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
+				
+				WHEN ld_229_4 =>		-- (bd,An,Xn)=>, --(bd,PC,Xn)=>
 					IF brief(1)='1' THEN  -- Outer Displacement
-						setdisp <= '1';   --add last_data_read
+						setdisp <= '1';	  --add last_data_read
 					END IF;
 					IF brief(6)='0' AND brief(2)='1' THEN --Postindex
 						set(briefext) <= '1';
@@ -2734,25 +3314,25 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 						set(get_ea_now) <='1';
 						setnextpass <= '1';
 					END IF;
-
-----------------------------------------------------------------------------------------
-				WHEN st_dAn1 =>         -- =>d(An)
+					
+----------------------------------------------------------------------------------------				
+				WHEN st_dAn1 =>		-- =>d(An)
 					setstate <= "11";
-					setdisp <= '1';             --word
+					setdisp <= '1';		--word
 					next_micro_state <= nop;
-
-				WHEN st_AnXn1 =>                -- =>d(An,Xn)
+					
+				WHEN st_AnXn1 =>		-- =>d(An,Xn)
 					IF brief(8)='0' OR extAddr_Mode=0 OR (cpu(1)='0' AND extAddr_Mode=2) THEN
-						setdisp <= '1';         --byte
+						setdisp <= '1';		--byte	
 						setdispbyte <= '1';
 						setstate <= "01";
 						set(briefext) <= '1';
 						next_micro_state <= st_AnXn2;
-					ELSE
-						IF brief(7)='1'THEN             --suppress Base
+					ELSE	
+						IF brief(7)='1'THEN		--suppress Base
 							set_suppress_base <= '1';
---                                              ELSIF exec(dispouter)='1' THEN
---                                                      set(dispouter) <= '1';
+--						ELSIF exec(dispouter)='1' THEN
+--							set(dispouter) <= '1';
 						END IF;
 						IF brief(5)='0' THEN --NULL Base Displacement
 							setstate <= "01";
@@ -2763,26 +3343,27 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 						END IF;
 						next_micro_state <= st_229_1;
 					END IF;
-
+					
 				WHEN st_AnXn2 =>
 					setstate <= "11";
-					setdisp <= '1';             --brief
+					setdisp <= '1';		--brief	
+					set(hold_dwr) <= '1';
 					next_micro_state <= nop;
-
--------------------------------------------------------------------------------------
-
-				WHEN st_229_1 =>                -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
+					
+-------------------------------------------------------------------------------------					
+					
+				WHEN st_229_1 =>		-- (bd,An,Xn)=>, --(bd,PC,Xn)=>
 					IF brief(5)='1' THEN    --Base Displacement
-						setdisp <= '1';         --add last_data_read
+						setdisp <= '1';		--add last_data_read
 					END IF;
 					IF brief(6)='0' AND brief(2)='0' THEN --Preindex or Index
 						set(briefext) <= '1';
 						setstate <= "01";
 						IF brief(1 downto 0)="00" THEN
 							next_micro_state <= st_AnXn2;
-						ELSE
+						ELSE	
 							next_micro_state <= st_229_2;
-						END IF;
+						END IF;	
 					ELSE
 						IF brief(1 downto 0)="00" THEN
 							setstate <= "11";
@@ -2794,18 +3375,18 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 							next_micro_state <= st_229_3;
 						END IF;
 					END IF;
-
-				WHEN st_229_2 =>                -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
-					setdisp <= '1';             -- add Index
+					
+				WHEN st_229_2 =>		-- (bd,An,Xn)=>, --(bd,PC,Xn)=>
+					setdisp <= '1';		-- add Index
 					set(hold_dwr) <= '1';
 					setstate <= "10";
 					set(longaktion) <= '1';
 					next_micro_state <= st_229_3;
-
-				WHEN st_229_3 =>                -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
+				
+				WHEN st_229_3 =>		-- (bd,An,Xn)=>, --(bd,PC,Xn)=>
 					set(hold_dwr) <= '1';
 					set_suppress_base <= '1';
-					set(dispouter) <= '1';
+					set(dispouter) <= '1'; 	
 					IF brief(1)='0' THEN --NULL Outer Displacement
 						setstate <= "01";
 					ELSE  --WORD Outer Displacement
@@ -2814,11 +3395,11 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 						END IF;
 					END IF;
 					next_micro_state <= st_229_4;
-
-				WHEN st_229_4 =>                -- (bd,An,Xn)=>, --(bd,PC,Xn)=>
+				
+				WHEN st_229_4 =>		-- (bd,An,Xn)=>, --(bd,PC,Xn)=>
 					set(hold_dwr) <= '1';
 					IF brief(1)='1' THEN  -- Outer Displacement
-						setdisp <= '1';   --add last_data_read
+						setdisp <= '1';	  --add last_data_read
 					END IF;
 					IF brief(6)='0' AND brief(2)='1' THEN --Postindex
 						set(briefext) <= '1';
@@ -2828,54 +3409,181 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 						setstate <= "11";
 						next_micro_state <= nop;
 					END IF;
-
-----------------------------------------------------------------------------------------
-				WHEN bra1 =>            --bra
+					
+----------------------------------------------------------------------------------------				
+				WHEN bra1 =>		--bra
 					IF exe_condition='1' THEN
-						TG68_PC_brw <= '1';     --pc+0000
+						TG68_PC_brw <= '1';	--pc+0000
 						next_micro_state <= nop;
-						skipFetch <= '1';
+						skipFetch <= '1';	
 					END IF;
-
-				WHEN bsr1 =>            --bsr short
-					TG68_PC_brw <= '1';
+					
+				WHEN bsr1 =>		--bsr short
+					TG68_PC_brw <= '1';	
 					next_micro_state <= nop;
-
-				WHEN bsr2 =>            --bsr
-					IF long_start='0' THEN
-						TG68_PC_brw <= '1';
+					
+				WHEN bsr2 =>		--bsr
+					IF long_start='0' THEN	
+						TG68_PC_brw <= '1';	
 					END IF;
-					skipFetch <= '1';
+					skipFetch <= '1';	
 					set(longaktion) <= '1';
 					writePC <= '1';
 					setstate <= "11";
 					next_micro_state <= nopnop;
 					setstackaddr <='1';
-				WHEN nopnop =>          --bsr
+				WHEN nopnop =>		--bsr
 					next_micro_state <= nop;
 
-				WHEN dbcc1 =>           --dbcc
+				WHEN dbcc1 =>		--dbcc
 					IF exe_condition='0' THEN
 						Regwrena_now <= '1';
 						IF c_out(1)='1' THEN
-							skipFetch <= '1';
+							skipFetch <= '1';				
 							next_micro_state <= nop;
-							TG68_PC_brw <= '1';
-						END IF;
-					END IF;
-
-				WHEN movem1 =>          --movem
+							TG68_PC_brw <= '1';	
+						END IF;	
+					END IF;
+
+				WHEN chk20 =>			--if C is set -> signed compare
+					set(ea_data_OP1) <= '1';
+					set(addsub) <= '1';
+					set(alu_exec) <= '1';
+					set(alu_setFlags) <= '1';
+					setstate <="01";
+					next_micro_state <= chk21;
+				WHEN chk21 =>			-- check lower bound
+					dest_2ndHbits <= '1';
+					IF sndOPC(15)='1' THEN
+						set_datatype <="10";	--long
+						dest_LDRareg <= '1';
+						IF opcode(10 downto 9)="00" THEN
+							set(opcEXTB) <= '1';
+						END IF;
+					END IF;
+					set(addsub) <= '1';
+					set(alu_exec) <= '1';
+					set(alu_setFlags) <= '1';
+					setstate <="01";
+					next_micro_state <= chk22;
+				WHEN chk22 =>			--check upper bound
+					dest_2ndHbits <= '1';
+					set(ea_data_OP2) <= '1';
+					IF sndOPC(15)='1' THEN
+						set_datatype <="10";	--long
+						dest_LDRareg <= '1';
+					END IF;
+					set(addsub) <= '1';
+					set(alu_exec) <= '1';
+					set(opcCHK2) <= '1';
+					set(opcEXTB) <= exec(opcEXTB);
+					IF sndOPC(11)='1' THEN
+						setstate <="01";
+						next_micro_state <= chk23;
+					END IF;
+				WHEN chk23 =>
+						setstate <="01";
+						next_micro_state <= chk24;
+				WHEN chk24 =>
+					IF Flags(0)='1'THEN
+						trapmake <= '1';
+					END IF;
+					
+					
+				WHEN cas1 =>
+						setstate <="01";
+						next_micro_state <= cas2;
+				WHEN cas2 =>
+					source_2ndMbits <= '1';
+					IF Flags(2)='1'THEN
+						setstate<="11";
+						set(write_reg) <= '1';
+						set(restore_ADDR) <= '1';
+						next_micro_state <= nop;
+					ELSE
+						set(Regwrena) <= '1';
+						set(ea_data_OP2) <='1';
+						dest_2ndLbits <= '1';
+						set(alu_move) <= '1';
+					END IF;
+					
+				WHEN cas21 =>
+					dest_2ndHbits <= '1';
+					dest_LDRareg <= sndOPC(15);
+					set(get_ea_now) <='1';
+					next_micro_state <= cas22;
+				WHEN cas22 =>
+					setstate <= "01";
+					source_2ndLbits <= '1';
+					set(ea_data_OP1) <= '1';
+					set(addsub) <= '1';
+					set(alu_exec) <= '1';
+					set(alu_setFlags) <= '1';
+					next_micro_state <= cas23;
+				WHEN cas23 =>
+					dest_LDRHbits <= '1';
+					set(get_ea_now) <='1';
+					next_micro_state <= cas24;
+				WHEN cas24 =>
+					IF Flags(2)='1'THEN
+						set(alu_setFlags) <= '1';
+					END IF;
+					setstate <="01";
+					set(hold_dwr) <= '1';
+					source_LDRLbits <= '1';
+					set(ea_data_OP1) <= '1';
+					set(addsub) <= '1';
+					set(alu_exec) <= '1';
+					next_micro_state <= cas25;
+				WHEN cas25 =>
+					setstate <= "01";
+					set(hold_dwr) <= '1';
+					next_micro_state <= cas26;
+				WHEN cas26 =>
+					IF Flags(2)='1'THEN -- write Update 1 to Destination 1
+						source_2ndMbits <= '1';
+						set(write_reg) <= '1';
+						dest_2ndHbits <= '1';
+						dest_LDRareg <= sndOPC(15);
+						setstate <= "11";
+						set(get_ea_now) <='1';
+						next_micro_state <= cas27;
+					ELSE		   			-- write Destination 2 to Compare 2 first
+						set(hold_dwr) <= '1';
+						set(hold_OP2) <='1';
+						dest_LDRLbits <= '1';
+						set(alu_move) <= '1';
+						set(Regwrena) <= '1';
+						set(ea_data_OP2) <='1';
+						next_micro_state <= cas28;
+					END IF;
+				WHEN cas27 =>				-- write Update 2 to Destination 2
+					source_LDRMbits <= '1';
+					set(write_reg) <= '1';
+					dest_LDRHbits <= '1';
+					setstate <= "11";
+					set(get_ea_now) <='1';
+					next_micro_state <= nopnop;
+				WHEN cas28 =>				-- write Destination 1 to Compare 1 second
+					dest_2ndLbits <= '1';
+					set(alu_move) <= '1';
+					set(Regwrena) <= '1';
+					
+				WHEN movem1 =>		--movem
 					IF last_data_read(15 downto 0)/=X"0000" THEN
 						setstate <="01";
 						IF opcode(5 downto 3)="100" THEN
-							set(mem_addsub) <= '1';
+							set(mem_addsub) <= '1';
+							IF cpu(1)='1' THEN
+								set(Regwrena) <= '1';	--tg
+							END IF;
 						END IF;
 						next_micro_state <= movem2;
 					END IF;
-				WHEN movem2 =>          --movem
+				WHEN movem2 =>		--movem
 					IF movem_run='0' THEN
 						setstate <="01";
-					ELSE
+					ELSE	
 						set(movem_action) <= '1';
 						set(mem_addsub) <= '1';
 						next_micro_state <= movem2;
@@ -2885,53 +3593,96 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 						ELSE
 							setstate <="10";
 						END IF;
-					END IF;
+					END IF;	
 
-				WHEN andi =>            --andi
+				WHEN andi =>		--andi
 					IF opcode(5 downto 4)/="00" THEN
 						setnextpass <= '1';
 					END IF;
 
-				WHEN op_AxAy =>         -- op -(Ax),-(Ay)
-								set_direct_data <= '1';
+				WHEN pack1 =>		-- pack -(Ax),-(Ay)
+					IF opcode(2 downto 0)="111" THEN
+						set(use_SP) <= '1';
+					END IF;
+					set(hold_ea_data) <= '1';	
+					set(update_ld) <= '1';
+					setstate <= "10";
+					set(presub) <= '1';
+					next_micro_state <= pack2;
+					dest_areg <= '1';				
+				WHEN pack2 =>	
+					IF opcode(11 downto 9)="111" THEN
+						set(use_SP) <= '1';
+					END IF;
+					set(hold_ea_data) <= '1';	
+					set_direct_data <= '1';
+					IF opcode(7 downto 6) = "01" THEN	--pack
+						datatype <= "00";		--Byte
+					ELSE								--unpk
+						datatype <= "01";		--Word
+					END IF;
+					set(presub) <= '1';
+					dest_hbits <= '1'; 
+					dest_areg <= '1';
+					setstate <= "10";
+					next_micro_state <= pack3;
+				WHEN pack3 =>	
+					skipFetch <= '1';
+					
+				WHEN op_AxAy =>		-- op -(Ax),-(Ay)
+					IF opcode(11 downto 9)="111" THEN
+						set(use_SP) <= '1';
+					END IF;
+					set_direct_data <= '1';
 					set(presub) <= '1';
-					dest_hbits <= '1';
+					dest_hbits <= '1'; 
 					dest_areg <= '1';
 					setstate <= "10";
 
-				WHEN cmpm =>            -- cmpm (Ay)+,(Ax)+
+				WHEN cmpm =>		-- cmpm (Ay)+,(Ax)+
+					IF opcode(11 downto 9)="111" THEN
+						set(use_SP) <= '1';
+					END IF;
 					set_direct_data <= '1';
 					set(postadd) <= '1';
-					dest_hbits <= '1';
+					dest_hbits <= '1'; 
 					dest_areg <= '1';
 					setstate <= "10";
-
-				WHEN link1 =>           -- link
+					
+				WHEN link1 =>		-- link
 					setstate <="11";
 					source_areg <= '1';
 					set(opcMOVE) <= '1';
 					set(Regwrena) <= '1';
 					next_micro_state <= link2;
-				WHEN link2 =>           -- link
+				WHEN link2 =>		-- link
 					setstackaddr <='1';
 					set(ea_data_OP2) <= '1';
-
-				WHEN unlink1 =>         -- unlink
+					
+				WHEN unlink1 =>		-- unlink
 					setstate <="10";
 					setstackaddr <='1';
 					set(postadd) <= '1';
 					next_micro_state <= unlink2;
-				WHEN unlink2 =>         -- unlink
-					set(ea_data_OP2) <= '1';
-
-				WHEN trap0 =>           -- TRAP
+				WHEN unlink2 =>		-- unlink
+					set(ea_data_OP2) <= '1';
+					
+-- paste and copy form TH	---------	
+				WHEN trap00 =>          -- TRAP format #2
+					next_micro_state <= trap0;
+					set(presub) <= '1';
+					setstackaddr <='1';
+					setstate <= "11";
+					datatype <= "10";
+------------------------------------
+				WHEN trap0 =>		-- TRAP
 					set(presub) <= '1';
 					setstackaddr <='1';
 					setstate <= "11";
-					IF VBR_Stackframe=1 OR (cpu(0)='1' AND VBR_Stackframe=2) THEN       --68010
+					IF use_VBR_Stackframe='1' THEN	--68010
 						set(writePC_add) <= '1';
 						datatype <= "01";
---                                              set_datatype <= "10";
+--						set_datatype <= "10";
 						next_micro_state <= trap1;
 					ELSE
 						IF trap_interrupt='1' OR trap_trace='1' OR trap_berr='1' THEN
@@ -2939,8 +3690,9 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 						END IF;
 						datatype <= "10";
 						next_micro_state <= trap2;
-					END IF;
-				WHEN trap1 =>           -- TRAP
+					END IF;
+
+				WHEN trap1 =>		-- TRAP
 					IF trap_interrupt='1' OR trap_trace='1' THEN
 						writePC <= '1';
 					END IF;
@@ -2949,59 +3701,69 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 					setstate <= "11";
 					datatype <= "10";
 					next_micro_state <= trap2;
-				WHEN trap2 =>           -- TRAP
+				WHEN trap2 =>		-- TRAP
 					set(presub) <= '1';
 					setstackaddr <='1';
 					setstate <= "11";
 					datatype <= "01";
 					writeSR <= '1';
-					IF trap_berr='1' THEN
-						next_micro_state <= trap4;
+					IF trap_berr='1' THEN
+						next_micro_state <= trap4;
 					ELSE
- 						next_micro_state <= trap3;
+						next_micro_state <= trap3;
 					END IF;
-				WHEN trap3 =>           -- TRAP
+				WHEN trap3 =>		-- TRAP
 					set_vectoraddr <= '1';
 					datatype <= "10";
-					set(direct_delta) <= '1';
+					set(direct_delta) <= '1';	
 					set(directPC) <= '1';
-					setstate <= "10";
-					next_micro_state <= nopnop;
-				WHEN trap4 =>		-- TRAP
-					set(presub) <= '1';
-					setstackaddr <='1';
-					setstate <= "11";
-					datatype <= "01";
-					writeSR <= '1';
-					next_micro_state <= trap5;
-				WHEN trap5 =>		-- TRAP
-					set(presub) <= '1';
-					setstackaddr <='1';
-					setstate <= "11";
-					datatype <= "10";
-					writeSR <= '1';
-					next_micro_state <= trap6;
-				WHEN trap6 =>		-- TRAP
-					set(presub) <= '1';
-					setstackaddr <='1';
-					setstate <= "11";
-					datatype <= "01";
-					writeSR <= '1';
-					next_micro_state <= trap3;
-                                WHEN rte1 =>            -- RTE
+					setstate <= "10";
+					next_micro_state <= nopnop;
+				WHEN trap4 =>		-- TRAP
+					set(presub) <= '1';
+					setstackaddr <='1';
+					setstate <= "11";
+					datatype <= "01";
+					writeSR <= '1';
+					next_micro_state <= trap5;
+				WHEN trap5 =>		-- TRAP
+					set(presub) <= '1';
+					setstackaddr <='1';
+					setstate <= "11";
+					datatype <= "10";
+					writeSR <= '1';
+					next_micro_state <= trap6;
+				WHEN trap6 =>		-- TRAP
+					set(presub) <= '1';
+					setstackaddr <='1';
+					setstate <= "11";
+					datatype <= "01";
+					writeSR <= '1';
+					next_micro_state <= trap3;
+					
+										-- return from exception - RTE
+										-- fetch PC and status register from stack
+										-- 010+ fetches another word containing
+										-- the 12 bit vector offset and the
+										-- frame format. If the frame format is
+										-- 2 another two words have to be taken
+										-- from the stack
+				WHEN rte1 =>		-- RTE
 					datatype <= "10";
 					setstate <= "10";
 					set(postadd) <= '1';
 					setstackaddr <= '1';
-					IF VBR_Stackframe=0 OR (cpu(0)='0' AND VBR_Stackframe=2) THEN
-						set(direct_delta) <= '1';
+					set(directPC) <= '1';	
+					IF use_VBR_Stackframe='0' OR opcode(2)='1' THEN	--opcode(2)='1' => opcode is RTR
+						set(update_FC) <= '1';
+						set(direct_delta) <= '1';	
 					END IF;
-					set(directPC) <= '1';
 					next_micro_state <= rte2;
-				WHEN rte2 =>            -- RTE
+				WHEN rte2 =>		-- RTE
 					datatype <= "01";
 					set(update_FC) <= '1';
-					IF VBR_Stackframe=1 OR (cpu(0)='1' AND VBR_Stackframe=2) THEN
+					IF use_VBR_Stackframe='1' AND opcode(2)='0' THEN
+												-- 010+ reads another word
 						setstate <= "10";
 						set(postadd) <= '1';
 						setstackaddr <= '1';
@@ -3009,31 +3771,59 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 					ELSE
 						next_micro_state <= nop;
 					END IF;
-				WHEN rte3 =>            -- RTE
-					next_micro_state <= nop;
---                                      set(update_FC) <= '1';
+--				WHEN rte3 =>			-- RTE
+--					next_micro_state <= nop;
+----					set(update_FC) <= '1';
+-- paste and copy form TH	---------	
+				when rte3 => -- RTE
+					setstate <= "01"; -- idle state to wait
+											-- for input data to
+											-- arrive
+					next_micro_state <= rte4;
+				WHEN rte4 =>         -- RTE
+											-- check for stack frame format #2
+					if last_data_in(15 downto 12)="0010" then
+										  -- read another 32 bits in this case
+						setstate <= "10"; -- read
+						datatype <= "10"; -- long word
+						set(postadd) <= '1';
+						setstackaddr <= '1';
+						next_micro_state <= rte5;
+					else
+						datatype <= "01";
+						next_micro_state <= nop;
+					end if;
+				WHEN rte5 =>            -- RTE
+					next_micro_state <= nop;
+-------------------------------------
 
-				WHEN movec1 =>          -- MOVEC
+				WHEN rtd1 =>		-- RTD
+					next_micro_state <= rtd2;
+				WHEN rtd2 =>		-- RTD
+					setstackaddr <= '1';
+					set(Regwrena) <= '1';
+					
+				WHEN movec1 =>		-- MOVEC
 					set(briefext) <= '1';
 					set_writePCbig <='1';
-					IF (brief(11 downto 0)=X"000" OR brief(11 downto 0)=X"001" OR brief(11 downto 0)=X"800" OR brief(11 downto 0)=X"801") OR
+					IF (brief(11 downto 0)=X"000" OR brief(11 downto 0)=X"001" OR brief(11 downto 0)=X"800" OR brief(11 downto 0)=X"801") OR 
 					   (cpu(1)='1' AND (brief(11 downto 0)=X"002" OR brief(11 downto 0)=X"802" OR brief(11 downto 0)=X"803" OR brief(11 downto 0)=X"804")) THEN
 						IF opcode(0)='0' THEN
 							set(Regwrena) <= '1';
 						END IF;
---                                      ELSIF brief(11 downto 0)=X"800"OR brief(11 downto 0)=X"001" OR brief(11 downto 0)=X"000" THEN
---                                              trap_addr_error <= '1';
---                                              trapmake <= '1';
+--					ELSIF brief(11 downto 0)=X"800"OR brief(11 downto 0)=X"001" OR brief(11 downto 0)=X"000" THEN
+--						trap_addr_error <= '1';
+--						trapmake <= '1';
 					ELSE
 						trap_illegal <= '1';
 						trapmake <= '1';
 					END IF;
-
-				WHEN movep1 =>          -- MOVEP d(An)
-					setdisp <= '1';
-					set(mem_addsub) <= '1';
+					
+				WHEN movep1 =>		-- MOVEP d(An)
+					setdisp <= '1';	
+					set(mem_addsub) <= '1';	
 					set(mem_byte) <= '1';
-					set(OP1addr) <= '1';
+					set(OP1addr) <= '1';		
 					IF opcode(6)='1' THEN
 						set(movepl) <= '1';
 					END IF;
@@ -3043,10 +3833,10 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 						setstate <= "11";
 					END IF;
 					next_micro_state <= movep2;
-				WHEN movep2 =>
+				WHEN movep2 =>		
 					IF opcode(6)='1' THEN
-						set(mem_addsub) <= '1';
-						set(OP1addr) <= '1';
+						set(mem_addsub) <= '1';	
+					    set(OP1addr) <= '1';		
 					END IF;
 					IF opcode(7)='0' THEN
 						setstate <= "10";
@@ -3054,10 +3844,10 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 						setstate <= "11";
 					END IF;
 					next_micro_state <= movep3;
-				WHEN movep3 =>
+				WHEN movep3 =>		
 					IF opcode(6)='1' THEN
-						set(mem_addsub) <= '1';
-						set(OP1addr) <= '1';
+						set(mem_addsub) <= '1';	
+					    set(OP1addr) <= '1';		
 						set(mem_byte) <= '1';
 						IF opcode(7)='0' THEN
 							setstate <= "10";
@@ -3065,20 +3855,20 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 							setstate <= "11";
 						END IF;
 						next_micro_state <= movep4;
-					ELSE
-						datatype <= "01";               --Word
+					ELSE	
+						datatype <= "01";		--Word
 					END IF;
-				WHEN movep4 =>
+				WHEN movep4 =>		
 					IF opcode(7)='0' THEN
 						setstate <= "10";
 					ELSE
 						setstate <= "11";
 					END IF;
 					next_micro_state <= movep5;
-				WHEN movep5 =>
-					datatype <= "10";           --Long
-
-				WHEN mul1       =>              -- mulu
+				WHEN movep5 =>		
+					datatype <= "10";		--Long
+					
+				WHEN mul1	=>		-- mulu
 					IF opcode(15)='1' OR MUL_Mode=0 THEN
 						set_rot_cnt <= "001110";
 					ELSE
@@ -3086,44 +3876,48 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 					END IF;
 					setstate <="01";
 					next_micro_state <= mul2;
-				WHEN mul2       =>              -- mulu
-					setstate <="01";
+				WHEN mul2	=>		-- mulu
+					setstate <="01";
 					IF rot_cnt="00001" THEN
-						next_micro_state <= mul_end1;
-					ELSE
+						next_micro_state <= mul_end1;
+
+					ELSE	
 						next_micro_state <= mul2;
 					END IF;
-				WHEN mul_end1   =>              -- mulu
+				WHEN mul_end1	=>		-- mulu
+					IF opcode(15)='0' THEN
+						set(hold_OP2) <= '1';
+					END IF;
 					datatype <= "10";
 					set(opcMULU) <= '1';
 					IF opcode(15)='0' AND (MUL_Mode=1 OR MUL_Mode=2) THEN
 						dest_2ndHbits <= '1';
-						source_2ndLbits <= '1';--???
 						set(write_lowlong) <= '1';
 						IF sndOPC(10)='1' THEN
 							setstate <="01";
 							next_micro_state <= mul_end2;
-						END IF;
+						END IF;	
 						set(Regwrena) <= '1';
 					END IF;
 					datatype <= "10";
-				WHEN mul_end2   =>              -- divu
+				WHEN mul_end2	=>		-- divu
+					dest_2ndLbits <= '1';
 					set(write_reminder) <= '1';
 					set(Regwrena) <= '1';
 					set(opcMULU) <= '1';
 
-				WHEN div1       =>              -- divu
+				WHEN div1	=>		-- divu
 					setstate <="01";
 					next_micro_state <= div2;
-				WHEN div2       =>              -- divu
-					IF (OP2out(31 downto 16)=x"0000" OR opcode(15)='1' OR DIV_Mode=0) AND OP2out(15 downto 0)=x"0000" THEN              --div zero
+				WHEN div2	=>		-- divu
+					IF (OP2out(31 downto 16)=x"0000" OR opcode(15)='1' OR DIV_Mode=0) AND OP2out(15 downto 0)=x"0000" THEN		--div zero
 						set_Z_error <= '1';
 					ELSE
 						next_micro_state <= div3;
 					END IF;
-					set(ld_rot_cnt) <= '1';
+					set(ld_rot_cnt) <= '1'; 
 					setstate <="01";
-				WHEN div3       =>              -- divu
+				WHEN div3	=>		-- divu
 					IF opcode(15)='1' OR DIV_Mode=0 THEN
 						set_rot_cnt <= "001101";
 					ELSE
@@ -3131,64 +3925,44 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 					END IF;
 					setstate <="01";
 					next_micro_state <= div4;
-				WHEN div4       =>              -- divu
+				WHEN div4	=>		-- divu
 					setstate <="01";
 					IF rot_cnt="00001" THEN
 						next_micro_state <= div_end1;
-					ELSE
+					ELSE	
 						next_micro_state <= div4;
 					END IF;
-				WHEN div_end1   =>              -- divu
+				WHEN div_end1	=>		-- divu
+					IF z_error='0' AND set_V_Flag='0' THEN
+						set(Regwrena) <= '1';
+					END IF;
 					IF opcode(15)='0' AND (DIV_Mode=1 OR DIV_Mode=2) THEN
+						dest_2ndLbits <= '1';
 						set(write_reminder) <= '1';
 						next_micro_state <= div_end2;
 						setstate <="01";
 					END IF;
 					set(opcDIVU) <= '1';
 					datatype <= "10";
-				WHEN div_end2   =>              -- divu
+				WHEN div_end2	=>		-- divu
+					IF exec(Regwrena)='1' THEN
+						set(Regwrena) <= '1';
+					ELSE	
+						set(no_Flags) <= '1';
+					END IF;
 					dest_2ndHbits <= '1';
-					source_2ndLbits <= '1';--???
 					set(opcDIVU) <= '1';
-
-				WHEN rota1      =>
+					
+				WHEN rota1	=>
 					IF OP2out(5 downto 0)/="000000" THEN
 						set_rot_cnt <= OP2out(5 downto 0);
 					ELSE
 						set_exec(rot_nop) <= '1';
 					END IF;
-
+					
 				WHEN bf1 =>
 					setstate <="10";
-
-        when pack1 =>
-          -- result computation
-          IF opcode(7 downto 6) = "10" THEN -- UNPK reads a byte
-            datatype <= "00"; -- Byte
-          END IF;
-          set(ea_data_OP2) <= '1';
-          set(opcPACK) <= '1';
-          next_micro_state <= pack2;
-
-        when pack2 =>
-          -- write result
-          IF opcode(7 downto 6) = "01" THEN -- PACK writes a byte
-            datatype <= "00";
-          END IF;
-          set(presub) <= '1';
-          setstate <= "11";
-          dest_hbits <= '1'; 
-          dest_areg <= '1';
-          next_micro_state <= pack3;
-
-          when pack3 =>
-            -- this is just to keep datatype == 00
-            -- for byte writes
-            -- write result
-            IF opcode(7 downto 6) = "01" THEN -- PACK writes a byte
-              datatype <= "00";
-            END IF;
-
+	
 				WHEN OTHERS => NULL;
 			END CASE;
 	END PROCESS;
@@ -3196,33 +3970,41 @@ PROCESS (clk, cpu, OP1out, OP2out, opcode, exe_condition, nextpass, micro_state,
 -----------------------------------------------------------------------------
 -- MOVEC
 -----------------------------------------------------------------------------
-PROCESS (clk, VBR, CACR, brief)
-	BEGIN
-		IF rising_edge(clk) THEN
-			IF Reset = '1' THEN
-				VBR <= (OTHERS => '0');
-				CACR <= (OTHERS => '0');
-			ELSIF clkena_lw='1' AND exec(movec_wr)='1' THEN
-				CASE brief(11 downto 0) IS
-					WHEN X"002" => CACR <= reg_QA(3 downto 0);
-					WHEN X"801" => VBR <= reg_QA;
-					WHEN OTHERS => NULL;
-				END CASE;
-			END IF;
-		END IF;
-		movec_data <= (OTHERS=>'0');
-		CASE brief(11 downto 0) IS
-                        WHEN X"002" => movec_data <= "0000000000000000000000000000" & (CACR AND "0011");
-			WHEN X"801" => --IF VBR_Stackframe=1 OR (cpu(0)='1' AND VBR_Stackframe=2) THEN
-								movec_data <= VBR;
-						   --END IF;
-			WHEN OTHERS => NULL;
-		END CASE;
-	END PROCESS;
-
-  CACR_out <= CACR;
-  VBR_out <= VBR;
-
+  process (clk, VBR, CACR, brief)
+  begin
+	-- all other hexa codes should give illegal isntruction exception
+	if rising_edge(clk) then
+	  if Reset = '1' then
+		VBR <= (others => '0');
+		CACR <= (others => '0');
+	  elsif clkena_lw = '1' and exec(movec_wr) = '1' then
+		case brief(11 downto 0) is
+		  when X"000" => NULL; -- SFC -- 68010+
+		  when X"001" => NULL; -- DFC -- 68010+
+		  when X"002" => CACR <= reg_QA(3 downto 0); -- 68020+
+		  when X"800" => NULL; -- USP -- 68010+
+		  when X"801" => VBR <= reg_QA; -- 68010+
+		  when X"802" => NULL; -- CAAR -- 68020+
+		  when X"803" => NULL; -- MSP -- 68020+
+		  when X"804" => NULL; -- isP -- 68020+
+		  when others => NULL;
+		end case;
+	  end if;
+	end if;
+
+	movec_data <= (others => '0');
+	case brief(11 downto 0) is
+	  when X"002" => movec_data <= "0000000000000000000000000000" & (CACR AND "0011");
+
+	  when X"801" => 
+		movec_data <= VBR;
+		--end if;
+	  when others => NULL;
+	end case;
+  end process;
+
+  CACR_out <= CACR;
+  VBR_out <= VBR;
 -----------------------------------------------------------------------------
 -- Conditions
 -----------------------------------------------------------------------------
@@ -3248,7 +4030,7 @@ PROCESS (exe_opcode, Flags)
 			WHEN OTHERS => NULL;
 		END CASE;
 	END PROCESS;
-
+	
 -----------------------------------------------------------------------------
 -- Movem
 -----------------------------------------------------------------------------
@@ -3256,7 +4038,7 @@ PROCESS (clk)
 	BEGIN
 		IF rising_edge(clk) THEN
 			IF clkena_lw='1' THEN
-				movem_actiond <= exec(movem_action);
+				movem_actiond <= exec(movem_action); 
 				IF decodeOPC='1' THEN
 					sndOPC <= data_read(15 downto 0);
 				ELSIF exec(movem_action)='1' OR set(movem_action) ='1' THEN
@@ -3283,7 +4065,7 @@ PROCESS (clk)
 			END IF;
 		END IF;
 	END PROCESS;
-
+	
 PROCESS (sndOPC, movem_mux)
 	BEGIN
 		movem_regaddr <="0000";
@@ -3311,99 +4093,11 @@ PROCESS (sndOPC, movem_mux)
 			movem_regaddr(1) <= '1';
 			IF movem_mux(2)='0' THEN
 				movem_regaddr(0) <= '1';
-			END IF;
-		ELSE
+			END IF;	
+		ELSE		
 			IF movem_mux(0)='0' THEN
 				movem_regaddr(0) <= '1';
-			END IF;
+			END IF;	
 		END  IF;
 	END PROCESS;
-
-	exec_d.opcMOVE        <= exec(opcMOVE);
-	exec_d.opcMOVEQ       <= exec(opcMOVEQ);
-	exec_d.opcMOVESR      <= exec(opcMOVESR);
-	exec_d.opcADD         <= exec(opcADD);
-	exec_d.opcADDQ        <= exec(opcADDQ);
-	exec_d.opcOR          <= exec(opcOR);
-	exec_d.opcAND         <= exec(opcAND);
-	exec_d.opcEOR         <= exec(opcEOR);
-	exec_d.opcCMP         <= exec(opcCMP);
-	exec_d.opcROT         <= exec(opcROT);
-	exec_d.opcCPMAW       <= exec(opcCPMAW);
-	exec_d.opcEXT         <= exec(opcEXT);
-	exec_d.opcABCD        <= exec(opcABCD);
-	exec_d.opcSBCD        <= exec(opcSBCD);
-	exec_d.opcBITS        <= exec(opcBITS);
-	exec_d.opcSWAP        <= exec(opcSWAP);
-	exec_d.opcScc         <= exec(opcScc);
-	exec_d.andiSR         <= exec(andiSR);
-	exec_d.eoriSR         <= exec(eoriSR);
-	exec_d.oriSR          <= exec(oriSR);
-	exec_d.opcMULU        <= exec(opcMULU);
-	exec_d.opcDIVU        <= exec(opcDIVU);
-	exec_d.dispouter      <= exec(dispouter);
-	exec_d.rot_nop        <= exec(rot_nop);
-	exec_d.ld_rot_cnt     <= exec(ld_rot_cnt);
-	exec_d.writePC_add    <= exec(writePC_add);
-	exec_d.ea_data_OP1    <= exec(ea_data_OP1);
-	exec_d.ea_data_OP2    <= exec(ea_data_OP2);
-	exec_d.use_XZFlag     <= exec(use_XZFlag);
-	exec_d.get_bfoffset   <= exec(get_bfoffset);
-	exec_d.save_memaddr   <= exec(save_memaddr);
-	exec_d.opcCHK         <= exec(opcCHK);
-	exec_d.movec_rd       <= exec(movec_rd);
-	exec_d.movec_wr       <= exec(movec_wr);
-	exec_d.Regwrena       <= exec(Regwrena);
-	exec_d.update_FC      <= exec(update_FC);
-	exec_d.linksp         <= exec(linksp);
-	exec_d.movepl         <= exec(movepl);
-	exec_d.update_ld      <= exec(update_ld);
-	exec_d.OP1addr        <= exec(OP1addr);
-	exec_d.write_reg      <= exec(write_reg);
-	exec_d.changeMode     <= exec(changeMode);
-	exec_d.ea_build       <= exec(ea_build);
-	exec_d.trap_chk       <= exec(trap_chk);
-	exec_d.store_ea_data  <= exec(store_ea_data);
-	exec_d.addrlong       <= exec(addrlong);
-	exec_d.postadd        <= exec(postadd);
-	exec_d.presub         <= exec(presub);
-	exec_d.subidx         <= exec(subidx);
-	exec_d.no_Flags       <= exec(no_Flags);
-	exec_d.use_SP         <= exec(use_SP);
-	exec_d.to_CCR         <= exec(to_CCR);
-	exec_d.to_SR          <= exec(to_SR);
-	exec_d.OP2out_one     <= exec(OP2out_one);
-	exec_d.OP1out_zero    <= exec(OP1out_zero);
-	exec_d.mem_addsub     <= exec(mem_addsub);
-	exec_d.addsub         <= exec(addsub);
-	exec_d.directPC       <= exec(directPC);
-	exec_d.direct_delta   <= exec(direct_delta);
-	exec_d.directSR       <= exec(directSR);
-	exec_d.directCCR      <= exec(directCCR);
-	exec_d.exg            <= exec(exg);
-	exec_d.get_ea_now     <= exec(get_ea_now);
-	exec_d.ea_to_pc       <= exec(ea_to_pc);
-	exec_d.hold_dwr       <= exec(hold_dwr);
-	exec_d.to_USP         <= exec(to_USP);
-	exec_d.from_USP       <= exec(from_USP);
-	exec_d.write_lowlong  <= exec(write_lowlong);
-	exec_d.write_reminder <= exec(write_reminder);
-	exec_d.movem_action   <= exec(movem_action);
-	exec_d.briefext       <= exec(briefext);
-	exec_d.get_2ndOPC     <= exec(get_2ndOPC);
-	exec_d.mem_byte       <= exec(mem_byte);
-	exec_d.longaktion     <= exec(longaktion);
-	exec_d.opcRESET       <= exec(opcRESET);
-	exec_d.opcBF          <= exec(opcBF);
-	exec_d.opcBFwb        <= exec(opcBFwb);
-	exec_d.s2nd_hbits     <= exec(s2nd_hbits);
-
---When the instruction has completed, the decremented address
---register contains the address of the last operand stored. For
---the MC68020, MC68030, and MC68040, if the addressing
---register is also moved to memory, the value written is the
---initial register value decremented by the size of the oper-
---ation. The MC68000 writes the initial register value
---(not decremented).
-
-END;
+END; 
diff --git a/cores/plus_too/addrController_top.v b/cores/plus_too/addrController_top.v
index 1c4d561..d2fe0bd 100644
--- a/cores/plus_too/addrController_top.v
+++ b/cores/plus_too/addrController_top.v
@@ -1,7 +1,9 @@
 module addrController_top(
 	// clocks:
-	input clk8,						// 8.125 MHz CPU clock
-	
+	input clk,
+	input clk8_en_p, // 8.125 MHz CPU clock enables
+	input clk8_en_n,
+
 	// system config:
 	input turbo,               // 0 = normal, 1 = faster
 	input configROMSize,			// 0 = 64K ROM, 1 = 128K ROM
@@ -60,12 +62,12 @@ module addrController_top(
 	reg [19:0] snd_div;
 	
 	reg sndReadAckD;
-	always @(negedge clk8)
-		sndReadAckD <= sndReadAck;
+	always @(posedge clk)
+		if (clk8_en_n) sndReadAckD <= sndReadAck;
 	
 	reg vblankD, vblankD2;
-	always @(posedge clk8) begin
-		if(sndReadAckD) begin
+	always @(posedge clk) begin
+		if(clk8_en_p && sndReadAckD) begin
 			vblankD <= _vblank;
 			vblankD2 <= vblankD;
 		
@@ -82,24 +84,24 @@ module addrController_top(
 			end
 		end
 	end
-	
+
 	assign dioBusControl = extraBusControl;
 
 	// interleaved RAM access for CPU and video
 	reg [1:0] busCycle;
 	reg [1:0] extra_slot_count;
 	reg [1:0] subCycle;
-	
-	always @(posedge clk8)
-		busCycle <= busCycle + 2'd1;
-		
+
+	always @(posedge clk)
+		if (clk8_en_p) busCycle <= busCycle + 2'd1;
+
 	reg extra_slot_advance;
-	always @(negedge clk8)
-		extra_slot_advance <= (busCycle == 2'b11);
-	
+	always @(posedge clk)
+		if (clk8_en_n) extra_slot_advance <= (busCycle == 2'b11);
+
 	// allocate memory slots in the extra cycle
-	always @(posedge clk8) begin
-		if(extra_slot_advance) begin
+	always @(posedge clk) begin
+		if(clk8_en_p && extra_slot_advance) begin
 			extra_slot_count <= extra_slot_count + 2'd1;
 			
 			// the subcycle counter counts 0-1-2-0-1-2 and is used to give
@@ -194,7 +196,8 @@ module addrController_top(
 
 	// video
 	videoTimer vt(
-		.clk8(clk8), 
+		.clk(clk),
+		.clk_en(clk8_en_p),
 		.busCycle(busCycle), 
 		.videoAddr(videoAddr), 
 		.hsync(hsync), 
diff --git a/cores/plus_too/dataController_top.v b/cores/plus_too/dataController_top.v
index 5eab83f..c50792e 100644
--- a/cores/plus_too/dataController_top.v
+++ b/cores/plus_too/dataController_top.v
@@ -2,6 +2,8 @@ module dataController_top(
 	// clocks:
 	input clk32,					// 32.5 MHz pixel clock
 	output clk8,						// 8.125 MHz CPU clock
+	output clk8_en_p,
+	output clk8_en_n,
 	
 	// system control:
 	input _systemReset,
@@ -60,6 +62,8 @@ module dataController_top(
 	input [1:0] insertDisk,
 	input [1:0] diskSides,
 	output [1:0] diskEject,
+	output [1:0] diskMotor,
+	output [1:0] diskAct,
 
 	output [21:0] dskReadAddrInt,
 	input dskReadAckInt,
@@ -67,14 +71,16 @@ module dataController_top(
 	input dskReadAckExt,
 
 	// connections to io controller
-   output [31:0] io_lba,
-   output 	     io_rd,
-   output 	     io_wr,
-   input 	     io_ack,
-   input [7:0]   io_din,
-   input 	     io_din_strobe,
-   output [7:0]  io_dout,
-   input 	     io_dout_strobe
+	input   [1:0] img_mounted,
+	input  [31:0] img_size,
+	output [31:0] io_lba,
+	output  [1:0] io_rd,
+	output  [1:0] io_wr,
+	input         io_ack,
+	input   [8:0] sd_buff_addr,
+	input   [7:0] sd_buff_dout,
+	output  [7:0] sd_buff_din,
+	input         sd_buff_wr
 );
 	
 	// add binary volume levels according to volume setting
@@ -89,13 +95,13 @@ module dataController_top(
 	wire [10:0] audio_x4 = {    audio_latch[7]  , audio_latch, 2'b00};
 	
 	reg loadSoundD;
-	always @(negedge clk8)
-		loadSoundD <= loadSound;
+	always @(posedge clk32)
+		if (clk8_en_n) loadSoundD <= loadSound;
 
 	// read audio data and convert to signed for further volume adjustment
 	reg [7:0] audio_latch;
-	always @(posedge clk8) begin
-		if(loadSoundD) begin
+	always @(posedge clk32) begin
+		if(clk8_en_p && loadSoundD) begin
 			if(snd_ena) audio_latch <= 8'h00;
 			else  	 	audio_latch <= memoryDataIn[15:8] - 8'd128;
 		end
@@ -106,6 +112,8 @@ module dataController_top(
 	always @(posedge clk32)
 		clkPhase <= clkPhase + 2'd1;
 	assign clk8 = clkPhase[1];
+	assign clk8_en_p = clkPhase == 2'b01;
+	assign clk8_en_n = clkPhase == 2'b11;
 	
 	// CPU reset generation
 	// For initial CPU reset, RESET and HALT must be asserted for at least 100ms = 800,000 clocks of clk8
@@ -117,11 +125,11 @@ module dataController_top(
 		resetDelay <= 20'hFFFFF;
 	end
 	
-	always @(posedge clk8 or negedge _systemReset) begin
+	always @(posedge clk32 or negedge _systemReset) begin
 		if (_systemReset == 1'b0) begin
 			resetDelay <= 20'hFFFFF;
 		end
-		else if (isResetting) begin
+		else if (clk8_en_p && isResetting) begin
 			resetDelay <= resetDelay - 1'b1;
 		end
 	end
@@ -154,36 +162,41 @@ module dataController_top(
 	
 	// Memory-side
 	assign memoryDataOut = cpuDataIn;
-	
+
 	// SCSI
 	ncr5380 scsi(
-		.sysclk(clk8),
-      .reset(!_cpuReset),
-      .bus_cs(selectSCSI && cpuBusControl),
-      .bus_we(!_cpuRW),
-      .bus_rs(cpuAddrRegMid),
-      .dack(cpuAddrRegHi[0]),   // A9
-      .wdata(cpuDataIn[15:8]),
-      .rdata(scsiDataOut),
+		.clk(clk32),
+		.ce(clk8_en_p),
+		.reset(!_cpuReset),
+		.bus_cs(selectSCSI && cpuBusControl),
+		.bus_we(!_cpuRW),
+		.bus_rs(cpuAddrRegMid),
+		.dack(cpuAddrRegHi[0]),   // A9
+		.wdata(cpuDataIn[15:8]),
+		.rdata(scsiDataOut),
 
 		// connections to io controller
+		.img_mounted( img_mounted ),
+		.img_size( img_size ),
 		.io_lba ( io_lba ),
 		.io_rd ( io_rd ),
 		.io_wr ( io_wr ),
 		.io_ack ( io_ack ),
-		.io_din ( io_din ),
-		.io_din_strobe ( io_din_strobe ),
-		.io_dout ( io_dout ),
-		.io_dout_strobe ( io_dout_strobe )
+
+		.sd_buff_addr(sd_buff_addr),
+		.sd_buff_dout(sd_buff_dout),
+		.sd_buff_din(sd_buff_din),
+		.sd_buff_wr(sd_buff_wr)
 	);
 
-	
 	// VIA
 	wire [2:0] snd_vol;
 	wire snd_ena;
 	
 	via v(
-		.clk8(clk8),
+		.clk32(clk32),
+		.clk8_en_p(clk8_en_p),
+		.clk8_en_n(clk8_en_n),
 		._reset(_cpuReset),
 		.selectVIA(selectVIA && cpuBusControl),
 		._cpuRW(_cpuRW),
@@ -213,7 +226,9 @@ module dataController_top(
 		
 	// IWM
 	iwm i(
-		.clk8(clk8),
+		.clk(clk32),
+		.cep(clk8_en_p),
+		.cen(clk8_en_n),
 		._reset(_cpuReset),
 		.selectIWM(selectIWM && cpuBusControl),
 		._cpuRW(_cpuRW),
@@ -225,7 +240,9 @@ module dataController_top(
 		.insertDisk(insertDisk),
 		.diskSides(diskSides),
 		.diskEject(diskEject),
-		
+		.diskMotor(diskMotor),
+		.diskAct(diskAct),
+
 		.dskReadAddrInt(dskReadAddrInt),
 		.dskReadAckInt(dskReadAckInt),
 		.dskReadAddrExt(dskReadAddrExt),
@@ -235,14 +252,16 @@ module dataController_top(
 
 	// SCC
 	scc s(
-		.sysclk(clk8),
-	   .reset_hw(~_cpuReset),
-	   .cs(selectSCC && (_cpuLDS == 1'b0 || _cpuUDS == 1'b0) && cpuBusControl),
-	   .we(!_cpuRW),
-	   .rs(cpuAddrRegLo), 
-	   .wdata(cpuDataIn[15:8]),
-	   .rdata(sccDataOut),
-	   ._irq(_sccIrq),
+		.clk(clk32),
+		.cep(clk8_en_p),
+		.cen(clk8_en_n),
+		.reset_hw(~_cpuReset),
+		.cs(selectSCC && (_cpuLDS == 1'b0 || _cpuUDS == 1'b0) && cpuBusControl),
+		.we(!_cpuRW),
+		.rs(cpuAddrRegLo), 
+		.wdata(cpuDataIn[15:8]),
+		.rdata(sccDataOut),
+		._irq(_sccIrq),
 		.dcd_a(mouseX1),
 		.dcd_b(mouseY1),
 		.wreq(sccWReq));
@@ -257,7 +276,8 @@ module dataController_top(
 	
 	// Mouse
 	ps2_mouse mouse(
-		.sysclk(clk8),
+		.sysclk(clk32),
+		.clk_en(clk8_en_p),
 		.reset(~_cpuReset),
 		.ps2dat(mouseData),
 		.ps2clk(mouseClk),
@@ -267,14 +287,15 @@ module dataController_top(
 		.y2(mouseY2),
 		.button(mouseButton));
 
-   wire [7:0] kbd_in_data;
+	wire [7:0] kbd_in_data;
 	wire kbd_in_strobe;
-   wire [7:0] kbd_out_data;
+	wire [7:0] kbd_out_data;
 	wire kbd_out_strobe;
-		
+
 	// Keyboard
 	ps2_kbd kbd(
-		.sysclk(clk8),
+		.sysclk(clk32),
+		.clk_en(clk8_en_p),
 		.reset(~_cpuReset),
 		.ps2dat(keyData),
 		.ps2clk(keyClk),
diff --git a/cores/plus_too/floppy.v b/cores/plus_too/floppy.v
index c0b2e61..1e12c85 100644
--- a/cores/plus_too/floppy.v
+++ b/cores/plus_too/floppy.v
@@ -58,8 +58,12 @@
 `define DRIVE_REG_INSTALLED	14 /* R: drive present (0 = yes ??) */
 `define DRIVE_REG_DRVIN		15 /* R: 400K/800k: drive present (0=yes, 1=no), Superdrive: disk capacity (0=HD, 1=DD) */
 
-module floppy(
-	input clk8,
+module floppy
+(
+	input clk,
+	input cep,
+	input cen,
+
 	input _reset,
 	input ca0,				// PH0
 	input ca1,				// PH1
@@ -76,11 +80,17 @@ module floppy(
 	input diskSides,
 	output diskEject,
 
+	output motor,
+	output act,
+
 	output [21:0] dskReadAddr,
 	input dskReadAck,
 	input [7:0] dskReadData
 );
 
+	assign motor = ~driveRegs[`DRIVE_REG_MOTORON];
+	assign act = lstrbEdge;
+
 	reg [15:0] driveRegs;
 	reg [6:0] driveTrack;
 	reg driveSide;
@@ -107,20 +117,24 @@ module floppy(
 	};
 
 	reg dskReadAckD;
-	always @(negedge clk8)
-		dskReadAckD <= dskReadAck;
+	always @(posedge clk) if(cen) dskReadAckD <= dskReadAck;
 
 	// latch incoming data
 	reg [7:0] dskReadDataLatch;
-	always @(posedge clk8)
-		if(dskReadAckD)
-			dskReadDataLatch <= dskReadData;
+	always @(posedge clk) if(cep && dskReadAckD) dskReadDataLatch <= dskReadData;
 		
 	wire [7:0] dskReadDataEnc;
 	
+	reg old_newByteReady;
+	always @(posedge clk) old_newByteReady <= newByteReady;
+	
 	// include track encoder
-	floppy_track_encoder enc (
-		.clk		( newByteReady ),   
+	floppy_track_encoder enc
+	(
+
+		.clk		( clk ),
+		.ready	( ~old_newByteReady & newByteReady ),
+
 		.rst     ( !_reset ),
 		
 		.side    ( driveSide ),
@@ -128,8 +142,6 @@ module floppy(
 		.track   ( driveTrack ),
 
 		.addr    ( dskReadAddr ),
-		
-		.strobe  ( ), 			    
 		.idata   ( dskReadDataLatch ),
 		.odata   ( dskReadDataEnc )
 	);
@@ -144,8 +156,8 @@ module floppy(
 	reg [6:0] diskDataByteTimer; 
 	reg [7:0] diskImageData;	
 	reg readyToAdvanceHead;
-	always @(posedge clk8 or negedge _reset) begin
-		if (_reset == 1'b0) begin		
+	always @(posedge clk or negedge _reset) begin
+		if (_reset == 0) begin		
 			driveSide <= 0;
 			diskImageData <= 8'h00;
 			diskDataIn <= 8'hFF;
@@ -154,10 +166,11 @@ module floppy(
 			newByteReady <= 1'b0;
 		end 
 		else begin			
+			if(cep) begin
 			// at time 0, latch a new byte and advance the drive head
 			if (diskDataByteTimer == 0 && readyToAdvanceHead && diskImageData != 0) begin
 				diskDataIn <= diskImageData;
-				newByteReady <= 1'b1;
+					newByteReady <= 1;
 				diskDataByteTimer <= 1;  // make timer run again
 									
 				// clear diskImageData after it's used, so we can tell when we get a new one from the disk	
@@ -194,11 +207,11 @@ module floppy(
 				driveSide <= 1;	
 		end
 	end
+	end
 	
 	// create a signal on the falling edge of lstrb
 	reg lstrbPrev;
-	always @(posedge clk8)
-		lstrbPrev <= lstrb;
+	always @(posedge clk) if(cep) lstrbPrev <= lstrb;
 		
 	wire lstrbEdge = lstrb == 1'b0 && lstrbPrev == 1'b1;
 	
@@ -209,11 +222,11 @@ module floppy(
 	wire [2:0] driveWriteAddr = {ca1,ca0,SEL};
 	
 	// DRIVE_REG_DIRTN		0  /* R/W: step direction (0=toward track 79, 1=toward track 0) */
-	always @(posedge clk8 or negedge _reset) begin
+	always @(posedge clk or negedge _reset) begin
 		if (_reset == 1'b0) begin		
 			driveRegs[`DRIVE_REG_DIRTN] <= 1'b0;
 		end 
-		else if (_enable == 1'b0 && lstrbEdge == 1'b1 && driveWriteAddr == `DRIVE_REG_DIRTN) begin
+		else if(cep && _enable == 1'b0 && lstrbEdge == 1'b1 && driveWriteAddr == `DRIVE_REG_DIRTN) begin
 			driveRegs[`DRIVE_REG_DIRTN] <= ca2;
 		end
 	end
@@ -225,33 +238,35 @@ module floppy(
 	reg [23:0] ejectIndicatorTimer;
 	assign diskEject = (ejectIndicatorTimer != 0);
 	
-	always @(posedge clk8 or negedge _reset) begin
+	always @(posedge clk or negedge _reset) begin
 		if (_reset == 1'b0) begin		
 			driveRegs[`DRIVE_REG_CSTIN] <= 1'b1;
 			ejectIndicatorTimer <= 24'd0;
 		end 
-		else if (_enable == 1'b0 && lstrbEdge == 1'b1 && driveWriteAddr == `DRIVE_REG_EJECT && ca2 == 1'b1) begin
-			// eject the disk
-			driveRegs[`DRIVE_REG_CSTIN] <= 1'b1;
-			ejectIndicatorTimer <= 24'hFFFFFF;
-		end
-		else if (insertDisk) begin
-			// insert a disk
-			driveRegs[`DRIVE_REG_CSTIN] <= 1'b0;
-		end
-		else begin
-			if (ejectIndicatorTimer != 0)
-				ejectIndicatorTimer <= ejectIndicatorTimer - 1'b1;
+		else if(cep) begin
+			if (_enable == 1'b0 && lstrbEdge == 1'b1 && driveWriteAddr == `DRIVE_REG_EJECT && ca2 == 1'b1) begin
+				// eject the disk
+				driveRegs[`DRIVE_REG_CSTIN] <= 1'b1;
+				ejectIndicatorTimer <= 24'hFFFFFF;
+			end
+			else if (insertDisk) begin
+				// insert a disk
+				driveRegs[`DRIVE_REG_CSTIN] <= 1'b0;
+			end
+			else begin
+				if (ejectIndicatorTimer != 0)
+					ejectIndicatorTimer <= ejectIndicatorTimer - 1'b1;
+			end
 		end
 	end									
 									
 	//`define DRIVE_REG_STEP		2  /* R: drive head stepping (1 = complete) */
 												/* W: 0 = step drive head */
-	always @(posedge clk8 or negedge _reset) begin
+	always @(posedge clk or negedge _reset) begin
 		if (_reset == 1'b0) begin	
 			driveTrack <= 0; 
 		end 
-		else if (_enable == 1'b0 && lstrbEdge == 1'b1 && driveWriteAddr == `DRIVE_REG_STEP && ca2 == 1'b0) begin
+		else if(cep && _enable == 1'b0 && lstrbEdge == 1'b1 && driveWriteAddr == `DRIVE_REG_STEP && ca2 == 1'b0) begin
 			if (driveRegs[`DRIVE_REG_DIRTN] == 1'b0 && driveTrack != 7'h4F) begin
 				driveTrack <= driveTrack + 1'b1;
 			end
@@ -262,11 +277,11 @@ module floppy(
 	end
 	
 	// DRIVE_REG_MOTORON	4  /* R/W: 0 = motor on */
-	always @(posedge clk8 or negedge _reset) begin
+	always @(posedge clk or negedge _reset) begin
 		if (_reset == 1'b0) begin		
 			driveRegs[`DRIVE_REG_MOTORON] <= 1'b1;
 		end 
-		else if (_enable == 1'b0 && lstrbEdge == 1'b1 && driveWriteAddr == `DRIVE_REG_MOTORON) begin
+		else if (cep && _enable == 1'b0 && lstrbEdge == 1'b1 && driveWriteAddr == `DRIVE_REG_MOTORON) begin
 			driveRegs[`DRIVE_REG_MOTORON] <= ca2;
 		end
 	end
@@ -307,12 +322,12 @@ module floppy(
 		endcase
 	end
 	
-	always @(posedge clk8 or negedge _reset) begin
+	always @(posedge clk or negedge _reset) begin
 		if (_reset == 1'b0) begin		
 			driveRegs[`DRIVE_REG_TACH] <= 1'b0;
 			driveTachTimer <= 0;
 		end 
-		else begin
+		else if(cep) begin
 			if (driveTachTimer == driveTachPeriod) begin
 				driveTachTimer <= 0;
 				driveRegs[`DRIVE_REG_TACH] <= ~driveRegs[`DRIVE_REG_TACH];
diff --git a/cores/plus_too/floppy_track_encoder.v b/cores/plus_too/floppy_track_encoder.v
index 6deb8f4..d6254f1 100644
--- a/cores/plus_too/floppy_track_encoder.v
+++ b/cores/plus_too/floppy_track_encoder.v
@@ -12,23 +12,26 @@
 module floppy_track_encoder (
    // system signals
    input 			clk, // clock at which data bytes are delivered via odata
+   input				ready,
    input 			rst,
 
    input 			side,
    input 			sides,
    input [6:0] 	track, // current track
 
-	output [21:0] 	addr,   // address to fetch from
+	output reg [21:0] 	addr,   // address to fetch from
    input [7:0] 	idata,
 			     
    output [7:0] 	odata 
 );
 
-assign addr = 
-	{ 3'b00, soff, 9'd0 } +                 // sector offset * 512 for two sides
-	(sides?{ 3'b00, soff, 9'd0 }:22'd0) +   // another sector offset * 512 for two sides
-	(side?{ 9'd0, spt, 9'd0 }:22'd0) +      // side * sectors * 512
-	{ 9'd0, sector, src_offset };           // offset within track
+always @(posedge clk) begin
+	addr <= 
+		{ 3'b00, soff, 9'd0 } +                 // sector offset * 512 for two sides
+		(sides?{ 3'b00, soff, 9'd0 }:22'd0) +   // another sector offset * 512 for two sides
+		(side?{ 9'd0, spt, 9'd0 }:22'd0) +      // side * sectors * 512
+		{ 9'd0, sector, src_offset };           // offset within track
+end
 
    // number of sectors on current track
    wire [3:0] spt =
@@ -189,11 +192,9 @@ assign addr =
 		    ((state == STATE_DATA) && (count < 683-4-1))) 
 					&& (cnt != 3);
 
-   reg [7:0] data_latch;
-   always @(posedge clk)
-     if(strobe)
-       data_latch <= idata;
-   
+reg [7:0] data_latch;
+always @(posedge clk) if(ready && strobe) data_latch <= idata;
+
 always @(posedge clk or posedge nibbler_reset) begin
    if(nibbler_reset) begin
 		c1 <= 8'h00;
@@ -205,7 +206,7 @@ always @(posedge clk or posedge nibbler_reset) begin
 		nib_xor_0 <= 8'h00;
 		nib_xor_1 <= 8'h00;
 		nib_xor_2 <= 8'h00;
-   end else if((state == STATE_DPRE) || (state == STATE_DATA)) begin
+   end else if(ready && ((state == STATE_DPRE) || (state == STATE_DATA))) begin
 		cnt <= cnt + 2'd1;
   
 		// memory read during cnt 0-3
@@ -263,7 +264,7 @@ always @(posedge clk or posedge rst) begin
 		state <= STATE_SYN0;
 		sector <= 4'd0;
 	   src_offset <= 9'd0;
-	end else begin
+	end else if(ready) begin
 		count <= count + 10'd1;
 	 
 	   if(strobe)
diff --git a/cores/plus_too/iwm.v b/cores/plus_too/iwm.v
index 4b907a0..0007f6d 100644
--- a/cores/plus_too/iwm.v
+++ b/cores/plus_too/iwm.v
@@ -29,8 +29,12 @@
 	   being defined as both /DEV being low and D7 (the MSB) outputting a one from the read data register for at least one fclk period.
 */		
 
-module iwm(
-	input clk8,
+module iwm
+(
+	input clk,
+	input cep,
+	input cen,
+
 	input _reset,
 	input selectIWM,
 	input _cpuRW,
@@ -43,6 +47,9 @@ module iwm(
 	output [1:0] diskEject,
 	input [1:0] diskSides,
 	
+	output [1:0] diskMotor,
+	output [1:0] diskAct,
+	
 	// interface to fetch data for internal drive
 	output [21:0] dskReadAddrInt,
 	input dskReadAckInt,
@@ -75,8 +82,12 @@ module iwm(
 	wire [7:0] readDataExt;
 	wire senseExt = readDataExt[7]; // bit 7 doubles as the sense line here
 	
-	floppy floppyInt(
-		.clk8(clk8),
+	floppy floppyInt
+	(
+		.clk(clk),
+		.cep(cep),
+		.cen(cen),
+
 		._reset(_reset),
 		.ca0(ca0),
 		.ca1(ca1),
@@ -91,14 +102,21 @@ module iwm(
 		.insertDisk(insertDisk[0]),
 		.diskSides(diskSides[0]),
 		.diskEject(diskEject[0]),	
-		
+
+		.motor(diskMotor[0]),
+		.act(diskAct[0]),
+
 		.dskReadAddr(dskReadAddrInt),
 		.dskReadAck(dskReadAckInt),
 		.dskReadData(dskReadData)
 	);
 		
-	floppy floppyExt(
-		.clk8(clk8),
+	floppy floppyExt
+	(
+		.clk(clk),
+		.cep(cep),
+		.cen(cen),
+
 		._reset(_reset),
 		.ca0(ca0),
 		.ca1(ca1),
@@ -114,6 +132,9 @@ module iwm(
 		.diskSides(diskSides[1]),
 		.diskEject(diskEject[1]),
 		
+		.motor(diskMotor[1]),
+		.act(diskAct[1]),
+
 		.dskReadAddr(dskReadAddrExt),
 		.dskReadAck(dskReadAckExt),
 		.dskReadData(dskReadData)
@@ -185,7 +206,7 @@ module iwm(
 	end
 	
 	// update IWM bit registers
-	always @(negedge clk8 or negedge _reset) begin
+	always @(posedge clk or negedge _reset) begin
 		if (_reset == 1'b0) begin
 			ca0 <= 0;
 			ca1 <= 0;
@@ -197,7 +218,7 @@ module iwm(
 			q6 <= 0;
 			q7 <= 0;
 		end
-		else begin
+		else if(cen) begin
 			ca0 <= ca0Next;
 			ca1 <= ca1Next;
 			ca2 <= ca2Next;
@@ -228,12 +249,12 @@ module iwm(
 	end
 	
 	// write IWM state
-	always @(negedge clk8 or negedge _reset) begin
+	always @(posedge clk or negedge _reset) begin
 		if (_reset == 1'b0) begin		
 			iwmMode <= 0;
 			writeData <= 0;
 		end
-		else begin
+		else if(cen) begin
 			if (_cpuRW == 0 && selectIWM == 1'b1 && _cpuLDS == 1'b0) begin
 				// writing to any IWM address modifies state as selected by Q7 and Q6
 				case ({q7Next,q6Next})
@@ -252,13 +273,13 @@ module iwm(
 	wire iwmRead = (_cpuRW == 1'b1 && selectIWM == 1'b1 && _cpuLDS == 1'b0);
 	reg iwmReadPrev;
 	reg [3:0] readLatchClearTimer; 
-	always @(negedge clk8 or negedge _reset) begin
+	always @(posedge clk or negedge _reset) begin
 		if (_reset == 1'b0) begin	
 			readDataLatch <= 0;
 			readLatchClearTimer <= 0;
 			iwmReadPrev <= 0;
 		end 
-		else begin
+		else if(cen) begin
 			// a countdown timer governs how long after a data latch read before the latch is cleared
 			if (readLatchClearTimer != 0) begin
 				readLatchClearTimer <= readLatchClearTimer - 1'b1;
diff --git a/cores/plus_too/ncr5380.v b/cores/plus_too/ncr5380.v
index 55bbd30..cbf1a80 100644
--- a/cores/plus_too/ncr5380.v
+++ b/cores/plus_too/ncr5380.v
@@ -13,7 +13,7 @@
 `define RREG_RST        3'h7    /* Reset */
 
 /* Write registers */
-`define WREG_ODR        3'h0    /* Ouptut data */
+`define WREG_ODR        3'h0    /* Output data */
 `define WREG_ICR        3'h1    /* Initiator Command */
 `define WREG_MR         3'h2    /* Mode register */
 `define WREG_TCR        3'h3    /* Target Command */
@@ -42,148 +42,170 @@
 `define TCR_A_CD        1
 `define TCR_A_IO        0
 
-module ncr5380(input    sysclk,
-               input 	     reset,
-	       
-               /* Bus interface. 3-bit address, to be wired
-                * appropriately upstream (to A4..A6) plus one
-                * more bit (A9) wired as dack.
-                */
-               input 	     bus_cs,
-               input 	     bus_we,
-               input [2:0]   bus_rs,
-               input 	     dack,
-               input [7:0]   wdata,
-               output [7:0]  rdata,
-	       
-	       
-	       // connections to io controller
-	       output [31:0] io_lba,
-	       output 	     io_rd,
-	       output 	     io_wr,
-	       input 	     io_ack,
-               output [7:0]  io_dout,
-               input 	     io_dout_strobe,
-               input [7:0]   io_din,
-               input 	     io_din_strobe
-               );
-   
-   reg [7:0]  mr;        /* Mode Register */
-   reg [7:0]  icr;       /* Initiator Command Register */
-   reg [3:0]  tcr;       /* Target Command Register */
-   wire [7:0] csr;       /* SCSI bus status register */
-   
-   /* Data in and out latches and associated
-    * control logic for DMA
-    */
-   wire [7:0]  din;
-   reg [7:0]  dout;
-   reg 	      dphase;
-   reg 	      dma_en;
-   
-   /* --- Main host-side interface --- */
-   
-   /* Register & DMA accesses decodes */
-   wire       dma_rd = bus_cs &  dack & ~bus_we;
-   wire       dma_wr = bus_cs &  dack &  bus_we;
-   wire       reg_rd = bus_cs & ~dack & ~bus_we;
-   wire       reg_wr = bus_cs & ~dack &  bus_we;
-   
-   /* System bus reads */
-   assign rdata = dack                ? cur_data         :
-                  bus_rs == `RREG_CDR ? cur_data         :
-                  bus_rs == `RREG_ICR ? icr_read         :
-                  bus_rs == `RREG_MR  ? mr               :
-                  bus_rs == `RREG_TCR ? { 4'h0, tcr }    :
-                  bus_rs == `RREG_CSR ? csr              :
-                  bus_rs == `RREG_BSR ? bsr              :
-                  bus_rs == `RREG_IDR ? cur_data         :
-                  bus_rs == `RREG_RST ? 8'hff            :
-                  8'hff;
-   
+module ncr5380
+(
+	input    		clk,
+	input    		ce,
+
+	input 	     	reset,
+
+	/* Bus interface. 3-bit address, to be wired
+	 * appropriately upstream (to A4..A6) plus one
+	 * more bit (A9) wired as dack.
+	 */
+	input 	     bus_cs,
+	input 	     bus_we,
+	input   [2:0] bus_rs,
+	input 	     dack,
+	input   [7:0] wdata,
+	output  [7:0] rdata,
+
+
+	// connections to io controller
+	input   [1:0] img_mounted,
+	input  [31:0] img_size,
+	
+	output [15:0] io_req_type,
+	output [31:0] io_lba,
+	output  [1:0] io_rd,
+	output  [1:0] io_wr,
+	input 	     io_ack,
+
+	input   [8:0] sd_buff_addr,
+	input   [7:0] sd_buff_dout,
+	output  [7:0] sd_buff_din,
+	input         sd_buff_wr
+);
+
+	reg  [7:0] mr;        /* Mode Register */
+	reg  [7:0] icr;       /* Initiator Command Register */
+	reg  [3:0] tcr;       /* Target Command Register */
+	wire [7:0] csr;       /* SCSI bus status register */
+
+	/* Data in and out latches and associated
+	* control logic for DMA
+	*/
+	wire [7:0] din;
+	reg  [7:0] dout;
+	reg        dphase;
+	reg        dma_en;
+
+	/* --- Main host-side interface --- */
+
+	/* Register & DMA accesses decodes */
+	reg dma_rd;
+	reg dma_wr;
+	reg reg_wr;
+
+	wire i_dma_rd = bus_cs &  dack & ~bus_we;
+	wire i_dma_wr = bus_cs &  dack &  bus_we;
+	wire i_reg_wr = bus_cs & ~dack &  bus_we;
+
+	always @(posedge clk) begin
+		reg old_dma_rd, old_dma_wr, old_reg_wr;
+
+		old_dma_rd <= i_dma_rd;
+		old_dma_wr <= i_dma_wr;
+		old_reg_wr <= i_reg_wr;
+
+		dma_rd <= 0;
+		dma_wr <= 0;
+		reg_wr <= 0;
+
+		if(~old_dma_wr & i_dma_wr) dma_wr <= 1;
+		else if(~old_dma_rd & i_dma_rd) dma_rd <= 1;
+		else if(~old_reg_wr & i_reg_wr) reg_wr <= 1;
+	end
+
+	/* System bus reads */
+	assign rdata = dack                ? cur_data         :
+	               bus_rs == `RREG_CDR ? cur_data         :
+	               bus_rs == `RREG_ICR ? icr_read         :
+	               bus_rs == `RREG_MR  ? mr               :
+	               bus_rs == `RREG_TCR ? { 4'h0, tcr }    :
+	               bus_rs == `RREG_CSR ? csr              :
+	               bus_rs == `RREG_BSR ? bsr              :
+	               bus_rs == `RREG_IDR ? cur_data         :
+	               bus_rs == `RREG_RST ? 8'hff            :
+	               8'hff;
+
    /* DMA handhsaking logic. Two phase logic, in phase 0
     * DRQ follows SCSI _REQ until we see DACK. In phase 1
     * we just wait for SCSI _REQ to go down and go back to
     * phase 0. We assert SCSI _ACK in phase 1.
     */
-   always@(negedge sysclk or posedge reset) begin
-      if (reset) begin
-         dphase <= 0;
-      end else begin
-         if (!dma_en) begin
-            dphase <= 0;
-         end else if (dphase == 0) begin
-            /* Be careful to do that in bus phase 1,
-             * not phase 0, or we would incorrectly
-             * assert bus_hold and lock up the system
-             */
-            if ((dma_rd || dma_wr) && scsi_req) begin
-               dphase <= 1;
-            end
-         end else if (!scsi_req) begin
-            dphase <= 0;
-         end
-      end
-   end
+	always@(posedge clk or posedge reset) begin
+		if (reset) begin
+			dphase <= 0;
+		end else begin
+			if (!dma_en) begin
+				dphase <= 0;
+			end else if (dphase == 0) begin
+				/* Be careful to do that in bus phase 1,
+				* not phase 0, or we would incorrectly
+				* assert bus_hold and lock up the system
+				*/
+				if ((dma_rd || dma_wr) && scsi_req) begin
+					dphase <= 1;
+				end
+			end else if (!scsi_req) begin
+				dphase <= 0;
+			end
+		end
+	end
    
-   /* Data out latch (in DMA mode, this is one cycle after we've
-    * asserted ACK)
+	/* Data out latch (in DMA mode, this is one cycle after we've
+	* asserted ACK)
+	*/
+	always@(posedge clk) if((reg_wr && bus_rs == `WREG_ODR) || dma_wr) dout <= wdata;
+   
+	/* Current data register. Simplified logic: We loop back the
+	* output data if we are asserting the bus, else we get the
+	* input latch
     */
-   always@(negedge sysclk)
-		if ((reg_wr && bus_rs == `WREG_ODR) || dma_wr)
-			dout <= wdata;
+	wire [7:0] cur_data = out_en ? dout : din;
    
-   /* Current data register. Simplified logic: We loop back the
-    * output data if we are asserting the bus, else we get the
-    * input latch
-    */
-   wire [7:0] cur_data = out_en ? dout : din;
+	/* Logic for "asserting the bus" simplified */
+	wire       out_en = icr[`ICR_A_DATA] | mr[`MR_ARB];
    
-   /* Logic for "asserting the bus" simplified */
-   wire       out_en = icr[`ICR_A_DATA] | mr[`MR_ARB];
+	/* ICR read wires */
+	wire [7:0] icr_read = { icr[`ICR_A_RST],
+	                        icr_aip,
+	                        icr_la,
+	                        icr[`ICR_A_ACK],
+	                        icr[`ICR_A_BSY],
+	                        icr[`ICR_A_SEL],
+	                        icr[`ICR_A_ATN],
+	                        icr[`ICR_A_DATA] };
+
+	/* ICR write */
+	always@(posedge clk or posedge reset) begin
+		if (reset) begin
+			icr <= 0;
+		end else if (reg_wr && (bus_rs == `WREG_ICR)) begin
+			icr <= wdata;
+		end
+	end
    
-   /* ICR read wires */
-   wire [7:0] icr_read = { icr[`ICR_A_RST],
-                           icr_aip,
-                           icr_la,
-                           icr[`ICR_A_ACK],
-                           icr[`ICR_A_BSY],
-                           icr[`ICR_A_SEL],
-                           icr[`ICR_A_ATN],
-                           icr[`ICR_A_DATA] };
+	/* MR write */
+	always@(posedge clk or posedge reset) begin
+		if (reset) mr <= 8'b0;
+		else if (reg_wr && (bus_rs == `WREG_MR)) mr <= wdata;
+	end
    
-   /* ICR write */
-   always@(negedge sysclk or posedge reset) begin
-      if (reset) begin
-         icr <= 0;
-      end else if (reg_wr && (bus_rs == `WREG_ICR)) begin
-         icr <= wdata;
-      end
-   end
+	/* TCR write */
+	always@(posedge clk or posedge reset) begin
+		if (reset) tcr <= 4'b0;
+		else if (reg_wr && (bus_rs == `WREG_TCR)) tcr <= wdata[3:0];
+	end
    
-   /* MR write */
-   always@(negedge sysclk or posedge reset) begin
-      if (reset)
-        mr <= 8'b0;
-      else if (reg_wr && (bus_rs == `WREG_MR))
-        mr <= wdata;
-   end
-   
-   /* TCR write */
-   always@(negedge sysclk or posedge reset) begin
-      if (reset)
-        tcr <= 4'b0;
-      else if (reg_wr && (bus_rs == `WREG_TCR))
-        tcr <= wdata[3:0];
-   end
-   
-   /* DMA start send & receive registers. We currently ignore
-    * the direction.
-    */
-   always@(negedge sysclk or posedge reset) begin
-      if (reset) begin
+	/* DMA start send & receive registers. We currently ignore
+	* the direction.
+	*/
+	always@(posedge clk or posedge reset) begin
+		if (reset) begin
 			dma_en <= 0;
-      end else begin
+		end else begin
 			if (!mr[`MR_DMA_MODE]) begin
 				dma_en <= 0;
 			end else if (reg_wr && (bus_rs == `WREG_DMAS)) begin
@@ -191,87 +213,155 @@ module ncr5380(input    sysclk,
 			end else if (reg_wr && (bus_rs == `WREG_IDMAR)) begin
 				dma_en <= 1;
 			end
-      end
-   end
-   
-   /* CSR (read only). We don't do parity */
-   assign csr = { scsi_rst, scsi_bsy, scsi_req, scsi_msg,
-		  scsi_cd, scsi_io, scsi_sel, 1'b0 };	
-   
-   /* Bus and Status register */
-   /* BSR (read only). We don't do a few things... */
-   wire bsr_eodma = 1'b0;	/* We don't do EOP */
-   wire bsr_dmarq = scsi_req & ~dphase & dma_en;
-   wire bsr_perr = 1'b0;	/* We don't do parity */
-   wire bsr_irq = 1'b0;	        /* XXX ? Does MacOS use this ? */
-   wire bsr_pmatch = 
-			tcr[`TCR_A_MSG] == scsi_msg &&
-			tcr[`TCR_A_CD ] == scsi_cd  &&
-			tcr[`TCR_A_IO ] == scsi_io;
-   
-   wire bsr_berr = 1'b0;	/* XXX ? Does MacOS use this ? */
-   wire [7:0] bsr = { bsr_eodma, bsr_dmarq, bsr_perr, bsr_irq,
-		      bsr_pmatch, bsr_berr, scsi_atn, scsi_ack };
+		end
+	end
    
+	/* CSR (read only). We don't do parity */
+	assign csr = { scsi_rst, scsi_bsy, scsi_req, scsi_msg,
+	               scsi_cd, scsi_io, scsi_sel, 1'b0 };	
+
+	/* Bus and Status register */
+	/* BSR (read only). We don't do a few things... */
+	wire bsr_eodma = 1'b0;	/* We don't do EOP */
+	wire bsr_dmarq = scsi_req & dma_en;
+	wire bsr_perr = 1'b0;	/* We don't do parity */
+	wire bsr_irq = 1'b0;	        /* XXX ? Does MacOS use this ? */
+	wire bsr_pmatch = 
+	         tcr[`TCR_A_MSG] == scsi_msg &&
+	         tcr[`TCR_A_CD ] == scsi_cd  &&
+	         tcr[`TCR_A_IO ] == scsi_io;
+
+	wire bsr_berr = 1'b0;	/* XXX ? Does MacOS use this ? */
+	wire [7:0] bsr = { bsr_eodma, bsr_dmarq, bsr_perr, bsr_irq,
+	                   bsr_pmatch, bsr_berr, scsi_atn, scsi_ack };
+
    /* --- Simulated SCSI Signals --- */
 
    /* BSY logic (simplified arbitration, see notes) */
-   wire scsi_bsy = 
-		icr[`ICR_A_BSY] |
-		scsi2_bsy |
-		mr[`MR_ARB];
-   
-   /* Remains of simplified arbitration logic */
-   wire icr_aip = mr[`MR_ARB];
-   wire icr_la = 0;
+	wire scsi_bsy = 
+	    icr[`ICR_A_BSY] |
+	    scsi2_bsy |
+	    //scsi6_bsy |
+	    mr[`MR_ARB];
 
-   reg 	dma_ack;
-   always @(posedge sysclk)
-     dma_ack <= dphase;
-   
-   /* Other ORed SCSI signals */
-   wire scsi_sel = icr[`ICR_A_SEL];
-   wire scsi_rst = icr[`ICR_A_RST];
-   wire scsi_ack = icr[`ICR_A_ACK] | dma_ack;
-   wire scsi_atn = icr[`ICR_A_ATN];
-   
-   /* Other trivial lines set by target */
-   wire scsi_cd = scsi2_cd;
-   wire scsi_io = scsi2_io;
-   wire scsi_msg = scsi2_msg;
-   wire scsi_req = scsi2_req;
+	/* Remains of simplified arbitration logic */
+	wire icr_aip = mr[`MR_ARB];
+	wire icr_la = 0;
 
-   assign din = scsi2_bsy?scsi2_dout:8'h55;
-   
-   // input signals from target 2
-   wire scsi2_bsy, scsi2_msg, scsi2_io, scsi2_cd, scsi2_req;
-   wire [7:0] scsi2_dout;
+	reg 	dma_ack;
+	always @(posedge clk) if(ce) dma_ack <= dphase;
 
-   // connect a target
-   scsi #(.ID(2)) scsi2(.sysclk ( sysclk ),
-			.rst    ( scsi_rst ),
-			.sel    ( scsi_sel ),
-			.atn    ( scsi_atn ),
-			.bsy    ( scsi2_bsy ),
-			.msg    ( scsi2_msg ),
-			.cd     ( scsi2_cd ),
-			.io     ( scsi2_io ),
-			.req    ( scsi2_req ),
-			.ack    ( scsi_ack ),
-			.dout   ( scsi2_dout ),
-			.din    ( dout ),
+	/* Other ORed SCSI signals */
+	wire scsi_sel = icr[`ICR_A_SEL];
+	wire scsi_rst = icr[`ICR_A_RST];
+	wire scsi_ack = icr[`ICR_A_ACK] | dma_ack;
+	wire scsi_atn = icr[`ICR_A_ATN];
+
+	wire scsi_cd  = scsi2_cd;
+	wire scsi_io  = scsi2_io;
+	wire scsi_msg = scsi2_msg;
+	wire scsi_req = scsi2_req;
+	
+	assign din = scsi2_dout;
+
+	assign io_lba      = io_lba_2;
+	assign sd_buff_din = sd_buff_din_2;
+	/* Other trivial lines set by target */
+	/*
+	wire scsi_cd  = (scsi2_bsy) ? scsi2_cd : scsi6_cd;
+	wire scsi_io  = (scsi2_bsy) ? scsi2_io : scsi6_io;
+	wire scsi_msg = (scsi2_bsy) ? scsi2_msg : scsi6_msg;
+	wire scsi_req = (scsi2_bsy) ? scsi2_req : scsi6_req;
+	
+	assign din = scsi2_bsy ? scsi2_dout : 
+	             scsi6_bsy ? scsi6_dout : 
+	             8'h55;
+
+	assign io_lba      = (scsi2_bsy) ? io_lba_2 : io_lba_6;
+	assign sd_buff_din = (scsi2_bsy) ? sd_buff_din_2 : sd_buff_din_6;
+	assign io_req_type = 16'h0000;	// Not used atm. Could be used for CD-ROM sector requests later. ElectronAsh.
+*/
+	// input signals from target 2
+	wire scsi2_bsy, scsi2_msg, scsi2_io, scsi2_cd, scsi2_req;
+	wire [7:0] scsi2_dout;
+
+	wire [31:0] io_lba_2;
+	wire [7:0] sd_buff_din_2;
+
+	// connect a target
+	scsi #(.ID(2)) scsi2
+	(
+		.clk    ( clk ),
+		.rst    ( scsi_rst ),
+		.sel    ( scsi_sel ),
+		.atn    ( scsi_atn ),
+		
+		.ack    ( scsi_ack ),
+		
+		.bsy    ( scsi2_bsy ),
+		.msg    ( scsi2_msg ),
+		.cd     ( scsi2_cd ),
+		.io     ( scsi2_io ),
+		.req    ( scsi2_req ),
+		.dout   ( scsi2_dout ),
+		
+		.din    ( dout ),
+
+		// connection to io controller to read and write sectors
+		// to sd card
+		.img_mounted(img_mounted[0]),
+		.img_blocks(img_size[31:9]),
+		.io_lba ( io_lba_2 ),
+		.io_rd  ( io_rd[0] ),
+		.io_wr  ( io_wr[0] ),
+		.io_ack ( io_ack & scsi2_bsy ),
+
+		.sd_buff_addr( sd_buff_addr ),
+		.sd_buff_dout( sd_buff_dout ),
+		.sd_buff_din( sd_buff_din_2 ),
+		.sd_buff_wr( sd_buff_wr & scsi2_bsy )
+	);
+
+/*
+	// input signals from target 6
+	wire scsi6_bsy, scsi6_msg, scsi6_io, scsi6_cd, scsi6_req;
+	wire [7:0] scsi6_dout;
+	
+	wire [31:0] io_lba_6;
+	wire [7:0] sd_buff_din_6;
+
+	scsi #(.ID(6)) scsi6
+	(
+		.clk		( clk ) ,           // input  clk
+		.rst		( scsi_rst ) ,      // input  rst
+		.sel		( scsi_sel ) ,      // input  sel
+		.atn		( scsi_atn ) ,      // input  atn
+		
+		.ack		( scsi_ack ) ,      // input  ack
+		
+		.bsy		( scsi6_bsy ) ,     // output  bsy
+		.msg		( scsi6_msg ) ,     // output  msg
+		.cd         ( scsi6_cd ) ,      // output  cd
+		.io         ( scsi6_io ) ,      // output  io
+		.req		( scsi6_req ) ,     // output  req
+		.dout		( scsi6_dout ) ,    // output [7:0] dout
+
+		.din		( dout ) ,          // input [7:0] din
+
+		// connection to io controller to read and write sectors
+		// to sd card
+		.img_mounted( img_mounted[1] ),
+		.img_blocks( img_size[31:9] ),
+		.io_lba	( io_lba_6 ) ,		// output [31:0] io_lba
+		.io_rd	( io_rd[1] ) ,		// output  io_rd
+		.io_wr	( io_wr[1] ) ,		// output  io_wr
+		.io_ack	( io_ack & scsi6_bsy ) ,		// input  io_ack
+
+		.sd_buff_addr( sd_buff_addr ) ,	// input [8:0] sd_buff_addr
+		.sd_buff_dout( sd_buff_dout ) ,	// input [7:0] sd_buff_dout
+		.sd_buff_din( sd_buff_din_6 ) ,	// output [7:0] sd_buff_din
+		.sd_buff_wr( sd_buff_wr & scsi6_bsy ) 	// input  sd_buff_wr
+	);
+*/
 
-			// connection to io controller to read and write sectors
-			// to sd card
-			.io_lba ( io_lba ),
-			.io_rd  ( io_rd ),
-			.io_wr  ( io_wr ),
-			.io_ack ( io_ack ),
-			.io_dout ( io_dout ),
-			.io_dout_strobe ( io_dout_strobe ),
-			.io_din ( io_din ),
-			.io_din_strobe ( io_din_strobe )
-			);
-   
-   
 endmodule
diff --git a/cores/plus_too/osd.v b/cores/plus_too/osd.v
deleted file mode 100644
index a654b40..0000000
--- a/cores/plus_too/osd.v
+++ /dev/null
@@ -1,182 +0,0 @@
-// A simple OSD implementation. Can be hooked up between a cores
-// VGA output and the physical VGA pins
-
-module osd (
-	// OSDs pixel clock, should be synchronous to cores pixel clock to
-	// avoid jitter.
-	input 			pclk,
-
-	// SPI interface
-	input         sck,
-	input         ss,
-	input         sdi,
-
-	// VGA signals coming from core
-	input [5:0]  	red_in,
-	input [5:0]  	green_in,
-	input [5:0]  	blue_in,
-	input				hs_in,
-	input				vs_in,
-	
-	// VGA signals going to video connector
-	output [5:0]  	red_out,
-	output [5:0]  	green_out,
-	output [5:0]  	blue_out,
-	output			hs_out,
-	output			vs_out
-);
-
-parameter OSD_X_OFFSET = 10'd0;
-parameter OSD_Y_OFFSET = 10'd0;
-parameter OSD_COLOR    = 3'd0;
-
-localparam OSD_WIDTH  = 10'd256;
-localparam OSD_HEIGHT = 10'd128;
-
-// *********************************************************************************
-// spi client
-// *********************************************************************************
-
-// this core supports only the display related OSD commands
-// of the minimig
-reg [7:0]      sbuf;
-reg [7:0]      cmd;
-reg [4:0]      cnt;
-reg [10:0]     bcnt;
-reg    			osd_enable;
-
-reg [7:0] osd_buffer [2047:0];  // the OSD buffer itself
-
-// the OSD has its own SPI interface to the io controller
-always@(posedge sck, posedge ss) begin
-  if(ss == 1'b1) begin
-      cnt <= 5'd0;
-      bcnt <= 11'd0;
-  end else begin
-    sbuf <= { sbuf[6:0], sdi};
-
-    // 0:7 is command, rest payload
-    if(cnt < 15)
-      cnt <= cnt + 4'd1;
-    else
-      cnt <= 4'd8;
-
-      if(cnt == 7) begin
-       cmd <= {sbuf[6:0], sdi};
-      
-      // lower three command bits are line address
-      bcnt <= { sbuf[1:0], sdi, 8'h00};
-
-      // command 0x40: OSDCMDENABLE, OSDCMDDISABLE
-      if(sbuf[6:3] == 4'b0100)
-        osd_enable <= sdi;
-    end
-
-    // command 0x20: OSDCMDWRITE
-    if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin
-      osd_buffer[bcnt] <= {sbuf[6:0], sdi};
-      bcnt <= bcnt + 11'd1;
-    end
-  end
-end
-
-// *********************************************************************************
-// video timing and sync polarity anaylsis
-// *********************************************************************************
-
-// horizontal counter
-reg [9:0] h_cnt;
-reg hsD, hsD2;
-reg [9:0] hs_low, hs_high;
-wire hs_pol = hs_high < hs_low;
-wire [9:0] h_dsp_width = hs_pol?hs_low:hs_high;
-wire [9:0] h_dsp_ctr = { 1'b0, h_dsp_width[9:1] };
-
-always @(posedge pclk) begin
-	// bring hsync into local clock domain
-	hsD <= hs_in;
-	hsD2 <= hsD;
-
-	// falling edge of hs_in
-	if(!hsD && hsD2) begin	
-		h_cnt <= 10'd0;
-		hs_high <= h_cnt;
-	end
-
-	// rising edge of hs_in
-	else if(hsD && !hsD2) begin	
-		h_cnt <= 10'd0;
-		hs_low <= h_cnt;
-	end 
-	
-	else
-		h_cnt <= h_cnt + 10'd1;
-end
-
-// vertical counter
-reg [9:0] v_cnt;
-reg vsD, vsD2;
-reg [9:0] vs_low, vs_high;
-wire vs_pol = vs_high < vs_low;
-wire [9:0] v_dsp_width = vs_pol?vs_low:vs_high;
-wire [9:0] v_dsp_ctr = { 1'b0, v_dsp_width[9:1] };
-
-always @(posedge hs_in) begin
-	// bring vsync into local clock domain
-	vsD <= vs_in;
-	vsD2 <= vsD;
-
-	// falling edge of vs_in
-	if(!vsD && vsD2) begin	
-		v_cnt <= 10'd0;
-		vs_high <= v_cnt;
-	end
-
-	// rising edge of vs_in
-	else if(vsD && !vsD2) begin	
-		v_cnt <= 10'd0;
-		vs_low <= v_cnt;
-	end 
-	
-	else
-		v_cnt <= v_cnt + 10'd1;
-end
-
-// area in which OSD is being displayed
-wire [9:0] h_osd_start = h_dsp_ctr + OSD_X_OFFSET - (OSD_WIDTH >> 1);
-wire [9:0] h_osd_end   = h_dsp_ctr + OSD_X_OFFSET + (OSD_WIDTH >> 1) - 1;
-wire [9:0] v_osd_start = v_dsp_ctr + OSD_Y_OFFSET - (OSD_HEIGHT >> 1);
-wire [9:0] v_osd_end   = v_dsp_ctr + OSD_Y_OFFSET + (OSD_HEIGHT >> 1) - 1;
-
-reg h_osd_active, v_osd_active;
-always @(posedge pclk) begin
-	if(hs_in != hs_pol) begin
-		if(h_cnt == h_osd_start) h_osd_active <= 1'b1;
-		if(h_cnt == h_osd_end)   h_osd_active <= 1'b0;
-	end
-	if(vs_in != vs_pol) begin
-		if(v_cnt == v_osd_start) v_osd_active <= 1'b1;
-		if(v_cnt == v_osd_end)   v_osd_active <= 1'b0;
-	end
-end
-
-wire osd_de = osd_enable && h_osd_active && v_osd_active;
-
-wire [7:0] osd_hcnt = h_cnt - h_osd_start + 7'd1;  // one pixel offset for osd_byte register
-wire [6:0] osd_vcnt = v_cnt - v_osd_start;
-
-wire osd_pixel = osd_byte[osd_vcnt[3:1]];
-
-reg [7:0] osd_byte; 
-always @(posedge pclk)
-  osd_byte <= osd_buffer[{osd_vcnt[6:4], osd_hcnt}];
-
-wire [2:0] osd_color = OSD_COLOR;
-assign red_out   = !osd_de?red_in:  {osd_pixel, osd_pixel, osd_color[2], red_in[5:3]  };
-assign green_out = !osd_de?green_in:{osd_pixel, osd_pixel, osd_color[1], green_in[5:3]};
-assign blue_out  = !osd_de?blue_in: {osd_pixel, osd_pixel, osd_color[0], blue_in[5:3] };
-
-assign hs_out = hs_in;
-assign vs_out = vs_in;
-
-endmodule
\ No newline at end of file
diff --git a/cores/plus_too/pll.v b/cores/plus_too/pll.v
index cb441c4..cd13efa 100644
--- a/cores/plus_too/pll.v
+++ b/cores/plus_too/pll.v
@@ -14,7 +14,7 @@
 // ************************************************************
 // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 //
-// 13.1.4 Build 182 03/12/2014 SJ Web Edition
+// 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition
 // ************************************************************
 
 
@@ -102,10 +102,10 @@ module pll (
 		altpll_component.clk0_duty_cycle = 50,
 		altpll_component.clk0_multiply_by = 65,
 		altpll_component.clk0_phase_shift = "0",
-		altpll_component.clk1_divide_by = 27,
+		altpll_component.clk1_divide_by = 54,
 		altpll_component.clk1_duty_cycle = 50,
 		altpll_component.clk1_multiply_by = 65,
-		altpll_component.clk1_phase_shift = "-2500",
+		altpll_component.clk1_phase_shift = "0",
 		altpll_component.compensate_clock = "CLK0",
 		altpll_component.inclk0_input_frequency = 37037,
 		altpll_component.intended_device_family = "Cyclone III",
@@ -184,7 +184,7 @@ endmodule
 // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "65.000000"
-// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "65.000000"
+// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "32.500000"
 // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -213,7 +213,7 @@ endmodule
 // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
 // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
 // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "65.00000000"
-// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "65.00000000"
+// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "32.50000000"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
 // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
@@ -221,7 +221,7 @@ endmodule
 // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1"
 // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
 // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
-// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-2500.00000000"
+// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000"
 // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
 // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps"
@@ -263,10 +263,10 @@ endmodule
 // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
 // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "65"
 // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
-// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27"
+// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "54"
 // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
 // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "65"
-// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-2500"
+// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
 // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037"
 // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
diff --git a/cores/plus_too/plusToo_top.qsf b/cores/plus_too/plusToo_top.qsf
index ce32bd5..fd20c11 100644
--- a/cores/plus_too/plusToo_top.qsf
+++ b/cores/plus_too/plusToo_top.qsf
@@ -26,13 +26,13 @@ set_global_assignment -name DEVICE EP3C25E144C8
 set_global_assignment -name TOP_LEVEL_ENTITY plusToo_top
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:27:29  OCTOBER 30, 2007"
-set_global_assignment -name LAST_QUARTUS_VERSION 13.1
+set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26"
 set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace
 set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144
 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR"
 set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)"
-set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF
-set_global_assignment -name FITTER_EFFORT "FAST FIT"
+set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS"
+set_global_assignment -name FITTER_EFFORT "AUTO FIT"
 set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4
 set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
 set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED"
@@ -122,13 +122,13 @@ set_location_assignment PIN_43 -to SDRAM_CLK
 
 set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED
 set_global_assignment -name SMART_RECOMPILE ON
-set_global_assignment -name ENABLE_SIGNALTAP ON
-set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp
+set_global_assignment -name ENABLE_SIGNALTAP OFF
+set_global_assignment -name USE_SIGNALTAP_FILE out/cpu.stp
 set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
 set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON
 set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL
 set_global_assignment -name FMAX_REQUIREMENT "114 MHz"
-set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF
+set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON
 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
 set_global_assignment -name USE_CONFIGURATION_DEVICE ON
@@ -136,7 +136,7 @@ set_global_assignment -name TPD_REQUIREMENT "2 ns"
 set_global_assignment -name TSU_REQUIREMENT "2 ns"
 set_global_assignment -name TCO_REQUIREMENT "2 ns"
 set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF
-set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
 set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION OFF
 set_global_assignment -name AUTO_RAM_RECOGNITION ON
 set_global_assignment -name AUTO_ROM_RECOGNITION ON
@@ -237,6 +237,8 @@ set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[13]
 set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[14]
 set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[15]
 
+set_location_assignment PLL_1 -to "pll:cs0|altpll:altpll_component"
+
 set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk8
 set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk64
 set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to SDRAM_CLK
@@ -337,208 +339,10 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_R
 set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to UART_RX
 
 
-set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "TG68:m68k|data_in[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "TG68:m68k|data_in[10]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "TG68:m68k|data_in[11]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "TG68:m68k|data_in[12]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "TG68:m68k|data_in[13]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "TG68:m68k|data_in[14]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "TG68:m68k|data_in[15]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "TG68:m68k|data_in[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "TG68:m68k|data_in[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "TG68:m68k|data_in[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "TG68:m68k|data_in[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "TG68:m68k|data_in[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "TG68:m68k|data_in[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "TG68:m68k|data_in[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "TG68:m68k|data_in[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "TG68:m68k|data_in[9]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "TG68:m68k|reset" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "TG68KdotC_Kernel:m68k|IPL[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "TG68KdotC_Kernel:m68k|IPL[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "TG68KdotC_Kernel:m68k|IPL[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "TG68KdotC_Kernel:m68k|addr[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "TG68KdotC_Kernel:m68k|addr[10]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "TG68KdotC_Kernel:m68k|addr[11]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "TG68KdotC_Kernel:m68k|addr[12]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "TG68KdotC_Kernel:m68k|addr[13]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "TG68KdotC_Kernel:m68k|addr[14]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "TG68KdotC_Kernel:m68k|addr[15]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "TG68KdotC_Kernel:m68k|addr[16]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "TG68KdotC_Kernel:m68k|addr[17]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "TG68KdotC_Kernel:m68k|addr[18]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "TG68KdotC_Kernel:m68k|addr[19]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "TG68KdotC_Kernel:m68k|addr[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "TG68KdotC_Kernel:m68k|addr[20]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "TG68KdotC_Kernel:m68k|addr[21]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "TG68KdotC_Kernel:m68k|addr[22]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "TG68KdotC_Kernel:m68k|addr[23]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "TG68KdotC_Kernel:m68k|addr[24]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "TG68KdotC_Kernel:m68k|addr[25]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "TG68KdotC_Kernel:m68k|addr[26]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "TG68KdotC_Kernel:m68k|addr[27]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "TG68KdotC_Kernel:m68k|addr[28]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "TG68KdotC_Kernel:m68k|addr[29]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "TG68KdotC_Kernel:m68k|addr[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "TG68KdotC_Kernel:m68k|addr[30]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "TG68KdotC_Kernel:m68k|addr[31]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "TG68KdotC_Kernel:m68k|addr[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "TG68KdotC_Kernel:m68k|addr[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "TG68KdotC_Kernel:m68k|addr[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "TG68KdotC_Kernel:m68k|addr[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "TG68KdotC_Kernel:m68k|addr[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "TG68KdotC_Kernel:m68k|addr[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "TG68KdotC_Kernel:m68k|addr[9]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "TG68KdotC_Kernel:m68k|busstate[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "TG68KdotC_Kernel:m68k|busstate[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "TG68KdotC_Kernel:m68k|clk" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "TG68KdotC_Kernel:m68k|clkena_in" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "TG68KdotC_Kernel:m68k|data_write[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "TG68KdotC_Kernel:m68k|data_write[10]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "TG68KdotC_Kernel:m68k|data_write[11]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "TG68KdotC_Kernel:m68k|data_write[12]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "TG68KdotC_Kernel:m68k|data_write[13]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "TG68KdotC_Kernel:m68k|data_write[14]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "TG68KdotC_Kernel:m68k|data_write[15]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "TG68KdotC_Kernel:m68k|data_write[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "TG68KdotC_Kernel:m68k|data_write[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "TG68KdotC_Kernel:m68k|data_write[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "TG68KdotC_Kernel:m68k|data_write[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "TG68KdotC_Kernel:m68k|data_write[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "TG68KdotC_Kernel:m68k|data_write[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "TG68KdotC_Kernel:m68k|data_write[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "TG68KdotC_Kernel:m68k|data_write[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "TG68KdotC_Kernel:m68k|data_write[9]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "TG68KdotC_Kernel:m68k|exe_opcode[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "TG68KdotC_Kernel:m68k|exe_opcode[10]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "TG68KdotC_Kernel:m68k|exe_opcode[11]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "TG68KdotC_Kernel:m68k|exe_opcode[12]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to "TG68KdotC_Kernel:m68k|exe_opcode[13]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to "TG68KdotC_Kernel:m68k|exe_opcode[14]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to "TG68KdotC_Kernel:m68k|exe_opcode[15]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to "TG68KdotC_Kernel:m68k|exe_opcode[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to "TG68KdotC_Kernel:m68k|exe_opcode[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to "TG68KdotC_Kernel:m68k|exe_opcode[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to "TG68KdotC_Kernel:m68k|exe_opcode[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to "TG68KdotC_Kernel:m68k|exe_opcode[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to "TG68KdotC_Kernel:m68k|exe_opcode[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to "TG68KdotC_Kernel:m68k|exe_opcode[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "TG68KdotC_Kernel:m68k|exe_opcode[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "TG68KdotC_Kernel:m68k|exe_opcode[9]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "TG68KdotC_Kernel:m68k|nLDS" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "TG68KdotC_Kernel:m68k|nReset" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "TG68KdotC_Kernel:m68k|nUDS" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "TG68KdotC_Kernel:m68k|nWr" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[92] -to "addrController_top:ac0|_cpuDTACK" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "TG68:m68k|data_in[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "TG68:m68k|data_in[10]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "TG68:m68k|data_in[11]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "TG68:m68k|data_in[12]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "TG68:m68k|data_in[13]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "TG68:m68k|data_in[14]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "TG68:m68k|data_in[15]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "TG68:m68k|data_in[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "TG68:m68k|data_in[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "TG68:m68k|data_in[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "TG68:m68k|data_in[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "TG68:m68k|data_in[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "TG68:m68k|data_in[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "TG68:m68k|data_in[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "TG68:m68k|data_in[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "TG68:m68k|data_in[9]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "TG68:m68k|reset" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "TG68KdotC_Kernel:m68k|IPL[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "TG68KdotC_Kernel:m68k|IPL[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "TG68KdotC_Kernel:m68k|IPL[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "TG68KdotC_Kernel:m68k|addr[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "TG68KdotC_Kernel:m68k|addr[10]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "TG68KdotC_Kernel:m68k|addr[11]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "TG68KdotC_Kernel:m68k|addr[12]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "TG68KdotC_Kernel:m68k|addr[13]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "TG68KdotC_Kernel:m68k|addr[14]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "TG68KdotC_Kernel:m68k|addr[15]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "TG68KdotC_Kernel:m68k|addr[16]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "TG68KdotC_Kernel:m68k|addr[17]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "TG68KdotC_Kernel:m68k|addr[18]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "TG68KdotC_Kernel:m68k|addr[19]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "TG68KdotC_Kernel:m68k|addr[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "TG68KdotC_Kernel:m68k|addr[20]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "TG68KdotC_Kernel:m68k|addr[21]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "TG68KdotC_Kernel:m68k|addr[22]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "TG68KdotC_Kernel:m68k|addr[23]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "TG68KdotC_Kernel:m68k|addr[24]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "TG68KdotC_Kernel:m68k|addr[25]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "TG68KdotC_Kernel:m68k|addr[26]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "TG68KdotC_Kernel:m68k|addr[27]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "TG68KdotC_Kernel:m68k|addr[28]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "TG68KdotC_Kernel:m68k|addr[29]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "TG68KdotC_Kernel:m68k|addr[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "TG68KdotC_Kernel:m68k|addr[30]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "TG68KdotC_Kernel:m68k|addr[31]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "TG68KdotC_Kernel:m68k|addr[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "TG68KdotC_Kernel:m68k|addr[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "TG68KdotC_Kernel:m68k|addr[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "TG68KdotC_Kernel:m68k|addr[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "TG68KdotC_Kernel:m68k|addr[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "TG68KdotC_Kernel:m68k|addr[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "TG68KdotC_Kernel:m68k|addr[9]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "TG68KdotC_Kernel:m68k|busstate[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "TG68KdotC_Kernel:m68k|busstate[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "TG68KdotC_Kernel:m68k|clk" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "TG68KdotC_Kernel:m68k|clkena_in" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "TG68KdotC_Kernel:m68k|data_write[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "TG68KdotC_Kernel:m68k|data_write[10]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "TG68KdotC_Kernel:m68k|data_write[11]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "TG68KdotC_Kernel:m68k|data_write[12]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "TG68KdotC_Kernel:m68k|data_write[13]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "TG68KdotC_Kernel:m68k|data_write[14]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "TG68KdotC_Kernel:m68k|data_write[15]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "TG68KdotC_Kernel:m68k|data_write[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "TG68KdotC_Kernel:m68k|data_write[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "TG68KdotC_Kernel:m68k|data_write[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "TG68KdotC_Kernel:m68k|data_write[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "TG68KdotC_Kernel:m68k|data_write[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "TG68KdotC_Kernel:m68k|data_write[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "TG68KdotC_Kernel:m68k|data_write[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "TG68KdotC_Kernel:m68k|data_write[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "TG68KdotC_Kernel:m68k|data_write[9]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "TG68KdotC_Kernel:m68k|exe_opcode[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "TG68KdotC_Kernel:m68k|exe_opcode[10]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "TG68KdotC_Kernel:m68k|exe_opcode[11]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "TG68KdotC_Kernel:m68k|exe_opcode[12]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "TG68KdotC_Kernel:m68k|exe_opcode[13]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "TG68KdotC_Kernel:m68k|exe_opcode[14]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "TG68KdotC_Kernel:m68k|exe_opcode[15]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "TG68KdotC_Kernel:m68k|exe_opcode[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "TG68KdotC_Kernel:m68k|exe_opcode[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "TG68KdotC_Kernel:m68k|exe_opcode[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "TG68KdotC_Kernel:m68k|exe_opcode[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "TG68KdotC_Kernel:m68k|exe_opcode[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "TG68KdotC_Kernel:m68k|exe_opcode[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "TG68KdotC_Kernel:m68k|exe_opcode[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "TG68KdotC_Kernel:m68k|exe_opcode[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "TG68KdotC_Kernel:m68k|exe_opcode[9]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "TG68KdotC_Kernel:m68k|nLDS" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "TG68KdotC_Kernel:m68k|nReset" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "TG68KdotC_Kernel:m68k|nUDS" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "TG68KdotC_Kernel:m68k|nWr" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "addrController_top:ac0|_cpuDTACK" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0
+set_global_assignment -name ENABLE_CONFIGURATION_PINS OFF
+set_global_assignment -name ENABLE_NCE_PIN OFF
+set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF
+set_global_assignment -name SYSTEMVERILOG_FILE plusToo_top.sv
 set_global_assignment -name VERILOG_FILE scsi.v
 set_global_assignment -name VERILOG_FILE ncr5380.v
 set_global_assignment -name VERILOG_FILE sigma_delta_dac.v
@@ -548,8 +352,6 @@ set_global_assignment -name VHDL_FILE TG68K_Pack.vhd
 set_global_assignment -name VHDL_FILE TG68KdotC_Kernel.vhd
 set_global_assignment -name VHDL_FILE TG68K_ALU.vhd
 set_global_assignment -name VERILOG_FILE data_io.v
-set_global_assignment -name VERILOG_FILE user_io.v
-set_global_assignment -name VERILOG_FILE osd.v
 set_global_assignment -name VERILOG_FILE sdram.v
 set_global_assignment -name SDC_FILE plusToo_top.sdc
 set_global_assignment -name VERILOG_FILE scc.v
@@ -562,362 +364,8 @@ set_global_assignment -name VERILOG_FILE addrController_top.v
 set_global_assignment -name VERILOG_FILE dataController_top.v
 set_global_assignment -name VERILOG_FILE videoTimer.v
 set_global_assignment -name VERILOG_FILE videoShifter.v
-set_global_assignment -name VERILOG_FILE plusToo_top.v
 set_global_assignment -name VERILOG_FILE floppy.v
-set_global_assignment -name SIGNALTAP_FILE stp1.stp
 set_global_assignment -name QIP_FILE pll.qip
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "addrController_top:ac0|_memoryLDS" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "addrController_top:ac0|_memoryUDS" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "addrController_top:ac0|_memoryLDS" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "addrController_top:ac0|_memoryUDS" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=256" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=256" -section_id auto_signaltap_0
-set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "pll:cs0|altpll:altpll_component|pll_altpll:auto_generated|wire_pll1_clk[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "addrController_top:ac0|videoBusControl" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "clock325MHz:cs0|locked" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "dataController_top:dc0|ncr5380:scsi|bus_cs" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "dataController_top:dc0|ncr5380:scsi|bus_rs[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "dataController_top:dc0|ncr5380:scsi|bus_rs[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to "dataController_top:dc0|ncr5380:scsi|bus_rs[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to "dataController_top:dc0|ncr5380:scsi|bus_we" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to "dataController_top:dc0|ncr5380:scsi|dack" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|ack" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|bsy" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[110] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[111] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[112] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[113] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cd" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "addrController_top:ac0|videoBusControl" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "clock325MHz:cs0|locked" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "dataController_top:dc0|ncr5380:scsi|bus_cs" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "dataController_top:dc0|ncr5380:scsi|bus_rs[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "dataController_top:dc0|ncr5380:scsi|bus_rs[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "dataController_top:dc0|ncr5380:scsi|bus_rs[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "dataController_top:dc0|ncr5380:scsi|bus_we" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "dataController_top:dc0|ncr5380:scsi|dack" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|ack" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|bsy" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[110] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[111] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[112] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|buffer_dout[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[113] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cd" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[114] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[115] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[116] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[117] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[118] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[119] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[120] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[121] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[122] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd_cnt[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[123] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd_cnt[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[124] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd_cnt[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[125] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd_cnt[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[126] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd_cpl" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[127] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd_read" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[128] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[129] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[10]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[130] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[11]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[131] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[12]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[132] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[13]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[133] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[14]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[134] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[15]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[135] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[16]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[136] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[17]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[137] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[18]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[138] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[19]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[139] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[140] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[20]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[141] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[21]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[142] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[22]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[143] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[23]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[144] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[24]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[145] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[25]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[146] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[26]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[147] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[27]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[148] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[28]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[149] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[29]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[150] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[151] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[30]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[152] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[31]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[153] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[154] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[155] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[156] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[157] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[158] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[159] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[9]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[160] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[161] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[162] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[163] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[164] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[165] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[166] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[167] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[168] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[169] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[170] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[171] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[172] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[173] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[174] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[175] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[176] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[177] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[178] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[179] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[180] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[181] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[182] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[183] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[184] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_ack" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[185] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[186] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[10]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[187] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[11]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[188] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[12]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[189] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[13]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[190] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[14]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[191] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[15]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[192] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[16]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[193] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[17]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[194] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[18]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[195] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[19]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[196] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[197] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[20]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[198] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[21]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[199] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[22]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[200] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[23]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[201] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[24]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[202] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[25]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[203] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[26]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[204] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[27]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[205] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[28]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[206] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[29]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[207] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[208] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[30]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[209] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[31]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[210] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[211] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[212] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[213] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[214] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[215] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[216] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[9]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[217] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_rd" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[114] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[115] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[116] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[117] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[118] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[119] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[120] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[121] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd[0][7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[122] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd_cnt[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[123] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd_cnt[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[124] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd_cnt[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[125] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd_cnt[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[126] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd_cpl" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[127] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|cmd_read" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[128] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[129] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[10]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[130] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[11]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[131] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[12]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[132] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[13]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[133] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[14]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[134] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[15]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[135] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[16]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[136] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[17]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[137] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[18]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[138] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[19]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[139] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[140] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[20]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[141] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[21]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[142] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[22]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[143] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[23]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[144] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[24]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[145] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[25]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[146] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[26]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[147] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[27]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[148] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[28]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[149] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[29]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[150] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[151] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[30]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[152] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[31]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[153] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[154] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[155] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[156] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[157] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[158] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[159] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|data_cnt[9]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[160] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[161] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[162] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[163] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[164] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[165] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[166] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[167] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dbg_cmds[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[168] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[169] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[170] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[171] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[172] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[173] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[174] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[175] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|din[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[176] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[177] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[178] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[179] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[180] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[181] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[182] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[183] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|dout[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[184] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_ack" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[185] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[186] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[10]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[187] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[11]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[188] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[12]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[189] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[13]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[190] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[14]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[191] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[15]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[192] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[16]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[193] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[17]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[194] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[18]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[195] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[19]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[196] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[197] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[20]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[198] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[21]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[199] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[22]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[200] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[23]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[201] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[24]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[202] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[25]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[203] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[26]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[204] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[27]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[205] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[28]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[206] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[29]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[207] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[208] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[30]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[209] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[31]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[210] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[211] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[212] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[213] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[214] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[215] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[216] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_lba[9]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[217] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_rd" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=265" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=265" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=817" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=40745" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[218] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_wr" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[219] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|phase.000" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[220] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|phase.001" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[221] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|phase.010" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[222] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|phase.011" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[223] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|phase.100" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[224] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|phase.101" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[225] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|req" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[226] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|rst" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[227] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|sel" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[228] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[229] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[10]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[230] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[11]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[231] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[12]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[232] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[13]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[233] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[14]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[234] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[15]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[235] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[236] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[237] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[238] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[239] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[240] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[241] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[242] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[243] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[9]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[244] -to "dataController_top:dc0|ncr5380:scsi|scsi_bsy" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[245] -to "user_io:user_io|bit_cnt[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[246] -to "user_io:user_io|bit_cnt[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[247] -to "user_io:user_io|bit_cnt[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[248] -to "user_io:user_io|byte_cnt[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[249] -to "user_io:user_io|byte_cnt[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[250] -to "user_io:user_io|byte_cnt[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[251] -to "user_io:user_io|byte_cnt[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[252] -to "user_io:user_io|byte_cnt[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[253] -to "user_io:user_io|byte_cnt[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[254] -to "user_io:user_io|byte_cnt[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[255] -to "user_io:user_io|byte_cnt[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[256] -to "user_io:user_io|sd_din[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[257] -to "user_io:user_io|sd_din[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[258] -to "user_io:user_io|sd_din[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[259] -to "user_io:user_io|sd_din[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[260] -to "user_io:user_io|sd_din[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[261] -to "user_io:user_io|sd_din[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[262] -to "user_io:user_io|sd_din[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[263] -to "user_io:user_io|sd_din[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[264] -to "user_io:user_io|sd_din_strobe" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[218] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|io_wr" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[219] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|phase.000" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[220] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|phase.001" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[221] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|phase.010" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[222] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|phase.011" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[223] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|phase.100" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[224] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|phase.101" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[225] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|req" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[226] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|rst" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[227] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|sel" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[228] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[229] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[10]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[230] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[11]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[231] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[12]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[232] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[13]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[233] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[14]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[234] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[15]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[235] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[236] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[237] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[238] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[239] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[240] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[241] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[242] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[8]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[243] -to "dataController_top:dc0|ncr5380:scsi|scsi:scsi2|tlen[9]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[244] -to "dataController_top:dc0|ncr5380:scsi|scsi_bsy" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[245] -to "user_io:user_io|bit_cnt[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[246] -to "user_io:user_io|bit_cnt[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[247] -to "user_io:user_io|bit_cnt[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[248] -to "user_io:user_io|byte_cnt[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[249] -to "user_io:user_io|byte_cnt[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[250] -to "user_io:user_io|byte_cnt[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[251] -to "user_io:user_io|byte_cnt[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[252] -to "user_io:user_io|byte_cnt[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[253] -to "user_io:user_io|byte_cnt[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[254] -to "user_io:user_io|byte_cnt[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[255] -to "user_io:user_io|byte_cnt[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[256] -to "user_io:user_io|sd_din[0]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[257] -to "user_io:user_io|sd_din[1]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[258] -to "user_io:user_io|sd_din[2]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[259] -to "user_io:user_io|sd_din[3]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[260] -to "user_io:user_io|sd_din[4]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[261] -to "user_io:user_io|sd_din[5]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[262] -to "user_io:user_io|sd_din[6]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[263] -to "user_io:user_io|sd_din[7]" -section_id auto_signaltap_0
-set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[264] -to "user_io:user_io|sd_din_strobe" -section_id auto_signaltap_0
-set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=9780" -section_id auto_signaltap_0
-set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
-set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp
\ No newline at end of file
+set_global_assignment -name QIP_FILE "../../mist-modules/mist_core.qip"
+set_global_assignment -name SIGNALTAP_FILE out/cpu.stp
+set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
\ No newline at end of file
diff --git a/cores/plus_too/plusToo_top.sdc b/cores/plus_too/plusToo_top.sdc
index 8691306..ea16f36 100644
--- a/cores/plus_too/plusToo_top.sdc
+++ b/cores/plus_too/plusToo_top.sdc
@@ -38,17 +38,19 @@ set_time_format -unit ns -decimal_places 3
 # Create Clock
 #**************************************************************
 
-create_clock -name {altera_reserved_tck} -period 100.000 -waveform { 0.000 50.000 } [get_ports {altera_reserved_tck}]
-create_clock -name {clk50} -period 20.000 -waveform { 0.000 10.000 } [get_ports {clk50}]
-create_clock -name {dataController_top:dc0|clkPhase[1]} -period 123.076 -waveform { 0.000 61.538 } [get_registers { dataController_top:dc0|clkPhase[1] }]
-
+
+create_clock -name "CLOCK_27" -period 37.037 [get_ports {CLOCK_27[0]}]
+create_clock -name {SPI_SCK}  -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}]
+
 
 #**************************************************************
 # Create Generated Clock
 #**************************************************************
 
-create_generated_clock -name {clock325MHz:cs0|altpll:altpll_component|_clk0} -source [get_pins {cs0|altpll_component|pll|inclk[0]}] -duty_cycle 50.000 -multiply_by 13 -divide_by 20 -master_clock {clk50} [get_pins {cs0|altpll_component|pll|clk[0]}] 
-
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
 
 #**************************************************************
 # Set Clock Latency
@@ -78,7 +80,7 @@ create_generated_clock -name {clock325MHz:cs0|altpll:altpll_component|_clk0} -so
 # Set Clock Groups
 #**************************************************************
 
-set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}] 
+set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {cs0|altpll_component|auto_generated|pll1|clk[*]}]
 
 
 #**************************************************************
@@ -109,3 +111,17 @@ set_clock_groups -asynchronous -group [get_clocks {altera_reserved_tck}]
 # Set Input Transition
 #**************************************************************
 
+
+# SDRAM delays
+set_input_delay -clock [get_clocks {cs0|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports {SDRAM_CLK}] -max 6.4 [get_ports SDRAM_DQ[*]]
+set_input_delay -clock [get_clocks {cs0|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports {SDRAM_CLK}] -min 3.2 [get_ports SDRAM_DQ[*]]
+
+set_output_delay -clock [get_clocks {cs0|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+set_output_delay -clock [get_clocks {cs0|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}]
+
+# VGA delayes
+set_output_delay -clock [get_clocks {cs0|altpll_component|auto_generated|pll1|clk[1]}] -max 0 [get_ports {VGA_*}]
+set_output_delay -clock [get_clocks {cs0|altpll_component|auto_generated|pll1|clk[1]}] -min -5 [get_ports {VGA_*}]
+
+set_multicycle_path -to {VGA_*[*]} -setup 2
+set_multicycle_path -to {VGA_*[*]} -hold 1
diff --git a/cores/plus_too/plusToo_top.v b/cores/plus_too/plusToo_top.sv
similarity index 65%
rename from cores/plus_too/plusToo_top.v
rename to cores/plus_too/plusToo_top.sv
index 41c14ff..11c95d8 100644
--- a/cores/plus_too/plusToo_top.v
+++ b/cores/plus_too/plusToo_top.sv
@@ -39,6 +39,8 @@ module plusToo_top(
   input wire            CONF_DATA0  // SPI_SS for user_io
   );
 
+assign LED = ~(dio_download || |(diskAct ^ diskMotor));
+
 // ------------------------------ Plus Too Bus Timing ---------------------------------
 // for stability and maintainability reasons the whole timing has been simplyfied:
 //                00           01             10           11
@@ -48,28 +50,6 @@ module plusToo_top(
 //                        |                    |      |
 //                      video                 cpu    cpu
 //                       read                write   read
-  
-// include the OSD into the video data path
-osd #(10,0,2) osd (
-   .pclk       ( clk32        ),
-
-   // spi for OSD
-   .sdi        ( SPI_DI       ),
-   .sck        ( SPI_SCK      ),
-   .ss         ( SPI_SS3      ),
-
-   .red_in     ( { red, 2'b00 }   ),
-   .green_in   ( { green, 2'b00 } ),
-   .blue_in    ( { blue, 2'b00 }  ),
-   .hs_in      ( hsync        ),
-   .vs_in      ( vsync        ),
-
-   .red_out    ( VGA_R        ),
-   .green_out  ( VGA_G        ),
-   .blue_out   ( VGA_B        ),
-   .hs_out     ( VGA_HS       ),
-   .vs_out     ( VGA_VS       )
-);
 
 // -------------------------------------------------------------------------
 // ------------------------------ data_io ----------------------------------
@@ -92,21 +72,24 @@ wire dsk_ext_ins = dsk_ext_ds || dsk_ext_ss;
 
 // at the end of a download latch file size
 // diskEject is set by macos on eject
-always @(negedge dio_download or posedge diskEject[0]) begin
+reg dio_download_d;
+always @(posedge clk32) dio_download_d <= dio_download;
+
+always @(posedge clk32) begin
 	if(diskEject[0]) begin
 		dsk_int_ds <= 1'b0;
 		dsk_int_ss <= 1'b0;
-	end else if(dio_index == 1) begin
+	end else if(~dio_download && dio_download_d && dio_index == 1) begin
 		dsk_int_ds <= (dio_addr == 409599);   // double sides disk, addr counts words, not bytes
 		dsk_int_ss <= (dio_addr == 204799);   // single sided disk
 	end
 end	
-	
-always @(negedge dio_download or posedge diskEject[1]) begin
+
+always @(posedge clk32) begin
 	if(diskEject[1]) begin
 		dsk_ext_ds <= 1'b0;
 		dsk_ext_ss <= 1'b0;
-	end else if(dio_index == 2) begin
+	end else if(~dio_download && dio_download_d && dio_index == 2) begin
 		dsk_ext_ds <= (dio_addr == 409599);   // double sided disk, addr counts words, not bytes
 		dsk_ext_ss <= (dio_addr == 204799);   // single sided disk
 	end
@@ -142,37 +125,26 @@ wire [3:0] key = 4'd0;
 // send to the VGA
 wire hsync;
 wire vsync;
-wire [3:0] red;
-wire [3:0] green;
-wire [3:0] blue;
 	 
 // ps2 interface for mouse, to be mapped into user_io
 wire mouseClk;
 wire mouseData;
 wire keyClk;
 wire keyData;
-	
+
 	// synthesize a 32.5 MHz clock
 	wire clk64;
 	wire pll_locked;
-	
-	reg clk32; 
-	always @(posedge clk64)
-		clk32 <= !clk32;
-	
+	wire clk32;
+
 	pll cs0(
 		.inclk0	( CLOCK_27[0]	),
-		.c0		( clk64			), 	
-		.c1	   ( SDRAM_CLK    ),
+		.c0		( clk64			),
+		.c1     ( clk32         ),
 		.locked	( pll_locked	)
 	);
-	
-	// generate ~16kHz for ps2
-	wire ps2_clk = ps2_clk_div[8];
-	reg [8:0] ps2_clk_div;
-	always @(posedge clk8)
-		ps2_clk_div <= ps2_clk_div + 9'd1;
-	
+	assign SDRAM_CLK = clk64;
+
 	// set the real-world inputs to sane defaults
 	localparam serialIn = 1'b0,
 				  configROMSize = 1'b1;  // 128K ROM
@@ -182,6 +154,7 @@ wire keyData;
 	// interconnects
 	// CPU
 	wire clk8, _cpuReset, _cpuUDS, _cpuLDS, _cpuRW;
+	wire clk8_en_p, clk8_en_n;
 	wire [2:0] _cpuIPL;
 	wire [7:0] cpuAddrHi;
 	wire [23:0] cpuAddr;
@@ -211,79 +184,81 @@ wire keyData;
 	wire [21:0] dskReadAddrInt;
 	wire dskReadAckExt;
 	wire [21:0] dskReadAddrExt;
-	
-	// convert 1-bit pixel data to 4:4:4 RGB
-	assign red[3:0] =   { pixelOut, pixelOut, pixelOut, pixelOut };
-	assign green[3:0] = { pixelOut, pixelOut, pixelOut, pixelOut };
-	assign blue[3:0] =  { pixelOut, pixelOut, pixelOut, pixelOut };
-	
+
 	// the configuration string is returned to the io controller to allow
 	// it to control the menu on the OSD 
 	parameter CONF_STR = {
-        "PLUS_TOO;;",
-        "F1,DSK;",
-        "F2,DSK;",
-		  "S3,IMG;",
-		  "O4,Memory,1MB,4MB;",
-		  "O5,Speed,Normal,Turbo;",
-        "T6,Reset"
+		"PLUS_TOO;;",
+		"F1,DSK;",
+		"F2,DSK;",
+		"S0,IMG;",
+		"O4,Memory,1MB,4MB;",
+		"O5,Speed,Normal,Turbo;",
+		"O67,CPU,68000,68010,68020;",
+        "T0,Reset"
 	};
-	
+
 	wire status_mem = status[4];
 	wire status_turbo = status[5];
-	wire status_reset = status[6];
-	
-	parameter CONF_STR_LEN = 10+7+7+7+18+22+8;
+	wire [1:0] status_cpu = status[7:6];
+	wire status_reset = status[0];
 
 	// the status register is controlled by the on screen display (OSD)
 	wire [7:0] status;
 	wire [1:0] buttons;
+	wire       ypbpr;
 
 	wire [31:0] io_lba;
-	wire io_rd;
-	wire io_wr;
-	wire io_ack;
-	wire [7:0] io_din;
-	wire io_din_strobe;
-	wire [7:0] io_dout;
-	wire io_dout_strobe;
- 
+	wire [1:0] io_rd;
+	wire [1:0] io_wr;
+	wire       io_ack;
+	wire [1:0] img_mounted;
+	wire [31:0] img_size;
+	wire [7:0] sd_buff_dout;
+	wire       sd_buff_wr;
+	wire [8:0] sd_buff_addr;
+	wire [7:0] sd_buff_din;
+
 	// include user_io module for arm controller communication
-	user_io #(.STRLEN(CONF_STR_LEN)) user_io ( 
-		.conf_str   	( CONF_STR   	  ),
+	user_io #(.STRLEN($size(CONF_STR)>>3)) user_io (
+		.clk_sys        ( clk32          ),
+		.clk_sd         ( clk32          ),
+		.conf_str       ( CONF_STR       ),
 
-		.SPI_CLK    	( SPI_SCK    	  ),	
-		.SPI_SS_IO  	( CONF_DATA0 	  ),
-		.SPI_MISO   	( SPI_DO     	  ),
-		.SPI_MOSI   	( SPI_DI     	  ),
+		.SPI_CLK        ( SPI_SCK        ),	
+		.SPI_SS_IO      ( CONF_DATA0     ),
+		.SPI_MISO       ( SPI_DO         ),
+		.SPI_MOSI       ( SPI_DI         ),
 
-      .status     	( status     	  ),
-      .buttons    	( buttons     	  ),
-                 
-      // ps2 interface
-      .ps2_clk    	( ps2_clk     	  ),
-      .ps2_kbd_clk	( keyClk      	  ),
-      .ps2_kbd_data	( keyData 		  ),
-		.ps2_mouse_clk ( mouseClk		  ),
-      .ps2_mouse_data( mouseData	     ),
+		.status         ( status         ),
+		.buttons        ( buttons        ),
+		.ypbpr          ( ypbpr          ),
+
+		// ps2 interface
+		.ps2_kbd_clk    ( keyClk         ),
+		.ps2_kbd_data   ( keyData        ),
+		.ps2_mouse_clk  ( mouseClk       ),
+		.ps2_mouse_data ( mouseData	     ),
 
 		// SD/block device interface
-		.sd_lba        ( io_lba         ),
-		.sd_rd         ( io_rd          ),
-      .sd_wr         ( io_wr          ),
-      .sd_ack        ( io_ack         ),
-      .sd_conf       ( 1'b0           ),
-      .sd_sdhc       ( 1'b1           ),
-      .sd_dout       ( io_din         ),
-      .sd_dout_strobe( io_din_strobe  ),
-      .sd_din        ( io_dout        ),
-      .sd_din_strobe ( io_dout_strobe )
+		.img_mounted    ( img_mounted    ),
+		.img_size       ( img_size       ),
+		.sd_lba         ( io_lba         ),
+		.sd_rd          ( io_rd          ),
+		.sd_wr          ( io_wr          ),
+		.sd_ack         ( io_ack         ),
+		.sd_conf        ( 1'b0           ),
+		.sd_sdhc        ( 1'b1           ),
+		.sd_dout        ( sd_buff_dout   ),
+		.sd_dout_strobe ( sd_buff_wr     ),
+		.sd_buff_addr   ( sd_buff_addr   ),
+		.sd_din         ( sd_buff_din    )
 	);
 
 	wire [1:0] cpu_busstate;
-	wire cpu_clkena = cpuBusControl || (cpu_busstate == 2'b01);
-	TG68KdotC_Kernel #(0,0,0,0,0,0) m68k (
-        .clk            ( clk8           ),
+	wire cpu_clkena = clk8_en_p && (cpuBusControl || (cpu_busstate == 2'b01));
+	TG68KdotC_Kernel #(2,2,2,2,2,2,0,0) m68k (
+        .clk            ( clk32          ),
         .nReset         ( _cpuReset      ),
         .clkena_in      ( cpu_clkena     ), 
         .data_in        ( dataControllerDataOut ),
@@ -291,8 +266,8 @@ wire keyData;
         .IPL_autovector ( 1'b1           ),
         .berr           ( 1'b0           ),
         .clr_berr       ( 1'b0           ),
-        .CPU            ( 2'b00          ),   // 00=68000
-        .addr           ( {cpuAddrHi, cpuAddr} ),
+        .CPU            ( { status_cpu[1], |status_cpu } ),   // 00->68000  01->68010  11->68020
+        .addr_out       ( {cpuAddrHi, cpuAddr} ),
         .data_write     ( cpuDataOut     ),
         .nUDS           ( _cpuUDS        ),
         .nLDS           ( _cpuLDS        ),
@@ -300,11 +275,12 @@ wire keyData;
         .busstate       ( cpu_busstate   ), // 00-> fetch code 10->read data 11->write data 01->no memaccess
         .nResetOut      (                ),
         .FC             (                )
-);
+	);
 
-	
 	addrController_top ac0(
-		.clk8(clk8), 
+		.clk(clk32),
+		.clk8_en_p(clk8_en_p),
+		.clk8_en_n(clk8_en_n),
 		.cpuAddr(cpuAddr), 
 		._cpuUDS(_cpuUDS),
 		._cpuLDS(_cpuLDS),
@@ -340,23 +316,26 @@ wire keyData;
 		.dskReadAddrExt(dskReadAddrExt),
 		.dskReadAckExt(dskReadAckExt)
 	);
-	
+
 	wire [1:0] diskEject;
-	
+	wire [1:0] diskMotor, diskAct;
+
 	// addional ~8ms delay in reset
 	wire rom_download = dio_download && (dio_index == 0);
 	wire n_reset = (rst_cnt == 0);
 	reg [15:0] rst_cnt;
 	reg last_mem_config;
-	always @(posedge clk8) begin
-		last_mem_config <= status_mem;
+	always @(posedge clk32) begin
+		if (clk8_en_p) begin
+			last_mem_config <= status_mem;
 	
-		// various sources can reset the mac
-		if(!pll_locked || status[0] || status_reset || buttons[1] || 
-			rom_download || (last_mem_config != status_mem)) 
-			rst_cnt <= 16'd65535;
-		else if(rst_cnt != 0)
-			rst_cnt <= rst_cnt - 16'd1;
+			// various sources can reset the mac
+			if(!pll_locked || status_reset || buttons[1] || 
+				rom_download || (last_mem_config != status_mem)) 
+				rst_cnt <= 16'd65535;
+			else if(rst_cnt != 0)
+				rst_cnt <= rst_cnt - 16'd1;
+		end
 	end
 
 	wire [10:0] audio;
@@ -370,8 +349,10 @@ wire keyData;
 
 	dataController_top dc0(
 		.clk32(clk32), 
-		.clk8(clk8),  
-		._systemReset(n_reset), 
+		.clk8(clk8),
+		.clk8_en_p(clk8_en_p),
+		.clk8_en_n(clk8_en_n),
+		._systemReset(n_reset),
 		._cpuReset(_cpuReset), 
 		._cpuIPL(_cpuIPL),
 		._cpuUDS(_cpuUDS), 
@@ -390,26 +371,26 @@ wire keyData;
 		.videoBusControl(videoBusControl),
 		.memoryDataOut(memoryDataOut),
 		.memoryDataIn(sdram_do),
-		
+
 		// peripherals
 		.keyClk(keyClk), 
 		.keyData(keyData), 
 		.mouseClk(mouseClk),
 		.mouseData(mouseData),
 		.serialIn(serialIn), 
-		
+
 		// video
 		._hblank(_hblank),
 		._vblank(_vblank), 
 		.pixelOut(pixelOut),
 		.loadPixels(loadPixels),
-		
+
 		.memoryOverlayOn(memoryOverlayOn),
 
 		.audioOut(audio),
 		.snd_alt(snd_alt),
 		.loadSound(loadSound),
-		
+
 		// floppy disk interface
 		.insertDisk( { dsk_ext_ins, dsk_int_ins} ),
 		.diskSides( { dsk_ext_ds, dsk_int_ds} ),
@@ -418,18 +399,59 @@ wire keyData;
 		.dskReadAckInt(dskReadAckInt),
 		.dskReadAddrExt(dskReadAddrExt),
 		.dskReadAckExt(dskReadAckExt),
+		.diskMotor(diskMotor),
+		.diskAct(diskAct),
 
 		// block device interface for scsi disk
-		.io_lba 			( io_lba 			),
-		.io_rd 			( io_rd 				),
-		.io_wr 			( io_wr 				),
-		.io_ack 			( io_ack				),
-		.io_din 			( io_din				),
-		.io_din_strobe ( io_din_strobe	),
-		.io_dout 		( io_dout			),
-		.io_dout_strobe( io_dout_strobe	)
+		.img_mounted  ( img_mounted  ),
+		.img_size     ( img_size     ),
+		.io_lba       ( io_lba       ),
+		.io_rd        ( io_rd        ),
+		.io_wr        ( io_wr        ),
+		.io_ack       ( io_ack       ),
+		.sd_buff_addr ( sd_buff_addr ),
+		.sd_buff_dout ( sd_buff_dout ),
+		.sd_buff_din  ( sd_buff_din  ),
+		.sd_buff_wr   ( sd_buff_wr   )
 	);
-		
+
+// video output
+mist_video #(.COLOR_DEPTH(1)) mist_video (
+	.clk_sys     ( clk32      ),
+
+	// OSD SPI interface
+	.SPI_SCK     ( SPI_SCK    ),
+	.SPI_SS3     ( SPI_SS3    ),
+	.SPI_DI      ( SPI_DI     ),
+
+	// 0 = HVSync 31KHz, 1 = CSync 15KHz
+	// no scandoubler for plus_too
+	.scandoubler_disable ( 1'b1 ),
+	// disable csync without scandoubler
+	.no_csync    ( 1'b1       ),
+	// YPbPr always uses composite sync
+	.ypbpr       ( ypbpr      ),
+	// Rotate OSD [0] - rotate [1] - left or right
+	.rotate      ( 2'b00      ),
+	// composite-like blending
+	.blend       ( 1'b0       ),
+
+	// video in
+	.R           ( pixelOut   ),
+	.G           ( pixelOut   ),
+	.B           ( pixelOut   ),
+
+	.HSync       ( hsync      ),
+	.VSync       ( vsync      ),
+
+	// MiST video output signals
+	.VGA_R       ( VGA_R      ),
+	.VGA_G       ( VGA_G      ),
+	.VGA_B       ( VGA_B      ),
+	.VGA_VS      ( VGA_VS     ),
+	.VGA_HS      ( VGA_HS     )
+);
+
 // sdram used for ram/rom maps directly into 68k address space
 wire download_cycle = dio_download && dioBusControl;
 
@@ -440,7 +462,6 @@ wire [1:0] sdram_ds = download_cycle?2'b11:{ !_memoryUDS, !_memoryLDS };
 wire sdram_we = download_cycle?dio_write:!_ramWE;
 wire sdram_oe = download_cycle?1'b0:(!_ramOE || !_romOE);
 
-
 // during rom/disk download ffff is returned so the screen is black during download
 // "extra rom" is used to hold the disk image. It's expected to be byte wide and
 // we thus need to properly demultiplex the word returned from sdram in that case
@@ -449,35 +470,35 @@ wire [15:0] extra_rom_data_demux = memoryAddr[0]?
 wire [15:0] sdram_do = download_cycle?16'hffff:
 	(dskReadAckInt || dskReadAckExt)?extra_rom_data_demux:
 	sdram_out;
-	
+
 wire [15:0] sdram_out;
-	
+
 assign SDRAM_CKE         = 1'b1;
 
 sdram sdram (
 	// interface to the MT48LC16M16 chip
-   .sd_data        ( SDRAM_DQ                 ),
-   .sd_addr        ( SDRAM_A                  ),
-   .sd_dqm         ( {SDRAM_DQMH, SDRAM_DQML} ),
-   .sd_cs          ( SDRAM_nCS                ),
-   .sd_ba          ( SDRAM_BA                 ),
-   .sd_we          ( SDRAM_nWE                ),
-   .sd_ras         ( SDRAM_nRAS               ),
-   .sd_cas         ( SDRAM_nCAS               ),
+	.sd_data        ( SDRAM_DQ                 ),
+	.sd_addr        ( SDRAM_A                  ),
+	.sd_dqm         ( {SDRAM_DQMH, SDRAM_DQML} ),
+	.sd_cs          ( SDRAM_nCS                ),
+	.sd_ba          ( SDRAM_BA                 ),
+	.sd_we          ( SDRAM_nWE                ),
+	.sd_ras         ( SDRAM_nRAS               ),
+	.sd_cas         ( SDRAM_nCAS               ),
 
-   // system interface
-   .clk_64         ( clk64                    ),
-   .clk_8          ( clk8                     ),
-   .init           ( !pll_locked              ),
+	// system interface
+	.clk_64         ( clk64                    ),
+	.clk_8          ( clk8                     ),
+	.init           ( !pll_locked              ),
 
-   // cpu/chipset interface
+	// cpu/chipset interface
 	// map rom to sdram word address $200000 - $20ffff
-  .din            ( sdram_din                 ),
-  .addr           ( sdram_addr                ),
-  .ds             ( sdram_ds                  ),
-  .we             ( sdram_we                  ),
-  .oe             ( sdram_oe                  ),
-  .dout           ( sdram_out                 )
+	.din            ( sdram_din                ),
+	.addr           ( sdram_addr               ),
+	.ds             ( sdram_ds                 ),
+	.we             ( sdram_we                 ),
+	.oe             ( sdram_oe                 ),
+	.dout           ( sdram_out                )
 );
 
 endmodule
diff --git a/cores/plus_too/ps2.v b/cores/plus_too/ps2.v
index 5c8aa7f..acc807d 100644
--- a/cores/plus_too/ps2.v
+++ b/cores/plus_too/ps2.v
@@ -12,24 +12,25 @@
  */
 
 module ps2(input	sysclk,
-	   input	reset,
+	input clk_en,
+	input reset,
 
 //	   inout	ps2dat,
 //	   inout	ps2clk,
-	   input	ps2dat,
-	   input	ps2clk,
+	input ps2dat,
+	input ps2clk,
 
-	   output	istrobe,
-	   output [7:0] ibyte,
+	output istrobe,
+	output [7:0] ibyte,
 
-	   input	oreq,
-	   input [7:0]	obyte,
-	   output	oack,
+	input	oreq,
+	input [7:0]	obyte,
+	output	oack,
 
-	   output	timeout,
+	output	timeout,
 
-	   output[1:0]	dbg_state
-	   );
+	output[1:0]	dbg_state
+	);
 
 	reg [7:0] 	clkbuf;
 	reg [7:0] 	datbuf;
@@ -54,7 +55,7 @@ module ps2(input	sysclk,
 	always@(posedge sysclk or posedge reset) begin
 		if (reset)
 		  state <= ps2_state_idle;
-		else begin
+		else if (clk_en) begin
 			if (timeout && !oreq)
 			  state <= ps2_state_idle;
 			else
@@ -93,7 +94,7 @@ module ps2(input	sysclk,
 	always@(posedge sysclk or posedge reset) begin
 		if (reset)
 		  shiftcnt <= 10;
-		else begin
+		else if (clk_en) begin
 			if (state == ps2_state_idle)
 			  shiftcnt <= 10;
 			else if (state == ps2_state_ring)
@@ -107,7 +108,7 @@ module ps2(input	sysclk,
 	always@(posedge sysclk or posedge reset) begin
 		if (reset)
 		  shiftreg <= 0;
-		else begin
+		else if (clk_en) begin
 			if (oreq)
 			  shiftreg <= { 1'b1, opar, obyte, 1'b0 };
 			else if (clkdown && state != ps2_state_ring)
@@ -128,7 +129,7 @@ module ps2(input	sysclk,
 			clkbuf <= 0;
 			clksync <= 0;
 			clkprev <= 0;
-		end else begin
+		end else if (clk_en) begin
 			clkprev <= clksync;			
 			clkbuf <= { clkbuf[6:0], ps2clk };
 			if (clkbuf[7:2] == 6'b000000)
@@ -144,7 +145,7 @@ module ps2(input	sysclk,
 		if (reset) begin
 			datbuf <= 0;
 			datsync <= 0;
-		end else begin
+		end else if (clk_en) begin
 			datbuf <= { datbuf[6:0], ps2dat };
 			if (datbuf[7:2] == 6'b000000)
 			  datsync <= 0;
@@ -161,7 +162,7 @@ module ps2(input	sysclk,
 	always@(posedge sysclk or posedge reset) begin
 		if (reset)
 		  timecnt <= 0;
-		else begin
+		else if (clk_en) begin
 			if (clkdown | oreq)
 			  timecnt <= 0;
 			else
diff --git a/cores/plus_too/ps2_kbd.v b/cores/plus_too/ps2_kbd.v
index 11a7f1c..02037c0 100644
--- a/cores/plus_too/ps2_kbd.v
+++ b/cores/plus_too/ps2_kbd.v
@@ -4,16 +4,17 @@
  * PS2 Keyboard to Mac interface module
  */
 module ps2_kbd(	input			sysclk,
-		input			reset,
+		input  clk_en,
+		input  reset,
 
-		inout			ps2dat,
-		inout			ps2clk,
+		inout  ps2dat,
+		inout  ps2clk,
 		 
-	   	input [7:0]		data_out,
-		input			strobe_out,
+	   	input [7:0] data_out,
+		input strobe_out,
 
-		output [7:0]		data_in,
-		output 			strobe_in
+		output [7:0] data_in,
+		output strobe_in
 );
 
 	reg [8:0] 		keymac;
@@ -49,16 +50,17 @@ module ps2_kbd(	input			sysclk,
 	wire [1:0] 		dbg_lowstate;
 	
 	ps2 ps20(.sysclk(sysclk),
-		 .reset(reset),
-		 .ps2dat(ps2dat),
-		 .ps2clk(ps2clk),
-		 .istrobe(istrobe),
-		 .ibyte(ibyte),
-		 .oreq(oreq),
-		 .obyte(obyte),
-		 .oack(oack),
-		 .timeout(timeout),
-		 .dbg_state(dbg_lowstate));
+		.clk_en(clk_en),
+		.reset(reset),
+		.ps2dat(ps2dat),
+		.ps2clk(ps2clk),
+		.istrobe(istrobe),
+		.ibyte(ibyte),
+		.oreq(oreq),
+		.obyte(obyte),
+		.oack(oack),
+		.timeout(timeout),
+		.dbg_state(dbg_lowstate));
 	
 	/* --- PS2 side State machine ---
 	 *
@@ -148,17 +150,17 @@ module ps2_kbd(	input			sysclk,
 	always@(posedge sysclk or posedge reset)
 	  if (reset)
 	    state <= ps2k_state_wait;  // ps2k_state_init
-	  else
+	  else if (clk_en)
 	    state <= next;	
 	always@(posedge sysclk or posedge reset)
 	  if (reset)
 	    oreq <= 0;
-	  else
+	  else if (clk_en)
 	    oreq <= nreq;
 	always@(posedge sysclk or posedge reset)
 	  if (reset)
 	    obyte <= 0;
-	  else
+	  else if (clk_en)
 	    obyte <= nbyte;
 
 	assign got_key = (state == ps2k_state_wait) && istrobe;
@@ -172,7 +174,7 @@ module ps2_kbd(	input			sysclk,
 		  extended <= 0;
 		  keybreak <= 0;	
 		  capslock <= 0;
-	  end else if (got_key) begin
+	  end else if (clk_en && got_key) begin
 		  if (got_break)
 		    keybreak <= 1;
 		  else if (got_extend)
@@ -196,7 +198,7 @@ module ps2_kbd(	input			sysclk,
 		  cmd_instant <= 0;
 		  cmd_model <= 0;
 		  cmd_test <= 0;
-	  end else begin
+	  end else if (clk_en) begin
 		  if (strobe_out) begin
 			  cmd_inquiry <= 0;
 			  cmd_instant <= 0;
@@ -218,12 +220,12 @@ module ps2_kbd(	input			sysclk,
 	always@(posedge sysclk or posedge reset)
 	  if (reset)
 	    pacetimer <= 0;
-	  else begin
+	  else if (clk_en) begin
 		  /* reset counter on command from Mac */
 		  if (strobe_out)
 		    pacetimer <= 0;		  
 		  else if (!tick_long)
-		    pacetimer <= pacetimer + 1;
+		    pacetimer <= pacetimer + 1'd1;
 	  end
 	assign tick_long  = pacetimer == 22'h3fffff;
 	assign tick_short = pacetimer == 22'h000fff;
@@ -232,7 +234,7 @@ module ps2_kbd(	input			sysclk,
 	always@(posedge sysclk or posedge reset)
 	  if (reset)
 	    inquiry_active <= 0;
-	  else begin
+	  else if (clk_en) begin
 		  if (strobe_out | strobe_in)
 		    inquiry_active <= 0;
 		  else if (tick_short)
@@ -250,24 +252,24 @@ module ps2_kbd(	input			sysclk,
 	/* Handle key_pending, and multi-byte keypad responses */
 	reg keypad_byte2;
 	always @(posedge sysclk or posedge reset)
-	  if (reset) begin
-	    key_pending <= 0;
-		 keypad_byte2 <= 0;
-	  end
-	  else begin
-		  if (cmd_model | cmd_test)
-				key_pending <= 0;		 
-		  else if (pop_key) begin
-		    if (keymac[8] & !keypad_byte2)
-				keypad_byte2 <= 1;
-		    else begin
-				key_pending <= 0;	
-				keypad_byte2 <= 0;
-		    end				
-		  end			 
-		  else if (!key_pending & got_key && !got_break && !got_extend && !ignore_capslock)
-		    key_pending <= 1;			 
-	  end
+		if (reset) begin
+			key_pending <= 0;
+			keypad_byte2 <= 0;
+		end
+		else if (clk_en) begin
+			if (cmd_model | cmd_test)
+				key_pending <= 0;
+			else if (pop_key) begin
+				if (keymac[8] & !keypad_byte2)
+					keypad_byte2 <= 1;
+				else begin
+					key_pending <= 0;
+					keypad_byte2 <= 0;
+				end
+			end
+			else if (!key_pending & got_key && !got_break && !got_extend && !ignore_capslock)
+				key_pending <= 1;
+		end
 	
 	/* Data to Mac */
 	assign data_in = cmd_test 	? 8'h7d :
@@ -279,7 +281,7 @@ module ps2_kbd(	input			sysclk,
 	 * differently
 	 */
 	always @(posedge sysclk)
-	  if (got_key && !key_pending) begin
+	  if (clk_en && got_key && !key_pending) begin
 		  case({extended,ibyte}) // Scan Code Set 2
 			  9'h000:		keymac[8:0] <= 9'h07b;
 			  9'h001:		keymac[8:0] <= 9'h07b;	//F9
diff --git a/cores/plus_too/ps2_mouse.v b/cores/plus_too/ps2_mouse.v
index 41cedfa..14a8d2c 100644
--- a/cores/plus_too/ps2_mouse.v
+++ b/cores/plus_too/ps2_mouse.v
@@ -12,17 +12,19 @@
  * PS2 Mouse to Mac interface module
  */
 module ps2_mouse(input	sysclk,
-		 input	reset,
+	input clk_en,
+	input reset,
 
-		 input	ps2dat,
-		 input	ps2clk,
-		 
-		 output	reg x1,
-		 output reg y1,
-		 output reg x2,
-		 output reg y2,
-		 output reg button
+	input ps2dat,
+	input ps2clk,
+
+	output reg x1,
+	output reg y1,
+	output reg x2,
+	output reg y2,
+	output reg button
 );
+
 	wire 		istrobe;
 	wire [7:0] 	ibyte;
 	wire		timeout;
@@ -40,19 +42,21 @@ module ps2_mouse(input	sysclk,
 	reg [11:0] 	clkdiv;
 	wire		tick;	
 	wire[1:0]	dbg_lowstate;
-	
+
 	ps2 ps20(.sysclk(sysclk),
-		 .reset(reset),
-		 .ps2dat(ps2dat),
-		 .ps2clk(ps2clk),
-		 .istrobe(istrobe),
-		 .ibyte(ibyte),
-		 .oreq(oreq),
-		 .obyte(obyte),
-		 .oack(oack),
-		 .timeout(timeout),
-		 .dbg_state(dbg_lowstate));
-	
+		.clk_en(clk_en),
+		.reset(reset),
+		.ps2dat(ps2dat),
+		.ps2clk(ps2clk),
+		.istrobe(istrobe),
+		.ibyte(ibyte),
+		.oreq(oreq),
+		.obyte(obyte),
+		.oack(oack),
+		.timeout(timeout),
+		.dbg_state(dbg_lowstate)
+	);
+
 	/* State machine:
 	 *
 	 *  - at state_init: wait for BAT reply
@@ -149,24 +153,26 @@ module ps2_mouse(input	sysclk,
 	always@(posedge sysclk or posedge reset)
 		if (reset)
 		  state <= ps2m_state_byte0; // ps2m_state_init
-		else
+		else if (clk_en)
 		  state <= next;
+
 	always@(posedge sysclk or posedge reset)
 		if (reset)
 		  oreq <= 0;
-		else
+		else if (clk_en)
 		  oreq <= nreq;
+
 	always@(posedge sysclk or posedge reset)
 		if (reset)
 		  obyte <= 0;
-		else
+		else if (clk_en)
 		  obyte <= nbyte;
 
 	/* Capture button state */
 	always@(posedge sysclk or posedge reset)
 		if (reset)
 		  button <= 1;
-		else if (istrobe && state == ps2m_state_byte0)
+		else if (clk_en && istrobe && state == ps2m_state_byte0)
 			if(ibyte[3])
 				button <= ~ibyte[0];		
 
@@ -174,7 +180,7 @@ module ps2_mouse(input	sysclk,
 	always@(posedge sysclk or posedge reset)
 		if (reset)
 		  clkdiv <= 0;
-		else
+		else if (clk_en)
 		  clkdiv <= clkdiv + 1'b1;
 	assign tick = clkdiv == 0;
 
@@ -183,7 +189,7 @@ module ps2_mouse(input	sysclk,
 		if (reset) begin
 			x1 <= 0;
 			x2 <= 0;
-		end else if (tick && xacc != 0) begin
+		end else if (clk_en && tick && xacc != 0) begin
 			x1 <= ~x1;
 			x2 <= ~x1 ^ ~xacc[9];
 		end
@@ -192,7 +198,7 @@ module ps2_mouse(input	sysclk,
 		if (reset) begin
 			y1 <= 0;
 			y2 <= 0;
-		end else if (tick && yacc != 0) begin
+		end else if (clk_en && tick && yacc != 0) begin
 			y1 <= ~y1;
 			y2 <= ~y1 ^ ~yacc[9];
 		end
@@ -215,7 +221,7 @@ module ps2_mouse(input	sysclk,
 	always@(posedge sysclk or posedge reset) begin
 		if (reset)
 		  xacc <= 0;
-		else begin
+		else if (clk_en) begin
 			/* Add movement, convert to a 10-bit number if not over */
 			if (istrobe && state == ps2m_state_byte1 && xacc[8] == xacc[9])
 				xacc <= xacc + { xsign, xsign, ibyte };
@@ -229,7 +235,7 @@ module ps2_mouse(input	sysclk,
 	always@(posedge sysclk or posedge reset) begin
 		if (reset)
 		  yacc <= 0;
-		else begin
+		else if (clk_en) begin
 			/* Add movement, convert to a 10-bit number if not over*/
 			if (istrobe && state == ps2m_state_byte2 && yacc[8] == yacc[9])
 				yacc <= yacc + { ysign, ysign, ibyte };
diff --git a/cores/plus_too/scc.v b/cores/plus_too/scc.v
index df1822d..92a0323 100644
--- a/cores/plus_too/scc.v
+++ b/cores/plus_too/scc.v
@@ -12,48 +12,49 @@
  * for now, it's all very simplified
  */
 
-module scc(input	sysclk,
-	   input	reset_hw,
+module scc
+(
+	input clk,
+	input cep,
+	input cen,
+
+	input	reset_hw,
 
-	   /* Bus interface. 2-bit address, to be wired
-	    * appropriately upstream (to A1..A2).
-	    */
-	   input	cs,
-	   input	we,
-	   input [1:0]	rs, /* [1] = data(1)/ctl [0] = a_side(1)/b_side */
-	   input [7:0]	wdata,
-	   output [7:0]	rdata,
-	   output	_irq,
+	/* Bus interface. 2-bit address, to be wired
+	 * appropriately upstream (to A1..A2).
+	 */
+	input	cs,
+	input	we,
+	input [1:0]	rs, /* [1] = data(1)/ctl [0] = a_side(1)/b_side */
+	input [7:0]	wdata,
+	output [7:0]	rdata,
+	output	_irq,
 
-	   /* A single serial port on Minimig */
-	   input	rxd,
-	   output	txd,
-	   input	cts, /* normally wired to device DTR output
-			      * on Mac cables. That same line is also
-			      * connected to the TRxC input of the SCC
-			      * to do fast clocking but we don't do that
-			      * here
-			      */
-	   output	rts, /* on a real mac this activates line
-			      * drivers when low */
+	/* A single serial port on Minimig */
+	input	rxd,
+	output	txd,
+	input	cts, /* normally wired to device DTR output
+				* on Mac cables. That same line is also
+				* connected to the TRxC input of the SCC
+				* to do fast clocking but we don't do that
+				* here
+				*/
+	output	rts, /* on a real mac this activates line
+				* drivers when low */
 
-	   /* DCD for both ports are hijacked by mouse interface */
-	   input	dcd_a, /* We don't synchronize those inputs */
-	   input	dcd_b,
+	/* DCD for both ports are hijacked by mouse interface */
+	input	dcd_a, /* We don't synchronize those inputs */
+	input	dcd_b,
 
-	   /* Write request */
-	   output	wreq
-	   );
+	/* Write request */
+	output	wreq
+);
 
 	/* Register access is semi-insane */
 	reg [3:0]	rindex;
 	reg [3:0]	rindex_latch;
 	wire 		wreg_a;
 	wire 		wreg_b;
-	wire 		wdata_a;
-	wire 		wdata_b;
-	wire 		rdata_a;
-	wire 		rdata_b;
 
 	/* Resets via WR9, one clk pulses */
 	wire		reset_a;
@@ -83,23 +84,15 @@ module scc(input	sysclk,
 	reg [7:0] 	wr1_a;
 	reg [7:0] 	wr1_b;
 	reg [7:0] 	wr2;
-	reg [7:0] 	wr3_a;
-	reg [7:0] 	wr3_b;
-	reg [7:0] 	wr4_a;
-	reg [7:0] 	wr4_b;
 	reg [7:0] 	wr5_a;
 	reg [7:0] 	wr5_b;
 	reg [7:0] 	wr6_a;
 	reg [7:0] 	wr6_b;
-	reg [7:0] 	wr7_a;
-	reg [7:0] 	wr7_b;
 	reg [7:0] 	wr8_a;
 	reg [7:0] 	wr8_b;
 	reg [5:0] 	wr9;
 	reg [7:0] 	wr10_a;
 	reg [7:0] 	wr10_b;
-	reg [7:0] 	wr11_a;
-	reg [7:0] 	wr11_b;
 	reg [7:0] 	wr12_a;
 	reg [7:0] 	wr12_b;
 	reg [7:0] 	wr13_a;
@@ -135,23 +128,18 @@ module scc(input	sysclk,
 	/* Register/Data access helpers */
 	assign wreg_a  = cs & we & (~rs[1]) &  rs[0];
 	assign wreg_b  = cs & we & (~rs[1]) & ~rs[0];
-	assign wdata_a = cs & we & (rs[1] | (rindex == 8)) &  rs[0];
-	assign wdata_b = cs & we & (rs[1] | (rindex == 8)) & ~rs[0];
-	assign rdata_a = cs & (~we) & (rs[1] | (rindex == 8)) &  rs[0];
-	assign rdata_b = cs & (~we) & (rs[1] | (rindex == 8)) & ~rs[0];
 
 	// make sure rindex changes after the cpu cycle has ended so
 	// read data is still stable while cpu advances
-	always@(negedge sysclk)
-		rindex <= rindex_latch;
+	always@(posedge clk) if(cen) rindex <= rindex_latch;
 
 	/* Register index is set by a write to WR0 and reset
 	 * after any subsequent write. We ignore the side
 	 */
-	always@(negedge sysclk or posedge reset) begin
+	always@(posedge clk or posedge reset) begin
 		if (reset)
 		  rindex_latch <= 0;
-		else if (cs && !rs[1]) begin
+		else if (cen && cs && !rs[1]) begin
 			/* Default, reset index */
 			rindex_latch <= 0;
 
@@ -179,20 +167,20 @@ module scc(input	sysclk,
 
 	/* WR1
 	 * Reset: bit 5 and 2 unchanged */
-	always@(negedge sysclk or posedge reset_hw) begin
+	always@(posedge clk or posedge reset_hw) begin
 		if (reset_hw)
 		  wr1_a <= 0;
-		else begin
+		else if(cen) begin
 			if (reset_a)
 			  wr1_a <= { 2'b00, wr1_a[5], 2'b00, wr1_a[2], 2'b00 };
 			else if (wreg_a && rindex == 1)
 			  wr1_a <= wdata;
 		end
 	end
-	always@(negedge sysclk or posedge reset_hw) begin
+	always@(posedge clk or posedge reset_hw) begin
 		if (reset_hw)
 		  wr1_b <= 0;
-		else begin
+		else if(cen) begin
 			if (reset_b)
 			  wr1_b <= { 2'b00, wr1_b[5], 2'b00, wr1_b[2], 2'b00 };
 			else if (wreg_b && rindex == 1)
@@ -203,78 +191,30 @@ module scc(input	sysclk,
 	/* WR2
 	 * Reset: unchanged 
 	 */
-	always@(negedge sysclk or posedge reset_hw) begin
+	always@(posedge clk or posedge reset_hw) begin
 		if (reset_hw)
 		  wr2 <= 0;
-		else if ((wreg_a || wreg_b) && rindex == 2)
+		else if (cen && (wreg_a || wreg_b) && rindex == 2)
 		  wr2 <= wdata;			
 	end
 
-	/* WR3
-	 * Reset: bit 0 to 0, otherwise unchanged.
-	 */
-	always@(negedge sysclk or posedge reset_hw) begin
-		if (reset_hw)
-		  wr3_a <= 0;
-		else begin
-			if (reset_a)
-			  wr3_a[0] <= 0;
-			else if (wreg_a && rindex == 3)
-			  wr3_a <= wdata;
-		end
-	end
-	always@(negedge sysclk or posedge reset_hw) begin
-		if (reset_hw)
-		  wr3_b <= 0;
-		else begin
-			if (reset_b)
-			  wr3_b[0] <= 0;
-			else if (wreg_b && rindex == 3)
-			  wr3_b <= wdata;
-		end
-	end
-
-	/* WR4
-	 * Reset: Bit 2 to 1, otherwise unchanged
-	 */
-	always@(negedge sysclk or posedge reset_hw) begin
-		if (reset_hw)
-		  wr4_a <= 0;
-		else begin
-			if (reset_a)
-			  wr4_a[2] <= 1;
-			else if (wreg_a && rindex == 4)
-			  wr4_a <= wdata;
-		end
-	end
-	always@(negedge sysclk or posedge reset_hw) begin
-		if (reset_hw)
-		  wr4_b <= 0;
-		else begin
-			if (reset_b)
-			  wr4_b[2] <= 1;
-			else if (wreg_b && rindex == 4)
-			  wr4_b <= wdata;
-		end
-	end
-
 	/* WR5
 	 * Reset: Bits 7,4,3,2,1 to 0
 	 */
-	always@(negedge sysclk or posedge reset_hw) begin
+	always@(posedge clk or posedge reset_hw) begin
 		if (reset_hw)
 		  wr5_a <= 0;
-		else begin
+		else if(cen) begin
 			if (reset_a)
 			  wr5_a <= { 1'b0, wr5_a[6:5], 4'b0000, wr5_a[0] };			
 			else if (wreg_a && rindex == 5)
 			  wr5_a <= wdata;
 		end
 	end
-	always@(negedge sysclk or posedge reset_hw) begin
+	always@(posedge clk or posedge reset_hw) begin
 		if (reset_hw)
 		  wr5_b <= 0;
-		else begin
+		else if(cen) begin
 			if (reset_b)
 			  wr5_b <= { 1'b0, wr5_b[6:5], 4'b0000, wr5_b[0] };			
 			else if (wreg_b && rindex == 5)
@@ -282,65 +222,33 @@ module scc(input	sysclk,
 		end
 	end
 
-	/* WR6
-	 * Reset: Unchanged.
-	 */
-	always@(negedge sysclk or posedge reset_hw) begin
-		if (reset_hw)
-		  wr6_a <= 0;
-		else if (wreg_a && rindex == 6)
-		  wr6_a <= wdata;
-	end
-	always@(negedge sysclk or posedge reset_hw) begin
-		if (reset_hw)
-		  wr6_b <= 0;
-		else if (wreg_b && rindex == 6)
-		  wr6_b <= wdata;
-	end
-
-	/* WR7
-	 * Reset: Unchanged.
-	 */
-	always@(negedge sysclk or posedge reset_hw) begin
-		if (reset_hw)
-		  wr7_a <= 0;
-		else if (wreg_a && rindex == 7)
-		  wr7_a <= wdata;
-	end
-	always@(negedge sysclk or posedge reset_hw) begin
-		if (reset_hw)
-		  wr7_b <= 0;
-		else if (wreg_b && rindex == 7)
-		  wr7_b <= wdata;
-	end
-	
 	/* WR9. Special: top bits are reset, handled separately, bottom
 	 * bits are only reset by a hw reset
 	 */
-	always@(negedge sysclk or posedge reset_hw) begin
+	always@(posedge clk or posedge reset_hw) begin
 		if (reset_hw)
 		  wr9 <= 0;
-		else if ((wreg_a || wreg_b) && rindex == 9)
+		else if (cen && (wreg_a || wreg_b) && rindex == 9)
 		  wr9 <= wdata[5:0];			
 	end
 
 	/* WR10
 	 * Reset: all 0, except chanel reset retains 6 and 5
 	 */
-	always@(negedge sysclk or posedge reset) begin
+	always@(posedge clk or posedge reset) begin
 		if (reset)
 		  wr10_a <= 0;
-		else begin
+		else if(cen) begin
 			if (reset_a)
 			  wr10_a <= { 1'b0, wr10_a[6:5], 5'b00000 };
 			else if (wreg_a && rindex == 10)
 			  wr10_a <= wdata;
 		end		
 	end
-	always@(negedge sysclk or posedge reset) begin
+	always@(posedge clk or posedge reset) begin
 		if (reset)
 		  wr10_b <= 0;
-		else begin
+		else if(cen) begin
 			if (reset_b)
 			  wr10_b <= { 1'b0, wr10_b[6:5], 5'b00000 };
 			else if (wreg_b && rindex == 10)
@@ -348,51 +256,35 @@ module scc(input	sysclk,
 		end		
 	end
 
-	/* WR11
-	 * Reset: On full reset only, not channel reset
-	 */
-	always@(negedge sysclk or posedge reset) begin
-		if (reset)
-		  wr11_a <= 8'b00001000;
-		else if (wreg_a && rindex == 11)
-		  wr11_a <= wdata;
-	end
-	always@(negedge sysclk or posedge reset) begin
-		if (reset)
-		  wr11_b <= 8'b00001000;
-		else if (wreg_b && rindex == 11)
-		  wr11_b <= wdata;
-	end
-
 	/* WR12
 	 * Reset: Unchanged
 	 */
-	always@(negedge sysclk or posedge reset_hw) begin
+	always@(posedge clk or posedge reset_hw) begin
 		if (reset_hw)
 		  wr12_a <= 0;
-		else if (wreg_a && rindex == 12)
+		else if (cen && wreg_a && rindex == 12)
 		  wr12_a <= wdata;
 	end
-	always@(negedge sysclk or posedge reset_hw) begin
+	always@(posedge clk or posedge reset_hw) begin
 		if (reset_hw)
 		  wr12_b <= 0;		
-		else if (wreg_b && rindex == 12)
+		else if (cen && wreg_b && rindex == 12)
 		  wr12_b <= wdata;
 	end
 
 	/* WR13
 	 * Reset: Unchanged
 	 */
-	always@(negedge sysclk or posedge reset_hw) begin
+	always@(posedge clk or posedge reset_hw) begin
 		if (reset_hw)
 		  wr13_a <= 0;
-		else if (wreg_a && rindex == 13)
+		else if (cen && wreg_a && rindex == 13)
 		  wr13_a <= wdata;
 	end
-	always@(negedge sysclk or posedge reset_hw) begin
+	always@(posedge clk or posedge reset_hw) begin
 		if (reset_hw)
 		  wr13_b <= 0;		
-		else if (wreg_b && rindex == 13)
+		else if (cen && wreg_b && rindex == 13)
 		  wr13_b <= wdata;
 	end
 
@@ -401,10 +293,10 @@ module scc(input	sysclk,
 	 * Chan reset also maitains bottom 2 bits, bit 4 also
 	 * reset to a different value
 	 */
-	always@(negedge sysclk or posedge reset_hw) begin
+	always@(posedge clk or posedge reset_hw) begin
 		if (reset_hw)
 		  wr14_a <= 0;
-		else begin
+		else if(cen) begin
 			if (reset)
 			  wr14_a <= { wr14_a[7:6], 6'b110000 };
 			else if (reset_a)
@@ -413,10 +305,10 @@ module scc(input	sysclk,
 			  wr14_a <= wdata;
 		end		
 	end
-	always@(negedge sysclk or posedge reset_hw) begin
+	always@(posedge clk or posedge reset_hw) begin
 		if (reset_hw)
 		  wr14_b <= 0;
-		else begin
+		else if(cen) begin
 			if (reset)
 			  wr14_b <= { wr14_b[7:6], 6'b110000 };
 			else if (reset_b)
@@ -427,11 +319,11 @@ module scc(input	sysclk,
 	end
 
 	/* WR15 */
-	always@(negedge sysclk or posedge reset) begin
+	always@(posedge clk or posedge reset) begin
 		if (reset) begin
 		  wr15_a <= 8'b11111000;
 		  wr15_b <= 8'b11111000;
-		end else if (rindex == 15) begin
+		end else if (cen && rindex == 15) begin
 		  if(wreg_a) wr15_a <= wdata;			
 		  if(wreg_b) wr15_b <= wdata;			
 		end
@@ -622,38 +514,42 @@ module scc(input	sysclk,
 	assign do_latch_b = latch_open_b & (dcd_ip_b /* | cts... */);
 
 	/* "Master" interrupt, set when latch close & WR1[0] is set */
-	always@(posedge sysclk or posedge reset) begin
+	always@(posedge clk or posedge reset) begin
 		if (reset)
 		  ex_irq_ip_a <= 0;
-		else if (do_extreset_a)
-		  ex_irq_ip_a <= 0;
-		else if (do_latch_a && wr1_a[0])
-		  ex_irq_ip_a <= 1;
+		else if(cep) begin
+			if (do_extreset_a)
+			  ex_irq_ip_a <= 0;
+			else if (do_latch_a && wr1_a[0])
+			  ex_irq_ip_a <= 1;
+		end
 	end
-	always@(posedge sysclk or posedge reset) begin
+	always@(posedge clk or posedge reset) begin
 		if (reset)
 		  ex_irq_ip_b <= 0;
-		else if (do_extreset_b)
-		  ex_irq_ip_b <= 0;
-		else if (do_latch_b && wr1_b[0])
-		  ex_irq_ip_b <= 1;
+		else if(cep) begin
+			if (do_extreset_b)
+			  ex_irq_ip_b <= 0;
+			else if (do_latch_b && wr1_b[0])
+			  ex_irq_ip_b <= 1;
+		end
 	end
 
 	/* Latch open/close control */
-	always@(posedge sysclk or posedge reset) begin
+	always@(posedge clk or posedge reset) begin
 		if (reset)
 		  latch_open_a <= 1;
-		else begin
+		else if(cep) begin
 			if (do_extreset_a)
 			  latch_open_a <= 1;
 			else if (do_latch_a)
 			  latch_open_a <= 0;
 		end
 	end
-	always@(posedge sysclk or posedge reset) begin
+	always@(posedge clk or posedge reset) begin
 		if (reset)
 		  latch_open_b <= 1;
-		else begin
+		else if(cep) begin
 			if (do_extreset_b)
 			  latch_open_b <= 1;
 			else if (do_latch_b)
@@ -662,27 +558,27 @@ module scc(input	sysclk,
 	end
 
 	/* Latches proper */
-	always@(posedge sysclk or posedge reset) begin
+	always@(posedge clk or posedge reset) begin
 		if (reset) begin
 			dcd_latch_a <= 0;
 			/* cts ... */
-		end else begin
+		end else if(cep) begin
 			if (do_latch_a)
 			  dcd_latch_a <= dcd_a;
 			/* cts ... */
 		end
 	end
-	always@(posedge sysclk or posedge reset) begin
+	always@(posedge clk or posedge reset) begin
 		if (reset) begin
 			dcd_latch_b <= 0;			
 			/* cts ... */
-		end else begin
+		end else if(cep) begin
 			if (do_latch_b)
 			  dcd_latch_b <= dcd_b;
 			/* cts ... */
 		end
 	end
-	
+
 	/* NYI */
 	assign txd = 1;
 	assign rts = 1;
diff --git a/cores/plus_too/scsi.v b/cores/plus_too/scsi.v
index 548c38c..2e08d4c 100644
--- a/cores/plus_too/scsi.v
+++ b/cores/plus_too/scsi.v
@@ -1,390 +1,348 @@
-/* verilator lint_off UNUSED */
-/* verilator lint_off SYNCASYNCNET */
-
-// scsi.v
-// implements a target only scsi device
-  
-module scsi(input       sysclk,
-
-	    // scsi interface
-	    input 	  rst, // bus reset from initiator
-	    input 	  sel,
-	    input 	  atn, // initiator requests to send a message
-	    output 	  bsy, // target holds bus
-	    
-	    output 	  msg,
-	    output 	  cd,
-	    output 	  io,
-	    
-	    output 	  req,
-	    input 	  ack, // initiator acknowledges a request
-	    
-	    input [7:0]   din, // data from initiator to target
-	    output [7:0]  dout, // data from target to initiator
-	    
-	    // interface to io controller 
-	    output [31:0] io_lba,
-	    output reg 	  io_rd,
-	    output reg 	  io_wr,
-	    input 	  io_ack,
-	    
-	    // data sent to io controller
-            output reg [7:0]  io_dout,
-            input 	  io_dout_strobe,
-
-	    // data coming in from io controller
-            input [7:0]   io_din,
-            input 	  io_din_strobe
-
-    );
-
-   
-   // SCSI device id
-   parameter ID = 0; 
-
-   `define PHASE_IDLE        3'd0
-   `define PHASE_CMD_IN      3'd1
-   `define PHASE_DATA_OUT    3'd2
-   `define PHASE_DATA_IN     3'd3
-   `define PHASE_STATUS_OUT  3'd4
-   `define PHASE_MESSAGE_OUT 3'd5
-   reg [2:0]  phase;
-
-	reg cmd_in;
-	always @(posedge sysclk)
-		cmd_in <= (phase == `PHASE_CMD_IN);
-		
-   // ---------------- buffer read engine -----------------------
-   // the buffer itself. Can hold one sector
-   reg [7:0]  buffer_out [511:0];
-   reg [8:0]  buffer_out_rptr;
-   reg 	      buffer_out_read_strobe;
-   
-   always @(posedge io_dout_strobe or posedge cmd_cpl_strobe) begin
-      if(cmd_cpl_strobe) buffer_out_rptr <= 9'd0;
-      else			       begin	
-			io_dout <= buffer_out[buffer_out_rptr];
-			buffer_out_rptr <= buffer_out_rptr + 9'd1;
-		end
-   end
-
-   
-   // ---------------- buffer write engine -----------------------
-   // the buffer itself. Can hold one sector
-   reg [7:0]  buffer_in [511:0];
-   reg [8:0]  buffer_in_wptr;
-   reg 	      buffer_in_write_strobe;
-
-	always @(posedge io_din_strobe)
-		buffer_in[buffer_in_wptr] <= io_din;	
-
-	wire cmd_cpl_strobe = cmd_in && cmd_cpl;
-   always @(negedge io_din_strobe or posedge cmd_cpl_strobe) begin
-      if(cmd_cpl_strobe) buffer_in_wptr <= 9'd0;
-      else			       buffer_in_wptr <= buffer_in_wptr + 9'd1;
-   end
-
-   // status replies
-   reg [7:0]  status;
-   `define STATUS_OK 8'h00
-   `define STATUS_CHECK_CONDITION 8'h02
-
-   // message codes
-   `define MSG_CMD_COMPLETE 8'h00
-	
-   // drive scsi signals according to phase
-   assign msg = (phase == `PHASE_MESSAGE_OUT);
-   assign cd = (phase == `PHASE_CMD_IN) || (phase == `PHASE_STATUS_OUT) || (phase == `PHASE_MESSAGE_OUT);
-   assign io = (phase == `PHASE_DATA_OUT) || (phase == `PHASE_STATUS_OUT) || (phase == `PHASE_MESSAGE_OUT);
-   assign req = (phase != `PHASE_IDLE) && !ack && !io_rd && !io_wr; 
-   assign bsy = (phase != `PHASE_IDLE);
-
-   assign dout = (phase == `PHASE_STATUS_OUT)?status:
-		 (phase == `PHASE_MESSAGE_OUT)?`MSG_CMD_COMPLETE:
-		 (phase == `PHASE_DATA_OUT)?cmd_dout:
-		 8'h00;
-
-   // de-multiplex different data sources
-   wire [7:0] cmd_dout =
-	      cmd_read?buffer_dout:
-	      cmd_inquiry?inquiry_dout:
-	      cmd_read_capacity?read_capacity_dout:
-	      cmd_mode_sense?mode_sense_dout:
-	      8'h00;
-   
-   // output of inquiry command, identify as "SEAGATE ST225N"
-   wire [7:0] inquiry_dout =
-	      (data_cnt == 32'd4 )?8'd32:  // length
-
-	      (data_cnt == 32'd8 )?" ":(data_cnt == 32'd9 )?"S":
-	      (data_cnt == 32'd10)?"E":(data_cnt == 32'd11)?"A":
-	      (data_cnt == 32'd12)?"G":(data_cnt == 32'd13)?"A":
-	      (data_cnt == 32'd14)?"T":(data_cnt == 32'd15)?"E":
-	      (data_cnt == 32'd16)?" ":(data_cnt == 32'd17)?" ":
-	      (data_cnt == 32'd18)?" ":(data_cnt == 32'd19)?" ":
-	      (data_cnt == 32'd20)?" ":(data_cnt == 32'd21)?" ":
-	      (data_cnt == 32'd22)?" ":(data_cnt == 32'd23)?" ":
-	      (data_cnt == 32'd24)?" ":(data_cnt == 32'd25)?" ":
-
-	      (data_cnt == 32'd26)?"S":(data_cnt == 32'd27)?"T":
-	      (data_cnt == 32'd28)?"2":(data_cnt == 32'd29)?"2":
-	      (data_cnt == 32'd30)?"5":(data_cnt == 32'd31)?"N":
-	      8'h00;
-
-   // output of read capacity command
-   wire [31:0] capacity = 32'd41056;   // 40960 + 96 blocks = 20MB
-   wire [31:0] capacity_m1 = capacity - 32'd1;
-   wire [7:0] read_capacity_dout =
-	      (data_cnt == 32'd0 )?capacity_m1[31:24]:
-	      (data_cnt == 32'd1 )?capacity_m1[23:16]:
-	      (data_cnt == 32'd2 )?capacity_m1[15:8]:
-	      (data_cnt == 32'd3 )?capacity_m1[7:0]:
-	      (data_cnt == 32'd6 )?8'd2:             // 512 bytes per sector
-	      8'h00;
-
-   wire [7:0] mode_sense_dout =
-	      (data_cnt == 32'd3 )?8'd8:
-	      (data_cnt == 32'd5 )?capacity[23:16]:
-	      (data_cnt == 32'd6 )?capacity[15:8]:
-	      (data_cnt == 32'd7 )?capacity[7:0]:
-	      (data_cnt == 32'd10 )?8'd2:
-	      8'h00;
-
-   // clock data out of buffer to allow for embedded ram
-   reg [7:0] buffer_dout;
-   wire      buffer_out_clk = req && !io_rd;
-   always @(posedge sysclk) // buffer_out_clk)
-     buffer_dout <= buffer_in[data_cnt];
-
-   // debug signals
-   reg [7:0]  dbg_cmds /* synthesis noprune */;
-   always @(posedge cmd_cpl or posedge rst) begin
-      if(rst) dbg_cmds <= 8'd0;
-		else    dbg_cmds <= dbg_cmds + 8'd1;
-	end
-   
-   // buffer to store incoming commands
-   reg [3:0]  cmd_cnt;
-   reg [7:0]  cmd [9:0];
-
-	/* ----------------------- request data from/to io controller ----------------------- */
-	
-	// base address of current block. Subtract one when writing since the writing happens
-   // after a block has been transferred and data_cnt has thus already been increased by 512
-   assign io_lba = lba + { 9'd0, data_cnt[31:9] } -
-		   (cmd_write ? 32'd1 : 32'd0);
-   
-   reg 	      req_io_rd, req_io_wr;
-   always @(posedge sysclk) begin
-      // generate an io_rd signal whenever the first byte of a 512 byte block is required and io_wr whenever
-      // the last byte of a 512 byte block has been revceived
-     req_io_rd <= (phase == `PHASE_DATA_OUT) && cmd_read && (data_cnt[8:0] == 0) && !data_complete;
-      // generate an io_wr signal whenever a 512 byte block has been received or when the status
-      // phase of a write command has been reached
-     req_io_wr <= (((phase == `PHASE_DATA_IN) && (data_cnt[8:0] == 0) && (data_cnt != 0)) ||
-		  (phase == `PHASE_STATUS_OUT)) && cmd_write;
-   end
-      
-	always @(posedge req_io_rd or posedge io_ack) begin
-		if(io_ack) io_rd <= 1'b0;
-		else 	   io_rd <= 1'b1;
-	end
-	  
-	always @(posedge req_io_wr or posedge io_ack) begin
-		if(io_ack) io_wr <= 1'b0;
-		else 	   io_wr <= 1'b1;
-	end
-	  
-   // store incoming command in buffer
-   reg cmd_idle;
-	always @(posedge sysclk) 
-		cmd_idle <= (phase == `PHASE_IDLE);
-	
-	// store data on rising edge of ack, ...
-   always @(posedge ack) begin
-      if(phase == `PHASE_CMD_IN)
-			cmd[cmd_cnt] <= din;
-      if(phase == `PHASE_DATA_IN)
-			buffer_out[data_cnt] <= din;
-   end
-
-	// ... advance counter on falling edge
-   always @(negedge ack or posedge cmd_idle) begin
-      if(cmd_idle)				cmd_cnt <= 4'd0;
-      else if(cmd_cnt != 15)	cmd_cnt <= cmd_cnt + 4'd1;
-	end
-
-   // count data bytes. don't increase counter while we are waiting for data from
-   // the io controller
-   reg [31:0] 		 data_cnt;
-	reg        data_complete;
-
-   reg 		   data_io;
-	always @(posedge sysclk)
-		data_io <= (phase == `PHASE_DATA_OUT) || (phase == `PHASE_DATA_IN) || 
-			   (phase == `PHASE_STATUS_OUT) || (phase == `PHASE_MESSAGE_OUT);
-
-   // For block transfers tlen contains the number of 512 bytes blocks to transfer.
-   // Most other commands have the bytes length stored in the transfer length field.
-   // And some have a fixed length idependent from any header field.
-   // The data transfer has finished once the data counter reaches this
-   // number.
-      wire [31:0] data_len =
-	       cmd_read_capacity?32'd8:
-	       cmd_read?{ 7'd0, tlen, 9'd0 }:   // read command length is in 512 bytes blocks
-	       cmd_write?{ 7'd0, tlen, 9'd0 }:  // write command length is in 512 bytes blocks
-	       { 16'd0, tlen };                 // inquiry etc have length in bytes
-   
-   always @(negedge ack or negedge data_io) begin
-      if(!data_io) begin
-			data_cnt <= 32'd0;
-			data_complete <= 1'b0;
-      end else begin	
-			data_cnt <= data_cnt + 32'd1;
-			data_complete <= (data_len - 32'd1) == data_cnt;
-		end
-   end
-
-   // check whether status byte has been sent
-	wire status_out = (phase == `PHASE_STATUS_OUT);
-   reg status_sent;
-   always @(negedge ack or negedge status_out) begin
-      if(!status_out) 	status_sent <= 1'b0;
-      else	      		status_sent <= 1'b1;
-   end
-
-   // check whether message byte has been sent
-   reg message_sent;
-	wire message_out = (phase == `PHASE_MESSAGE_OUT);
-   always @(negedge ack or negedge message_out) begin
-      if(!message_out) 	message_sent <= 1'b0;
-      else	       		message_sent <= 1'b1;
-   end
-
-	/* ----------------------- command decoding ------------------------------- */
-
-   wire cmd_wr_x = cmd_cpl && cmd_write && (tlen > 1);
-   
-   
-   // parse commands
-   wire [7:0] op_code = cmd[0];
-   wire [2:0] cmd_group = op_code[7:5];
-   wire [4:0] cmd_code = op_code[4:0];
-
-   wire       cmd_unknown = cmd_cpl && !cmd_ok;
-   
-   // check if a complete command has been received
-   wire       cmd_cpl = cmd6_cpl || cmd10_cpl;
-   wire       cmd6_cpl = (cmd_group == 3'b000) && (cmd_cnt == 6);
-   wire       cmd10_cpl = ((cmd_group == 3'b010) || (cmd_group == 3'b001)) && (cmd_cnt == 10);
-
-   // https://en.wikipedia.org/wiki/SCSI_command
-   wire       cmd_read = cmd_read6 || cmd_read10;
-   wire       cmd_read6 = (op_code == 8'h08);
-   wire       cmd_read10 = (op_code == 8'h28);
-   wire       cmd_write = cmd_write6 || cmd_write10;
-   wire       cmd_write6 = (op_code == 8'h0a);
-   wire       cmd_write10 = (op_code == 8'h2a);
-   wire       cmd_inquiry = (op_code == 8'h12);
-   wire       cmd_format = (op_code == 8'h04);
-   wire       cmd_mode_select = (op_code == 8'h15);
-   wire       cmd_mode_sense = (op_code == 8'h1a);
-   wire       cmd_test_unit_ready = (op_code == 8'h00);
-   wire       cmd_read_capacity = (op_code == 8'h25);
-
-   // valid command in buffer? TODO: check for valid command parameters
-   wire       cmd_ok = cmd_read || cmd_write || cmd_inquiry || cmd_test_unit_ready || 
-	        cmd_read_capacity || cmd_mode_select || cmd_format || cmd_mode_sense;
-     
-   // latch parameters once command is complete
-   reg [31:0] lba;
-   reg [15:0] tlen;
-   reg [2:0]  lun;
-   
-   always @(posedge sysclk) begin
-		if(cmd_cpl && (phase == `PHASE_CMD_IN)) begin
-			lba <= cmd6_cpl?{11'd0, lba6}:lba10;
-			tlen <= cmd6_cpl?{7'd0, tlen6}:tlen10;
-			lun <= cmd6_cpl?lun6:3'd0;
-		end
-   end
-   
-   // logical block address
-   wire [7:0] cmd1 = cmd[1];
-   wire [2:0] lun6 = cmd1[7:5];
-   wire [20:0] lba6 = { cmd1[4:0], cmd[2], cmd[3] };
-   wire [31:0] lba10 = { cmd[2], cmd[3], cmd[4], cmd[5] };
-
-   // transfer length
-   wire [8:0]  tlen6 = (cmd[4] == 0)?9'd256:{1'b0,cmd[4]};
-   wire [15:0] tlen10 = { cmd[7], cmd[8] };
-
-
-	// the 5380 changes phase in the falling edge, thus we monitor it
-	// on the rising edge
-   always @(posedge sysclk) begin
-      if(rst) begin
-			phase <= `PHASE_IDLE;
-      end else begin
-//			case(phase)
-			if(phase == `PHASE_IDLE) begin
-				if(sel && din[ID])  // own id on bus during selection?
-					phase <= `PHASE_CMD_IN;
-			end
-			   
-			else if(phase == `PHASE_CMD_IN) begin
-				// check if a full command is in the buffer
-				if(cmd_cpl) begin
-					// is this a supported and valid command?
-					if(cmd_ok) begin
-						// yes, continue
-						status <= `STATUS_OK;
-
-						// continue according to command
-
-					        // these commands return data
-					        if(cmd_read || cmd_inquiry || cmd_read_capacity || cmd_mode_sense)
-						  phase <= `PHASE_DATA_OUT;
-					        // these commands receive dataa
-					        else if(cmd_write || cmd_mode_select)
-						  phase <= `PHASE_DATA_IN;
-					        // and all other valid commands are just "ok"
-						else 
-					          phase <= `PHASE_STATUS_OUT;
-					end else begin
-						// no, report failure
-						status <= `STATUS_CHECK_CONDITION;
-						phase <= `PHASE_STATUS_OUT;
-					end
-				end
-			end
-
-			else if(phase == `PHASE_DATA_OUT) begin
-				if(data_complete)
-					phase <= `PHASE_STATUS_OUT;
-			end
-
- 			else if(phase == `PHASE_DATA_IN) begin
-				if(data_complete)
-					phase <= `PHASE_STATUS_OUT;
-			end
-
-			else if(phase == `PHASE_STATUS_OUT) begin
-				if(status_sent)
-					phase <= `PHASE_MESSAGE_OUT;
-			end
-
-			else if(phase == `PHASE_MESSAGE_OUT) begin
-				if(message_sent)
-					phase <= `PHASE_IDLE;
-			end
-			
-			else
-				phase <= `PHASE_IDLE;  // should never happen
-	   
-//			endcase
-      end
-   end
-   
-   
-endmodule
+/* verilator lint_off UNUSED */
+/* verilator lint_off SYNCASYNCNET */
+
+// scsi.v
+// implements a target only scsi device
+  
+module scsi
+(
+	input      clk,
+
+	// scsi interface
+	input 	  rst, // bus reset from initiator
+	input 	  sel,
+	input 	  atn, // initiator requests to send a message
+	output 	  bsy, // target holds bus
+
+	output 	  msg,
+	output 	  cd,
+	output 	  io,
+
+	output 	  req,
+	input 	  ack, // initiator acknowledges a request
+
+	input   [7:0] din, // data from initiator to target
+	output  [7:0] dout, // data from target to initiator
+
+	// interface to io controller
+	input         img_mounted,
+	input  [23:0] img_blocks,
+	output [31:0] io_lba,
+	output reg 	  io_rd,
+	output reg 	  io_wr,
+	input         io_ack,
+
+	input      [8:0] sd_buff_addr,
+	input      [7:0] sd_buff_dout,
+	output reg [7:0] sd_buff_din,
+	input            sd_buff_wr
+);
+
+   
+// SCSI device id
+parameter [7:0] ID = 0; 
+
+`define PHASE_IDLE        3'd0
+`define PHASE_CMD_IN      3'd1
+`define PHASE_DATA_OUT    3'd2
+`define PHASE_DATA_IN     3'd3
+`define PHASE_STATUS_OUT  3'd4
+`define PHASE_MESSAGE_OUT 3'd5
+reg [2:0]  phase;
+
+// ---------------- buffer read engine -----------------------
+// the buffer itself. Can hold one sector
+reg [7:0] buffer_out [512];
+always @(posedge clk) sd_buff_din <= buffer_out[sd_buff_addr];
+
+// ---------------- buffer write engine ----------------------
+// the buffer itself. Can hold one sector
+reg [7:0] buffer_in [512];
+always @(posedge clk) if(sd_buff_wr) buffer_in[sd_buff_addr] <= sd_buff_dout;
+
+// -----------------------------------------------------------
+
+// status replies
+reg [7:0]  status;
+`define STATUS_OK 8'h00
+`define STATUS_CHECK_CONDITION 8'h02
+
+// message codes
+`define MSG_CMD_COMPLETE 8'h00
+	
+// drive scsi signals according to phase
+assign msg = (phase == `PHASE_MESSAGE_OUT);
+assign cd = (phase == `PHASE_CMD_IN) || (phase == `PHASE_STATUS_OUT) || (phase == `PHASE_MESSAGE_OUT);
+assign io = (phase == `PHASE_DATA_OUT) || (phase == `PHASE_STATUS_OUT) || (phase == `PHASE_MESSAGE_OUT);
+assign req = (phase != `PHASE_IDLE) && !ack && !io_rd && !io_wr && !io_ack; 
+assign bsy = (phase != `PHASE_IDLE);
+
+assign dout = (phase == `PHASE_STATUS_OUT)?status:
+	 (phase == `PHASE_MESSAGE_OUT)?`MSG_CMD_COMPLETE:
+	 (phase == `PHASE_DATA_OUT)?cmd_dout:
+	 8'h00;
+
+// de-multiplex different data sources
+wire [7:0] cmd_dout =
+		cmd_read?buffer_dout:
+		cmd_inquiry?inquiry_dout:
+		cmd_read_capacity?read_capacity_dout:
+		cmd_mode_sense?mode_sense_dout:
+		8'h00;
+
+// output of inquiry command, identify as "SEAGATE ST225N"
+wire [7:0] inquiry_dout =
+		(data_cnt == 32'd4 )?8'd32:  // length
+
+		(data_cnt == 32'd8 )?" ":(data_cnt == 32'd9 )?"S":
+		(data_cnt == 32'd10)?"E":(data_cnt == 32'd11)?"A":
+		(data_cnt == 32'd12)?"G":(data_cnt == 32'd13)?"A":
+		(data_cnt == 32'd14)?"T":(data_cnt == 32'd15)?"E":
+		(data_cnt == 32'd16)?" ":(data_cnt == 32'd17)?" ":
+		(data_cnt == 32'd18)?" ":(data_cnt == 32'd19)?" ":
+		(data_cnt == 32'd20)?" ":(data_cnt == 32'd21)?" ":
+		(data_cnt == 32'd22)?" ":(data_cnt == 32'd23)?" ":
+		(data_cnt == 32'd24)?" ":(data_cnt == 32'd25)?" ":
+
+		(data_cnt == 32'd26)?"S":(data_cnt == 32'd27)?"T":
+		(data_cnt == 32'd28)?"2":(data_cnt == 32'd29)?"2":
+		(data_cnt == 32'd30)?"5":(data_cnt == 32'd31)?"N" + ID:	// TESTING. ElectronAsh.
+		8'h00;
+
+// output of read capacity command
+//wire [31:0] capacity = 32'd41056;   // 40960 + 96 blocks = 20MB
+//wire [31:0] capacity = 32'd1024096;   // 1024000 + 96 blocks = 500MB
+reg [31:0] capacity;
+always @(posedge clk) begin
+	if (img_mounted) capacity <= img_blocks + 8'd96;
+end
+
+wire [31:0] capacity_m1 = capacity - 32'd1;
+wire [7:0] read_capacity_dout =
+		(data_cnt == 32'd0 )?capacity_m1[31:24]:
+		(data_cnt == 32'd1 )?capacity_m1[23:16]:
+		(data_cnt == 32'd2 )?capacity_m1[15:8]:
+		(data_cnt == 32'd3 )?capacity_m1[7:0]:
+		(data_cnt == 32'd6 )?8'd2:             // 512 bytes per sector
+		8'h00;
+
+wire [7:0] mode_sense_dout =
+		(data_cnt == 32'd3 )?8'd8:
+		(data_cnt == 32'd5 )?capacity[23:16]:
+		(data_cnt == 32'd6 )?capacity[15:8]:
+		(data_cnt == 32'd7 )?capacity[7:0]:
+		(data_cnt == 32'd10 )?8'd2:
+		8'h00;
+
+// clock data out of buffer to allow for embedded ram
+reg [7:0] buffer_dout;
+always @(posedge clk) buffer_dout <= buffer_in[data_cnt];
+
+// buffer to store incoming commands
+reg [3:0]  cmd_cnt;
+reg [7:0]  cmd [9:0];
+
+/* ----------------------- request data from/to io controller ----------------------- */
+
+// base address of current block. Subtract one when writing since the writing happens
+// after a block has been transferred and data_cnt has thus already been increased by 512
+assign io_lba = lba + { 9'd0, data_cnt[31:9] } -
+		(cmd_write ? 32'd1 : 32'd0);
+
+wire req_rd = ((phase == `PHASE_DATA_OUT) && cmd_read && (data_cnt[8:0] == 0) && !data_complete);
+wire req_wr = ((((phase == `PHASE_DATA_IN) && (data_cnt[8:0] == 0) && (data_cnt != 0)) || (phase == `PHASE_STATUS_OUT)) && cmd_write);
+always @(posedge clk) begin
+	reg old_rd, old_wr;
+
+	old_rd <= req_rd;
+	old_wr <= req_wr;
+	
+	if(io_ack) begin
+		io_rd <= 1'b0;
+		io_wr <= 1'b0;
+	end else begin
+		// generate an io_rd signal whenever the first byte of a 512 byte block is required and io_wr whenever
+		// the last byte of a 512 byte block has been revceived
+		if(~old_rd & req_rd) io_rd <= 1;
+
+		// generate an io_wr signal whenever a 512 byte block has been received or when the status
+		// phase of a write command has been reached
+		if(~old_wr & req_wr) io_wr <= 1;
+	end
+end
+
+reg  stb_ack;
+reg  stb_adv;
+always @(posedge clk) begin
+	reg old_ack;
+	
+	old_ack <= ack;
+	stb_ack <= (~old_ack & ack);
+	stb_adv <= stb_ack;
+end
+
+// store data on rising edge of ack, ...
+always @(posedge clk) begin
+	if(stb_ack) begin
+		if(phase == `PHASE_CMD_IN)  cmd[cmd_cnt] <= din;
+		if(phase == `PHASE_DATA_IN) buffer_out[data_cnt] <= din;
+	end
+end
+
+// ... advance counter on falling edge
+always @(posedge clk) begin
+	if(phase == `PHASE_IDLE) cmd_cnt <= 4'd0;
+	else if(stb_adv && (phase == `PHASE_CMD_IN) && (cmd_cnt != 15)) cmd_cnt <= cmd_cnt + 4'd1;
+end
+
+// count data bytes. don't increase counter while we are waiting for data from
+// the io controller
+reg [31:0] data_cnt;
+reg        data_complete;
+
+// For block transfers tlen contains the number of 512 bytes blocks to transfer.
+// Most other commands have the bytes length stored in the transfer length field.
+// And some have a fixed length idependent from any header field.
+// The data transfer has finished once the data counter reaches this
+// number.
+wire [31:0] data_len =
+		 cmd_read_capacity?32'd8:
+		 cmd_read?{ 7'd0, tlen, 9'd0 }:   // read command length is in 512 bytes blocks
+		 cmd_write?{ 7'd0, tlen, 9'd0 }:  // write command length is in 512 bytes blocks
+		 { 16'd0, tlen };                 // inquiry etc have length in bytes
+
+always @(posedge clk) begin
+	if((phase != `PHASE_DATA_OUT) && (phase != `PHASE_DATA_IN) && (phase != `PHASE_STATUS_OUT) && (phase != `PHASE_MESSAGE_OUT)) begin
+		data_cnt <= 0;
+		data_complete <= 0;
+	end else begin	
+		if(stb_adv)begin	
+			if(!data_complete) data_cnt <= data_cnt + 1'd1;
+			data_complete <= (data_len - 1'd1) == data_cnt;
+		end
+	end
+end
+
+// check whether status byte has been sent
+reg status_sent;
+always @(posedge clk) begin
+	if(phase != `PHASE_STATUS_OUT) status_sent <= 0;
+	else if(stb_adv) status_sent <= 1;
+end
+
+// check whether message byte has been sent
+reg message_sent;
+always @(posedge clk) begin
+	if(phase != `PHASE_MESSAGE_OUT) message_sent <= 0;
+	else if(stb_adv) message_sent <= 1;
+end
+
+/* ----------------------- command decoding ------------------------------- */
+
+
+// parse commands
+wire [7:0] op_code = cmd[0];
+wire [2:0] cmd_group = op_code[7:5];
+
+// check if a complete command has been received
+wire       cmd_cpl = cmd6_cpl || cmd10_cpl;
+wire       cmd6_cpl = (cmd_group == 3'b000) && (cmd_cnt == 6);
+wire       cmd10_cpl = ((cmd_group == 3'b010) || (cmd_group == 3'b001)) && (cmd_cnt == 10);
+
+// https://en.wikipedia.org/wiki/SCSI_command
+wire       cmd_read = cmd_read6 || cmd_read10;
+wire       cmd_read6 = (op_code == 8'h08);
+wire       cmd_read10 = (op_code == 8'h28);
+wire       cmd_write = cmd_write6 || cmd_write10;
+wire       cmd_write6 = (op_code == 8'h0a);
+wire       cmd_write10 = (op_code == 8'h2a);
+wire       cmd_inquiry = (op_code == 8'h12);
+wire       cmd_format = (op_code == 8'h04);
+wire       cmd_mode_select = (op_code == 8'h15);
+wire       cmd_mode_sense = (op_code == 8'h1a);
+wire       cmd_test_unit_ready = (op_code == 8'h00);
+wire       cmd_read_capacity = (op_code == 8'h25);
+
+// valid command in buffer? TODO: check for valid command parameters
+wire  cmd_ok = cmd_read || cmd_write || cmd_inquiry || cmd_test_unit_ready || 
+		  cmd_read_capacity || cmd_mode_select || cmd_format || cmd_mode_sense;
+
+// latch parameters once command is complete
+reg [31:0] lba;
+reg [15:0] tlen;
+
+always @(posedge clk) begin
+	if(cmd_cpl && (phase == `PHASE_CMD_IN)) begin
+		lba <= cmd6_cpl?{11'd0, lba6}:lba10;
+		tlen <= cmd6_cpl?{7'd0, tlen6}:tlen10;
+	end
+end
+   
+// logical block address
+wire [7:0] cmd1 = cmd[1];
+wire [20:0] lba6 = { cmd1[4:0], cmd[2], cmd[3] };
+wire [31:0] lba10 = { cmd[2], cmd[3], cmd[4], cmd[5] };
+
+// transfer length
+wire [8:0]  tlen6 = (cmd[4] == 0)?9'd256:{1'b0,cmd[4]};
+wire [15:0] tlen10 = { cmd[7], cmd[8] };
+
+
+// the 5380 changes phase in the falling edge, thus we monitor it
+// on the rising edge
+always @(posedge clk) begin
+	if(rst) begin
+		phase <= `PHASE_IDLE;
+	end else begin
+		if(phase == `PHASE_IDLE) begin
+			if(sel && din[ID])  // own id on bus during selection?
+				phase <= `PHASE_CMD_IN;
+		end
+
+		else if(phase == `PHASE_CMD_IN) begin
+			// check if a full command is in the buffer
+			if(cmd_cpl) begin
+				// is this a supported and valid command?
+				if(cmd_ok) begin
+					// yes, continue
+					status <= `STATUS_OK;
+
+					// continue according to command
+
+					// these commands return data
+					if(cmd_read || cmd_inquiry || cmd_read_capacity || cmd_mode_sense) phase <= `PHASE_DATA_OUT;
+					// these commands receive dataa
+					else if(cmd_write || cmd_mode_select) phase <= `PHASE_DATA_IN;
+					// and all other valid commands are just "ok"
+					else phase <= `PHASE_STATUS_OUT;
+				end else begin
+					// no, report failure
+					status <= `STATUS_CHECK_CONDITION;
+					phase <= `PHASE_STATUS_OUT;
+				end
+			end
+		end
+
+		else if(phase == `PHASE_DATA_OUT) begin
+			if(data_complete) phase <= `PHASE_STATUS_OUT;
+		end
+
+		else if(phase == `PHASE_DATA_IN) begin
+			if(data_complete) phase <= `PHASE_STATUS_OUT;
+		end
+
+		else if(phase == `PHASE_STATUS_OUT) begin
+			if(status_sent) phase <= `PHASE_MESSAGE_OUT;
+		end
+
+		else if(phase == `PHASE_MESSAGE_OUT) begin
+			if(message_sent) phase <= `PHASE_IDLE;
+		end
+		
+		else
+			phase <= `PHASE_IDLE;  // should never happen
+	end
+end
+   
+   
+endmodule
diff --git a/cores/plus_too/sdram.v b/cores/plus_too/sdram.v
index 1aad3bb..f9e1938 100644
--- a/cores/plus_too/sdram.v
+++ b/cores/plus_too/sdram.v
@@ -22,26 +22,26 @@
 module sdram (
 
 	// interface to the MT48LC16M16 chip
-	inout [15:0]  		sd_data,    // 16 bit bidirectional data bus
-	output reg [12:0]	sd_addr,    // 13 bit multiplexed address bus
-	output reg [1:0] 	sd_dqm,     // two byte masks
-	output reg [1:0] 	sd_ba,      // two banks
-	output 				sd_cs,      // a single chip select
-	output 				sd_we,      // write enable
-	output 				sd_ras,     // row address select
-	output 				sd_cas,     // columns address select
+	inout  reg [15:0]   sd_data,    // 16 bit bidirectional data bus
+	output reg [12:0]   sd_addr,    // 13 bit multiplexed address bus
+	output reg [1:0]    sd_dqm,     // two byte masks
+	output reg [1:0]    sd_ba,      // two banks
+	output              sd_cs,      // a single chip select
+	output              sd_we,      // write enable
+	output              sd_ras,     // row address select
+	output              sd_cas,     // columns address select
 
 	// cpu/chipset interface
-	input 		 		init,			// init signal after FPGA config to initialize RAM
-	input 		 		clk_64,		// sdram is accessed at 64MHz
-	input          	clk_8,      // 8MHz chipset clock to which sdram state machine is synchonized
-	
-	input [15:0]  		din,			// data input from chipset/cpu
-	output [15:0]     dout,			// data output to chipset/cpu
-	input [23:0]   	addr,       // 24 bit word address
-	input [1:0]    	ds,         // upper/lower data strobe
-	input 		 		oe,         // cpu/chipset requests read
-	input 		 		we          // cpu/chipset requests write
+	input               init,       // init signal after FPGA config to initialize RAM
+	input               clk_64,     // sdram is accessed at 64MHz
+	input               clk_8,      // 8MHz chipset clock to which sdram state machine is synchonized
+
+	input [15:0]        din,        // data input from chipset/cpu
+	output [15:0]       dout,       // data output to chipset/cpu
+	input [23:0]        addr,       // 24 bit word address
+	input [1:0]         ds,         // upper/lower data strobe
+	input               oe,         // cpu/chipset requests read
+	input               we          // cpu/chipset requests write
 );
 
 localparam RASCAS_DELAY   = 3'd2;   // tRCD=20ns -> 3 cycles@128MHz
@@ -113,12 +113,11 @@ assign sd_ras = sd_cmd[2];
 assign sd_cas = sd_cmd[1];
 assign sd_we  = sd_cmd[0];
 
-// drive ram data lines when writing, set them as inputs otherwise
-assign sd_data = we?din:16'bZZZZZZZZZZZZZZZZ;
 assign dout = sd_data;
 
 always @(posedge clk_64) begin
 	sd_cmd <= CMD_INHIBIT;  // default: idle
+	sd_data <= 16'bZZZZZZZZZZZZZZZZ;
 
 	if(reset != 0) begin
 		// initialization takes place at the end of the reset phase
@@ -128,38 +127,42 @@ always @(posedge clk_64) begin
 				sd_cmd <= CMD_PRECHARGE;
 				sd_addr[10] <= 1'b1;      // precharge all banks
 			end
-				
+
 			if(reset == 2) begin
 				sd_cmd <= CMD_LOAD_MODE;
 				sd_addr <= MODE;
 			end
-			
+
 		end
 	end else begin
 		// normal operation
-		
+
 		// -------------------  cpu/chipset read/write ----------------------
 		if(we || oe) begin
-		
+
 			// RAS phase
 			if(t == STATE_CMD_START) begin
 				sd_cmd <= CMD_ACTIVE;
 				sd_addr <= { 1'b0, addr[19:8] };
 				sd_ba <= addr[21:20];
-				
+
 				// always return both bytes in a read. The cpu may not
 				// need it, but the caches need to be able to store everything
 				if(!we) sd_dqm <= 2'b00;
 				else    sd_dqm <= ~ds;
 			end
-				
+
 			// CAS phase 
 			if(t == STATE_CMD_CONT) begin
 				sd_cmd <= we?CMD_WRITE:CMD_READ;
+				if (we) sd_data <= din;
 				sd_addr <= { 4'b0010, addr[22], addr[7:0] };  // auto precharge
 			end
+
+			// Data ready
+			//if (t == STATE_READ && !we) dout <= sd_data;
 		end
-		
+
 		// ------------------------ no access --------------------------
 		else begin
 			if(t == STATE_CMD_START)
@@ -168,6 +171,4 @@ always @(posedge clk_64) begin
 	end
 end
 
-
-
 endmodule
diff --git a/cores/plus_too/user_io.v b/cores/plus_too/user_io.v
deleted file mode 100644
index a87138b..0000000
--- a/cores/plus_too/user_io.v
+++ /dev/null
@@ -1,410 +0,0 @@
-//
-// user_io.v
-//
-// user_io for the MiST board
-// http://code.google.com/p/mist-board/
-//
-// Copyright (c) 2014 Till Harbaum <till@harbaum.org>
-//
-// This source file is free software: you can redistribute it and/or modify
-// it under the terms of the GNU General Public License as published
-// by the Free Software Foundation, either version 3 of the License, or
-// (at your option) any later version.
-//
-// This source file is distributed in the hope that it will be useful,
-// but WITHOUT ANY WARRANTY; without even the implied warranty of
-// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-// GNU General Public License for more details.
-//
-// You should have received a copy of the GNU General Public License
-// along with this program.  If not, see <http://www.gnu.org/licenses/>.
-//
-
-// parameter STRLEN and the actual length of conf_str have to match
- 
-module user_io #(parameter STRLEN=0) (
-	input [(8*STRLEN)-1:0] conf_str,
-
-	input      		SPI_CLK,
-	input      		SPI_SS_IO,
-	output     		reg SPI_MISO,
-	input      		SPI_MOSI,
-	
-	output reg [7:0] 	joystick_0,
-	output reg [7:0] 	joystick_1,
-	output reg [15:0] joystick_analog_0,
-	output reg [15:0] joystick_analog_1,
-	output [1:0] 		buttons,
-	output [1:0] 		switches,
-
-	output reg [7:0]   status,
-
-	// connection to sd card emulation
-	input [31:0]  sd_lba,
-	input         sd_rd,
-	input         sd_wr,
-	output reg	  sd_ack,
-	input         sd_conf,
-	input         sd_sdhc,
-	output [7:0]  sd_dout,  // valid on rising edge of sd_dout_strobe
-	output reg	  sd_dout_strobe,
-	input [7:0]   sd_din,
-	output reg 	  sd_din_strobe,
-	
-
-	// ps2 keyboard emulation
-	input 	  		ps2_clk,				// 12-16khz provided by core
-	output	 		ps2_kbd_clk,
-	output reg 		ps2_kbd_data,
-	output	 		ps2_mouse_clk,
-	output reg 		ps2_mouse_data,
-
-	// serial com port 
-	input [7:0]		serial_data,
-	input				serial_strobe
-);
-
-reg [6:0]         sbuf;
-reg [7:0]         cmd;
-reg [2:0] 	      bit_cnt;    // counts bits 0-7 0-7 ...
-reg [9:0]         byte_cnt;   // counts bytes
-reg [5:0]         joystick0;
-reg [5:0]         joystick1;
-reg [3:0] 	      but_sw;
-reg [2:0]         stick_idx;
-
-assign buttons = but_sw[1:0];
-assign switches = but_sw[3:2];
-assign sd_dout = { sbuf, SPI_MOSI};
-
-// this variant of user_io is for 8 bit cores (type == a4) only
-wire [7:0] core_type = 8'ha4;
-
-// command byte read by the io controller
-wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd };
-
-// filter spi clock. the 8 bit gate delay is ~2.5ns in total
-wire [7:0] spi_sck_D = { spi_sck_D[6:0], SPI_CLK } /* synthesis keep */;
-wire spi_sck = (spi_sck && spi_sck_D != 8'h00) || (!spi_sck && spi_sck_D == 8'hff);
-
-// drive MISO only when transmitting core id
-always@(negedge spi_sck or posedge SPI_SS_IO) begin
-	if(SPI_SS_IO == 1) begin
-	   SPI_MISO <= 1'bZ;
-	end else begin
-
-		// first byte returned is always core type, further bytes are 
-		// command dependent
-      if(byte_cnt == 0) begin
-		  SPI_MISO <= core_type[~bit_cnt];
-
-		end else begin
-			// reading serial fifo
-		   if(cmd == 8'h1b) begin
-				// send alternating flag byte and data
-				if(byte_cnt[0]) 	SPI_MISO <= serial_out_status[~bit_cnt];
-				else					SPI_MISO <= serial_out_byte[~bit_cnt];
-			end
-			
-			// reading config string
-		   else if(cmd == 8'h14) begin
-				// returning a byte from string
-				if(byte_cnt < STRLEN + 1)
-					SPI_MISO <= conf_str[{STRLEN - byte_cnt,~bit_cnt}];
-				else
-					SPI_MISO <= 1'b0;
-			end
-			
-			// reading sd card status
-		   else if(cmd == 8'h16) begin
-				if(byte_cnt == 1)
-					SPI_MISO <= sd_cmd[~bit_cnt];
-				else if((byte_cnt >= 2) && (byte_cnt < 6))
-					SPI_MISO <= sd_lba[{5-byte_cnt, ~bit_cnt}];
-				else
-					SPI_MISO <= 1'b0;
-			end
-			
-			// reading sd card write data
-		   else if(cmd == 8'h18)
-				SPI_MISO <= sd_din[~bit_cnt];
-				
-			else
-				SPI_MISO <= 1'b0;
-		end
-   end
-end
-
-// ---------------- PS2 ---------------------
-
-// 8 byte fifos to store ps2 bytes
-localparam PS2_FIFO_BITS = 3;
-
-// keyboard
-reg [7:0] ps2_kbd_fifo [(2**PS2_FIFO_BITS)-1:0];
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_kbd_tx_state;
-reg [7:0] ps2_kbd_tx_byte;
-reg ps2_kbd_parity;
-
-assign ps2_kbd_clk = ps2_clk || (ps2_kbd_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_kbd_r_inc;
-always@(posedge ps2_clk) begin
-	ps2_kbd_r_inc <= 1'b0;
-	
-	if(ps2_kbd_r_inc)
-		ps2_kbd_rptr <= ps2_kbd_rptr + 1;
-
-	// transmitter is idle?
-	if(ps2_kbd_tx_state == 0) begin
-		// data in fifo present?
-		if(ps2_kbd_wptr != ps2_kbd_rptr) begin
-			// load tx register from fifo
-			ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr];
-			ps2_kbd_r_inc <= 1'b1;
-			
-			// reset parity
-			ps2_kbd_parity <= 1'b1;
-			
-			// start transmitter
-			ps2_kbd_tx_state <= 4'd1;
-
-			// put start bit on data line
-			ps2_kbd_data <= 1'b0;			// start bit is 0
-		end
-	end else begin
-	
-		// transmission of 8 data bits
-		if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin
-			ps2_kbd_data <= ps2_kbd_tx_byte[0];			  // data bits
-			ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down
-			if(ps2_kbd_tx_byte[0]) 
-				ps2_kbd_parity <= !ps2_kbd_parity;
-		end
-
-		// transmission of parity
-		if(ps2_kbd_tx_state == 9)
-			ps2_kbd_data <= ps2_kbd_parity;
-			
-		// transmission of stop bit
-		if(ps2_kbd_tx_state == 10)
-			ps2_kbd_data <= 1'b1;			// stop bit is 1
-
-		// advance state machine
-		if(ps2_kbd_tx_state < 11)
-			ps2_kbd_tx_state <= ps2_kbd_tx_state + 4'd1;
-		else	
-			ps2_kbd_tx_state <= 4'd0;
-	
-	end
-end
-  
-// mouse
-reg [7:0] ps2_mouse_fifo [(2**PS2_FIFO_BITS)-1:0];
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr;
-reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr;
-
-// ps2 transmitter state machine
-reg [3:0] ps2_mouse_tx_state;
-reg [7:0] ps2_mouse_tx_byte;
-reg ps2_mouse_parity;
-
-assign ps2_mouse_clk = ps2_clk || (ps2_mouse_tx_state == 0);
-
-// ps2 transmitter
-// Takes a byte from the FIFO and sends it in a ps2 compliant serial format.
-reg ps2_mouse_r_inc;
-always@(posedge ps2_clk) begin
-	ps2_mouse_r_inc <= 1'b0;
-	
-	if(ps2_mouse_r_inc)
-		ps2_mouse_rptr <= ps2_mouse_rptr + 1;
-
-	// transmitter is idle?
-	if(ps2_mouse_tx_state == 0) begin
-		// data in fifo present?
-		if(ps2_mouse_wptr != ps2_mouse_rptr) begin
-			// load tx register from fifo
-			ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr];
-			ps2_mouse_r_inc <= 1'b1;
-			
-			// reset parity
-			ps2_mouse_parity <= 1'b1;
-			
-			// start transmitter
-			ps2_mouse_tx_state <= 4'd1;
-
-			// put start bit on data line
-			ps2_mouse_data <= 1'b0;			// start bit is 0
-		end
-	end else begin
-	
-		// transmission of 8 data bits
-		if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin
-			ps2_mouse_data <= ps2_mouse_tx_byte[0];			  // data bits
-			ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down
-			if(ps2_mouse_tx_byte[0]) 
-				ps2_mouse_parity <= !ps2_mouse_parity;
-		end
-
-		// transmission of parity
-		if(ps2_mouse_tx_state == 9)
-			ps2_mouse_data <= ps2_mouse_parity;
-			
-		// transmission of stop bit
-		if(ps2_mouse_tx_state == 10)
-			ps2_mouse_data <= 1'b1;			// stop bit is 1
-
-		// advance state machine
-		if(ps2_mouse_tx_state < 11)
-			ps2_mouse_tx_state <= ps2_mouse_tx_state + 4'd1;
-		else	
-			ps2_mouse_tx_state <= 4'd0;
-	
-	end
-end
-
-// fifo to receive serial data from core to be forwarded to io controller
-
-// 16 byte fifo to store serial bytes
-localparam SERIAL_OUT_FIFO_BITS = 6;
-reg [7:0] serial_out_fifo [(2**SERIAL_OUT_FIFO_BITS)-1:0];
-reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_wptr;
-reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_rptr;
- 
-wire serial_out_data_available = serial_out_wptr != serial_out_rptr;
-wire [7:0] serial_out_byte = serial_out_fifo[serial_out_rptr] /* synthesis keep */;
-wire [7:0] serial_out_status = { 7'b1000000, serial_out_data_available};
-
-// status[0] is reset signal from io controller and is thus used to flush
-// the fifo
-always @(posedge serial_strobe or posedge status[0]) begin
-	if(status[0] == 1) begin
-		serial_out_wptr <= 0;
-	end else begin 
-		serial_out_fifo[serial_out_wptr] <= serial_data;
-		serial_out_wptr <= serial_out_wptr + 1;
-	end
-end 
-
-always@(negedge spi_sck or posedge status[0]) begin
-	if(status[0] == 1) begin
-		serial_out_rptr <= 0;
-	end else begin
-		if((byte_cnt != 0) && (cmd == 8'h1b)) begin
-			// read last bit -> advance read pointer
-			if((bit_cnt == 7) && !byte_cnt[0] && serial_out_data_available)
-				serial_out_rptr <= serial_out_rptr + 1;
-		end
-	end
-end
-
-// SPI receiver
-always@(posedge spi_sck or posedge SPI_SS_IO) begin
-
-	if(SPI_SS_IO == 1) begin
-	   bit_cnt <= 3'd0;
-	   byte_cnt <= 10'd0;
-		sd_ack <= 1'b0;
-		sd_dout_strobe <= 1'b0;
-		sd_din_strobe <= 1'b0;
-	end else begin
-		sd_dout_strobe <= 1'b0;
-		sd_din_strobe <= 1'b0;
-		
-		if(bit_cnt != 7)
-			sbuf[6:0] <= { sbuf[5:0], SPI_MOSI };
-			
-		bit_cnt <= bit_cnt + 3'd1;
-		if((bit_cnt == 7)&&(byte_cnt != 10'd1023)) 
-			byte_cnt <= byte_cnt + 10'd1;
-
-		// finished reading command byte
-      if(bit_cnt == 7) begin
-			if(byte_cnt == 0) begin
-				cmd <= { sbuf, SPI_MOSI};
-			
-				// fetch first byte when sectore FPGA->IO command has been seen
-				if({ sbuf, SPI_MOSI} == 8'h18)
-					sd_din_strobe <= 1'b1;
-					
-				if(({ sbuf, SPI_MOSI} == 8'h17) || ({ sbuf, SPI_MOSI} == 8'h18))
-					sd_ack <= 1'b1;
-					
-			end else begin
-			
-				// buttons and switches
-				if(cmd == 8'h01)
-					but_sw <= { sbuf[2:0], SPI_MOSI }; 
-
-				if(cmd == 8'h02)
-					joystick_0 <= { sbuf, SPI_MOSI };
-				 
-				if(cmd == 8'h03)
-					joystick_1 <= { sbuf, SPI_MOSI };
-				 
-				if(cmd == 8'h04) begin
-					// store incoming ps2 mouse bytes 
-					ps2_mouse_fifo[ps2_mouse_wptr] <= { sbuf, SPI_MOSI }; 
-					ps2_mouse_wptr <= ps2_mouse_wptr + 1;
-				end
-
-				if(cmd == 8'h05) begin
-					// store incoming ps2 keyboard bytes 
-					ps2_kbd_fifo[ps2_kbd_wptr] <= { sbuf, SPI_MOSI }; 
-					ps2_kbd_wptr <= ps2_kbd_wptr + 1;
-				end
-				
-				if(cmd == 8'h15)
-					status <= { sbuf[6:0], SPI_MOSI };
-				
-				// send sector IO -> FPGA
-				if(cmd == 8'h17) begin
-					// flag that download begins
-					sd_dout_strobe <= 1'b1;
-				end
-				
-				// send sector FPGA -> IO
-				if((cmd == 8'h18) && (byte_cnt < 512))
-					sd_din_strobe <= 1'b1;
-				
-				// send SD config IO -> FPGA
-				if(cmd == 8'h19) begin
-					// flag that download begins
-					// sd card knows data is config if sd_dout_strobe is asserted
-					// with sd_ack still being inactive (low)
-					sd_dout_strobe <= 1'b1;
-				end
-				
-				// joystick analog
-				if(cmd == 8'h1a) begin
-					// first byte is joystick indes
-					if(byte_cnt == 1)
-						stick_idx <= { sbuf[1:0], SPI_MOSI };
-					else if(byte_cnt == 2) begin
-						// second byte is x axis
-						if(stick_idx == 0)
-							joystick_analog_0[15:8] <= { sbuf, SPI_MOSI };
-						else if(stick_idx == 1)
-							joystick_analog_1[15:8] <= { sbuf, SPI_MOSI };
-					end else if(byte_cnt == 3) begin
-						// third byte is y axis
-						if(stick_idx == 0)
-							joystick_analog_0[7:0] <= { sbuf, SPI_MOSI };
-						else if(stick_idx == 1)
-							joystick_analog_1[7:0] <= { sbuf, SPI_MOSI };
-					end
-				end
-
-			end
-		end
-	end
-end
-   
-endmodule
diff --git a/cores/plus_too/via.v b/cores/plus_too/via.v
index c96fb47..4b60d7b 100644
--- a/cores/plus_too/via.v
+++ b/cores/plus_too/via.v
@@ -100,7 +100,9 @@
 `define INT_T1				6
 
 module via(
-	input clk8,
+	input clk32,
+	input clk8_en_p,
+	input clk8_en_n,
 	input _reset,
 	input selectVIA,
 	input _cpuRW,
@@ -150,10 +152,10 @@ module via(
 	// shift register can be written by CPU and by external source
 	/* Write to SR (including external input) */
 	assign kbd_out_data = viaSR;
-   always @(negedge clk8 or negedge _reset) begin
+   always @(posedge clk32 or negedge _reset) begin
 		if (_reset == 1'b0)
 			viaSR <= 8'b0;           
-		else begin
+		else if (clk8_en_n) begin
 			if((selectVIA == 1'b1) && (_cpuUDS == 1'b0) && 
 				(_cpuRW == 1'b0) && (cpuAddrRegHi == 4'hA))
 						viaSR <= dataInHi;
@@ -164,10 +166,10 @@ module via(
 	end
 
 	/* Generate sr_out_strobe */
-   always @(negedge clk8 or negedge _reset) begin
+   always @(posedge clk32 or negedge _reset) begin
 	if (_reset == 1'b0)
 		kbd_out_strobe <= 1'b0;                
-   else begin
+   else if (clk8_en_n) begin
 		if((selectVIA == 1'b1) && (_cpuUDS == 1'b0) && 
 			(_cpuRW == 1'b0) && (cpuAddrRegHi == 4'hA) && 
 			(viaACR[4:2] == 3'b111))
@@ -179,29 +181,33 @@ module via(
  	
 	// divide by 10 clock divider for the VIA timers: 0.78336 MHz
 	reg [3:0] clkDiv;
-	always @(posedge clk8) begin
-		if (clkDiv == 4'h9)
-			clkDiv <= 0;
-		else
-			clkDiv <= clkDiv + 1'b1;
+	always @(posedge clk32) begin
+		if (clk8_en_p) begin
+			if (clkDiv == 4'h9)
+				clkDiv <= 0;
+			else
+				clkDiv <= clkDiv + 1'b1;
+		end
 	end
 	wire timerStrobe = (clkDiv == 0);
 	
 	// store previous vblank value, for edge detection
 	reg _lastVblank;
-	always @(negedge clk8) begin
-		_lastVblank <= _vblank;
+	always @(posedge clk32) begin
+		if (clk8_en_n) _lastVblank <= _vblank;
 	end
 
 	// count vblanks, and set 1 second interrupt after 60 vblanks
 	reg [5:0] vblankCount;
-	always @(negedge clk8) begin
-		if (_vblank == 1'b0 && _lastVblank == 1'b1) begin
-			if (vblankCount != 59) begin
-				vblankCount <= vblankCount + 1'b1;
-			end
-			else begin
-				vblankCount <= 6'h0;
+	always @(posedge clk32) begin
+		if (clk8_en_n) begin
+			if (_vblank == 1'b0 && _lastVblank == 1'b1) begin
+				if (vblankCount != 59) begin
+					vblankCount <= vblankCount + 1'b1;
+				end
+				else begin
+					vblankCount <= 6'h0;
+				end
 			end
 		end
 	end
@@ -209,7 +215,7 @@ module via(
 	
 	// register write
 	wire loadT2 = selectVIA == 1'b1 && _cpuUDS == 1'b0 && _cpuRW == 1'b0 && cpuAddrRegHi == 4'h9;
-	always @(negedge clk8 or negedge _reset) begin
+	always @(posedge clk32 or negedge _reset) begin
 		if (_reset == 1'b0) begin
 			viaB0DDR <= 1'b1;
 			viaADataOut <= 8'b01111111;
@@ -223,7 +229,7 @@ module via(
 			viaTimer2LatchLow <= 8'h00;
 			viaTimer2Armed <= 0;
 		end
-		else begin
+		else if (clk8_en_n) begin
 			if (selectVIA == 1'b1 && _cpuUDS == 1'b0) begin
 				if (_cpuRW == 1'b0) begin
 					// normal register writes
diff --git a/cores/plus_too/videoShifter.v b/cores/plus_too/videoShifter.v
index 6b2338a..18e625d 100644
--- a/cores/plus_too/videoShifter.v
+++ b/cores/plus_too/videoShifter.v
@@ -1,9 +1,9 @@
 module videoShifter(
-    input clk32,
-	 input [1:0] clkPhase,
-	 input [15:0] dataIn,
-	 input loadPixels,
-    output pixelOut
+	input clk32,
+	input [1:0] clkPhase,
+	input [15:0] dataIn,
+	input loadPixels,
+	output pixelOut
     );
 	
 	reg [15:0] shiftRegister;
@@ -22,5 +22,5 @@ module videoShifter(
 			shiftRegister <= { shiftRegister[14:0], 1'b1 };
 		end
 	end
-	
+
 endmodule
diff --git a/cores/plus_too/videoTimer.v b/cores/plus_too/videoTimer.v
index 11f86ba..1df358e 100644
--- a/cores/plus_too/videoTimer.v
+++ b/cores/plus_too/videoTimer.v
@@ -1,13 +1,14 @@
 // generates 1024x768 (actually 512x768) @ 60Hz, from a 32.5MHz input clock
 module videoTimer(
-    input clk8,
-	 input [1:0] busCycle,
-	 output [21:0] videoAddr,	 
-	 output reg hsync,
-	 output reg vsync,
-	 output _hblank,
-	 output _vblank,
-	 output loadPixels
+	input clk,
+	input clk_en,
+	input [1:0] busCycle,
+	output [21:0] videoAddr,	 
+	output reg hsync,
+	output reg vsync,
+	output _hblank,
+	output _vblank,
+	output loadPixels
 );
 
 	// timing data from http://tinyvga.com/vga-timing/1024x768@60Hz
@@ -31,28 +32,34 @@ module videoTimer(
 
 	wire endline = (xpos == kTotalWidth-1);
 
-	always @(posedge clk8) begin
-		if (endline)
-			xpos <= 0;
-		else if (xpos == 0 && busCycle != 0)
-			// hold xpos at 0, until xpos and busCycle are in phase
-			xpos <= 0;
-		else
-			xpos <= xpos + 1'b1;
-	end
-
-	always @(posedge clk8) begin
-		if (endline) begin
-			if (ypos == kTotalHeight-1)
-				ypos <= 0;
+	always @(posedge clk) begin
+		if (clk_en) begin
+			if (endline)
+				xpos <= 0;
+			else if (xpos == 0 && busCycle != 0)
+				// hold xpos at 0, until xpos and busCycle are in phase
+				xpos <= 0;
 			else
-				ypos <= ypos + 1'b1;	
+				xpos <= xpos + 1'b1;
 		end
 	end
 
-	always @(posedge clk8) begin
-		hsync <= ~(xpos >= kHsyncStart+kPixelLatency && xpos <= kHsyncEnd+kPixelLatency);  
-		vsync <= ~(ypos >= kVsyncStart && ypos <= kVsyncEnd);
+	always @(posedge clk) begin
+		if (clk_en) begin
+			if (endline) begin
+				if (ypos == kTotalHeight-1)
+					ypos <= 0;
+				else
+					ypos <= ypos + 1'b1;	
+			end
+		end
+	end
+
+	always @(posedge clk) begin
+		if (clk_en) begin
+			hsync <= ~(xpos >= kHsyncStart+kPixelLatency && xpos <= kHsyncEnd+kPixelLatency);  
+			vsync <= ~(ypos >= kVsyncStart && ypos <= kVsyncEnd);
+		end
 	end
 
 	assign _hblank = ~(xpos >= kVisibleWidth);