diff --git a/cores/nes/mist/NES_mist.v b/cores/nes/mist/NES_mist.v index 0dc6d68..7a36ab1 100644 --- a/cores/nes/mist/NES_mist.v +++ b/cores/nes/mist/NES_mist.v @@ -180,13 +180,14 @@ wire ps2_kbd_clk, ps2_kbd_data; user_io #(.STRLEN(CONF_STR_LEN)) user_io( + .clk_sys(clk), .conf_str(CONF_STR), // the spi interface - .SPI_SCK(SPI_SCK), - .CONF_DATA0(CONF_DATA0), - .SPI_DO(SPI_DO), // tristate handling inside user_io - .SPI_DI(SPI_DI), + .SPI_CLK(SPI_SCK), + .SPI_SS_IO(CONF_DATA0), + .SPI_MISO(SPI_DO), // tristate handling inside user_io + .SPI_MOSI(SPI_DI), .switches(switches), .buttons(buttons), @@ -198,7 +199,6 @@ user_io #(.STRLEN(CONF_STR_LEN)) user_io( .status(status), - .ps2_clk(ps2_clk), // should be 10-16kHz for ps2 clock .ps2_kbd_clk(ps2_kbd_clk), .ps2_kbd_data(ps2_kbd_data) ); @@ -210,12 +210,13 @@ wire [7:0] nes_joy_B = (reset_nes || osd_visible) ? 8'd0 : wire clock_locked; wire clk85; - clk clock_21mhz(.inclk0(CLOCK_27[0]), .c0(clk85), .c1(SDRAM_CLK), .locked(clock_locked)); + wire clk; + clk clock_21mhz(.inclk0(CLOCK_27[0]), .c0(clk85), .c1(SDRAM_CLK), .c2(clk), .locked(clock_locked)); // reset after download reg [7:0] download_reset_cnt; wire download_reset = download_reset_cnt != 0; - always @(posedge CLOCK_27[0]) begin + always @(posedge clk) begin if(downloading) download_reset_cnt <= 8'd255; else if(download_reset_cnt != 0) @@ -223,20 +224,11 @@ wire [7:0] nes_joy_B = (reset_nes || osd_visible) ? 8'd0 : end // hold machine in reset until first download starts - reg init_reset; - always @(posedge CLOCK_27[0]) begin - if(!clock_locked) - init_reset <= 1'b1; - else if(downloading) - init_reset <= 1'b0; + reg init_reset = 1; + always @(posedge clk) begin + if(downloading) init_reset <= 1'b0; end - reg [12:0] clkcnt; - always @(posedge clk85) - clkcnt <= clkcnt + 2'd1; - wire clk = clkcnt[1]; - wire ps2_clk = clkcnt[12]; - wire [8:0] cycle; wire [8:0] scanline; wire [15:0] sample; @@ -301,12 +293,12 @@ wire [7:0] nes_joy_B = (reset_nes || osd_visible) ? 8'd0 : mapper_flags <= loader_flags; // LED displays loader status - reg [12:0] led_blink; // divide PS2 clock to around 1Hz - always @(posedge ps2_clk) begin + reg [23:0] led_blink; // divide 21MHz clock to around 1Hz + always @(posedge clk) begin led_blink <= led_blink + 13'd1; end - assign LED = downloading ? 0 : loader_fail ? led_blink[12] : 1; + assign LED = downloading ? 0 : loader_fail ? led_blink[23] : 1; wire osd_visible; diff --git a/cores/nes/mist/clk.v b/cores/nes/mist/clk.v index 97ea342..9f2e0f0 100644 --- a/cores/nes/mist/clk.v +++ b/cores/nes/mist/clk.v @@ -40,26 +40,30 @@ module clk ( inclk0, c0, c1, + c2, locked); input inclk0; output c0; output c1; + output c2; output locked; wire [4:0] sub_wire0; wire sub_wire2; - wire [0:0] sub_wire6 = 1'h0; + wire [0:0] sub_wire7 = 1'h0; + wire [2:2] sub_wire4 = sub_wire0[2:2]; wire [0:0] sub_wire3 = sub_wire0[0:0]; wire [1:1] sub_wire1 = sub_wire0[1:1]; wire c1 = sub_wire1; wire locked = sub_wire2; wire c0 = sub_wire3; - wire sub_wire4 = inclk0; - wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; + wire c2 = sub_wire4; + wire sub_wire5 = inclk0; + wire [1:0] sub_wire6 = {sub_wire7, sub_wire5}; altpll altpll_component ( - .inclk (sub_wire5), + .inclk (sub_wire6), .clk (sub_wire0), .locked (sub_wire2), .activeclock (), @@ -106,6 +110,10 @@ module clk ( altpll_component.clk1_duty_cycle = 50, altpll_component.clk1_multiply_by = 7159, altpll_component.clk1_phase_shift = "-1500", + altpll_component.clk2_divide_by = 44, + altpll_component.clk2_duty_cycle = 50, + altpll_component.clk2_multiply_by = 35, + altpll_component.clk2_phase_shift = "0", altpll_component.compensate_clock = "CLK0", altpll_component.inclk0_input_frequency = 37037, altpll_component.intended_device_family = "Cyclone III", @@ -140,7 +148,7 @@ module clk ( altpll_component.port_scanwrite = "PORT_UNUSED", altpll_component.port_clk0 = "PORT_USED", altpll_component.port_clk1 = "PORT_USED", - altpll_component.port_clk2 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_USED", altpll_component.port_clk3 = "PORT_UNUSED", altpll_component.port_clk4 = "PORT_UNUSED", altpll_component.port_clk5 = "PORT_UNUSED", @@ -181,10 +189,13 @@ endmodule // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" // Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" // Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "44" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "85.907997" // Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "85.907997" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "21.477272" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -206,25 +217,33 @@ endmodule // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" // Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" // Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "35" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "85.90800000" // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "85.90800000" +// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-1500.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" @@ -248,13 +267,16 @@ endmodule // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: USE_CLK0 STRING "1" // Retrieval info: PRIVATE: USE_CLK1 STRING "1" +// Retrieval info: PRIVATE: USE_CLK2 STRING "1" // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all @@ -267,6 +289,10 @@ endmodule // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "7159" // Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-1500" +// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "44" +// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "35" +// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" @@ -300,7 +326,7 @@ endmodule // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" @@ -319,12 +345,14 @@ endmodule // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" +// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 +// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 // Retrieval info: GEN_FILE: TYPE_NORMAL clk.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL clk.ppf TRUE diff --git a/cores/nes/mist/constraints.sdc b/cores/nes/mist/constraints.sdc new file mode 100644 index 0000000..e0d6b5f --- /dev/null +++ b/cores/nes/mist/constraints.sdc @@ -0,0 +1,121 @@ +## Generated SDC file "hello_led.out.sdc" + +## Copyright (C) 1991-2011 Altera Corporation +## Your use of Altera Corporation's design tools, logic functions +## and other software and tools, and its AMPP partner logic +## functions, and any output files from any of the foregoing +## (including device programming or simulation files), and any +## associated documentation or information are expressly subject +## to the terms and conditions of the Altera Program License +## Subscription Agreement, Altera MegaCore Function License +## Agreement, or other applicable license agreement, including, +## without limitation, that your use is for the sole purpose of +## programming logic devices manufactured by Altera and sold by +## Altera or its authorized distributors. Please refer to the +## applicable agreement for further details. + + +## VENDOR "Altera" +## PROGRAM "Quartus II" +## VERSION "Version 11.1 Build 216 11/23/2011 Service Pack 1 SJ Web Edition" + +## DATE "Fri Jul 06 23:05:47 2012" + +## +## DEVICE "EP3C25Q240C8" +## + + +#************************************************************** +# Time Information +#************************************************************** + +set_time_format -unit ns -decimal_places 3 + + + +#************************************************************** +# Create Clock +#************************************************************** + +create_clock -name clk_27 -period 37.037 [get_ports {CLOCK_27[0]}] +create_clock -name {SPI_SCK} -period 41.666 -waveform { 20.8 41.666 } [get_ports {SPI_SCK}] + +#************************************************************** +# Create Generated Clock +#************************************************************** + +derive_pll_clocks + +#************************************************************** +# Set Clock Latency +#************************************************************** + + +#************************************************************** +# Set Clock Uncertainty +#************************************************************** + +derive_clock_uncertainty; + +#************************************************************** +# Set Input Delay +#************************************************************** + +# SDRAM is clocked from sd1clk_pin, but the SDRAM controller uses memclk +set_input_delay -clock [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[0]}] -max 6.4 [get_ports SDRAM_DQ[*]] +set_input_delay -clock [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[0]}] -min 3.2 [get_ports SDRAM_DQ[*]] + + +#************************************************************** +# Set Output Delay +#************************************************************** + +set_output_delay -clock [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] +set_output_delay -clock [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[0]}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] +set_output_delay -clock [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[1]}] -max 1.5 [get_ports SDRAM_CLK] +set_output_delay -clock [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[1]}] -min -0.8 [get_ports SDRAM_CLK] + +set_output_delay -clock [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[2]}] -max 0 [get_ports {VGA_*}] +set_output_delay -clock [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[2]}] -min -5 [get_ports {VGA_*}] + +#************************************************************** +# Set Clock Groups +#************************************************************** + +set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[*]}] + +#************************************************************** +# Set False Path +#************************************************************** + +set_false_path -to [get_ports {UART_TX}] +set_false_path -to [get_ports {AUDIO_L}] +set_false_path -to [get_ports {AUDIO_R}] +set_false_path -to [get_ports {LED}] + +#************************************************************** +# Set Multicycle Path +#************************************************************** + +set_multicycle_path -from [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[0]}] -setup 4 +set_multicycle_path -from [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[0]}] -hold 4 + +set_multicycle_path -to {VGA_*[*]} -setup 2 +set_multicycle_path -to {VGA_*[*]} -hold 2 + +#************************************************************** +# Set Maximum Delay +#************************************************************** + + + +#************************************************************** +# Set Minimum Delay +#************************************************************** + + + +#************************************************************** +# Set Input Transition +#************************************************************** diff --git a/cores/nes/mist/sdram.v b/cores/nes/mist/sdram.v index 72671f7..8d05ee4 100644 --- a/cores/nes/mist/sdram.v +++ b/cores/nes/mist/sdram.v @@ -24,14 +24,14 @@ module sdram ( // interface to the MT48LC16M16 chip - inout [15:0] sd_data, // 16 bit bidirectional data bus - output [12:0] sd_addr, // 13 bit multiplexed address bus - output [1:0] sd_dqm, // two byte masks - output [1:0] sd_ba, // two banks - output sd_cs, // a single chip select - output sd_we, // write enable - output sd_ras, // row address select - output sd_cas, // columns address select + inout reg [15:0] sd_data, // 16 bit bidirectional data bus + output reg [12:0] sd_addr, // 13 bit multiplexed address bus + output reg [1:0] sd_dqm, // two byte masks + output reg [1:0] sd_ba, // two banks + output reg sd_cs, // a single chip select + output reg sd_we, // write enable + output reg sd_ras, // row address select + output reg sd_cas, // columns address select // cpu/chipset interface input init, // init signal after FPGA config to initialize RAM @@ -108,18 +108,6 @@ localparam CMD_LOAD_MODE = 4'b0000; wire [3:0] sd_cmd; // current command sent to sd ram -// drive control signals according to current command -assign sd_cs = sd_cmd[3]; -assign sd_ras = sd_cmd[2]; -assign sd_cas = sd_cmd[1]; -assign sd_we = sd_cmd[0]; - -// drive ram data lines when writing, set them as inputs otherwise -// the eight bits are sent on both bytes ports. Which one's actually -// written depends on the state of dqm of which only one is active -// at a time when writing -assign sd_data = we?{din, din}:16'bZZZZZZZZZZZZZZZZ; - wire oe = oeA || oeB; reg addr0; @@ -154,10 +142,26 @@ wire [12:0] reset_addr = (reset == 13)?13'b0010000000000:MODE; wire [12:0] run_addr = (q == STATE_CMD_START)?addr[21:9]:{ 4'b0010, addr[24], addr[8:1]}; -assign sd_addr = (reset != 0)?reset_addr:run_addr; +//register SDRAM output signals +always @(posedge clk) begin -assign sd_ba = addr[23:22]; +// drive ram data lines when writing, set them as inputs otherwise +// the eight bits are sent on both bytes ports. Which one's actually +// written depends on the state of dqm of which only one is active +// at a time when writing + sd_data <= we?{din, din}:16'bZZZZZZZZZZZZZZZZ; -assign sd_dqm = we?{ addr[0], ~addr[0] }:2'b00; + sd_addr <= (reset != 0)?reset_addr:run_addr; + + sd_ba <= addr[23:22]; + + sd_dqm <= we?{ addr[0], ~addr[0] }:2'b00; + + // drive control signals according to current command + sd_cs <= sd_cmd[3]; + sd_ras <= sd_cmd[2]; + sd_cas <= sd_cmd[1]; + sd_we <= sd_cmd[0]; +end endmodule diff --git a/cores/nes/mist/user_io.v b/cores/nes/mist/user_io.v index 17dd624..c850c8c 100644 --- a/cores/nes/mist/user_io.v +++ b/cores/nes/mist/user_io.v @@ -22,127 +22,91 @@ // parameter STRLEN and the actual length of conf_str have to match -module user_io #(parameter STRLEN=0) ( +module user_io #(parameter STRLEN=0, parameter PS2DIV=100) ( input [(8*STRLEN)-1:0] conf_str, - input SPI_SCK, - input CONF_DATA0, - output reg SPI_DO, - input SPI_DI, - - output reg [7:0] joystick_0, - output reg [7:0] joystick_1, - output reg [15:0] joystick_analog_0, - output reg [15:0] joystick_analog_1, - output [1:0] buttons, - output [1:0] switches, - output scandoubler_disable, - output ypbpr, + input clk_sys, // clock for system-related messages (kbd, joy, etc...) + input clk_sd, // clock for SD-card related messages - output reg [7:0] status, + input SPI_CLK, + input SPI_SS_IO, + output reg SPI_MISO, + input SPI_MOSI, + + output reg [31:0] joystick_0, + output reg [31:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, + output ypbpr, + output reg [31:0] status, // connection to sd card emulation - input [31:0] sd_lba, - input sd_rd, - input sd_wr, - output reg sd_ack, - input sd_conf, - input sd_sdhc, - output reg [7:0] sd_dout, - output reg sd_dout_strobe, - input [7:0] sd_din, - output reg sd_din_strobe, - output sd_mounted, + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + output reg sd_ack_conf, + input sd_conf, + input sd_sdhc, + output reg [7:0] sd_dout, // valid on rising edge of sd_dout_strobe + output reg sd_dout_strobe, + input [7:0] sd_din, + output reg sd_din_strobe, + output reg [8:0] sd_buff_addr, + output reg img_mounted, //rising edge if a new image is mounted + output reg [31:0] img_size, // size of image in bytes // ps2 keyboard emulation - input ps2_clk, // 12-16khz provided by core - output ps2_kbd_clk, - output reg ps2_kbd_data, - output ps2_mouse_clk, - output reg ps2_mouse_data, + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, // serial com port - input [7:0] serial_data, - input serial_strobe + input [7:0] serial_data, + input serial_strobe ); -reg [6:0] sbuf; -reg [7:0] cmd; -reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... -reg [7:0] byte_cnt; // counts bytes -reg [7:0] but_sw; -reg [2:0] stick_idx; - -reg mount_strobe = 1'b0; -assign sd_mounted = mount_strobe; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [7:0] byte_cnt; // counts bytes +reg [5:0] joystick0; +reg [5:0] joystick1; +reg [7:0] but_sw; +reg [2:0] stick_idx; assign buttons = but_sw[1:0]; assign switches = but_sw[3:2]; assign scandoubler_disable = but_sw[4]; assign ypbpr = but_sw[5]; -wire [7:0] dout = { sbuf, SPI_DI}; - // this variant of user_io is for 8 bit cores (type == a4) only wire [7:0] core_type = 8'ha4; // command byte read by the io controller wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; -// drive MISO only when transmitting core id -always@(negedge SPI_SCK or posedge CONF_DATA0) begin - if(CONF_DATA0 == 1) begin - SPI_DO <= 1'bZ; - end else begin - - // first byte returned is always core type, further bytes are - // command dependent - if(byte_cnt == 0) begin - SPI_DO <= core_type[~bit_cnt]; - - end else begin - // reading serial fifo - if(cmd == 8'h1b) begin - // send alternating flag byte and data - if(byte_cnt[0]) SPI_DO <= serial_out_status[~bit_cnt]; - else SPI_DO <= serial_out_byte[~bit_cnt]; - end - - // reading config string - else if(cmd == 8'h14) begin - // returning a byte from string - if(byte_cnt < STRLEN + 1) - SPI_DO <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; - else - SPI_DO <= 1'b0; - end - - // reading sd card status - else if(cmd == 8'h16) begin - if(byte_cnt == 1) - SPI_DO <= sd_cmd[~bit_cnt]; - else if((byte_cnt >= 2) && (byte_cnt < 6)) - SPI_DO <= sd_lba[{5-byte_cnt, ~bit_cnt}]; - else - SPI_DO <= 1'b0; - end - - // reading sd card write data - else if(cmd == 8'h18) - SPI_DO <= sd_din[~bit_cnt]; - - else - SPI_DO <= 1'b0; - end - end -end +wire spi_sck = SPI_CLK; // ---------------- PS2 --------------------- - // 8 byte fifos to store ps2 bytes localparam PS2_FIFO_BITS = 3; +reg ps2_clk; +always @(negedge clk_sys) begin + integer cnt; + cnt <= cnt + 1'd1; + if(cnt == PS2DIV) begin + ps2_clk <= ~ps2_clk; + cnt <= 0; + end +end + // keyboard reg [7:0] ps2_kbd_fifo [(2**PS2_FIFO_BITS)-1:0]; reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr; @@ -158,56 +122,60 @@ assign ps2_kbd_clk = ps2_clk || (ps2_kbd_tx_state == 0); // ps2 transmitter // Takes a byte from the FIFO and sends it in a ps2 compliant serial format. reg ps2_kbd_r_inc; -always@(posedge ps2_clk) begin - ps2_kbd_r_inc <= 1'b0; - - if(ps2_kbd_r_inc) - ps2_kbd_rptr <= ps2_kbd_rptr + 3'd1; +always@(posedge clk_sys) begin + reg ps2_clkD; - // transmitter is idle? - if(ps2_kbd_tx_state == 0) begin - // data in fifo present? - if(ps2_kbd_wptr != ps2_kbd_rptr) begin - // load tx register from fifo - ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr]; - ps2_kbd_r_inc <= 1'b1; - - // reset parity - ps2_kbd_parity <= 1'b1; - - // start transmitter - ps2_kbd_tx_state <= 4'd1; + ps2_clkD <= ps2_clk; + if (~ps2_clkD & ps2_clk) begin + ps2_kbd_r_inc <= 1'b0; - // put start bit on data line - ps2_kbd_data <= 1'b0; // start bit is 0 + if(ps2_kbd_r_inc) + ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1; + + // transmitter is idle? + if(ps2_kbd_tx_state == 0) begin + // data in fifo present? + if(ps2_kbd_wptr != ps2_kbd_rptr) begin + // load tx register from fifo + ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr]; + ps2_kbd_r_inc <= 1'b1; + + // reset parity + ps2_kbd_parity <= 1'b1; + + // start transmitter + ps2_kbd_tx_state <= 4'd1; + + // put start bit on data line + ps2_kbd_data <= 1'b0; // start bit is 0 + end + end else begin + + // transmission of 8 data bits + if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; + end + + // transmission of parity + if(ps2_kbd_tx_state == 9) + ps2_kbd_data <= ps2_kbd_parity; + + // transmission of stop bit + if(ps2_kbd_tx_state == 10) + ps2_kbd_data <= 1'b1; // stop bit is 1 + + // advance state machine + if(ps2_kbd_tx_state < 11) + ps2_kbd_tx_state <= ps2_kbd_tx_state + 4'd1; + else + ps2_kbd_tx_state <= 4'd0; end - end else begin - - // transmission of 8 data bits - if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin - ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits - ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down - if(ps2_kbd_tx_byte[0]) - ps2_kbd_parity <= !ps2_kbd_parity; - end - - // transmission of parity - if(ps2_kbd_tx_state == 9) - ps2_kbd_data <= ps2_kbd_parity; - - // transmission of stop bit - if(ps2_kbd_tx_state == 10) - ps2_kbd_data <= 1'b1; // stop bit is 1 - - // advance state machine - if(ps2_kbd_tx_state < 11) - ps2_kbd_tx_state <= ps2_kbd_tx_state + 4'd1; - else - ps2_kbd_tx_state <= 4'd0; - end end - + // mouse reg [7:0] ps2_mouse_fifo [(2**PS2_FIFO_BITS)-1:0]; reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr; @@ -223,53 +191,57 @@ assign ps2_mouse_clk = ps2_clk || (ps2_mouse_tx_state == 0); // ps2 transmitter // Takes a byte from the FIFO and sends it in a ps2 compliant serial format. reg ps2_mouse_r_inc; -always@(posedge ps2_clk) begin - ps2_mouse_r_inc <= 1'b0; - - if(ps2_mouse_r_inc) - ps2_mouse_rptr <= ps2_mouse_rptr + 3'd1; +always@(posedge clk_sys) begin + reg ps2_clkD; - // transmitter is idle? - if(ps2_mouse_tx_state == 0) begin - // data in fifo present? - if(ps2_mouse_wptr != ps2_mouse_rptr) begin - // load tx register from fifo - ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr]; - ps2_mouse_r_inc <= 1'b1; - - // reset parity - ps2_mouse_parity <= 1'b1; - - // start transmitter - ps2_mouse_tx_state <= 4'd1; + ps2_clkD <= ps2_clk; + if (~ps2_clkD & ps2_clk) begin + ps2_mouse_r_inc <= 1'b0; - // put start bit on data line - ps2_mouse_data <= 1'b0; // start bit is 0 + if(ps2_mouse_r_inc) + ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1; + + // transmitter is idle? + if(ps2_mouse_tx_state == 0) begin + // data in fifo present? + if(ps2_mouse_wptr != ps2_mouse_rptr) begin + // load tx register from fifo + ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr]; + ps2_mouse_r_inc <= 1'b1; + + // reset parity + ps2_mouse_parity <= 1'b1; + + // start transmitter + ps2_mouse_tx_state <= 4'd1; + + // put start bit on data line + ps2_mouse_data <= 1'b0; // start bit is 0 + end + end else begin + + // transmission of 8 data bits + if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) + ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) + ps2_mouse_data <= 1'b1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) + ps2_mouse_tx_state <= ps2_mouse_tx_state + 4'd1; + else + ps2_mouse_tx_state <= 4'd0; end - end else begin - - // transmission of 8 data bits - if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin - ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits - ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down - if(ps2_mouse_tx_byte[0]) - ps2_mouse_parity <= !ps2_mouse_parity; - end - - // transmission of parity - if(ps2_mouse_tx_state == 9) - ps2_mouse_data <= ps2_mouse_parity; - - // transmission of stop bit - if(ps2_mouse_tx_state == 10) - ps2_mouse_data <= 1'b1; // stop bit is 1 - - // advance state machine - if(ps2_mouse_tx_state < 11) - ps2_mouse_tx_state <= ps2_mouse_tx_state + 4'd1; - else - ps2_mouse_tx_state <= 4'd0; - end end @@ -292,113 +264,265 @@ always @(posedge serial_strobe or posedge status[0]) begin serial_out_wptr <= 0; end else begin serial_out_fifo[serial_out_wptr] <= serial_data; - serial_out_wptr <= serial_out_wptr + 6'd1; + serial_out_wptr <= serial_out_wptr + 1'd1; end end -always@(negedge SPI_SCK or posedge status[0]) begin +always@(negedge spi_sck or posedge status[0]) begin if(status[0] == 1) begin serial_out_rptr <= 0; end else begin if((byte_cnt != 0) && (cmd == 8'h1b)) begin // read last bit -> advance read pointer if((bit_cnt == 7) && !byte_cnt[0] && serial_out_data_available) - serial_out_rptr <= serial_out_rptr + 6'd1; + serial_out_rptr <= serial_out_rptr + 1'd1; end end end -// SPI receiver -always@(posedge SPI_SCK or posedge CONF_DATA0) begin - if(CONF_DATA0 == 1) begin - bit_cnt <= 3'd0; - byte_cnt <= 8'd0; - sd_ack <= 1'b0; - sd_dout_strobe <= 1'b0; - sd_din_strobe <= 1'b0; +// SPI bit and byte counters +always@(posedge spi_sck or posedge SPI_SS_IO) begin + if(SPI_SS_IO == 1) begin + bit_cnt <= 0; + byte_cnt <= 0; end else begin - sd_dout_strobe <= 1'b0; - sd_din_strobe <= 1'b0; - - sbuf <= dout[6:0]; - bit_cnt <= bit_cnt + 3'd1; + if((bit_cnt == 7)&&(byte_cnt != 8'd255)) + byte_cnt <= byte_cnt + 8'd1; - // finished reading command byte - if(bit_cnt == 7) begin - if(byte_cnt != 8'd255) byte_cnt <= byte_cnt + 8'd1; - if(byte_cnt == 0) begin - cmd <= dout; - - // fetch first byte when sectore FPGA->IO command has been seen - if(dout == 8'h18) - sd_din_strobe <= 1'b1; - - if((dout == 8'h17) || (dout == 8'h18)) - sd_ack <= 1'b1; + bit_cnt <= bit_cnt + 1'd1; + end +end - mount_strobe <= 1'b0; - - end else begin - - case(cmd) - // buttons and switches - 8'h01: but_sw <= dout; - 8'h02: joystick_0 <= dout; - 8'h03: joystick_1 <= dout; +// SPI transmitter FPGA -> IO +reg [7:0] spi_byte_out; - // store incoming ps2 mouse bytes - 8'h04: begin - ps2_mouse_fifo[ps2_mouse_wptr] <= dout; - ps2_mouse_wptr <= ps2_mouse_wptr + 3'd1; - end +always@(negedge spi_sck or posedge SPI_SS_IO) begin + if(SPI_SS_IO == 1) begin + SPI_MISO <= 1'bZ; + end else begin + SPI_MISO <= spi_byte_out[~bit_cnt]; + end +end - // store incoming ps2 keyboard bytes - 8'h05: begin - ps2_kbd_fifo[ps2_kbd_wptr] <= dout; - ps2_kbd_wptr <= ps2_kbd_wptr + 3'd1; - end - - 8'h15: status <= dout; - - // send SD config IO -> FPGA - // flag that download begins - // sd card knows data is config if sd_dout_strobe is asserted - // with sd_ack still being inactive (low) - 8'h19, - // send sector IO -> FPGA - // flag that download begins - 8'h17: begin - sd_dout <= dout; - sd_dout_strobe <= 1'b1; - end - - // send sector FPGA -> IO - 8'h18: sd_din_strobe <= 1'b1; - - // joystick analog - 8'h1a: begin - // first byte is joystick index - if(byte_cnt == 1) stick_idx <= dout[2:0]; - else if(byte_cnt == 2) begin - // second byte is x axis - if(stick_idx == 0) joystick_analog_0[15:8] <= dout; - else if(stick_idx == 1) joystick_analog_1[15:8] <= dout; - end else if(byte_cnt == 3) begin - // third byte is y axis - if(stick_idx == 0) joystick_analog_0[7:0] <= dout; - else if(stick_idx == 1) joystick_analog_1[7:0] <= dout; - end - end +always@(posedge spi_sck or posedge SPI_SS_IO) begin + reg [31:0] sd_lba_r; + + if(SPI_SS_IO == 1) begin + spi_byte_out <= core_type; + end else begin + // read the command byte to choose the response + if(bit_cnt == 7) begin + if(!byte_cnt) cmd <= {sbuf, SPI_MOSI}; - // notify image selection - 8'h1c: mount_strobe <= 1'b1; + spi_byte_out <= 0; + case({(!byte_cnt) ? {sbuf, SPI_MOSI} : cmd}) + // reading config string + 8'h14: if(byte_cnt < STRLEN) spi_byte_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8]; - default: ; - endcase - end + // reading sd card status + 8'h16: if(byte_cnt == 0) begin + spi_byte_out <= sd_cmd; + sd_lba_r <= sd_lba; + end + else if(byte_cnt < 5) spi_byte_out <= sd_lba_r[(4-byte_cnt)<<3 +:8]; + + // reading sd card write data + 8'h18: spi_byte_out <= sd_din; + 8'h1b: + // send alternating flag byte and data + if(byte_cnt[0]) spi_byte_out <= serial_out_status; + else spi_byte_out <= serial_out_byte; + endcase end end end - + +// SPI receiver IO -> FPGA + +reg spi_receiver_strobe_r; +reg spi_transfer_end_r; +reg [7:0] spi_byte_in_r; + +// Read at spi_sck clock domain, assemble bytes for transferring to clk_sys +always@(posedge spi_sck or posedge SPI_SS_IO) begin + + if(SPI_SS_IO == 1) begin + spi_receiver_strobe_r <= 0; + spi_transfer_end_r <= 1; + end else begin + spi_receiver_strobe_r <= 0; + spi_transfer_end_r <= 0; + + if(bit_cnt != 7) + sbuf[6:0] <= { sbuf[5:0], SPI_MOSI }; + + // finished reading a byte, prepare to transfer to clk_sys + if(bit_cnt == 7) begin + spi_byte_in_r <= { sbuf, SPI_MOSI}; + spi_receiver_strobe_r <= 1; + end + end +end + +// Process bytes from SPI at the clk_sys domain +always @(posedge clk_sys) begin + + reg spi_receiver_strobe; + reg spi_transfer_end; + reg [7:0] spi_byte_in; + reg spi_receiver_strobeD; + reg spi_transfer_endD; + reg [7:0] spi_byte_inD; + reg [7:0] acmd; + reg [7:0] abyte_cnt; // counts bytes + + //synchronize between SPI and sys clock domains + spi_receiver_strobeD <= spi_receiver_strobe_r; + spi_receiver_strobe <= spi_receiver_strobeD; + spi_transfer_endD <= spi_transfer_end_r; + spi_transfer_end <= spi_transfer_endD; + spi_byte_inD <= spi_byte_in_r; + spi_byte_in <= spi_byte_inD; + + if (~spi_transfer_endD & spi_transfer_end) begin + abyte_cnt <= 8'd0; + end else if (~spi_receiver_strobeD & spi_receiver_strobe) begin + + if(abyte_cnt != 8'd255) + abyte_cnt <= byte_cnt + 8'd1; + + if(abyte_cnt == 0) begin + acmd <= spi_byte_in; + end else begin + case(acmd) + // buttons and switches + 8'h01: but_sw <= spi_byte_in; + 8'h02: joystick_0 <= spi_byte_in; + 8'h03: joystick_1 <= spi_byte_in; + 8'h04: begin + // store incoming ps2 mouse bytes + ps2_mouse_fifo[ps2_mouse_wptr] <= spi_byte_in; + ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; + end + 8'h05: begin + // store incoming ps2 keyboard bytes + ps2_kbd_fifo[ps2_kbd_wptr] <= spi_byte_in; + ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; + end + + // joystick analog + 8'h1a: begin + // first byte is joystick indes + if(abyte_cnt == 1) + stick_idx <= spi_byte_in[2:0]; + else if(abyte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) + joystick_analog_0[15:8] <= spi_byte_in; + else if(stick_idx == 1) + joystick_analog_1[15:8] <= spi_byte_in; + end else if(abyte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) + joystick_analog_0[7:0] <= spi_byte_in; + else if(stick_idx == 1) + joystick_analog_1[7:0] <= spi_byte_in; + end + end + + 8'h15: status <= spi_byte_in; + + // status, 32bit version + 8'h1e: if(abyte_cnt<6) status[(abyte_cnt-2)<<3 +:8] <= spi_byte_in; + + endcase + end + end +end + +// Process SD-card related bytes from SPI at the clk_sd domain +always @(posedge clk_sd) begin + + reg spi_receiver_strobe; + reg spi_transfer_end; + reg [7:0] spi_byte_in; + reg spi_receiver_strobeD; + reg spi_transfer_endD; + reg [7:0] spi_byte_inD; + reg [7:0] acmd; + reg [7:0] abyte_cnt; // counts bytes + + //synchronize between SPI and sd clock domains + spi_receiver_strobeD <= spi_receiver_strobe_r; + spi_receiver_strobe <= spi_receiver_strobeD; + spi_transfer_endD <= spi_transfer_end_r; + spi_transfer_end <= spi_transfer_endD; + spi_byte_inD <= spi_byte_in_r; + spi_byte_in <= spi_byte_inD; + + if(sd_dout_strobe) begin + sd_dout_strobe<= 0; + if(~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; + end + + if(sd_din_strobe) begin + sd_din_strobe<= 0; + if(~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; + end + + img_mounted <= 0; + + if (~spi_transfer_endD & spi_transfer_end) begin + abyte_cnt <= 8'd0; + sd_ack <= 1'b0; + sd_ack_conf <= 1'b0; + sd_dout_strobe <= 1'b0; + sd_din_strobe <= 1'b0; + sd_buff_addr<= 0; + end else if (~spi_receiver_strobeD & spi_receiver_strobe) begin + + if(abyte_cnt != 8'd255) + abyte_cnt <= byte_cnt + 8'd1; + + if(abyte_cnt == 0) begin + acmd <= spi_byte_in; + + // fetch first byte when sectore FPGA->IO command has been seen + if(spi_byte_in == 8'h18) + sd_din_strobe <= 1'b1; + + if((spi_byte_in == 8'h17) || (spi_byte_in == 8'h18)) + sd_ack <= 1'b1; + + end else begin + case(acmd) + + // send sector IO -> FPGA + 8'h17: begin + // flag that download begins + sd_dout_strobe <= 1'b1; + sd_dout <= spi_byte_in; + end + + // send sector FPGA -> IO + 8'h18: sd_din_strobe <= 1'b1; + + // send SD config IO -> FPGA + 8'h19: begin + // flag that download begins + sd_dout_strobe <= 1'b1; + sd_ack_conf <= 1'b1; + sd_dout <= spi_byte_in; + end + + 8'h1c: img_mounted <= 1; + + // send image info + 8'h1d: if(abyte_cnt<6) img_size[(byte_cnt-2)<<3 +:8] <= spi_byte_in; + endcase + end + end +end + endmodule diff --git a/cores/nes/nes.qsf b/cores/nes/nes.qsf index fc38b3b..27a1af3 100644 --- a/cores/nes/nes.qsf +++ b/cores/nes/nes.qsf @@ -31,8 +31,8 @@ set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id e set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF -set_global_assignment -name FITTER_EFFORT "FAST FIT" +set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" +set_global_assignment -name FITTER_EFFORT "STANDARD FIT" set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4 set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" @@ -128,7 +128,7 @@ set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL set_global_assignment -name FMAX_REQUIREMENT "114 MHz" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name USE_CONFIGURATION_DEVICE ON @@ -240,50 +240,48 @@ set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[12] set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[13] set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[14] set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[15] -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk_8 -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk_128 set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to SDRAM_CLK set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to SPI_SCK -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[0] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[1] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[2] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[3] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[4] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[5] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[6] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[7] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[8] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[9] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[10] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[11] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[12] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[0] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[1] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[2] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[3] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[4] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[5] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[6] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[7] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[8] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[9] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[10] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[11] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[12] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[13] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[14] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[15] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[0] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[1] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQML -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQMH -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nRAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nWE -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCS -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CKE -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk_32 +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_A[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[13] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[14] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQ[15] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_BA[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQML +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_DQMH +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nWE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_nCS +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CKE +set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to SDRAM_CLK +set_global_assignment -name SDC_FILE mist/constraints.sdc set_global_assignment -name VERILOG_FILE mist/ps2_intf.v set_global_assignment -name VERILOG_FILE mist/keyboard.v set_global_assignment -name VERILOG_FILE mist/sigma_delta_dac.v