From 66584e822aa9dfdd5e111815fae9776a87264d96 Mon Sep 17 00:00:00 2001 From: Till Harbaum Date: Mon, 26 Oct 2015 21:06:21 +0100 Subject: [PATCH 1/4] [Plus Too] Floppy dsk support and various other small improvements --- cores/plus_too/addrController_top.v | 115 ++-- cores/plus_too/addrDecoder.v | 6 +- cores/plus_too/clock325MHz.qip | 4 - cores/plus_too/dataController_top.v | 86 +-- cores/plus_too/debugPanel.v | 218 ------- cores/plus_too/floppy.v | 134 ++-- cores/plus_too/floppy_track_encoder.v | 371 +++++++++++ cores/plus_too/fontGen.v | 173 ------ cores/plus_too/iwm.v | 64 +- cores/plus_too/led7seg.v | 30 - cores/plus_too/{clock325MHz.v => pll.v} | 118 +--- cores/plus_too/plusToo_top.qsf | 695 ++++++++++++++++++++- cores/plus_too/plusToo_top.v | 263 ++++---- cores/plus_too/ps2_kbd.v | 786 ++++++++++++++++++++++++ cores/plus_too/ps2_mouse.v | 36 +- cores/plus_too/readme.md | 10 +- cores/plus_too/scc.v | 79 +-- cores/plus_too/sdram.v | 20 +- cores/plus_too/testbench.v | 81 --- cores/plus_too/via.v | 134 ++-- cores/plus_too/videoTimer.v | 6 +- 21 files changed, 2375 insertions(+), 1054 deletions(-) delete mode 100644 cores/plus_too/clock325MHz.qip delete mode 100644 cores/plus_too/debugPanel.v create mode 100644 cores/plus_too/floppy_track_encoder.v delete mode 100644 cores/plus_too/fontGen.v delete mode 100644 cores/plus_too/led7seg.v rename cores/plus_too/{clock325MHz.v => pll.v} (74%) create mode 100644 cores/plus_too/ps2_kbd.v delete mode 100644 cores/plus_too/testbench.v diff --git a/cores/plus_too/addrController_top.v b/cores/plus_too/addrController_top.v index 8df5529..08c3a96 100644 --- a/cores/plus_too/addrController_top.v +++ b/cores/plus_too/addrController_top.v @@ -18,27 +18,23 @@ module addrController_top( output [21:0] memoryAddr, output _memoryUDS, output _memoryLDS, - output _romCS, output _romOE, - output _romWE, - output _ramCS, output _ramOE, output _ramWE, output videoBusControl, + output dioBusControl, // peripherals: output selectSCC, output selectIWM, output selectVIA, - output selectInterruptVectors, // video: output hsync, output vsync, output _hblank, output _vblank, - output loadNormalPixels, - output loadDebugPixels, + output loadPixels, // audio: output loadSound, @@ -46,23 +42,32 @@ module addrController_top( // misc input memoryOverlayOn, - // extra/debug ROM interface - input [21:0] extraRomReadAddr, - output extraRomReadAck + // interface to read dsk image from ram + input [21:0] dskReadAddrInt, + output dskReadAckInt, + input [21:0] dskReadAddrExt, + output dskReadAckExt ); +assign dioBusControl = extraBusControl; + // interleaved RAM access for CPU and video reg [1:0] busCycle; - always @(posedge clk8) begin + always @(posedge clk8) busCycle <= busCycle + 1'b1; - end + // video controls memory bus during the first clock of the four-clock cycle - assign videoBusControl = busCycle == 2'b00; - + assign videoBusControl = (busCycle == 2'b00); + // cpu controls memory bus during the third clock of the four-clock cycle + wire cpuBusControl = (busCycle == 2'b10); + + // + wire extraBusControl = (busCycle == 2'b01); + // DTACK generation // TODO: delay DTACK for once full bus cycle when RAM is accessed, to match Mac Plus memory timing // TODO: according to datasheet, /DTACK should continue to be asserted through the final bus cycle too - assign _cpuDTACK = ~(_cpuAS == 1'b0 && busCycle == 2'b10 && videoBusControl == 1'b0); + assign _cpuDTACK = ~(_cpuAS == 1'b0 && cpuBusControl); // interconnects wire selectRAM, selectROM; @@ -70,43 +75,62 @@ module addrController_top( // RAM/ROM control signals wire videoControlActive = _hblank == 1'b1 || loadSound; - assign _romCS = ~((videoBusControl == 1'b1 && videoControlActive == 1'b0) || (videoBusControl == 1'b0 && selectROM == 1'b1)); - assign _romOE = ~((videoBusControl == 1'b1 && videoControlActive == 1'b0) || (videoBusControl == 1'b0 && selectROM == 1'b1 && _cpuRW == 1'b1)); - assign _romWE = 1'b1; - assign _ramCS = ~((videoBusControl == 1'b1 && videoControlActive == 1'b1) || (videoBusControl == 1'b0 && selectRAM == 1'b1)); - assign _ramOE = ~((videoBusControl == 1'b1 && videoControlActive == 1'b1) || (videoBusControl == 1'b0 && selectRAM == 1'b1 && _cpuRW == 1'b1)); - assign _ramWE = ~(videoBusControl == 1'b0 && selectRAM && _cpuRW == 1'b0); - assign _memoryUDS = videoBusControl ? 1'b0 : _cpuUDS; - assign _memoryLDS = videoBusControl ? 1'b0 : _cpuLDS; + + assign _romOE = ~(extraBusControl || (cpuBusControl && selectROM == 1'b1 && _cpuRW == 1'b1)); +// assign _romOE = ~((videoBusControl && videoControlActive == 1'b0) || (cpuBusControl && selectROM == 1'b1 && _cpuRW == 1'b1)); + + assign _ramOE = ~((videoBusControl && videoControlActive == 1'b1) || + (cpuBusControl && selectRAM == 1'b1 && _cpuRW == 1'b1)); + assign _ramWE = ~(cpuBusControl && selectRAM && _cpuRW == 1'b0); + + assign _memoryUDS = cpuBusControl ? _cpuUDS : 1'b0; + assign _memoryLDS = cpuBusControl ? _cpuLDS : 1'b0; wire [21:0] addrMux = videoBusControl ? videoAddr : cpuAddr[21:0]; wire [21:0] macAddr; assign macAddr[15:0] = addrMux[15:0]; + + // video always addresses ram + wire ram_access = (cpuBusControl && selectRAM) || videoBusControl; // simulate smaller RAM/ROM sizes - assign macAddr[16] = selectROM == 1'b1 && configROMSize == 1'b0 ? 1'b0 : // force A16 to 0 for 64K ROM access + assign macAddr[16] = selectROM && configROMSize == 1'b0 ? 1'b0 : // force A16 to 0 for 64K ROM access addrMux[16]; - assign macAddr[17] = selectRAM == 1'b1 && configRAMSize == 2'b00 ? 1'b0 : // force A17 to 0 for 128K RAM access - selectROM == 1'b1 && configROMSize == 1'b1 ? 1'b0 : // force A17 to 0 for 128K ROM access - selectROM == 1'b1 && configROMSize == 1'b0 ? 1'b1 : // force A17 to 1 for 64K ROM access (64K ROM image is at $20000) + assign macAddr[17] = ram_access && configRAMSize == 2'b00 ? 1'b0 : // force A17 to 0 for 128K RAM access + selectROM && configROMSize == 1'b1 ? 1'b0 : // force A17 to 0 for 128K ROM access + selectROM && configROMSize == 1'b0 ? 1'b1 : // force A17 to 1 for 64K ROM access (64K ROM image is at $20000) addrMux[17]; - assign macAddr[18] = selectRAM == 1'b1 && configRAMSize == 2'b00 ? 1'b0 : // force A18 to 0 for 128K RAM access - selectROM == 1'b1 ? 1'b0 : // force A18 to 0 for ROM access + assign macAddr[18] = ram_access && configRAMSize == 2'b00 ? 1'b0 : // force A18 to 0 for 128K RAM access + selectROM ? 1'b0 : // force A18 to 0 for ROM access addrMux[18]; - assign macAddr[19] = selectRAM == 1'b1 && configRAMSize[1] == 1'b0 ? 1'b0 : // force A19 to 0 for 128K or 512K RAM access - selectROM == 1'b1 ? 1'b0 : // force A19 to 0 for ROM access + assign macAddr[19] = ram_access && configRAMSize[1] == 1'b0 ? 1'b0 : // force A19 to 0 for 128K or 512K RAM access + selectROM ? 1'b0 : // force A19 to 0 for ROM access addrMux[19]; - assign macAddr[20] = selectRAM == 1'b1 && configRAMSize != 2'b11 ? 1'b0 : // force A20 to 0 for all but 4MB RAM access - selectROM == 1'b1 ? 1'b0 : // force A20 to 0 for ROM access + assign macAddr[20] = ram_access && configRAMSize != 2'b11 ? 1'b0 : // force A20 to 0 for all but 4MB RAM access + selectROM ? 1'b0 : // force A20 to 0 for ROM access addrMux[20]; - assign macAddr[21] = selectRAM == 1'b1 && configRAMSize != 2'b11 ? 1'b0 : // force A21 to 0 for all but 4MB RAM access - selectROM == 1'b1 ? 1'b0 : // force A21 to 0 for ROM access + assign macAddr[21] = ram_access && configRAMSize != 2'b11 ? 1'b0 : // force A21 to 0 for all but 4MB RAM access + selectROM ? 1'b0 : // force A21 to 0 for ROM access addrMux[21]; - assign extraRomReadAck = videoBusControl == 1'b1 && videoControlActive == 1'b0; - assign memoryAddr = videoBusControl == 1'b1 && videoControlActive == 1'b0 ? extraRomReadAddr : macAddr; - + // allocate memory slots in the extra cycle + reg [2:0] extra_slot_count; + always @(posedge clk8) + if(busCycle == 2'b11) + extra_slot_count <= extra_slot_count + 2'd1; + + // loppy emulation gets extra slots 0 and 1 + assign dskReadAckInt = (extraBusControl == 1'b1) && (extra_slot_count == 0); + assign dskReadAckExt = (extraBusControl == 1'b1) && (extra_slot_count == 1); + + assign memoryAddr = + dskReadAckInt ? dskReadAddrInt + 22'h100000: // first dsk image at 1MB + dskReadAckExt ? dskReadAddrExt + 22'h200000: // second dsk image at 2MB + macAddr; + // address decoding wire selectSCCByAddress; + wire selectIWMByAddress; + wire selectVIAByAddress; addrDecoder ad( .address(cpuAddr), .enable(!videoBusControl), @@ -115,11 +139,12 @@ module addrController_top( .selectRAM(selectRAM), .selectROM(selectROM), .selectSCC(selectSCCByAddress), - .selectIWM(selectIWM), - .selectVIA(selectVIA), - .selectInterruptVectors(selectInterruptVectors)); + .selectIWM(selectIWMByAddress), + .selectVIA(selectVIAByAddress)); - /* SCC register access is a mess. Reads and writes can have side-effects that alter the meaning of subsequent reads + /* TH: The following isn't 100% true anymore but kept for now for documentation purposes ... + + SCC register access is a mess. Reads and writes can have side-effects that alter the meaning of subsequent reads and writes to the same address. It's not safe to do multiple reads of the same address, or multiple writes of the same value to the same address. So we need to be sure we only perform one read or write per 4-clock CPU bus cycle. @@ -142,8 +167,9 @@ module addrController_top( Another solution would be to create a custom clock for the SCC, whose positive edge is the negative edge of clock 3 of the bus cycle. */ - assign selectSCC = selectSCCByAddress && (busCycle == 2'b10 || // reads and writes enable on clock 2 - (_cpuRW == 1'b1 && busCycle == 2'b11 && clk8)); // reads enable on first half of clock 3 + assign selectSCC = selectSCCByAddress && cpuBusControl; + assign selectIWM = selectIWMByAddress && cpuBusControl; + assign selectVIA = selectVIAByAddress && cpuBusControl; // video videoTimer vt( @@ -154,8 +180,7 @@ module addrController_top( .vsync(vsync), ._hblank(_hblank), ._vblank(_vblank), - .loadNormalPixels(loadNormalPixels), - .loadDebugPixels(loadDebugPixels), + .loadPixels(loadPixels), .loadSound(loadSound)); endmodule diff --git a/cores/plus_too/addrDecoder.v b/cores/plus_too/addrDecoder.v index 8b4da3d..e889275 100644 --- a/cores/plus_too/addrDecoder.v +++ b/cores/plus_too/addrDecoder.v @@ -88,8 +88,7 @@ module addrDecoder( output reg selectROM, output reg selectSCC, output reg selectIWM, - output reg selectVIA, - output reg selectInterruptVectors + output reg selectVIA ); always @(*) begin @@ -98,7 +97,6 @@ module addrDecoder( selectSCC = 0; selectIWM = 0; selectVIA = 0; - selectInterruptVectors = 0; if (_cpuAS == 0 && enable == 1'b1) begin casez (address[23:20]) @@ -124,8 +122,6 @@ module addrDecoder( selectIWM = 1'b1; 4'b1110: selectVIA = 1'b1; - 4'b1111: - selectInterruptVectors = 1'b1; default: ; // select nothing endcase diff --git a/cores/plus_too/clock325MHz.qip b/cores/plus_too/clock325MHz.qip deleted file mode 100644 index bf6a93b..0000000 --- a/cores/plus_too/clock325MHz.qip +++ /dev/null @@ -1,4 +0,0 @@ -set_global_assignment -name IP_TOOL_NAME "ALTPLL" -set_global_assignment -name IP_TOOL_VERSION "13.1" -set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "clock325MHz.v"] -set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "clock325MHz.ppf"] diff --git a/cores/plus_too/dataController_top.v b/cores/plus_too/dataController_top.v index 16788a9..3e5b39d 100644 --- a/cores/plus_too/dataController_top.v +++ b/cores/plus_too/dataController_top.v @@ -1,8 +1,7 @@ module dataController_top( // clocks: input clk32, // 32.5 MHz pixel clock - input clk8, // 8.125 MHz CPU clock - output clk8out, // this module generates the 8.125MHz clock used for itself and other modules + output clk8, // 8.125 MHz CPU clock // system control: input _systemReset, @@ -19,27 +18,24 @@ module dataController_top( input _cpuLDS, input _cpuRW, output [15:0] cpuDataOut, - output cpuDriveData, // peripherals: input selectSCC, input selectIWM, input selectVIA, - input selectInterruptVectors, // RAM/ROM: input videoBusControl, input [15:0] memoryDataIn, output [15:0] memoryDataOut, - output memoryDriveData, // keyboard: input keyClk, // need pull-up input keyData, // need pull-up // mouse: - inout mouseClk, // need pull-up - inout mouseData, // need pull-up + input mouseClk, // need pull-up + input mouseData, // need pull-up // serial: input serialIn, // need pull-up @@ -54,17 +50,17 @@ module dataController_top( // audio: input loadSound, output sound, - - // debugging: - input interruptButton, - + // misc output memoryOverlayOn, input [1:0] insertDisk, - output [1:0] diskInDrive, - - output [21:0] extraRomReadAddr, - input extraRomReadAck + input [1:0] diskSides, + output [1:0] diskEject, + + output [21:0] dskReadAddrInt, + input dskReadAckInt, + output [21:0] dskReadAddrExt, + input dskReadAckExt ); // divide 32.5 MHz clock by four to get CPU clock @@ -72,7 +68,7 @@ module dataController_top( always @(posedge clk32) begin clkPhase <= clkPhase + 1'b1; end - assign clk8out = clkPhase[1]; + assign clk8 = clkPhase[1]; // CPU reset generation // For initial CPU reset, RESET and HALT must be asserted for at least 100ms = 800,000 clocks of clk8 @@ -103,7 +99,10 @@ module dataController_top( wire mouseX1, mouseX2, mouseY1, mouseY2, mouseButton; // interrupt control - assign _cpuIPL = { interruptButton, _sccIrq, ~(_sccIrq & ~_viaIrq) }; + assign _cpuIPL = + !_viaIrq?3'b110: + !_sccIrq?3'b101: + 3'b111; // Sound assign sound = 0; @@ -114,14 +113,11 @@ module dataController_top( // CPU-side data output mux assign cpuDataOut = selectIWM ? iwmDataOut : selectVIA ? viaDataOut : - selectSCC ? { sccDataOutDelayed, 8'hEF } : - selectInterruptVectors ? { 13'h3, cpuAddrRegLo } : // use A3-A1 to construct an interrupt vector number offset from $18 + selectSCC ? { sccDataOut, 8'hEF } : memoryDataIn; - assign cpuDriveData = _cpuRW == 1'b1; // Memory-side assign memoryDataOut = cpuDataIn; - assign memoryDriveData = _cpuRW == 1'b0 && videoBusControl == 1'b0; // VIA via v( @@ -141,8 +137,13 @@ module dataController_top( ._irq(_viaIrq), .dataOut(viaDataOut), .memoryOverlayOn(memoryOverlayOn), - .SEL(SEL)); - + .SEL(SEL), + .kbd_in_data(kbd_in_data), + .kbd_in_strobe(kbd_in_strobe), + .kbd_out_data(kbd_out_data), + .kbd_out_strobe(kbd_out_strobe) + ); + // IWM iwm i( .clk8(clk8), @@ -155,18 +156,22 @@ module dataController_top( .SEL(SEL), .dataOut(iwmDataOut), .insertDisk(insertDisk), - .diskInDrive(diskInDrive), + .diskSides(diskSides), + .diskEject(diskEject), - .extraRomReadAddr(extraRomReadAddr), - .extraRomReadAck(extraRomReadAck), - .extraRomReadData(memoryDataIn[7:0])); + .dskReadAddrInt(dskReadAddrInt), + .dskReadAckInt(dskReadAckInt), + .dskReadAddrExt(dskReadAddrExt), + .dskReadAckExt(dskReadAckExt), + .dskReadData(memoryDataIn[7:0]) + ); // SCC scc s( .sysclk(clk8), .reset_hw(~_cpuReset), .cs(selectSCC && (_cpuLDS == 1'b0 || _cpuUDS == 1'b0)), - .we(~_cpuRW), + .we(!_cpuRW), .rs(cpuAddrRegLo), .wdata(cpuDataIn[15:8]), .rdata(sccDataOut), @@ -174,14 +179,7 @@ module dataController_top( .dcd_a(mouseX1), .dcd_b(mouseY1), .wreq(sccWReq)); - - // apply a one cycle delay to CPU data reads from the SCC: - // see comment about SCC register access in addrController_top.v - reg [7:0] sccDataOutDelayed; - always @(posedge clk8) begin - sccDataOutDelayed <= sccDataOut; - end - + // Video videoShifter vs( .clk32(clk32), @@ -202,4 +200,20 @@ module dataController_top( .y2(mouseY2), .button(mouseButton)); + wire [7:0] kbd_in_data; + wire kbd_in_strobe; + wire [7:0] kbd_out_data; + wire kbd_out_strobe; + + // Keyboard + ps2_kbd kbd( + .sysclk(clk8), + .reset(~_cpuReset), + .ps2dat(keyData), + .ps2clk(keyClk), + .data_out(kbd_out_data), // data from mac + .strobe_out(kbd_out_strobe), + .data_in(kbd_in_data), // data to mac + .strobe_in(kbd_in_strobe)); + endmodule diff --git a/cores/plus_too/debugPanel.v b/cores/plus_too/debugPanel.v deleted file mode 100644 index 5764f08..0000000 --- a/cores/plus_too/debugPanel.v +++ /dev/null @@ -1,218 +0,0 @@ -module debugPanel( - input clk8, - input [9:0] sw, - input [3:0] key, - input videoBusControl, - input loadNormalPixels, - input loadDebugPixels, - output loadPixelsOut, - input _dtackIn, - input [7:0] cpuAddrHi, - input [23:0] cpuAddr, - input _cpuRW, - input _cpuUDS, - input _cpuLDS, - input [15:0] dataControllerDataOut, - input [15:0] cpuDataOut, - input [21:0] memoryAddr, - output _dtackOut, - output [6:0] hex0, - output [6:0] hex1, - output [6:0] hex2, - output [6:0] hex3, - output driveDebugData, - output [15:0] debugDataOut, - input extraRomReadAck -); - - /* debug interface: - sw0 = run/stop_and_disable_interrupts - sw2-9 = data in - key0 = step - key1 = load breakpoint addr[7:0] - key2 = load breakpoint addr[15:8] - key3 = load breakpoint addr[23:16] - key0+key1 = reset - */ - - wire singleStep = sw[0]; - - // sample dataControllerDataOut only when CPU owns the bus - // use negative edge sample, since that's when the CPU latches data - reg [15:0] dataControllerDataOutSample; - always @(negedge clk8) begin - if (videoBusControl == 0) - dataControllerDataOutSample <= dataControllerDataOut; - end - - // store the previous address, sort of a previous instruction address - reg [23:0] previousAddr; - reg [23:0] currAddr; - always @(negedge clk8) begin - if (videoBusControl == 1'b0 && cpuAddr != currAddr) begin - previousAddr <= currAddr; - currAddr <= cpuAddr; - end - end - - reg [23:0] breakpointAddr = 24'hDABEEF; - always @(negedge clk8) begin - if (singleStep == 1'b1 && key[1] == 1'b0) - breakpointAddr[7:0] <= sw[9:2]; - else if (singleStep == 1'b1 && key[2] == 1'b0) - breakpointAddr[15:8] <= sw[9:2]; - else if (singleStep == 1'b1 && key[3] == 1'b0) - breakpointAddr[23:16] <= sw[9:2]; - end - - // find xy position for debug panel - assign driveDebugData = loadDebugPixels && (memoryAddr[16:0] < 17'h00200); - assign loadPixelsOut = loadNormalPixels | driveDebugData; - wire [4:0] pixX = memoryAddr[5:1]; // 16-bit word: 0 to 31 - wire [2:0] pixY = memoryAddr[8:6]; // row: 0 to 7 - - // decide what characters to display - reg [5:0] char0; - reg [5:0] char1; - always @(*) begin - case (pixX) - 5'h0: begin - char0 = 6'hA; - char1 = 6'h3F; - end - 5'h1: begin - char0 = cpuAddr[23:20]; - char1 = cpuAddr[19:16]; - end - 5'h2: begin - char0 = cpuAddr[15:12]; - char1 = cpuAddr[11:8]; - end - 5'h3: begin - char0 = cpuAddr[7:4]; - char1 = cpuAddr[3:0]; - end - 5'h5: begin - char0 = 6'hD; - char1 = 6'h1; - end - 5'h6: begin - char0 = 6'h3F; - char1 = dataControllerDataOutSample[15:12]; - end - 5'h7: begin - char0 = dataControllerDataOutSample[11:8]; - char1 = dataControllerDataOutSample[7:4]; - end - 5'h8: begin - char0 = dataControllerDataOutSample[3:0]; - char1 = 6'h3F; - end - 5'h9: begin - char0 = 6'h3F; - char1 = 6'hD; - end - 5'hA: begin - char0 = 6'h0; - char1 = 6'h3F; - end - 5'hB: begin - char0 = cpuDataOut[15:12]; - char1 = cpuDataOut[11:8]; - end - 5'hC: begin - char0 = cpuDataOut[7:4]; - char1 = cpuDataOut[3:0]; - end - 5'hD: begin - char0 = 6'h3F; - char1 = _cpuRW ? 6'h1 : 6'h0; - end - 5'hE: begin - char0 = _cpuUDS ? 6'h1 : 6'h0; - char1 = _cpuLDS ? 6'h1 : 6'h0; - end - 5'hF: begin - char0 = 6'h3F; - char1 = 6'hA; - end - 5'h10: begin - char0 = 6'hA; - char1 = 6'h3F; - end - 5'h11: begin - char0 = previousAddr[23:20]; - char1 = previousAddr[19:16]; - end - 5'h12: begin - char0 = previousAddr[15:12]; - char1 = previousAddr[11:8]; - end - 5'h13: begin - char0 = previousAddr[7:4]; - char1 = previousAddr[3:0]; - end - 5'h14: begin - char0 = 6'h3F; - char1 = 6'h3F; - end - 5'h15: begin - char0 = 6'hB; - char1 = 6'h3F; - end - 5'h16: begin - char0 = breakpointAddr[23:20]; - char1 = breakpointAddr[19:16]; - end - 5'h17: begin - char0 = breakpointAddr[15:12]; - char1 = breakpointAddr[11:8]; - end - 5'h18: begin - char0 = breakpointAddr[7:4]; - char1 = breakpointAddr[3:0]; - end - default: begin - char0 = 6'h3F; - char1 = 6'h3F; - end - endcase - end - - // map characters to font data - wire [7:0] font0; - wire [7:0] font1; - fontGen fg0(.char(char0), .row(pixY), .dataOut(font0)); - fontGen fg1(.char(char1), .row(pixY), .dataOut(font1)); - assign debugDataOut = { font0, font1 }; - - // display extra ROM data on 7-segment LEDs - reg [7:0] extraRomData; - always @(posedge clk8) begin - if (extraRomReadAck) begin - extraRomData <= dataControllerDataOut[7:0]; - end - end - - // map the chosen data to the hex display - led7seg ls0(.data(extraRomData[3:0]), .segments(hex0)); - led7seg ls1(.data(extraRomData[7:4]), .segments(hex1)); - led7seg ls2(.data({4'b0000}), .segments(hex2)); - led7seg ls3(.data({4'b0000}), .segments(hex3)); - - // withhold DTACK if stopped and delay timer != 0 - reg [19:0] delayDTACK; - assign _dtackOut = (singleStep == 1'b0 && cpuAddr != breakpointAddr) ? _dtackIn : (_dtackIn | (delayDTACK != 0)); - - // debounce step key and set DTACK delay timer - always @(posedge clk8) begin - if (key[0] == 1'b1) - delayDTACK = 20'hFFFFE; - else - if (delayDTACK != 0 && delayDTACK != 20'hFFFFF) - delayDTACK = delayDTACK - 1'b1; - else if (delayDTACK == 0 && _dtackIn == 0) - delayDTACK = 20'hFFFFF; - end - -endmodule diff --git a/cores/plus_too/floppy.v b/cores/plus_too/floppy.v index fecc456..6dcffc6 100644 --- a/cores/plus_too/floppy.v +++ b/cores/plus_too/floppy.v @@ -70,15 +70,15 @@ module floppy( input [7:0] writeData, output [7:0] readData, - input useDiskImage, input advanceDriveHead, // prevents overrun when debugging, does not exist on a real Mac! output reg newByteReady, input insertDisk, - output diskInDrive, - - output [21:0] extraRomReadAddr, - input extraRomReadAck, - input [7:0] extraRomReadData + input diskSides, + output diskEject, + + output [21:0] dskReadAddr, + input dskReadAck, + input [7:0] dskReadData ); reg [15:0] driveRegs; @@ -105,63 +105,39 @@ module floppy( driveRegs[`DRIVE_REG_CSTIN], // disk in drive driveRegs[`DRIVE_REG_DIRTN] // step direction }; + + // latch incoming data + reg [7:0] dskReadDataLatch; + always @(posedge clk8) + if(dskReadAck) + dskReadDataLatch <= dskReadData; + + // generate glitch free data clock + reg data_clock; + always @(posedge clk8) + data_clock <= (diskDataByteTimer == 0); + + wire [7:0] dskReadDataEnc; + + // include track encoder + floppy_track_encoder enc ( + .clk ( newByteReady ), + .rst ( !_reset ), + + .side ( driveSide ), + .sides ( doubleSidedDisk ), + .track ( driveTrack ), + + .addr ( dskReadAddr ), + + .strobe ( ), + .idata ( dskReadDataLatch ), + .odata ( dskReadDataEnc ) + ); // TODO: auto-detect doubleSidedDisk from image file size - wire doubleSidedDisk = 1'b1; + wire doubleSidedDisk = diskSides; - // number of bytes in one side of the current track - reg [15:0] diskImageTrackSideLen; - always @(*) begin - case (driveTrack[6:4]) - 3'b000: - diskImageTrackSideLen = 12 * 1024; - 3'b001: - diskImageTrackSideLen = 11 * 1024; - 3'b010: - diskImageTrackSideLen = 10 * 1024; - 3'b011: - diskImageTrackSideLen = 9 * 1024; - 3'b100: - diskImageTrackSideLen = 8 * 1024; - default: - diskImageTrackSideLen = 8 * 1024; - endcase - end - wire [15:0] diskImageTrackLen = doubleSidedDisk ? {diskImageTrackSideLen[14:0], 1'b0 } : diskImageTrackSideLen; - // number of bytes in one side of the track before the current track (used for stepping backwards) - wire [6:0] driveTrackMinus1 = driveTrack - 1'b1; // can't step backward from track 0, so underflow doesn't matter - reg [15:0] diskImageTrackMinus1SideLen; - always @(*) begin - case (driveTrackMinus1[6:4]) - 3'b000: - diskImageTrackMinus1SideLen = 12 * 1024; - 3'b001: - diskImageTrackMinus1SideLen = 11 * 1024; - 3'b010: - diskImageTrackMinus1SideLen = 10 * 1024; - 3'b011: - diskImageTrackMinus1SideLen = 9 * 1024; - 3'b100: - diskImageTrackMinus1SideLen = 8 * 1024; - default: - diskImageTrackMinus1SideLen = 8 * 1024; - endcase - end - wire [15:0] diskImageTrackMinus1Len = doubleSidedDisk ? {diskImageTrackMinus1SideLen[14:0], 1'b0 } : diskImageTrackMinus1SideLen; - - - // offset from the start of the disk image to the start of the current track - reg [21:0] diskImageTrackBase; - - // bytes offset in the current side of the current track, must be less than diskImageTrackSideLen - reg [15:0] diskImageHeadOffset; - - assign extraRomReadAddr = - 22'h020000 + - diskImageTrackBase + - ((driveSide && doubleSidedDisk) ? diskImageTrackSideLen : 0) + - diskImageHeadOffset; - wire [3:0] driveReadAddr = {ca2,ca1,ca0,SEL}; // a byte is read or written every 128 clocks (2 us per bit * 8 bits = 16 us, @ 8 MHz = 128 clocks) @@ -171,40 +147,39 @@ module floppy( reg readyToAdvanceHead; always @(posedge clk8 or negedge _reset) begin if (_reset == 1'b0) begin - diskImageHeadOffset <= 1'b0; driveSide <= 0; diskImageData <= 8'h00; diskDataIn <= 8'hFF; diskDataByteTimer <= 0; readyToAdvanceHead <= 1; + newByteReady <= 1'b0; end else begin - // a timer governs when the next disk byte will become available - diskDataByteTimer <= diskDataByteTimer + 1'b1; - // at time 0, latch a new byte and advance the drive head if (diskDataByteTimer == 0 && readyToAdvanceHead && diskImageData != 0) begin - diskDataIn <= useDiskImage ? diskImageData : 8'hFF; + diskDataIn <= diskImageData; newByteReady <= 1'b1; - - if (diskImageHeadOffset + 1'b1 >= diskImageTrackSideLen) - diskImageHeadOffset <= 0; - else - diskImageHeadOffset <= diskImageHeadOffset + 1'b1; - + diskDataByteTimer <= 1; // make timer run again + // clear diskImageData after it's used, so we can tell when we get a new one from the disk diskImageData <= 0; // for debugging, don't advance the head until the IWM says it's ready readyToAdvanceHead <= 1'b1; // TEMP: treat IWM as always ready end + + // extraRomReadAck comes every hsync which is every 21us. The iwm data rates + // is 8MHZ/128 = 16us else begin + // a timer governs when the next disk byte will become available + diskDataByteTimer <= diskDataByteTimer + 1'b1; + newByteReady <= 1'b0; - if (extraRomReadAck) begin + if (dskReadAck) begin // whenever ACK is received, store the data from the current diskImageAddr - diskImageData <= extraRomReadData; - end + diskImageData <= dskReadDataEnc; // xyz + end if (advanceDriveHead) begin readyToAdvanceHead <= 1'b1; @@ -221,10 +196,11 @@ module floppy( end end + // create a signal on the falling edge of lstrb reg lstrbPrev; - always @(posedge clk8) begin + always @(posedge clk8) lstrbPrev <= lstrb; - end + wire lstrbEdge = lstrb == 1'b0 && lstrbPrev == 1'b1; assign readData = _enable == 1'b1 ? 8'hZZ : @@ -249,11 +225,12 @@ module floppy( /* W: ?? reset disk switch flag ? */ // disk in drive indicators reg [23:0] ejectIndicatorTimer; - assign diskInDrive = ~driveRegs[`DRIVE_REG_CSTIN] | ejectIndicatorTimer[20]; + assign diskEject = (ejectIndicatorTimer != 0); always @(posedge clk8 or negedge _reset) begin if (_reset == 1'b0) begin driveRegs[`DRIVE_REG_CSTIN] <= 1'b1; + ejectIndicatorTimer <= 24'd0; end else if (_enable == 1'b0 && lstrbEdge == 1'b1 && driveWriteAddr == `DRIVE_REG_EJECT && ca2 == 1'b1) begin // eject the disk @@ -275,16 +252,13 @@ module floppy( always @(posedge clk8 or negedge _reset) begin if (_reset == 1'b0) begin driveTrack <= 0; - diskImageTrackBase <= 0; end else if (_enable == 1'b0 && lstrbEdge == 1'b1 && driveWriteAddr == `DRIVE_REG_STEP && ca2 == 1'b0) begin if (driveRegs[`DRIVE_REG_DIRTN] == 1'b0 && driveTrack != 7'h4F) begin driveTrack <= driveTrack + 1'b1; - diskImageTrackBase <= diskImageTrackBase + diskImageTrackLen; end if (driveRegs[`DRIVE_REG_DIRTN] == 1'b1 && driveTrack != 0) begin driveTrack <= driveTrack - 1'b1; - diskImageTrackBase <= diskImageTrackBase - diskImageTrackMinus1Len; end end end diff --git a/cores/plus_too/floppy_track_encoder.v b/cores/plus_too/floppy_track_encoder.v new file mode 100644 index 0000000..aadfa4a --- /dev/null +++ b/cores/plus_too/floppy_track_encoder.v @@ -0,0 +1,371 @@ +/* + floppy_track_encoder.v + + encode a full floppy track from raw sector data on the fly + + */ + +/* verilator lint_off UNUSED */ +/* verilator lint_off UNDRIVEN */ +/* verilator lint_off CASEINCOMPLETE */ + +module floppy_track_encoder ( + // system signals + input clk, // clock at which data bytes are delivered via odata + input rst, + + input side, + input sides, + input [6:0] track, // current track + + output [21:0] addr, // address to fetch from + input [7:0] idata, + + output [7:0] odata +); + +assign addr = + { 3'b00, soff, 9'd0 } + // sector offset * 512 for two sides + (sides?{ 3'b00, soff, 9'd0 }:22'd0) + // another sector offset * 512 for two sides + (side?{ 9'd0, spt, 9'd0 }:22'd0) + // side * sectors * 512 + { 9'd0, sector, src_offset }; // offset within track + + // number of sectors on current track + wire [3:0] spt = + (track[6:4] == 3'd0)?4'd12: // track 0 - 15 + (track[6:4] == 3'd1)?4'd11: // track 16 - 31 + (track[6:4] == 3'd2)?4'd10: // track 32 - 47 + (track[6:4] == 3'd3)?4'd9: // track 48 - 63 + 4'd8; // track 64 - ... + + // all possible tack*sector factors + wire [9:0] track_times_12 = // x*12 = x*8 + x*4 + { track, 3'b000 } + // x<<3 + + { 1'b0, track, 2'b00 }; // x<<2 + + wire [9:0] track_times_11 = // x*11 = x*8 + x*2 + x*1 + { track, 3'b000 } + // x<<3 + + { 2'b00, track, 1'b0 } + // x<<1 + + { 3'b000, track }; // x<<0 + + wire [9:0] track_times_10 = // x*10 = x*8 + x*2 + { track, 3'b000 } + // x<<3 + + { 2'b00, track, 1'b0 }; // x<<1 + + wire [9:0] track_times_9 = // x*9 = x*8 + x*1 + { track, 3'b000 } + // x<<3 + + { 3'b000, track }; // x<<0 + + wire [9:0] track_times_8 = // x*8 + { track, 3'b000 }; // x<<3 + + // sector offset of current track is the sum of all sectors on all tracks before + wire [6:0] trackm1 = track - 7'd1; + wire [9:0] soff = + (track == 0)?10'd0: // track 0 + (trackm1[6:4] == 3'd0)?track_times_12: // track 1 - 16 + (trackm1[6:4] == 3'd1)?(track_times_11 + 10'd16): // track 17 - 32 + (trackm1[6:4] == 3'd2)?(track_times_10 + 10'd32 + 10'd16): // track 33 - 48 + (trackm1[6:4] == 3'd3)?(track_times_9 + 10'd48 + 10'd32 + 10'd16): // track 49 - 64 + (track_times_8 + 10'd64 + 10'd48 + 10'd32 + 10'd16); // track 65 - + + // parts of an address block + wire [5:0] sec_in_tr = {2'b00, sector}; + wire [5:0] track_low = track[5:0]; + wire [5:0] track_hi = { side, 4'b0000, track[6] }; + wire [5:0] format = { sides, 5'h2 }; // double sided = 22, single sided = 2 + wire [5:0] checksum = track_low ^ sec_in_tr ^ track_hi ^ format; + + // data input to the sony encoder during address block + wire [5:0] sony_addr_in = + (count == 3)?track_low: + (count == 4)?sec_in_tr: + (count == 5)?track_hi: + (count == 6)?format: + checksum; + + // data input to the sony encoder during data header + wire [5:0] sony_dhdr_in = sec_in_tr; + + wire [5:0] sony_dsum_in = + (count == 0)?{ c3[7:6], c2[7:6], c1[7:6] }: + (count == 1)?c3[5:0]: + (count == 2)?c2[5:0]: + c1[5:0]; + + // feed data into sony encoder + wire [5:0] si = + (state == STATE_ADDR)?sony_addr_in: + (state == STATE_DHDR)?sony_dhdr_in: + (state == STATE_DZRO)?nib_out: + (state == STATE_DPRE)?nib_out: + (state == STATE_DATA)?nib_out: + (state == STATE_DSUM)?sony_dsum_in: + 6'h3f; + + // encoder table taken from MESS emulator + wire [7:0] sony_to_disk_byte = + (si==6'h00)?8'h96:(si==6'h01)?8'h97:(si==6'h02)?8'h9a:(si==6'h03)?8'h9b: // 0x00 + (si==6'h04)?8'h9d:(si==6'h05)?8'h9e:(si==6'h06)?8'h9f:(si==6'h07)?8'ha6: + (si==6'h08)?8'ha7:(si==6'h09)?8'hab:(si==6'h0a)?8'hac:(si==6'h0b)?8'had: + (si==6'h0c)?8'hae:(si==6'h0d)?8'haf:(si==6'h0e)?8'hb2:(si==6'h0f)?8'hb3: + + (si==6'h10)?8'hb4:(si==6'h11)?8'hb5:(si==6'h12)?8'hb6:(si==6'h13)?8'hb7: // 0x10 + (si==6'h14)?8'hb9:(si==6'h15)?8'hba:(si==6'h16)?8'hbb:(si==6'h17)?8'hbc: + (si==6'h18)?8'hbd:(si==6'h19)?8'hbe:(si==6'h1a)?8'hbf:(si==6'h1b)?8'hcb: + (si==6'h1c)?8'hcd:(si==6'h1d)?8'hce:(si==6'h1e)?8'hcf:(si==6'h1f)?8'hd3: + + (si==6'h20)?8'hd6:(si==6'h21)?8'hd7:(si==6'h22)?8'hd9:(si==6'h23)?8'hda: // 0x20 + (si==6'h24)?8'hdb:(si==6'h25)?8'hdc:(si==6'h26)?8'hdd:(si==6'h27)?8'hde: + (si==6'h28)?8'hdf:(si==6'h29)?8'he5:(si==6'h2a)?8'he6:(si==6'h2b)?8'he7: + (si==6'h2c)?8'he9:(si==6'h2d)?8'hea:(si==6'h2e)?8'heb:(si==6'h2f)?8'hec: + + (si==6'h30)?8'hed:(si==6'h31)?8'hee:(si==6'h32)?8'hef:(si==6'h33)?8'hf2: // 0x30 + (si==6'h34)?8'hf3:(si==6'h35)?8'hf4:(si==6'h36)?8'hf5:(si==6'h37)?8'hf6: + (si==6'h38)?8'hf7:(si==6'h39)?8'hf9:(si==6'h3a)?8'hfa:(si==6'h3b)?8'hfb: + (si==6'h3c)?8'hfc:(si==6'h3d)?8'hfd:(si==6'h3e)?8'hfe: 8'hff; + + // states of encoder state machine + localparam STATE_SYN0 = 4'd0; // 56 bytes sync pattern (0xff) + localparam STATE_ADDR = 4'd1; // 10 bytes address block + localparam STATE_SYN1 = 4'd2; // 5 bytes sync pattern (0xff) + localparam STATE_DHDR = 4'd3; // 4 bytes data block header + localparam STATE_DZRO = 4'd4; // 8 encoded zero bytes in data block + localparam STATE_DPRE = 4'd5; // 4 bytes data prefetch + localparam STATE_DATA = 4'd6; // the payload itself + localparam STATE_DSUM = 4'd7; // 4 bytes data checksum + localparam STATE_DTRL = 4'd8; // 3 bytes data block trailer + localparam STATE_WAIT = 4'd15; // wait until start of next sector + + // output data during address block + wire [7:0] odata_addr = + (count == 0)?8'hd5: + (count == 1)?8'haa: + (count == 2)?8'h96: + (count == 8)?8'hde: + (count == 9)?8'haa: + sony_to_disk_byte; + + wire [7:0] odata_dhdr = + (count == 0)?8'hd5: + (count == 1)?8'haa: + (count == 2)?8'had: + sony_to_disk_byte; + + wire [7:0] odata_dsum = + sony_to_disk_byte; + + wire [7:0] odata_dtrl = + (count == 0)?8'hde: + (count == 1)?8'haa: + 8'hff; + + // demultiplex output data + assign odata = (state == STATE_ADDR)?odata_addr: + (state == STATE_DHDR)?odata_dhdr: + (state == STATE_DZRO)?sony_to_disk_byte: + (state == STATE_DPRE)?sony_to_disk_byte: + (state == STATE_DATA)?sony_to_disk_byte: + (state == STATE_DSUM)?sony_to_disk_byte: + (state == STATE_DTRL)?odata_dtrl: + 8'hff; + + // ------------------------ nibbler ---------------------------- + + reg [7:0] c1; + reg [7:0] c2; + reg c2x; + reg [7:0] c3; + reg c3x; + + wire nibbler_reset = (state == STATE_DHDR); + reg [1:0] cnt; + + reg [7:0] nib_xor_0; + reg [7:0] nib_xor_1; + reg [7:0] nib_xor_2; + + // request an input byte. this happens 4 byte ahead of output. + // only three bytes are read while four bytes are written due + // to 6:2 encoding + wire strobe = ((state == STATE_DPRE) || + ((state == STATE_DATA) && (count < 683-4-1))) + && (cnt != 3); + + reg [7:0] data_latch; + always @(posedge clk) + if(strobe) + data_latch <= idata; + +always @(posedge clk or posedge nibbler_reset) begin + if(nibbler_reset) begin + c1 <= 8'h00; + c2 <= 8'h00; + c2x <= 1'b0; + c3 <= 8'h00; + c3x <= 1'b0; + cnt <= 2'd0; + nib_xor_0 <= 8'h00; + nib_xor_1 <= 8'h00; + nib_xor_2 <= 8'h00; + end else if((state == STATE_DPRE) || (state == STATE_DATA)) begin + cnt <= cnt + 2'd1; + + // memory read during cnt 0-3 + if(count < 683-4) begin + + // encode first byte + if(cnt == 1) begin + c1 <= { c1[6:0], c1[7] }; + { c3x, c3 } <= { 1'b0, c3 } + { 1'b0, nib_in } + { 8'd0, c1[7] }; + nib_xor_0 <= nib_in ^ { c1[6:0], c1[7] }; + end + + // encode second byte + if(cnt == 2) begin + { c2x, c2 } <= { 1'b0, c2 } + { 1'b0, nib_in } + { 8'd0, c3x }; + c3x <= 1'b0; + nib_xor_1 <= nib_in ^ c3; + end + + // encode third byte + if(cnt == 3) begin + c1 <= c1 + nib_in + { 7'd0, c2x }; + c2x <= 1'b0; + nib_xor_2 <= nib_in ^ c2; + end + end else begin + // since there are 512/3 = 170 2/3 three byte blocks in a sector the + // last run has to be filled up with zeros + if(cnt == 3) + nib_xor_2 <= 8'h00; + end + end +end + +// bytes going into the nibbler +wire [7:0] nib_in = + (state == STATE_DZRO)?8'h00: + data_latch; + +// four six bit units come out of the nibbler +wire [5:0] nib_out = + (cnt == 1)?nib_xor_0[5:0]: + (cnt == 2)?nib_xor_1[5:0]: + (cnt == 3)?nib_xor_2[5:0]: + { nib_xor_0[7:6], nib_xor_1[7:6], nib_xor_2[7:6] }; + +// count bytes per sector +reg [3:0] state; +reg [9:0] count; +reg [3:0] sector; +reg [8:0] src_offset; +always @(posedge clk or posedge rst) begin + if(rst) begin + count <= 10'd0; + state <= STATE_SYN0; + sector <= 4'd0; + src_offset <= 9'd0; + end else begin + count <= count + 10'd1; + + if(strobe) + src_offset <= src_offset + 9'd1; + + case(state) + + // send 14*4=56 sync bytes + STATE_SYN0: begin + if(count == 55) begin + state <= STATE_ADDR; + count <= 10'd0; + end + end + + // send 10 bytes address block + STATE_ADDR: begin + if(count == 9) begin + state <= STATE_SYN1; + count <= 10'd0; + end + end + + // send 5 sync bytes + STATE_SYN1: begin + if(count == 4) begin + state <= STATE_DHDR; + count <= 10'd0; + end + end + + // send 4 bytes data block hdr + STATE_DHDR: begin + if(count == 3) begin + state <= STATE_DZRO; + count <= 10'd0; + end + end + + // send 8 zero bytes before data block + STATE_DZRO: begin + if(count == 11) begin + state <= STATE_DPRE; + count <= 10'd0; + end + end + + // start prefetching 4 bytes data + STATE_DPRE: begin + if(count == 3) begin + state <= STATE_DATA; + count <= 10'd0; + end + end + + // send 512 bytes data block 6:2 encoded in 683 bytes + STATE_DATA: begin + if(count == 682) begin + state <= STATE_DSUM; + count <= 10'd0; + end + end + + // send 4 bytes data checksum + STATE_DSUM: begin + if(count == 3) begin + state <= STATE_DTRL; + count <= 10'd0; + end + end + + // send 3 bytes data block trailer + STATE_DTRL: begin + if(count == 2) begin + state <= STATE_WAIT; + count <= 10'd0; + end + end + + // fill sector up to 1024 bytes + STATE_WAIT: begin +// if(count == 1023-56-10-5-4-12-4-683-4-3) + begin + count <= 10'd0; + state <= STATE_SYN0; + src_offset <= 9'd0; + + // interleave of 1 +// if(sector != spt-4'd1) sector <= sector + 4'd1; +// else sector <= 4'd0; + + // interleave of 2 + if((sector == spt-4'd2) || + (sector == spt-4'd1)) sector <= { 3'd0, !sector[0] }; + else sector <= sector + 4'd2; + end + end + endcase + end +end + +endmodule diff --git a/cores/plus_too/fontGen.v b/cores/plus_too/fontGen.v deleted file mode 100644 index 0c99dbd..0000000 --- a/cores/plus_too/fontGen.v +++ /dev/null @@ -1,173 +0,0 @@ -module fontGen( - input [5:0] char, - input [2:0] row, - output reg [7:0] dataOut -); - - always @(*) begin - case ( { char, row } ) - // 0 - { 4'h0, 3'h0 }: dataOut = 8'b11111111; - { 4'h0, 3'h1 }: dataOut = 8'b11000011; - { 4'h0, 3'h2 }: dataOut = 8'b10011001; - { 4'h0, 3'h3 }: dataOut = 8'b10010001; - { 4'h0, 3'h4 }: dataOut = 8'b10001001; - { 4'h0, 3'h5 }: dataOut = 8'b10011001; - { 4'h0, 3'h6 }: dataOut = 8'b11000011; - { 4'h0, 3'h7 }: dataOut = 8'b11111111; - - // 1 - { 4'h1, 3'h0 }: dataOut = 8'b11111111; - { 4'h1, 3'h1 }: dataOut = 8'b11100111; - { 4'h1, 3'h2 }: dataOut = 8'b11000111; - { 4'h1, 3'h3 }: dataOut = 8'b11100111; - { 4'h1, 3'h4 }: dataOut = 8'b11100111; - { 4'h1, 3'h5 }: dataOut = 8'b11100111; - { 4'h1, 3'h6 }: dataOut = 8'b10000001; - { 4'h1, 3'h7 }: dataOut = 8'b11111111; - - // 2 - { 4'h2, 3'h0 }: dataOut = 8'b11111111; - { 4'h2, 3'h1 }: dataOut = 8'b11000011; - { 4'h2, 3'h2 }: dataOut = 8'b10011001; - { 4'h2, 3'h3 }: dataOut = 8'b11110011; - { 4'h2, 3'h4 }: dataOut = 8'b11100111; - { 4'h2, 3'h5 }: dataOut = 8'b11001111; - { 4'h2, 3'h6 }: dataOut = 8'b10000001; - { 4'h2, 3'h7 }: dataOut = 8'b11111111; - - // 3 - { 4'h3, 3'h0 }: dataOut = 8'b11111111; - { 4'h3, 3'h1 }: dataOut = 8'b10000001; - { 4'h3, 3'h2 }: dataOut = 8'b11110011; - { 4'h3, 3'h3 }: dataOut = 8'b11100111; - { 4'h3, 3'h4 }: dataOut = 8'b11110011; - { 4'h3, 3'h5 }: dataOut = 8'b10011001; - { 4'h3, 3'h6 }: dataOut = 8'b11000011; - { 4'h3, 3'h7 }: dataOut = 8'b11111111; - - // 4 - { 4'h4, 3'h0 }: dataOut = 8'b11111111; - { 4'h4, 3'h1 }: dataOut = 8'b11110011; - { 4'h4, 3'h2 }: dataOut = 8'b11100011; - { 4'h4, 3'h3 }: dataOut = 8'b11000011; - { 4'h4, 3'h4 }: dataOut = 8'b10010011; - { 4'h4, 3'h5 }: dataOut = 8'b10000001; - { 4'h4, 3'h6 }: dataOut = 8'b11110011; - { 4'h4, 3'h7 }: dataOut = 8'b11111111; - - // 5 - { 4'h5, 3'h0 }: dataOut = 8'b11111111; - { 4'h5, 3'h1 }: dataOut = 8'b10000001; - { 4'h5, 3'h2 }: dataOut = 8'b10011111; - { 4'h5, 3'h3 }: dataOut = 8'b10000011; - { 4'h5, 3'h4 }: dataOut = 8'b11111001; - { 4'h5, 3'h5 }: dataOut = 8'b10011001; - { 4'h5, 3'h6 }: dataOut = 8'b11000011; - { 4'h5, 3'h7 }: dataOut = 8'b11111111; - - // 6 - { 4'h6, 3'h0 }: dataOut = 8'b11111111; - { 4'h6, 3'h1 }: dataOut = 8'b11000011; - { 4'h6, 3'h2 }: dataOut = 8'b10011111; - { 4'h6, 3'h3 }: dataOut = 8'b10000011; - { 4'h6, 3'h4 }: dataOut = 8'b10011001; - { 4'h6, 3'h5 }: dataOut = 8'b10011001; - { 4'h6, 3'h6 }: dataOut = 8'b11000011; - { 4'h6, 3'h7 }: dataOut = 8'b11111111; - - // 7 - { 4'h7, 3'h0 }: dataOut = 8'b11111111; - { 4'h7, 3'h1 }: dataOut = 8'b10000001; - { 4'h7, 3'h2 }: dataOut = 8'b11111001; - { 4'h7, 3'h3 }: dataOut = 8'b11110011; - { 4'h7, 3'h4 }: dataOut = 8'b11100111; - { 4'h7, 3'h5 }: dataOut = 8'b11001111; - { 4'h7, 3'h6 }: dataOut = 8'b11001111; - { 4'h7, 3'h7 }: dataOut = 8'b11111111; - - // 8 - { 4'h8, 3'h0 }: dataOut = 8'b11111111; - { 4'h8, 3'h1 }: dataOut = 8'b11000011; - { 4'h8, 3'h2 }: dataOut = 8'b10011001; - { 4'h8, 3'h3 }: dataOut = 8'b11000011; - { 4'h8, 3'h4 }: dataOut = 8'b10011001; - { 4'h8, 3'h5 }: dataOut = 8'b10011001; - { 4'h8, 3'h6 }: dataOut = 8'b11000011; - { 4'h8, 3'h7 }: dataOut = 8'b11111111; - - // 9 - { 4'h9, 3'h0 }: dataOut = 8'b11111111; - { 4'h9, 3'h1 }: dataOut = 8'b11000011; - { 4'h9, 3'h2 }: dataOut = 8'b10011001; - { 4'h9, 3'h3 }: dataOut = 8'b11000001; - { 4'h9, 3'h4 }: dataOut = 8'b11111001; - { 4'h9, 3'h5 }: dataOut = 8'b11110011; - { 4'h9, 3'h6 }: dataOut = 8'b11000111; - { 4'h9, 3'h7 }: dataOut = 8'b11111111; - - // A - { 4'hA, 3'h0 }: dataOut = 8'b11111111; - { 4'hA, 3'h1 }: dataOut = 8'b11100111; - { 4'hA, 3'h2 }: dataOut = 8'b11000011; - { 4'hA, 3'h3 }: dataOut = 8'b10011001; - { 4'hA, 3'h4 }: dataOut = 8'b10011001; - { 4'hA, 3'h5 }: dataOut = 8'b10000001; - { 4'hA, 3'h6 }: dataOut = 8'b10011001; - { 4'hA, 3'h7 }: dataOut = 8'b11111111; - - // B - { 4'hB, 3'h0 }: dataOut = 8'b11111111; - { 4'hB, 3'h1 }: dataOut = 8'b10000011; - { 4'hB, 3'h2 }: dataOut = 8'b10011001; - { 4'hB, 3'h3 }: dataOut = 8'b10000011; - { 4'hB, 3'h4 }: dataOut = 8'b10011001; - { 4'hB, 3'h5 }: dataOut = 8'b10011001; - { 4'hB, 3'h6 }: dataOut = 8'b10000011; - { 4'hB, 3'h7 }: dataOut = 8'b11111111; - - // C - { 4'hC, 3'h0 }: dataOut = 8'b11111111; - { 4'hC, 3'h1 }: dataOut = 8'b11000011; - { 4'hC, 3'h2 }: dataOut = 8'b10011001; - { 4'hC, 3'h3 }: dataOut = 8'b10011111; - { 4'hC, 3'h4 }: dataOut = 8'b10011111; - { 4'hC, 3'h5 }: dataOut = 8'b10011001; - { 4'hC, 3'h6 }: dataOut = 8'b11000011; - { 4'hC, 3'h7 }: dataOut = 8'b11111111; - - // D - { 4'hD, 3'h0 }: dataOut = 8'b11111111; - { 4'hD, 3'h1 }: dataOut = 8'b10000111; - { 4'hD, 3'h2 }: dataOut = 8'b10010011; - { 4'hD, 3'h3 }: dataOut = 8'b10011001; - { 4'hD, 3'h4 }: dataOut = 8'b10011001; - { 4'hD, 3'h5 }: dataOut = 8'b10010011; - { 4'hD, 3'h6 }: dataOut = 8'b10000111; - { 4'hD, 3'h7 }: dataOut = 8'b11111111; - - // E - { 4'hE, 3'h0 }: dataOut = 8'b11111111; - { 4'hE, 3'h1 }: dataOut = 8'b10000001; - { 4'hE, 3'h2 }: dataOut = 8'b10011111; - { 4'hE, 3'h3 }: dataOut = 8'b10000011; - { 4'hE, 3'h4 }: dataOut = 8'b10011111; - { 4'hE, 3'h5 }: dataOut = 8'b10011111; - { 4'hE, 3'h6 }: dataOut = 8'b10000001; - { 4'hE, 3'h7 }: dataOut = 8'b11111111; - - // F - { 4'hF, 3'h0 }: dataOut = 8'b11111111; - { 4'hF, 3'h1 }: dataOut = 8'b10000001; - { 4'hF, 3'h2 }: dataOut = 8'b10011111; - { 4'hF, 3'h3 }: dataOut = 8'b10000011; - { 4'hF, 3'h4 }: dataOut = 8'b10011111; - { 4'hF, 3'h5 }: dataOut = 8'b10011111; - { 4'hF, 3'h6 }: dataOut = 8'b10011111; - { 4'hF, 3'h7 }: dataOut = 8'b11111111; - - default: dataOut = 8'b11111111; - - endcase - end -endmodule diff --git a/cores/plus_too/iwm.v b/cores/plus_too/iwm.v index adeac35..4b907a0 100644 --- a/cores/plus_too/iwm.v +++ b/cores/plus_too/iwm.v @@ -40,11 +40,15 @@ module iwm( input SEL, // from VIA output [15:0] dataOut, input [1:0] insertDisk, - output [1:0] diskInDrive, + output [1:0] diskEject, + input [1:0] diskSides, - output [21:0] extraRomReadAddr, - input extraRomReadAck, - input [7:0] extraRomReadData + // interface to fetch data for internal drive + output [21:0] dskReadAddrInt, + input dskReadAckInt, + output [21:0] dskReadAddrExt, + input dskReadAckExt, + input [7:0] dskReadData ); wire [7:0] dataInLo = dataIn[7:0]; @@ -82,14 +86,17 @@ module iwm( ._enable(~diskEnableInt), .writeData(writeData), .readData(readDataInt), - .useDiskImage(1'b1), .advanceDriveHead(advanceDriveHead), .newByteReady(newByteReadyInt), .insertDisk(insertDisk[0]), - .diskInDrive(diskInDrive[0]), - .extraRomReadAddr(extraRomReadAddr), - .extraRomReadAck(extraRomReadAck), - .extraRomReadData(extraRomReadData)); + .diskSides(diskSides[0]), + .diskEject(diskEject[0]), + + .dskReadAddr(dskReadAddrInt), + .dskReadAck(dskReadAckInt), + .dskReadData(dskReadData) + ); + floppy floppyExt( .clk8(clk8), ._reset(_reset), @@ -101,11 +108,16 @@ module iwm( ._enable(~diskEnableExt), .writeData(writeData), .readData(readDataExt), - .useDiskImage(1'b0), .advanceDriveHead(advanceDriveHead), .newByteReady(newByteReadyExt), .insertDisk(insertDisk[1]), - .diskInDrive(diskInDrive[1])); + .diskSides(diskSides[1]), + .diskEject(diskEject[1]), + + .dskReadAddr(dskReadAddrExt), + .dskReadAck(dskReadAckExt), + .dskReadData(dskReadData) + ); wire [7:0] readData = selectExternalDrive ? readDataExt : readDataInt; wire newByteReady = selectExternalDrive ? newByteReadyExt : newByteReadyInt; @@ -173,7 +185,7 @@ module iwm( end // update IWM bit registers - always @(posedge clk8 or negedge _reset) begin + always @(negedge clk8 or negedge _reset) begin if (_reset == 1'b0) begin ca0 <= 0; ca1 <= 0; @@ -202,23 +214,21 @@ module iwm( always @(*) begin dataOutLo = 8'hEF; - if (_cpuRW == 1'b1 && selectIWM == 1'b1 && _cpuLDS == 1'b0) begin - // reading any IWM address returns state as selected by Q7 and Q6 - case ({q7Next,q6Next}) - 2'b00: // data-in register (from disk drive) - MSB is 1 when data is valid - dataOutLo <= readDataLatch; - 2'b01: // IWM status register - read only - dataOutLo <= { (selectExternalDriveNext ? senseExt : senseInt), 1'b0, diskEnableExt & diskEnableInt, iwmMode }; - 2'b10: // handshake - read only - dataOutLo <= { _iwmBusy, _writeUnderrun, 6'b000000 }; - 2'b11: // IWM mode register when not enabled (write-only), or (write?) data register when enabled - dataOutLo <= 0; - endcase - end + // reading any IWM address returns state as selected by Q7 and Q6 + case ({q7Next,q6Next}) + 2'b00: // data-in register (from disk drive) - MSB is 1 when data is valid + dataOutLo <= readDataLatch; + 2'b01: // IWM status register - read only + dataOutLo <= { (selectExternalDriveNext ? senseExt : senseInt), 1'b0, diskEnableExt & diskEnableInt, iwmMode }; + 2'b10: // handshake - read only + dataOutLo <= { _iwmBusy, _writeUnderrun, 6'b000000 }; + 2'b11: // IWM mode register when not enabled (write-only), or (write?) data register when enabled + dataOutLo <= 0; + endcase end // write IWM state - always @(posedge clk8 or negedge _reset) begin + always @(negedge clk8 or negedge _reset) begin if (_reset == 1'b0) begin iwmMode <= 0; writeData <= 0; @@ -242,7 +252,7 @@ module iwm( wire iwmRead = (_cpuRW == 1'b1 && selectIWM == 1'b1 && _cpuLDS == 1'b0); reg iwmReadPrev; reg [3:0] readLatchClearTimer; - always @(posedge clk8 or negedge _reset) begin + always @(negedge clk8 or negedge _reset) begin if (_reset == 1'b0) begin readDataLatch <= 0; readLatchClearTimer <= 0; diff --git a/cores/plus_too/led7seg.v b/cores/plus_too/led7seg.v deleted file mode 100644 index 38e683c..0000000 --- a/cores/plus_too/led7seg.v +++ /dev/null @@ -1,30 +0,0 @@ -module led7seg( - input [3:0] data, - output [6:0] segments -); - - reg [6:0] _segments; - assign segments = ~_segments; - - always @(data) begin - case (data) - 4'h0: _segments = 7'b0111111; - 4'h1: _segments = 7'b0000110; - 4'h2: _segments = 7'b1011011; - 4'h3: _segments = 7'b1001111; - 4'h4: _segments = 7'b1100110; - 4'h5: _segments = 7'b1101101; - 4'h6: _segments = 7'b1111101; - 4'h7: _segments = 7'b0000111; - 4'h8: _segments = 7'b1111111; - 4'h9: _segments = 7'b1101111; - 4'hA: _segments = 7'b1110111; - 4'hB: _segments = 7'b1111100; - 4'hC: _segments = 7'b0111001; - 4'hD: _segments = 7'b1011110; - 4'hE: _segments = 7'b1111001; - 4'hF: _segments = 7'b1110001; - endcase - end - -endmodule \ No newline at end of file diff --git a/cores/plus_too/clock325MHz.v b/cores/plus_too/pll.v similarity index 74% rename from cores/plus_too/clock325MHz.v rename to cores/plus_too/pll.v index dff1eae..44cfaa9 100644 --- a/cores/plus_too/clock325MHz.v +++ b/cores/plus_too/pll.v @@ -4,7 +4,7 @@ // MODULE: altpll // ============================================================ -// File Name: clock325MHz.v +// File Name: pll.v // Megafunction Name(s): // altpll // @@ -36,34 +36,26 @@ // synopsys translate_off `timescale 1 ps / 1 ps // synopsys translate_on -module clock325MHz ( +module pll ( inclk0, c0, - c1, - c2, locked); input inclk0; output c0; - output c1; - output c2; output locked; wire [4:0] sub_wire0; wire sub_wire2; - wire [0:0] sub_wire7 = 1'h0; - wire [2:2] sub_wire4 = sub_wire0[2:2]; - wire [0:0] sub_wire3 = sub_wire0[0:0]; - wire [1:1] sub_wire1 = sub_wire0[1:1]; - wire c1 = sub_wire1; + wire [0:0] sub_wire5 = 1'h0; + wire [0:0] sub_wire1 = sub_wire0[0:0]; + wire c0 = sub_wire1; wire locked = sub_wire2; - wire c0 = sub_wire3; - wire c2 = sub_wire4; - wire sub_wire5 = inclk0; - wire [1:0] sub_wire6 = {sub_wire7, sub_wire5}; + wire sub_wire3 = inclk0; + wire [1:0] sub_wire4 = {sub_wire5, sub_wire3}; altpll altpll_component ( - .inclk (sub_wire6), + .inclk (sub_wire4), .clk (sub_wire0), .locked (sub_wire2), .activeclock (), @@ -102,22 +94,14 @@ module clock325MHz ( .vcounderrange ()); defparam altpll_component.bandwidth_type = "AUTO", - altpll_component.clk0_divide_by = 54, + altpll_component.clk0_divide_by = 27, altpll_component.clk0_duty_cycle = 50, altpll_component.clk0_multiply_by = 65, altpll_component.clk0_phase_shift = "0", - altpll_component.clk1_divide_by = 27, - altpll_component.clk1_duty_cycle = 50, - altpll_component.clk1_multiply_by = 130, - altpll_component.clk1_phase_shift = "0", - altpll_component.clk2_divide_by = 27, - altpll_component.clk2_duty_cycle = 50, - altpll_component.clk2_multiply_by = 130, - altpll_component.clk2_phase_shift = "-2500", altpll_component.compensate_clock = "CLK0", altpll_component.inclk0_input_frequency = 37037, altpll_component.intended_device_family = "Cyclone III", - altpll_component.lpm_hint = "CBX_MODULE_PREFIX=clock325MHz", + altpll_component.lpm_hint = "CBX_MODULE_PREFIX=pll", altpll_component.lpm_type = "altpll", altpll_component.operation_mode = "NORMAL", altpll_component.pll_type = "AUTO", @@ -147,8 +131,8 @@ module clock325MHz ( altpll_component.port_scanread = "PORT_UNUSED", altpll_component.port_scanwrite = "PORT_UNUSED", altpll_component.port_clk0 = "PORT_USED", - altpll_component.port_clk1 = "PORT_USED", - altpll_component.port_clk2 = "PORT_USED", + altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk2 = "PORT_UNUSED", altpll_component.port_clk3 = "PORT_UNUSED", altpll_component.port_clk4 = "PORT_UNUSED", altpll_component.port_clk5 = "PORT_UNUSED", @@ -180,22 +164,16 @@ endmodule // Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0" // Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0" // Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0" -// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "1" +// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0" // Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0" // Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0" // Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0" // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" -// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "7" -// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "54" -// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" -// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1" +// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "32.500000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "130.000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "130.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "65.000000" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -216,34 +194,18 @@ endmodule // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" -// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "65" -// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" -// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "32.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "130.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "130.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "65.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "-2500.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" @@ -254,7 +216,7 @@ endmodule // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" -// Retrieval info: PRIVATE: RECONFIG_FILE STRING "clock325MHz.mif" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll.mif" // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0" @@ -262,37 +224,23 @@ endmodule // Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" // Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" // Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" -// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.000" +// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" // Retrieval info: PRIVATE: SPREAD_USE STRING "0" // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" -// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" -// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: USE_CLK0 STRING "1" -// Retrieval info: PRIVATE: USE_CLK1 STRING "1" -// Retrieval info: PRIVATE: USE_CLK2 STRING "1" // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" -// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "54" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" // Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "65" // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" -// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "130" -// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "27" -// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "130" -// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "-2500" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" @@ -325,8 +273,8 @@ endmodule // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" @@ -344,22 +292,18 @@ endmodule // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" -// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" -// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 -// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 -// Retrieval info: GEN_FILE: TYPE_NORMAL clock325MHz.v TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL clock325MHz.ppf TRUE -// Retrieval info: GEN_FILE: TYPE_NORMAL clock325MHz.inc FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL clock325MHz.cmp FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL clock325MHz.bsf FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL clock325MHz_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL clock325MHz_bb.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.ppf TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.inc FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.cmp FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll.bsf FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_inst.v FALSE +// Retrieval info: GEN_FILE: TYPE_NORMAL pll_bb.v FALSE // Retrieval info: LIB_FILE: altera_mf // Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/cores/plus_too/plusToo_top.qsf b/cores/plus_too/plusToo_top.qsf index 194f2ae..5c03037 100644 --- a/cores/plus_too/plusToo_top.qsf +++ b/cores/plus_too/plusToo_top.qsf @@ -122,7 +122,7 @@ set_location_assignment PIN_43 -to SDRAM_CLK set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name ENABLE_SIGNALTAP ON set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON @@ -337,6 +337,211 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_R set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to UART_RX +set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "pll:cs0|c0" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to "TG68:m68k|data_in[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to "TG68:m68k|data_in[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to "TG68:m68k|data_in[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to "TG68:m68k|data_in[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "TG68:m68k|data_in[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "TG68:m68k|data_in[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "TG68:m68k|data_in[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "TG68:m68k|data_in[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "TG68:m68k|data_in[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "TG68:m68k|data_in[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "TG68:m68k|data_in[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "TG68:m68k|data_in[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "TG68:m68k|data_in[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "TG68:m68k|data_in[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "TG68:m68k|data_in[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "TG68:m68k|data_in[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "TG68:m68k|reset" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "TG68KdotC_Kernel:m68k|IPL[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "TG68KdotC_Kernel:m68k|IPL[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "TG68KdotC_Kernel:m68k|IPL[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "TG68KdotC_Kernel:m68k|addr[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "TG68KdotC_Kernel:m68k|addr[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "TG68KdotC_Kernel:m68k|addr[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "TG68KdotC_Kernel:m68k|addr[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "TG68KdotC_Kernel:m68k|addr[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "TG68KdotC_Kernel:m68k|addr[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "TG68KdotC_Kernel:m68k|addr[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "TG68KdotC_Kernel:m68k|addr[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "TG68KdotC_Kernel:m68k|addr[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "TG68KdotC_Kernel:m68k|addr[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "TG68KdotC_Kernel:m68k|addr[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "TG68KdotC_Kernel:m68k|addr[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "TG68KdotC_Kernel:m68k|addr[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "TG68KdotC_Kernel:m68k|addr[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "TG68KdotC_Kernel:m68k|addr[22]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "TG68KdotC_Kernel:m68k|addr[23]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "TG68KdotC_Kernel:m68k|addr[24]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "TG68KdotC_Kernel:m68k|addr[25]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "TG68KdotC_Kernel:m68k|addr[26]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "TG68KdotC_Kernel:m68k|addr[27]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "TG68KdotC_Kernel:m68k|addr[28]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "TG68KdotC_Kernel:m68k|addr[29]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "TG68KdotC_Kernel:m68k|addr[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "TG68KdotC_Kernel:m68k|addr[30]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "TG68KdotC_Kernel:m68k|addr[31]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "TG68KdotC_Kernel:m68k|addr[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "TG68KdotC_Kernel:m68k|addr[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "TG68KdotC_Kernel:m68k|addr[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "TG68KdotC_Kernel:m68k|addr[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "TG68KdotC_Kernel:m68k|addr[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "TG68KdotC_Kernel:m68k|addr[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "TG68KdotC_Kernel:m68k|addr[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "TG68KdotC_Kernel:m68k|busstate[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "TG68KdotC_Kernel:m68k|busstate[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "TG68KdotC_Kernel:m68k|clk" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "TG68KdotC_Kernel:m68k|clkena_in" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "TG68KdotC_Kernel:m68k|data_write[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "TG68KdotC_Kernel:m68k|data_write[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "TG68KdotC_Kernel:m68k|data_write[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "TG68KdotC_Kernel:m68k|data_write[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "TG68KdotC_Kernel:m68k|data_write[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "TG68KdotC_Kernel:m68k|data_write[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "TG68KdotC_Kernel:m68k|data_write[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "TG68KdotC_Kernel:m68k|data_write[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "TG68KdotC_Kernel:m68k|data_write[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "TG68KdotC_Kernel:m68k|data_write[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "TG68KdotC_Kernel:m68k|data_write[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "TG68KdotC_Kernel:m68k|data_write[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "TG68KdotC_Kernel:m68k|data_write[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "TG68KdotC_Kernel:m68k|data_write[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "TG68KdotC_Kernel:m68k|data_write[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "TG68KdotC_Kernel:m68k|data_write[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "TG68KdotC_Kernel:m68k|exe_opcode[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "TG68KdotC_Kernel:m68k|exe_opcode[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "TG68KdotC_Kernel:m68k|exe_opcode[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "TG68KdotC_Kernel:m68k|exe_opcode[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to "TG68KdotC_Kernel:m68k|exe_opcode[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to "TG68KdotC_Kernel:m68k|exe_opcode[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to "TG68KdotC_Kernel:m68k|exe_opcode[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to "TG68KdotC_Kernel:m68k|exe_opcode[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to "TG68KdotC_Kernel:m68k|exe_opcode[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to "TG68KdotC_Kernel:m68k|exe_opcode[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to "TG68KdotC_Kernel:m68k|exe_opcode[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to "TG68KdotC_Kernel:m68k|exe_opcode[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to "TG68KdotC_Kernel:m68k|exe_opcode[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to "TG68KdotC_Kernel:m68k|exe_opcode[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "TG68KdotC_Kernel:m68k|exe_opcode[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "TG68KdotC_Kernel:m68k|exe_opcode[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "TG68KdotC_Kernel:m68k|nLDS" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "TG68KdotC_Kernel:m68k|nReset" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "TG68KdotC_Kernel:m68k|nUDS" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "TG68KdotC_Kernel:m68k|nWr" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[92] -to "addrController_top:ac0|_cpuDTACK" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to "TG68:m68k|data_in[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to "TG68:m68k|data_in[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to "TG68:m68k|data_in[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to "TG68:m68k|data_in[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "TG68:m68k|data_in[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "TG68:m68k|data_in[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "TG68:m68k|data_in[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "TG68:m68k|data_in[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "TG68:m68k|data_in[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "TG68:m68k|data_in[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "TG68:m68k|data_in[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "TG68:m68k|data_in[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "TG68:m68k|data_in[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "TG68:m68k|data_in[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "TG68:m68k|data_in[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "TG68:m68k|data_in[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "TG68:m68k|reset" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "TG68KdotC_Kernel:m68k|IPL[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "TG68KdotC_Kernel:m68k|IPL[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "TG68KdotC_Kernel:m68k|IPL[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "TG68KdotC_Kernel:m68k|addr[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "TG68KdotC_Kernel:m68k|addr[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "TG68KdotC_Kernel:m68k|addr[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "TG68KdotC_Kernel:m68k|addr[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "TG68KdotC_Kernel:m68k|addr[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "TG68KdotC_Kernel:m68k|addr[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "TG68KdotC_Kernel:m68k|addr[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "TG68KdotC_Kernel:m68k|addr[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "TG68KdotC_Kernel:m68k|addr[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "TG68KdotC_Kernel:m68k|addr[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "TG68KdotC_Kernel:m68k|addr[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "TG68KdotC_Kernel:m68k|addr[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "TG68KdotC_Kernel:m68k|addr[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "TG68KdotC_Kernel:m68k|addr[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "TG68KdotC_Kernel:m68k|addr[22]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "TG68KdotC_Kernel:m68k|addr[23]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "TG68KdotC_Kernel:m68k|addr[24]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "TG68KdotC_Kernel:m68k|addr[25]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "TG68KdotC_Kernel:m68k|addr[26]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "TG68KdotC_Kernel:m68k|addr[27]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "TG68KdotC_Kernel:m68k|addr[28]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "TG68KdotC_Kernel:m68k|addr[29]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "TG68KdotC_Kernel:m68k|addr[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "TG68KdotC_Kernel:m68k|addr[30]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "TG68KdotC_Kernel:m68k|addr[31]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "TG68KdotC_Kernel:m68k|addr[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "TG68KdotC_Kernel:m68k|addr[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "TG68KdotC_Kernel:m68k|addr[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "TG68KdotC_Kernel:m68k|addr[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "TG68KdotC_Kernel:m68k|addr[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "TG68KdotC_Kernel:m68k|addr[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "TG68KdotC_Kernel:m68k|addr[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "TG68KdotC_Kernel:m68k|busstate[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "TG68KdotC_Kernel:m68k|busstate[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "TG68KdotC_Kernel:m68k|clk" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "TG68KdotC_Kernel:m68k|clkena_in" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "TG68KdotC_Kernel:m68k|data_write[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "TG68KdotC_Kernel:m68k|data_write[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "TG68KdotC_Kernel:m68k|data_write[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "TG68KdotC_Kernel:m68k|data_write[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "TG68KdotC_Kernel:m68k|data_write[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "TG68KdotC_Kernel:m68k|data_write[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "TG68KdotC_Kernel:m68k|data_write[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "TG68KdotC_Kernel:m68k|data_write[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "TG68KdotC_Kernel:m68k|data_write[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "TG68KdotC_Kernel:m68k|data_write[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "TG68KdotC_Kernel:m68k|data_write[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "TG68KdotC_Kernel:m68k|data_write[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "TG68KdotC_Kernel:m68k|data_write[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "TG68KdotC_Kernel:m68k|data_write[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "TG68KdotC_Kernel:m68k|data_write[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "TG68KdotC_Kernel:m68k|data_write[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "TG68KdotC_Kernel:m68k|exe_opcode[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "TG68KdotC_Kernel:m68k|exe_opcode[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "TG68KdotC_Kernel:m68k|exe_opcode[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "TG68KdotC_Kernel:m68k|exe_opcode[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "TG68KdotC_Kernel:m68k|exe_opcode[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "TG68KdotC_Kernel:m68k|exe_opcode[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "TG68KdotC_Kernel:m68k|exe_opcode[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "TG68KdotC_Kernel:m68k|exe_opcode[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "TG68KdotC_Kernel:m68k|exe_opcode[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "TG68KdotC_Kernel:m68k|exe_opcode[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "TG68KdotC_Kernel:m68k|exe_opcode[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "TG68KdotC_Kernel:m68k|exe_opcode[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "TG68KdotC_Kernel:m68k|exe_opcode[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "TG68KdotC_Kernel:m68k|exe_opcode[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "TG68KdotC_Kernel:m68k|exe_opcode[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "TG68KdotC_Kernel:m68k|exe_opcode[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "TG68KdotC_Kernel:m68k|nLDS" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "TG68KdotC_Kernel:m68k|nReset" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "TG68KdotC_Kernel:m68k|nUDS" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "TG68KdotC_Kernel:m68k|nWr" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "addrController_top:ac0|_cpuDTACK" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0 +set_global_assignment -name VERILOG_FILE floppy_track_encoder.v +set_global_assignment -name VERILOG_FILE ps2_kbd.v set_global_assignment -name VHDL_FILE TG68K_Pack.vhd set_global_assignment -name VHDL_FILE TG68KdotC_Kernel.vhd set_global_assignment -name VHDL_FILE TG68K_ALU.vhd @@ -349,8 +554,6 @@ set_global_assignment -name VERILOG_FILE scc.v set_global_assignment -name VERILOG_FILE ps2_mouse.v set_global_assignment -name VERILOG_FILE ps2.v set_global_assignment -name VERILOG_FILE iwm.v -set_global_assignment -name VERILOG_FILE led7seg.v -set_global_assignment -name VERILOG_TEST_BENCH_FILE testbench.v set_global_assignment -name VERILOG_FILE via.v set_global_assignment -name VERILOG_FILE addrDecoder.v set_global_assignment -name VERILOG_FILE addrController_top.v @@ -358,10 +561,486 @@ set_global_assignment -name VERILOG_FILE dataController_top.v set_global_assignment -name VERILOG_FILE videoTimer.v set_global_assignment -name VERILOG_FILE videoShifter.v set_global_assignment -name VERILOG_FILE plusToo_top.v -set_global_assignment -name QIP_FILE clock325MHz.qip -set_global_assignment -name VERILOG_FILE debugPanel.v -set_global_assignment -name VERILOG_FILE fontGen.v -set_global_assignment -name VERILOG_FILE romAdapter.v set_global_assignment -name VERILOG_FILE floppy.v set_global_assignment -name SIGNALTAP_FILE stp1.stp -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file +set_global_assignment -name QIP_FILE pll.qip +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "addrController_top:ac0|_hblank" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "addrController_top:ac0|_memoryLDS" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "addrController_top:ac0|_memoryUDS" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "addrController_top:ac0|_hblank" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "addrController_top:ac0|_memoryLDS" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "addrController_top:ac0|_memoryUDS" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=128" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=128" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "addrController_top:ac0|_ramOE" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "addrController_top:ac0|_ramWE" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "addrController_top:ac0|_romOE" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "addrController_top:ac0|_vblank" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to "addrController_top:ac0|busCycle[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to "addrController_top:ac0|busCycle[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "addrController_top:ac0|_ramOE" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "addrController_top:ac0|_ramWE" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "addrController_top:ac0|_romOE" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "addrController_top:ac0|_vblank" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "addrController_top:ac0|busCycle[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "addrController_top:ac0|busCycle[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to "addrController_top:ac0|extra_slot_count[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to "addrController_top:ac0|extra_slot_count[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "addrController_top:ac0|extra_slot_count[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to "addrController_top:ac0|extra_slot_count[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAck" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[110] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[111] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[112] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[113] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[114] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[115] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[116] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[117] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[118] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[119] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[120] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[121] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[122] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[123] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[124] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[125] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[126] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[127] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[128] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[129] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[130] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[131] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[132] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[133] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[134] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[135] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[136] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[137] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[138] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAck" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[110] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[111] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[112] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[113] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[114] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[115] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[116] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[117] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[118] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[119] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[120] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[121] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[122] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[123] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[124] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[125] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[126] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[127] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[128] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[129] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[130] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[131] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[132] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[133] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[134] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[135] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[136] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[137] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[138] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to "addrController_top:ac0|videoBusControl" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to "clock325MHz:cs0|locked" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to "dataController_top:dc0|diskEject[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to "dataController_top:dc0|diskEject[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|diskEject" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[139] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskEject" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[140] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[141] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[142] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[143] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[144] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[145] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[146] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[147] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[148] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[149] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[150] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[151] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[152] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[153] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[154] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[155] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAck" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[156] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[157] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[158] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[159] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[160] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[161] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[162] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[163] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[164] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[165] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[166] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[167] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[168] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[169] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[170] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[171] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[172] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[173] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[174] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[175] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[176] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[177] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[178] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[179] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[180] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[181] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[182] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[183] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[184] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[185] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[186] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[187] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[188] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[189] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[190] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[191] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[192] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[193] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[194] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[195] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[196] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[197] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[198] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[199] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[200] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[201] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[202] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[203] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[204] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[205] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[206] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[207] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[208] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[209] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[210] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[211] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[212] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[213] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[214] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[215] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[216] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[217] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[218] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|clk" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[219] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[220] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[221] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[222] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[223] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[224] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[225] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[226] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[227] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[228] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[229] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[230] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[231] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[232] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[233] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[234] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[235] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[236] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[237] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[238] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[239] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[240] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[241] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[242] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[243] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[244] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[245] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|newByteReady" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[246] -to "data_io:data_io|addr[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[247] -to "data_io:data_io|addr[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[248] -to "data_io:data_io|addr[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[249] -to "data_io:data_io|addr[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[250] -to "data_io:data_io|addr[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[251] -to "data_io:data_io|addr[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[252] -to "data_io:data_io|addr[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[253] -to "data_io:data_io|addr[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[254] -to "data_io:data_io|addr[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[255] -to "data_io:data_io|addr[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[256] -to "data_io:data_io|addr[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[257] -to "data_io:data_io|addr[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[258] -to "data_io:data_io|addr[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[259] -to "data_io:data_io|addr[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[260] -to "data_io:data_io|addr[22]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[261] -to "data_io:data_io|addr[23]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[262] -to "data_io:data_io|addr[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[263] -to "data_io:data_io|addr[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[264] -to "data_io:data_io|addr[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[265] -to "data_io:data_io|addr[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[266] -to "data_io:data_io|addr[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[267] -to "data_io:data_io|addr[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[268] -to "data_io:data_io|addr[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[269] -to "data_io:data_io|addr[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[270] -to "data_io:data_io|downloading" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[271] -to "data_io:data_io|index[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[272] -to "data_io:data_io|index[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[273] -to "data_io:data_io|index[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[274] -to "data_io:data_io|index[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[275] -to "data_io:data_io|index[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[276] -to dsk_ext_ds -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[277] -to dsk_ext_ss -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[278] -to dsk_int_ds -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[279] -to dsk_int_ss -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[280] -to "sdram:sdram|addr[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[281] -to "sdram:sdram|addr[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[282] -to "sdram:sdram|addr[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[283] -to "sdram:sdram|addr[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[284] -to "sdram:sdram|addr[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[285] -to "sdram:sdram|addr[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[286] -to "sdram:sdram|addr[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[287] -to "sdram:sdram|addr[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[288] -to "sdram:sdram|addr[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[289] -to "sdram:sdram|addr[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[290] -to "sdram:sdram|addr[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[291] -to "sdram:sdram|addr[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[292] -to "sdram:sdram|addr[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[293] -to "sdram:sdram|addr[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[294] -to "sdram:sdram|addr[22]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[295] -to "sdram:sdram|addr[23]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[296] -to "sdram:sdram|addr[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[297] -to "sdram:sdram|addr[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[298] -to "sdram:sdram|addr[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[299] -to "sdram:sdram|addr[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[300] -to "sdram:sdram|addr[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[301] -to "sdram:sdram|addr[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[302] -to "sdram:sdram|addr[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[303] -to "sdram:sdram|addr[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[304] -to "sdram:sdram|dout[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[305] -to "sdram:sdram|dout[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[306] -to "sdram:sdram|dout[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[307] -to "sdram:sdram|dout[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[308] -to "sdram:sdram|dout[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[309] -to "sdram:sdram|dout[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[310] -to "sdram:sdram|dout[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[311] -to "sdram:sdram|dout[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[312] -to "sdram:sdram|dout[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[313] -to "sdram:sdram|dout[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[314] -to "sdram:sdram|dout[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[315] -to "sdram:sdram|dout[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[316] -to "sdram:sdram|dout[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[317] -to "sdram:sdram|dout[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[318] -to "sdram:sdram|dout[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[319] -to "sdram:sdram|dout[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[320] -to "sdram:sdram|sd_cas" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[321] -to "sdram:sdram|sd_cs" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[322] -to "sdram:sdram|sd_ras" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[323] -to "sdram:sdram|sd_we" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[324] -to "sdram:sdram|t[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[325] -to "sdram:sdram|t[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[326] -to "sdram:sdram|t[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[327] -to "sdram:sdram|we" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to "addrController_top:ac0|videoBusControl" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to "clock325MHz:cs0|locked" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to "dataController_top:dc0|diskEject[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to "dataController_top:dc0|diskEject[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|diskEject" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[139] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskEject" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[140] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[141] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[142] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[143] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[144] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[145] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[146] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[147] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[148] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[149] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[150] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[151] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[152] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[153] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[154] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[155] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAck" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[156] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[157] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[158] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[159] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[160] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[161] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[162] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[163] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[164] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[165] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[166] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[167] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[168] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[169] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[170] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[171] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[172] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[173] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[174] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[175] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[176] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[177] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[178] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[179] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[180] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[181] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[182] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[183] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[184] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[185] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[186] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[187] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[188] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[189] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[190] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[191] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[192] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[193] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[194] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[195] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[196] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[197] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[198] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[199] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[200] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[201] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[202] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[203] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[204] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[205] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[206] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[207] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[208] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[209] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[210] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[211] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[212] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[213] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[214] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[215] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[216] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[217] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[218] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|clk" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[219] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[220] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[221] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[222] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[223] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[224] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[225] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[226] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[227] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[228] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[229] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[230] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[231] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[232] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[233] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[234] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[235] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[236] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[237] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[238] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[239] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[240] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[241] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[242] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[243] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[244] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[245] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|newByteReady" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[246] -to "data_io:data_io|addr[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[247] -to "data_io:data_io|addr[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[248] -to "data_io:data_io|addr[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[249] -to "data_io:data_io|addr[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[250] -to "data_io:data_io|addr[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[251] -to "data_io:data_io|addr[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[252] -to "data_io:data_io|addr[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[253] -to "data_io:data_io|addr[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[254] -to "data_io:data_io|addr[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[255] -to "data_io:data_io|addr[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[256] -to "data_io:data_io|addr[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[257] -to "data_io:data_io|addr[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[258] -to "data_io:data_io|addr[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[259] -to "data_io:data_io|addr[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[260] -to "data_io:data_io|addr[22]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[261] -to "data_io:data_io|addr[23]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[262] -to "data_io:data_io|addr[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[263] -to "data_io:data_io|addr[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[264] -to "data_io:data_io|addr[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[265] -to "data_io:data_io|addr[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[266] -to "data_io:data_io|addr[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[267] -to "data_io:data_io|addr[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[268] -to "data_io:data_io|addr[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[269] -to "data_io:data_io|addr[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[270] -to "data_io:data_io|downloading" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[271] -to "data_io:data_io|index[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[272] -to "data_io:data_io|index[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[273] -to "data_io:data_io|index[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[274] -to "data_io:data_io|index[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[275] -to "data_io:data_io|index[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[276] -to dsk_ext_ds -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[277] -to dsk_ext_ss -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[278] -to dsk_int_ds -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[279] -to dsk_int_ss -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[280] -to "sdram:sdram|addr[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[281] -to "sdram:sdram|addr[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[282] -to "sdram:sdram|addr[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[283] -to "sdram:sdram|addr[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[284] -to "sdram:sdram|addr[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[285] -to "sdram:sdram|addr[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[286] -to "sdram:sdram|addr[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[287] -to "sdram:sdram|addr[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[288] -to "sdram:sdram|addr[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[289] -to "sdram:sdram|addr[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[290] -to "sdram:sdram|addr[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[291] -to "sdram:sdram|addr[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[292] -to "sdram:sdram|addr[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[293] -to "sdram:sdram|addr[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[294] -to "sdram:sdram|addr[22]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[295] -to "sdram:sdram|addr[23]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[296] -to "sdram:sdram|addr[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[297] -to "sdram:sdram|addr[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[298] -to "sdram:sdram|addr[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[299] -to "sdram:sdram|addr[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[300] -to "sdram:sdram|addr[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[301] -to "sdram:sdram|addr[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[302] -to "sdram:sdram|addr[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[303] -to "sdram:sdram|addr[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[304] -to "sdram:sdram|dout[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[305] -to "sdram:sdram|dout[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[306] -to "sdram:sdram|dout[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[307] -to "sdram:sdram|dout[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[308] -to "sdram:sdram|dout[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[309] -to "sdram:sdram|dout[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[310] -to "sdram:sdram|dout[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[311] -to "sdram:sdram|dout[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[312] -to "sdram:sdram|dout[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[313] -to "sdram:sdram|dout[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[314] -to "sdram:sdram|dout[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[315] -to "sdram:sdram|dout[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[316] -to "sdram:sdram|dout[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[317] -to "sdram:sdram|dout[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[318] -to "sdram:sdram|dout[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[319] -to "sdram:sdram|dout[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[320] -to "sdram:sdram|sd_cas" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[321] -to "sdram:sdram|sd_cs" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[322] -to "sdram:sdram|sd_ras" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[323] -to "sdram:sdram|sd_we" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[324] -to "sdram:sdram|t[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[325] -to "sdram:sdram|t[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[326] -to "sdram:sdram|t[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[327] -to "sdram:sdram|we" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=328" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=328" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=1005" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=61163" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=1089" -section_id auto_signaltap_0 +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top +set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp \ No newline at end of file diff --git a/cores/plus_too/plusToo_top.v b/cores/plus_too/plusToo_top.v index cc881fd..2d16956 100644 --- a/cores/plus_too/plusToo_top.v +++ b/cores/plus_too/plusToo_top.v @@ -39,6 +39,16 @@ module plusToo_top( input wire CONF_DATA0 // SPI_SS for user_io ); +// ------------------------------ Plus Too Bus Timing --------------------------------- +// for stability and maintainability reasons the whole timing has been simplyfied: +// 00 01 10 11 +// ______ _____________ _____________ _____________ _____________ ___ +// ______X_video_cycle_X______IO_____X__cpu_cycle__X___unused____X___ +// ^ ^ ^ +// | | | +// video cpu cpu +// read write read + // include the OSD into the video data path osd #(10,0,2) osd ( .pclk ( clk32 ), @@ -72,8 +82,41 @@ wire [23:0] dio_addr; wire [4:0] dio_index; wire [15:0] dio_data; -// disk image is being stored right after os rom at word offset 0x10000 -wire [20:0] dio_a = (dio_index == 0)?dio_addr[20:0]:{21'h10000 + dio_addr[20:0]}; +// good floppy image sizes are 819200 bytes and 409600 bytes +reg dsk_int_ds, dsk_ext_ds; // double sided image inserted +reg dsk_int_ss, dsk_ext_ss; // single sided image inserted + +// any known type of disk image inserted? +wire dsk_int_ins = dsk_int_ds || dsk_int_ss; +wire dsk_ext_ins = dsk_ext_ds || dsk_ext_ss; + +// at the end of a download latch file size +// diskEject is set by macos on eject +always @(negedge dio_download or posedge diskEject[0]) begin + if(diskEject[0]) begin + dsk_int_ds <= 1'b0; + dsk_int_ss <= 1'b0; + end else if(dio_index == 1) begin + dsk_int_ds <= (dio_addr == 409599); // double sides disk, addr counts words, not bytes + dsk_int_ss <= (dio_addr == 204799); // single sided disk + end +end + +always @(negedge dio_download or posedge diskEject[1]) begin + if(diskEject[1]) begin + dsk_ext_ds <= 1'b0; + dsk_ext_ss <= 1'b0; + end else if(dio_index == 2) begin + dsk_ext_ds <= (dio_addr == 409599); // double sides disk, addr counts words, not bytes + dsk_ext_ss <= (dio_addr == 204799); // single sided disk + end +end + +// disk images are being stored right after os rom at word offset 0x80000 and 0x100000 +wire [20:0] dio_a = + (dio_index == 0)?dio_addr[20:0]: // os rom + (dio_index == 1)?{21'h80000 + dio_addr[20:0]}: // first dsk image at 512k word addr + {21'h100000 + dio_addr[20:0]}; // second dsk image at 1M word addr data_io data_io ( // io controller spi interface @@ -85,7 +128,7 @@ data_io data_io ( .index ( dio_index ), // 0=rom download, 1=disk image // external ram interface - .clk ( clk8 ), + .clk ( download_cycle ), .wr ( dio_write ), .addr ( dio_addr ), .data ( dio_data ) @@ -102,32 +145,26 @@ wire vsync; wire [3:0] red; wire [3:0] green; wire [3:0] blue; - -// various debug signals for the DE1/DE2. These don't exist on the MIST -// and will be optimized away ... -wire [6:0] hex0; -wire [6:0] hex1; -wire [6:0] hex2; -wire [6:0] hex3; -wire [7:0] ledg; // ps2 interface for mouse, to be mapped into user_io wire mouseClk; wire mouseData; - - // NO REAL LOGIC SHOULD GO IN THIS MODULE! - // It may not exist in the hand-built Plus Too. - // Only interconnections and interfaces specific to the dev board should go here +wire keyClk; +wire keyData; + +assign SDRAM_CLK = !clk64; // synthesize a 32.5 MHz clock - wire clk32; - wire clk128; + wire clk64; wire pll_locked; - clock325MHz cs0( + + reg clk32; + always @(posedge clk64) + clk32 <= !clk32; + + pll cs0( .inclk0 ( CLOCK_27[0] ), - .c0 ( clk32 ), - .c1 ( clk128 ), - .c2 ( SDRAM_CLK ), + .c0 ( clk64 ), .locked ( pll_locked ) ); @@ -138,66 +175,55 @@ wire mouseData; ps2_clk_div <= ps2_clk_div + 9'd1; // set the real-world inputs to sane defaults - localparam keyClk = 1'b0, - keyData = 1'b0, - serialIn = 1'b0, - interruptButton = 1'b0, - configROMSize = 1'b1, // 128K ROM - configRAMSize = 2'b01; // 512K RAM + localparam serialIn = 1'b0, + configROMSize = 1'b1; // 128K ROM + + wire [1:0] configRAMSize = status[3]?2'b11:2'b10; // 1MB/4MB // interconnects // CPU - wire clk8, _cpuReset, _cpuAS, _cpuUDS, _cpuLDS, _cpuRW, _cpuDTACK, cpuDriveData; + wire clk8, _cpuReset, _cpuAS, _cpuUDS, _cpuLDS, _cpuRW, _cpuDTACK; wire [2:0] _cpuIPL; wire [7:0] cpuAddrHi; wire [23:0] cpuAddr; wire [15:0] cpuDataOut; // RAM/ROM - wire _romCS, _romOE; - wire _ramCS, _ramOE, _ramWE; + wire _romOE; + wire _ramOE, _ramWE; wire _memoryUDS, _memoryLDS; wire videoBusControl; + wire dioBusControl; wire [21:0] memoryAddr; wire [15:0] memoryDataOut; - wire memoryDriveData; - wire [15:0] memoryDataInMux; // peripherals - wire loadSound, loadNormalPixels, loadDebugPixels, pixelOut, _hblank, _vblank; - wire memoryOverlayOn, selectSCC, selectIWM, selectVIA, selectInterruptVectors; + wire loadSound, loadPixels, pixelOut, _hblank, _vblank; + wire memoryOverlayOn, selectSCC, selectIWM, selectVIA; wire [15:0] dataControllerDataOut; - wire dataControllerDriveData; - // debug panel - wire _debugDTACK, driveDebugData, loadPixels, extraRomReadAck; - wire [15:0] debugDataOut; - wire [21:0] extraRomReadAddr; - - // LED debug lights - assign ledg = { 2'b00, diskInDrive[1], diskInDrive[1], diskInDrive[0], diskInDrive[0], 2'b00 }; + // floppy disk image interface + wire dskReadAckInt; + wire [21:0] dskReadAddrInt; + wire dskReadAckExt; + wire [21:0] dskReadAddrExt; // convert 1-bit pixel data to 4:4:4 RGB - // force pixels in debug area to appear green - assign red[3:0] = _vblank == 1'b0 ? 4'h0 : { pixelOut, pixelOut, pixelOut, pixelOut }; + assign red[3:0] = { pixelOut, pixelOut, pixelOut, pixelOut }; assign green[3:0] = { pixelOut, pixelOut, pixelOut, pixelOut }; - assign blue[3:0] = _vblank == 1'b0 ? 4'h0 : { pixelOut, pixelOut, pixelOut, pixelOut }; + assign blue[3:0] = { pixelOut, pixelOut, pixelOut, pixelOut }; - // memory-side data input mux - // In a hand-built system, both RAM and ROM data will be on the same physical pins, - // making this mux unnecessary - assign memoryDataInMux = driveDebugData ? debugDataOut : - sdram_do; - // the configuration string is returned to the io controller to allow // it to control the menu on the OSD parameter CONF_STR = { "PLUS_TOO;;", - "F1,BIN;", - "T2,Reset" + "F1,DSK;", + "F2,DSK;", + "O3,Memory,1MB,4MB;", + "T4,Reset" }; - parameter CONF_STR_LEN = 10+7+8; + parameter CONF_STR_LEN = 10+7+7+18+8; // the status register is controlled by the on screen display (OSD) wire [7:0] status; @@ -217,67 +243,21 @@ wire mouseData; // ps2 interface .ps2_clk ( ps2_clk ), - .ps2_kbd_clk ( ), - .ps2_kbd_data ( ), + .ps2_kbd_clk ( keyClk ), + .ps2_kbd_data ( keyData ), .ps2_mouse_clk ( mouseClk ), .ps2_mouse_data( mouseData ) ); - - debugPanel dp( - .clk8(clk8), - .sw(sw), - .key(key), - .videoBusControl(videoBusControl), - .loadNormalPixels(loadNormalPixels), - .loadDebugPixels(loadDebugPixels), - .loadPixelsOut(loadPixels), - ._dtackIn(_cpuDTACK), - .cpuAddrHi(cpuAddrHi), - .cpuAddr(cpuAddr), - ._cpuRW(_cpuRW), - ._cpuUDS(_cpuUDS), - ._cpuLDS(_cpuLDS), - .dataControllerDataOut(dataControllerDataOut), - .cpuDataOut(cpuDataOut), - .memoryAddr(memoryAddr), - ._dtackOut(_debugDTACK), - .hex0(hex0), - .hex1(hex1), - .hex2(hex2), - .hex3(hex3), - .driveDebugData(driveDebugData), - .debugDataOut(debugDataOut), - .extraRomReadAck(extraRomReadAck)); - - wire [2:0] _debugIPL = sw[0] == 1'b1 ? 3'b111 : _cpuIPL; // suppress interrupts when sw0 on - -/* - TG68 m68k( - .clk(clk8), - .reset(_cpuReset), - .clkena_in(1'b1), - .data_in(dataControllerDataOut), - .IPL(_debugIPL), - .dtack(_debugDTACK), - .addr({cpuAddrHi, cpuAddr}), - .data_out(cpuDataOut), - .as(_cpuAS), - .uds(_cpuUDS), - .lds(_cpuLDS), - .rw(_cpuRW), - .drive_data(cpuDriveData)); -*/ - assign _cpuAS = !(cpu_busstate != 2'b01); wire [1:0] cpu_busstate; - wire cpu_clkena = (!_debugDTACK) || (cpu_busstate == 2'b01); + wire cpu_clkena = (!_cpuDTACK) || (cpu_busstate == 2'b01); TG68KdotC_Kernel #(0,0,0,0,0,0) m68k ( .clk ( clk8 ), .nReset ( _cpuReset ), .clkena_in ( cpu_clkena ), .data_in ( dataControllerDataOut ), - .IPL ( _debugIPL ), + .IPL ( _cpuIPL ), .IPL_autovector ( 1'b1 ), .berr ( 1'b0 ), .clr_berr ( 1'b0 ), @@ -306,36 +286,41 @@ wire mouseData; .memoryAddr(memoryAddr), ._memoryUDS(_memoryUDS), ._memoryLDS(_memoryLDS), - ._romCS(_romCS), ._romOE(_romOE), - ._ramCS(_ramCS), ._ramOE(_ramOE), ._ramWE(_ramWE), .videoBusControl(videoBusControl), + .dioBusControl(dioBusControl), .selectSCC(selectSCC), .selectIWM(selectIWM), .selectVIA(selectVIA), - .selectInterruptVectors(selectInterruptVectors), .hsync(hsync), .vsync(vsync), ._hblank(_hblank), ._vblank(_vblank), - .loadNormalPixels(loadNormalPixels), - .loadDebugPixels(loadDebugPixels), + .loadPixels(loadPixels), .loadSound(loadSound), .memoryOverlayOn(memoryOverlayOn), - - .extraRomReadAddr(extraRomReadAddr), - .extraRomReadAck(extraRomReadAck)); + + .dskReadAddrInt(dskReadAddrInt), + .dskReadAckInt(dskReadAckInt), + .dskReadAddrExt(dskReadAddrExt), + .dskReadAckExt(dskReadAckExt) + ); - wire [1:0] diskInDrive; + wire [1:0] diskEject; // addional ~8ms delay in reset + wire rom_download = dio_download && (dio_index == 0); wire n_reset = (rst_cnt == 0); reg [15:0] rst_cnt; + reg last_mem_config; always @(posedge clk8) begin + last_mem_config <= status[3]; + // various source can reset the mac - if(!pll_locked || status[0] || status[2] || buttons[1] || dio_download) + if(!pll_locked || status[0] || status[4] || buttons[1] || + rom_download || (last_mem_config != status[3])) rst_cnt <= 16'd65535; else if(rst_cnt != 0) rst_cnt <= rst_cnt - 16'd1; @@ -343,7 +328,6 @@ wire mouseData; dataController_top dc0( .clk32(clk32), - .clk8out(clk8), .clk8(clk8), ._systemReset(n_reset), ._cpuReset(_cpuReset), @@ -353,17 +337,14 @@ wire mouseData; ._cpuRW(_cpuRW), .cpuDataIn(cpuDataOut), .cpuDataOut(dataControllerDataOut), - .cpuDriveData(dataControllerDriveData), .cpuAddrRegHi(cpuAddr[12:9]), .cpuAddrRegLo(cpuAddr[2:1]), .selectSCC(selectSCC), .selectIWM(selectIWM), .selectVIA(selectVIA), - .selectInterruptVectors(selectInterruptVectors), .videoBusControl(videoBusControl), .memoryDataOut(memoryDataOut), - .memoryDataIn(memoryDataInMux), - .memoryDriveData(memoryDriveData), + .memoryDataIn(sdram_do), .keyClk(keyClk), .keyData(keyData), .mouseClk(mouseClk), @@ -371,34 +352,29 @@ wire mouseData; .serialIn(serialIn), ._hblank(_hblank), ._vblank(_vblank), - .pixelOut(pixelOut), + .pixelOut(pixelOut), .loadPixels(loadPixels), .loadSound(loadSound), - .interruptButton(1'b1), .memoryOverlayOn(memoryOverlayOn), - .insertDisk( 2'b01 ), - .diskInDrive(diskInDrive), + .insertDisk( { dsk_ext_ins, dsk_int_ins} ), + .diskSides( { dsk_ext_ds, dsk_int_ds} ), + .diskEject(diskEject), - .extraRomReadAddr(extraRomReadAddr), - .extraRomReadAck(extraRomReadAck)); + .dskReadAddrInt(dskReadAddrInt), + .dskReadAckInt(dskReadAckInt), + .dskReadAddrExt(dskReadAddrExt), + .dskReadAckExt(dskReadAckExt) + ); - // ram/rom maps directly into 68k address space +// sdram used for ram/rom maps directly into 68k address space +wire download_cycle = dio_download && dioBusControl; -// multiplex sdram between mac and the rom downloader -// 4MB RAM -// wire [24:0] sdram_addr = dio_download?{ 3'b001, dio_a[20:0] }:{ 2'b00, ~_romOE, memoryAddr[21:1] }; +wire [24:0] sdram_addr = download_cycle?{ 4'b0001, dio_a[20:0] }:{ 3'b000, ~_romOE, memoryAddr[21:1] }; -wire [20:0] memoryAddrEx = - extraRomReadAck?memoryAddr[21:1]: // full access to floppy image -// memoryAddr[21:1]; // CPU access not masked giving 4MB ram - { 3'b000, memoryAddr[18:1]} ; // CPU access masked for 512k ram - -wire [24:0] sdram_addr = dio_download?{ 4'b0001, dio_a[20:0] }:{ 3'b000, ~_romOE, memoryAddrEx }; - -wire [15:0] sdram_din = dio_download?dio_data:memoryDataOut; -wire [1:0] sdram_ds = dio_download?2'b11:{ !_memoryUDS, !_memoryLDS }; -wire sdram_we = dio_download?dio_write:!_ramWE; -wire sdram_oe = dio_download?1'b0:(!_ramOE || !_romOE); +wire [15:0] sdram_din = download_cycle?dio_data:memoryDataOut; +wire [1:0] sdram_ds = download_cycle?2'b11:{ !_memoryUDS, !_memoryLDS }; +wire sdram_we = download_cycle?dio_write:!_ramWE; +wire sdram_oe = download_cycle?1'b0:(!_ramOE || !_romOE); // during rom/disk download ffff is returned so the screen is black during download @@ -406,9 +382,10 @@ wire sdram_oe = dio_download?1'b0:(!_ramOE || !_romOE); // we thus need to properly demultiplex the word returned from sdram in that case wire [15:0] extra_rom_data_demux = memoryAddr[0]? {sdram_out[7:0],sdram_out[7:0]}:{sdram_out[15:8],sdram_out[15:8]}; -wire [15:0] sdram_do = dio_download?16'hffff: - extraRomReadAck?extra_rom_data_demux: +wire [15:0] sdram_do = download_cycle?16'hffff: + (dskReadAckInt || dskReadAckExt)?extra_rom_data_demux: sdram_out; + wire [15:0] sdram_out; assign SDRAM_CKE = 1'b1; @@ -425,7 +402,7 @@ sdram sdram ( .sd_cas ( SDRAM_nCAS ), // system interface - .clk_128 ( clk128 ), + .clk_64 ( clk64 ), .clk_8 ( clk8 ), .init ( !pll_locked ), diff --git a/cores/plus_too/ps2_kbd.v b/cores/plus_too/ps2_kbd.v new file mode 100644 index 0000000..920b698 --- /dev/null +++ b/cores/plus_too/ps2_kbd.v @@ -0,0 +1,786 @@ +`timescale 1ns / 100ps + +/* + * PS2 Keyboard to Mac interface module + */ +module ps2_kbd( input sysclk, + input reset, + + inout ps2dat, + inout ps2clk, + + input [7:0] data_out, + input strobe_out, + + output [7:0] data_in, + output strobe_in +); + + reg [8:0] keymac; + reg key_pending; + reg [21:0] pacetimer; + reg inquiry_active; + reg extended; + reg keybreak; + reg capslock; + reg haskey; + wire got_key; + wire got_break; + wire got_extend; + wire tick_short; + wire tick_long; + wire pop_key; + reg cmd_inquiry; + reg cmd_instant; + reg cmd_model; + reg cmd_test; + reg[1:0] state; + reg[1:0] next; + reg nreq; + reg[7:0] nbyte; + + /* PS2 interface signals */ + wire istrobe; + wire [7:0] ibyte; + reg oreq; + reg [7:0] obyte; + wire oack; + wire timeout; + wire [1:0] dbg_lowstate; + + ps2 ps20(.sysclk(sysclk), + .reset(reset), + .ps2dat(ps2dat), + .ps2clk(ps2clk), + .istrobe(istrobe), + .ibyte(ibyte), + .oreq(oreq), + .obyte(obyte), + .oack(oack), + .timeout(timeout), + .dbg_state(dbg_lowstate)); + + /* --- PS2 side State machine --- + * + * - at state_init: wait for BAT reply + * * 0xaa -> send 0xed -> state_led1 + * * bad reply -> send 0xff -> state_init + * * timeout -> send 0xff -> state_init + * + * - at state_led1: wait for ack, send LED state + * * 0xfa -> send 0xYY -> state_led2 YY=LED + * * bad reply -> send 0xff -> state_init + * * timeout -> send 0xff -> state_init + * + * - at state_led2: wait for ack, go wait data + * * 0xfa -> state_wait + * * bad reply -> send 0xff -> state_init + * * timeout -> send 0xff -> state_init + * + * - at state_wait: wait for data byte + * * capslock -> send 0xed -> state_led1 + * * other -> state_wait + * + * Works fine with my logitech USB/PS2 keyboard, but fails + * miserably with an old HP PS2 keyboard (which also behaves + * oddly with minimig as an amiga). Will eventually investigate... + */ + localparam ps2k_state_init = 0; + localparam ps2k_state_led1 = 1; + localparam ps2k_state_led2 = 2; + localparam ps2k_state_wait = 3; + + + /* Unlike my other modules, here I'll play with a big fat + * combo logic. The outputs are: + * - oreq : triggers sending of a byte. Set based on either + * timeout or istrobe, and as such only set for a + * clock. + * - next : next state + * - obyte : next byte to send + */ + always@(timeout or state or istrobe or ibyte or capslock) begin + nreq = 0; + next = state; + nbyte = 8'hff; + + if (istrobe || timeout) + case(state) + ps2k_state_init: begin + if (istrobe && ibyte == 8'haa) begin + nbyte = 8'hed; + nreq = 1; + next = ps2k_state_led1; + end else if (ibyte != 8'hfa) + nreq = 1; + end + ps2k_state_led1: begin + nreq = 1; + if (istrobe && ibyte == 8'hfa) begin + nbyte = { 5'b00000, capslock, 1'b1, 1'b0 }; + next = ps2k_state_led2; + end else + next = ps2k_state_init; + end + ps2k_state_led2: begin + if (istrobe && ibyte == 8'hfa) + next = ps2k_state_wait; + else begin + nreq = 1; + next = ps2k_state_init; + end + end + ps2k_state_wait: begin + /* Update LEDs */ +// if (istrobe && ibyte == 8'h58) begin +// nbyte = 8'hed; +// nreq = 1; +// next = ps2k_state_led1; +// end + end + endcase + end + + /* State related latches. We latch oreq and obyte, we don't + * necessarily have to but that avoids back to back + * receive/send at the low level which can upset things + */ + always@(posedge sysclk or posedge reset) + if (reset) + state <= ps2k_state_wait; // ps2k_state_init + else + state <= next; + always@(posedge sysclk or posedge reset) + if (reset) + oreq <= 0; + else + oreq <= nreq; + always@(posedge sysclk or posedge reset) + if (reset) + obyte <= 0; + else + obyte <= nbyte; + + assign got_key = (state == ps2k_state_wait) && istrobe; + assign got_break = { ibyte[7:1], 1'b0 } == 8'hf0; + assign got_extend = { ibyte[7:1], 1'b0 } == 8'he0; + + /* Latch key info from PS2, handle capslock state */ + always@(posedge sysclk or posedge reset) + if (reset) begin + extended <= 0; + keybreak <= 0; + capslock <= 0; + end else if (got_key) begin + if (got_break) + keybreak <= 1; + else if (got_extend) + extended <= 1; + else begin + keybreak <= 0; + extended <= 0; + + /* Capslock handling */ + if (ibyte == 8'h58 && !keybreak) + capslock <= ~capslock; + end + end + + /* --- Mac side --- */ + + /* Latch commands from Mac */ + always@(posedge sysclk or posedge reset) + if (reset) begin + cmd_inquiry <= 0; + cmd_instant <= 0; + cmd_model <= 0; + cmd_test <= 0; + end else begin + if (strobe_out) begin + cmd_inquiry <= 0; + cmd_instant <= 0; + cmd_model <= 0; + cmd_test <= 0; + case(data_out) + 8'h10: cmd_inquiry <= 1; + 8'h14: cmd_instant <= 1; + 8'h16: cmd_model <= 1; + 8'h36: cmd_test <= 1; + endcase + end + end + + /* Divide our clock to pace our responses to the Mac. tick_short ticks + * when we can respond to a command, and tick_long ticks when an inquiry + * command shall timeout + */ + always@(posedge sysclk or posedge reset) + if (reset) + pacetimer <= 0; + else begin + /* reset counter on command from Mac */ + if (strobe_out) + pacetimer <= 0; + else if (!tick_long) + pacetimer <= pacetimer + 1; + end + assign tick_long = pacetimer == 22'h3fffff; + assign tick_short = pacetimer == 22'h000fff; + + /* Delay inquiry responses to after tick_short */ + always@(posedge sysclk or posedge reset) + if (reset) + inquiry_active <= 0; + else begin + if (strobe_out | strobe_in) + inquiry_active <= 0; + else if (tick_short) + inquiry_active <= cmd_inquiry; + end + + /* Key answer to the mac XXX FIXME: keypad */ + assign pop_key = (cmd_instant & tick_short) | + (inquiry_active & tick_long) | + (inquiry_active & key_pending); + + /* Reply to Mac */ + assign strobe_in = ((cmd_model | cmd_test) & tick_short) | pop_key; + + /* Latch key_pending */ + always @(posedge sysclk or posedge reset) + if (reset) + key_pending <= 0; + else begin + if (pop_key | cmd_model | cmd_test) + key_pending <= 0; + else if (!key_pending & got_key && !got_break && !got_extend) + key_pending <= 1; + end + + /* Data to Mac ... XXX: Handle keypad and special case capslock */ + assign data_in = cmd_test ? 8'h7d : + cmd_model ? 8'h03 : + (key_pending && !keymac[8]) ? keymac[7:0] : 8'h7b; + + /* Keymap. XXX add option to assign ctrl/alt/windows to cmd/option + * differently + */ + always @(posedge sysclk) + if (got_key && !key_pending) begin + case({extended,ibyte}) // Scan Code Set 2 + 9'h000: keymac[8:0] <= 9'h07b; + 9'h001: keymac[8:0] <= 9'h07b; //F9 + 9'h002: keymac[8:0] <= 9'h07b; + 9'h003: keymac[8:0] <= 9'h07b; //F5 + 9'h004: keymac[8:0] <= 9'h07b; //F3 + 9'h005: keymac[8:0] <= 9'h07b; //F1 + 9'h006: keymac[8:0] <= 9'h07b; //F2 + 9'h007: keymac[8:0] <= 9'h07b; //F12 + 9'h008: keymac[8:0] <= 9'h07b; + 9'h009: keymac[8:0] <= 9'h07b; //F10 + 9'h00a: keymac[8:0] <= 9'h07b; //F8 + 9'h00b: keymac[8:0] <= 9'h07b; //F6 + 9'h00c: keymac[8:0] <= 9'h07b; //F4 + 9'h00d: keymac[8:0] <= 9'h061; //TAB + 9'h00e: keymac[8:0] <= 9'h065; //~ (`) + 9'h00f: keymac[8:0] <= 9'h07b; + 9'h010: keymac[8:0] <= 9'h07b; + 9'h011: keymac[8:0] <= 9'h075; //LEFT ALT (option) + 9'h012: keymac[8:0] <= 9'h071; //LEFT SHIFT + 9'h013: keymac[8:0] <= 9'h07b; + 9'h014: keymac[8:0] <= 9'h06f; //CTRL (command) + 9'h015: keymac[8:0] <= 9'h019; //q + 9'h016: keymac[8:0] <= 9'h025; //1 + 9'h017: keymac[8:0] <= 9'h07b; + 9'h018: keymac[8:0] <= 9'h07b; + 9'h019: keymac[8:0] <= 9'h07b; + 9'h01a: keymac[8:0] <= 9'h00d; //z + 9'h01b: keymac[8:0] <= 9'h003; //s + 9'h01c: keymac[8:0] <= 9'h001; //a + 9'h01d: keymac[8:0] <= 9'h01b; //w + 9'h01e: keymac[8:0] <= 9'h027; //2 + 9'h01f: keymac[8:0] <= 9'h07b; + 9'h020: keymac[8:0] <= 9'h07b; + 9'h021: keymac[8:0] <= 9'h011; //c + 9'h022: keymac[8:0] <= 9'h00f; //x + 9'h023: keymac[8:0] <= 9'h005; //d + 9'h024: keymac[8:0] <= 9'h01d; //e + 9'h025: keymac[8:0] <= 9'h02b; //4 + 9'h026: keymac[8:0] <= 9'h029; //3 + 9'h027: keymac[8:0] <= 9'h07b; + 9'h028: keymac[8:0] <= 9'h07b; + 9'h029: keymac[8:0] <= 9'h063; //SPACE + 9'h02a: keymac[8:0] <= 9'h013; //v + 9'h02b: keymac[8:0] <= 9'h007; //f + 9'h02c: keymac[8:0] <= 9'h023; //t + 9'h02d: keymac[8:0] <= 9'h01f; //r + 9'h02e: keymac[8:0] <= 9'h02f; //5 + 9'h02f: keymac[8:0] <= 9'h07b; + 9'h030: keymac[8:0] <= 9'h07b; + 9'h031: keymac[8:0] <= 9'h05b; //n + 9'h032: keymac[8:0] <= 9'h017; //b + 9'h033: keymac[8:0] <= 9'h009; //h + 9'h034: keymac[8:0] <= 9'h00b; //g + 9'h035: keymac[8:0] <= 9'h021; //y + 9'h036: keymac[8:0] <= 9'h02d; //6 + 9'h037: keymac[8:0] <= 9'h07b; + 9'h038: keymac[8:0] <= 9'h07b; + 9'h039: keymac[8:0] <= 9'h07b; + 9'h03a: keymac[8:0] <= 9'h05d; //m + 9'h03b: keymac[8:0] <= 9'h04d; //j + 9'h03c: keymac[8:0] <= 9'h041; //u + 9'h03d: keymac[8:0] <= 9'h035; //7 + 9'h03e: keymac[8:0] <= 9'h039; //8 + 9'h03f: keymac[8:0] <= 9'h07b; + 9'h040: keymac[8:0] <= 9'h07b; + 9'h041: keymac[8:0] <= 9'h057; //<, + 9'h042: keymac[8:0] <= 9'h051; //k + 9'h043: keymac[8:0] <= 9'h045; //i + 9'h044: keymac[8:0] <= 9'h03f; //o + 9'h045: keymac[8:0] <= 9'h03b; //0 + 9'h046: keymac[8:0] <= 9'h033; //9 + 9'h047: keymac[8:0] <= 9'h07b; + 9'h048: keymac[8:0] <= 9'h07b; + 9'h049: keymac[8:0] <= 9'h05f; //>. + 9'h04a: keymac[8:0] <= 9'h059; //FORWARD SLASH + 9'h04b: keymac[8:0] <= 9'h04b; //l + 9'h04c: keymac[8:0] <= 9'h053; //; + 9'h04d: keymac[8:0] <= 9'h047; //p + 9'h04e: keymac[8:0] <= 9'h037; //- + 9'h04f: keymac[8:0] <= 9'h07b; + 9'h050: keymac[8:0] <= 9'h07b; + 9'h051: keymac[8:0] <= 9'h07b; + 9'h052: keymac[8:0] <= 9'h04f; //'" + 9'h053: keymac[8:0] <= 9'h07b; + 9'h054: keymac[8:0] <= 9'h043; //[ + 9'h055: keymac[8:0] <= 9'h031; // = + 9'h056: keymac[8:0] <= 9'h07b; + 9'h057: keymac[8:0] <= 9'h07b; + 9'h058: keymac[8:0] <= 9'h073; //CAPSLOCK + 9'h059: keymac[8:0] <= 9'h071; //RIGHT SHIFT + 9'h05a: keymac[8:0] <= 9'h049; //ENTER + 9'h05b: keymac[8:0] <= 9'h03d; //] + 9'h05c: keymac[8:0] <= 9'h07b; + 9'h05d: keymac[8:0] <= 9'h055; //BACKSLASH + 9'h05e: keymac[8:0] <= 9'h07b; + 9'h05f: keymac[8:0] <= 9'h07b; + 9'h060: keymac[8:0] <= 9'h07b; + 9'h061: keymac[8:0] <= 9'h071; //international left shift cut out (German '<>' key), 0x56 Set#1 code + 9'h062: keymac[8:0] <= 9'h07b; + 9'h063: keymac[8:0] <= 9'h07b; + 9'h064: keymac[8:0] <= 9'h07b; + 9'h065: keymac[8:0] <= 9'h07b; + 9'h066: keymac[8:0] <= 9'h067; //BACKSPACE + 9'h067: keymac[8:0] <= 9'h07b; + 9'h068: keymac[8:0] <= 9'h07b; + 9'h069: keymac[8:0] <= 9'h127; //KP 1 + 9'h06a: keymac[8:0] <= 9'h07b; + 9'h06b: keymac[8:0] <= 9'h12d; //KP 4 + 9'h06c: keymac[8:0] <= 9'h133; //KP 7 + 9'h06d: keymac[8:0] <= 9'h07b; + 9'h06e: keymac[8:0] <= 9'h07b; + 9'h06f: keymac[8:0] <= 9'h07b; + 9'h070: keymac[8:0] <= 9'h125; //KP 0 + 9'h071: keymac[8:0] <= 9'h103; //KP . + 9'h072: keymac[8:0] <= 9'h129; //KP 2 + 9'h073: keymac[8:0] <= 9'h12f; //KP 5 + 9'h074: keymac[8:0] <= 9'h131; //KP 6 + 9'h075: keymac[8:0] <= 9'h137; //KP 8 + 9'h076: keymac[8:0] <= 9'b000; //ESCAPE + 9'h077: keymac[8:0] <= 9'h07b; //NUMLOCK + 9'h078: keymac[8:0] <= 9'h07b; //F11 + 9'h079: keymac[8:0] <= 9'h07b; //KP + + 9'h07a: keymac[8:0] <= 9'h12b; //KP 3 + 9'h07b: keymac[8:0] <= 9'h11d; //KP - + 9'h07c: keymac[8:0] <= 9'h07b; //KP * + 9'h07d: keymac[8:0] <= 9'h139; //KP 9 + 9'h07e: keymac[8:0] <= 9'h07b; //SCROLL LOCK / KP ) + 9'h07f: keymac[8:0] <= 9'h07b; + 9'h080: keymac[8:0] <= 9'h07b; + 9'h081: keymac[8:0] <= 9'h07b; + 9'h082: keymac[8:0] <= 9'h07b; + 9'h083: keymac[8:0] <= 9'h07b; //F7 + 9'h084: keymac[8:0] <= 9'h07b; + 9'h085: keymac[8:0] <= 9'h07b; + 9'h086: keymac[8:0] <= 9'h07b; + 9'h087: keymac[8:0] <= 9'h07b; + 9'h088: keymac[8:0] <= 9'h07b; + 9'h089: keymac[8:0] <= 9'h07b; + 9'h08a: keymac[8:0] <= 9'h07b; + 9'h08b: keymac[8:0] <= 9'h07b; + 9'h08c: keymac[8:0] <= 9'h07b; + 9'h08d: keymac[8:0] <= 9'h07b; + 9'h08e: keymac[8:0] <= 9'h07b; + 9'h08f: keymac[8:0] <= 9'h07b; + 9'h090: keymac[8:0] <= 9'h07b; + 9'h091: keymac[8:0] <= 9'h07b; + 9'h092: keymac[8:0] <= 9'h07b; + 9'h093: keymac[8:0] <= 9'h07b; + 9'h094: keymac[8:0] <= 9'h07b; + 9'h095: keymac[8:0] <= 9'h07b; + 9'h096: keymac[8:0] <= 9'h07b; + 9'h097: keymac[8:0] <= 9'h07b; + 9'h098: keymac[8:0] <= 9'h07b; + 9'h099: keymac[8:0] <= 9'h07b; + 9'h09a: keymac[8:0] <= 9'h07b; + 9'h09b: keymac[8:0] <= 9'h07b; + 9'h09c: keymac[8:0] <= 9'h07b; + 9'h09d: keymac[8:0] <= 9'h07b; + 9'h09e: keymac[8:0] <= 9'h07b; + 9'h09f: keymac[8:0] <= 9'h07b; + 9'h0a0: keymac[8:0] <= 9'h07b; + 9'h0a1: keymac[8:0] <= 9'h07b; + 9'h0a2: keymac[8:0] <= 9'h07b; + 9'h0a3: keymac[8:0] <= 9'h07b; + 9'h0a4: keymac[8:0] <= 9'h07b; + 9'h0a5: keymac[8:0] <= 9'h07b; + 9'h0a6: keymac[8:0] <= 9'h07b; + 9'h0a7: keymac[8:0] <= 9'h07b; + 9'h0a8: keymac[8:0] <= 9'h07b; + 9'h0a9: keymac[8:0] <= 9'h07b; + 9'h0aa: keymac[8:0] <= 9'h07b; + 9'h0ab: keymac[8:0] <= 9'h07b; + 9'h0ac: keymac[8:0] <= 9'h07b; + 9'h0ad: keymac[8:0] <= 9'h07b; + 9'h0ae: keymac[8:0] <= 9'h07b; + 9'h0af: keymac[8:0] <= 9'h07b; + 9'h0b0: keymac[8:0] <= 9'h07b; + 9'h0b1: keymac[8:0] <= 9'h07b; + 9'h0b2: keymac[8:0] <= 9'h07b; + 9'h0b3: keymac[8:0] <= 9'h07b; + 9'h0b4: keymac[8:0] <= 9'h07b; + 9'h0b5: keymac[8:0] <= 9'h07b; + 9'h0b6: keymac[8:0] <= 9'h07b; + 9'h0b7: keymac[8:0] <= 9'h07b; + 9'h0b8: keymac[8:0] <= 9'h07b; + 9'h0b9: keymac[8:0] <= 9'h07b; + 9'h0ba: keymac[8:0] <= 9'h07b; + 9'h0bb: keymac[8:0] <= 9'h07b; + 9'h0bc: keymac[8:0] <= 9'h07b; + 9'h0bd: keymac[8:0] <= 9'h07b; + 9'h0be: keymac[8:0] <= 9'h07b; + 9'h0bf: keymac[8:0] <= 9'h07b; + 9'h0c0: keymac[8:0] <= 9'h07b; + 9'h0c1: keymac[8:0] <= 9'h07b; + 9'h0c2: keymac[8:0] <= 9'h07b; + 9'h0c3: keymac[8:0] <= 9'h07b; + 9'h0c4: keymac[8:0] <= 9'h07b; + 9'h0c5: keymac[8:0] <= 9'h07b; + 9'h0c6: keymac[8:0] <= 9'h07b; + 9'h0c7: keymac[8:0] <= 9'h07b; + 9'h0c8: keymac[8:0] <= 9'h07b; + 9'h0c9: keymac[8:0] <= 9'h07b; + 9'h0ca: keymac[8:0] <= 9'h07b; + 9'h0cb: keymac[8:0] <= 9'h07b; + 9'h0cc: keymac[8:0] <= 9'h07b; + 9'h0cd: keymac[8:0] <= 9'h07b; + 9'h0ce: keymac[8:0] <= 9'h07b; + 9'h0cf: keymac[8:0] <= 9'h07b; + 9'h0d0: keymac[8:0] <= 9'h07b; + 9'h0d1: keymac[8:0] <= 9'h07b; + 9'h0d2: keymac[8:0] <= 9'h07b; + 9'h0d3: keymac[8:0] <= 9'h07b; + 9'h0d4: keymac[8:0] <= 9'h07b; + 9'h0d5: keymac[8:0] <= 9'h07b; + 9'h0d6: keymac[8:0] <= 9'h07b; + 9'h0d7: keymac[8:0] <= 9'h07b; + 9'h0d8: keymac[8:0] <= 9'h07b; + 9'h0d9: keymac[8:0] <= 9'h07b; + 9'h0da: keymac[8:0] <= 9'h07b; + 9'h0db: keymac[8:0] <= 9'h07b; + 9'h0dc: keymac[8:0] <= 9'h07b; + 9'h0dd: keymac[8:0] <= 9'h07b; + 9'h0de: keymac[8:0] <= 9'h07b; + 9'h0df: keymac[8:0] <= 9'h07b; + 9'h0e0: keymac[8:0] <= 9'h07b; //ps2 extended key + 9'h0e1: keymac[8:0] <= 9'h07b; + 9'h0e2: keymac[8:0] <= 9'h07b; + 9'h0e3: keymac[8:0] <= 9'h07b; + 9'h0e4: keymac[8:0] <= 9'h07b; + 9'h0e5: keymac[8:0] <= 9'h07b; + 9'h0e6: keymac[8:0] <= 9'h07b; + 9'h0e7: keymac[8:0] <= 9'h07b; + 9'h0e8: keymac[8:0] <= 9'h07b; + 9'h0e9: keymac[8:0] <= 9'h07b; + 9'h0ea: keymac[8:0] <= 9'h07b; + 9'h0eb: keymac[8:0] <= 9'h07b; + 9'h0ec: keymac[8:0] <= 9'h07b; + 9'h0ed: keymac[8:0] <= 9'h07b; + 9'h0ee: keymac[8:0] <= 9'h07b; + 9'h0ef: keymac[8:0] <= 9'h07b; + 9'h0f0: keymac[8:0] <= 9'h07b; //ps2 release code + 9'h0f1: keymac[8:0] <= 9'h07b; + 9'h0f2: keymac[8:0] <= 9'h07b; + 9'h0f3: keymac[8:0] <= 9'h07b; + 9'h0f4: keymac[8:0] <= 9'h07b; + 9'h0f5: keymac[8:0] <= 9'h07b; + 9'h0f6: keymac[8:0] <= 9'h07b; + 9'h0f7: keymac[8:0] <= 9'h07b; + 9'h0f8: keymac[8:0] <= 9'h07b; + 9'h0f9: keymac[8:0] <= 9'h07b; + 9'h0fa: keymac[8:0] <= 9'h07b; //ps2 ack code + 9'h0fb: keymac[8:0] <= 9'h07b; + 9'h0fc: keymac[8:0] <= 9'h07b; + 9'h0fd: keymac[8:0] <= 9'h07b; + 9'h0fe: keymac[8:0] <= 9'h07b; + 9'h0ff: keymac[8:0] <= 9'h07b; + 9'h100: keymac[8:0] <= 9'h07b; + 9'h101: keymac[8:0] <= 9'h07b; + 9'h102: keymac[8:0] <= 9'h07b; + 9'h103: keymac[8:0] <= 9'h07b; + 9'h104: keymac[8:0] <= 9'h07b; + 9'h105: keymac[8:0] <= 9'h07b; + 9'h106: keymac[8:0] <= 9'h07b; + 9'h107: keymac[8:0] <= 9'h07b; + 9'h108: keymac[8:0] <= 9'h07b; + 9'h109: keymac[8:0] <= 9'h07b; + 9'h10a: keymac[8:0] <= 9'h07b; + 9'h10b: keymac[8:0] <= 9'h07b; + 9'h10c: keymac[8:0] <= 9'h07b; + 9'h10d: keymac[8:0] <= 9'h07b; + 9'h10e: keymac[8:0] <= 9'h07b; + 9'h10f: keymac[8:0] <= 9'h07b; + 9'h110: keymac[8:0] <= 9'h07b; + 9'h111: keymac[8:0] <= 9'h075; //RIGHT ALT + 9'h112: keymac[8:0] <= 9'h07b; + 9'h113: keymac[8:0] <= 9'h07b; + 9'h114: keymac[8:0] <= 9'h07b; + 9'h115: keymac[8:0] <= 9'h07b; + 9'h116: keymac[8:0] <= 9'h07b; + 9'h117: keymac[8:0] <= 9'h07b; + 9'h118: keymac[8:0] <= 9'h07b; + 9'h119: keymac[8:0] <= 9'h07b; + 9'h11a: keymac[8:0] <= 9'h07b; + 9'h11b: keymac[8:0] <= 9'h07b; + 9'h11c: keymac[8:0] <= 9'h07b; + 9'h11d: keymac[8:0] <= 9'h07b; + 9'h11e: keymac[8:0] <= 9'h07b; + 9'h11f: keymac[8:0] <= 9'h06f; //LEFT COMMAND (LEFT GUI) + 9'h120: keymac[8:0] <= 9'h07b; + 9'h121: keymac[8:0] <= 9'h07b; + 9'h122: keymac[8:0] <= 9'h07b; + 9'h123: keymac[8:0] <= 9'h07b; + 9'h124: keymac[8:0] <= 9'h07b; + 9'h125: keymac[8:0] <= 9'h07b; + 9'h126: keymac[8:0] <= 9'h07b; + 9'h127: keymac[8:0] <= 9'h06f; //RIGHT AMIGA (RIGHT GUI) + 9'h128: keymac[8:0] <= 9'h07b; + 9'h129: keymac[8:0] <= 9'h07b; + 9'h12a: keymac[8:0] <= 9'h07b; + 9'h12b: keymac[8:0] <= 9'h07b; + 9'h12c: keymac[8:0] <= 9'h07b; + 9'h12d: keymac[8:0] <= 9'h07b; + 9'h12e: keymac[8:0] <= 9'h07b; + 9'h12f: keymac[8:0] <= 9'h06f; //RIGHT AMIGA (APPS) + 9'h130: keymac[8:0] <= 9'h07b; + 9'h131: keymac[8:0] <= 9'h07b; + 9'h132: keymac[8:0] <= 9'h07b; + 9'h133: keymac[8:0] <= 9'h07b; + 9'h134: keymac[8:0] <= 9'h07b; + 9'h135: keymac[8:0] <= 9'h07b; + 9'h136: keymac[8:0] <= 9'h07b; + 9'h137: keymac[8:0] <= 9'h07b; + 9'h138: keymac[8:0] <= 9'h07b; + 9'h139: keymac[8:0] <= 9'h07b; + 9'h13a: keymac[8:0] <= 9'h07b; + 9'h13b: keymac[8:0] <= 9'h07b; + 9'h13c: keymac[8:0] <= 9'h07b; + 9'h13d: keymac[8:0] <= 9'h07b; + 9'h13e: keymac[8:0] <= 9'h07b; + 9'h13f: keymac[8:0] <= 9'h07b; + 9'h140: keymac[8:0] <= 9'h07b; + 9'h141: keymac[8:0] <= 9'h07b; + 9'h142: keymac[8:0] <= 9'h07b; + 9'h143: keymac[8:0] <= 9'h07b; + 9'h144: keymac[8:0] <= 9'h07b; + 9'h145: keymac[8:0] <= 9'h07b; + 9'h146: keymac[8:0] <= 9'h07b; + 9'h147: keymac[8:0] <= 9'h07b; + 9'h148: keymac[8:0] <= 9'h07b; + 9'h149: keymac[8:0] <= 9'h07b; + 9'h14a: keymac[8:0] <= 9'h07b; //KP / + 9'h14b: keymac[8:0] <= 9'h07b; + 9'h14c: keymac[8:0] <= 9'h07b; + 9'h14d: keymac[8:0] <= 9'h07b; + 9'h14e: keymac[8:0] <= 9'h07b; + 9'h14f: keymac[8:0] <= 9'h07b; + 9'h150: keymac[8:0] <= 9'h07b; + 9'h151: keymac[8:0] <= 9'h07b; + 9'h152: keymac[8:0] <= 9'h07b; + 9'h153: keymac[8:0] <= 9'h07b; + 9'h154: keymac[8:0] <= 9'h07b; + 9'h155: keymac[8:0] <= 9'h07b; + 9'h156: keymac[8:0] <= 9'h07b; + 9'h157: keymac[8:0] <= 9'h07b; + 9'h158: keymac[8:0] <= 9'h07b; + 9'h159: keymac[8:0] <= 9'h07b; + 9'h15a: keymac[8:0] <= 9'h119; //KP ENTER + 9'h15b: keymac[8:0] <= 9'h07b; + 9'h15c: keymac[8:0] <= 9'h07b; + 9'h15d: keymac[8:0] <= 9'h07b; + 9'h15e: keymac[8:0] <= 9'h07b; + 9'h15f: keymac[8:0] <= 9'h07b; + 9'h160: keymac[8:0] <= 9'h07b; + 9'h161: keymac[8:0] <= 9'h07b; + 9'h162: keymac[8:0] <= 9'h07b; + 9'h163: keymac[8:0] <= 9'h07b; + 9'h164: keymac[8:0] <= 9'h07b; + 9'h165: keymac[8:0] <= 9'h07b; + 9'h166: keymac[8:0] <= 9'h07b; + 9'h167: keymac[8:0] <= 9'h07b; + 9'h168: keymac[8:0] <= 9'h07b; + 9'h169: keymac[8:0] <= 9'h07b; //END + 9'h16a: keymac[8:0] <= 9'h07b; + 9'h16b: keymac[8:0] <= 9'h10d; //ARROW LEFT + 9'h16c: keymac[8:0] <= 9'h07b; //HOME + 9'h16d: keymac[8:0] <= 9'h07b; + 9'h16e: keymac[8:0] <= 9'h07b; + 9'h16f: keymac[8:0] <= 9'h07b; + 9'h170: keymac[8:0] <= 9'h07b; //INSERT = HELP + 9'h171: keymac[8:0] <= 9'h10f; //DELETE + 9'h172: keymac[8:0] <= 9'h111; //ARROW DOWN + 9'h173: keymac[8:0] <= 9'h07b; + 9'h174: keymac[8:0] <= 9'h105; //ARROW RIGHT + 9'h175: keymac[8:0] <= 9'h10b; //ARROW UP + 9'h176: keymac[8:0] <= 9'h07b; + 9'h177: keymac[8:0] <= 9'h07b; + 9'h178: keymac[8:0] <= 9'h07b; + 9'h179: keymac[8:0] <= 9'h07b; + 9'h17a: keymac[8:0] <= 9'h07b; //PGDN + 9'h17b: keymac[8:0] <= 9'h07b; + 9'h17c: keymac[8:0] <= 9'h07b; //PRTSCR + 9'h17d: keymac[8:0] <= 9'h07b; //PGUP + 9'h17e: keymac[8:0] <= 9'h07b; //ctrl+break + 9'h17f: keymac[8:0] <= 9'h07b; + 9'h180: keymac[8:0] <= 9'h07b; + 9'h181: keymac[8:0] <= 9'h07b; + 9'h182: keymac[8:0] <= 9'h07b; + 9'h183: keymac[8:0] <= 9'h07b; + 9'h184: keymac[8:0] <= 9'h07b; + 9'h185: keymac[8:0] <= 9'h07b; + 9'h186: keymac[8:0] <= 9'h07b; + 9'h187: keymac[8:0] <= 9'h07b; + 9'h188: keymac[8:0] <= 9'h07b; + 9'h189: keymac[8:0] <= 9'h07b; + 9'h18a: keymac[8:0] <= 9'h07b; + 9'h18b: keymac[8:0] <= 9'h07b; + 9'h18c: keymac[8:0] <= 9'h07b; + 9'h18d: keymac[8:0] <= 9'h07b; + 9'h18e: keymac[8:0] <= 9'h07b; + 9'h18f: keymac[8:0] <= 9'h07b; + 9'h190: keymac[8:0] <= 9'h07b; + 9'h191: keymac[8:0] <= 9'h07b; + 9'h192: keymac[8:0] <= 9'h07b; + 9'h193: keymac[8:0] <= 9'h07b; + 9'h194: keymac[8:0] <= 9'h07b; + 9'h195: keymac[8:0] <= 9'h07b; + 9'h196: keymac[8:0] <= 9'h07b; + 9'h197: keymac[8:0] <= 9'h07b; + 9'h198: keymac[8:0] <= 9'h07b; + 9'h199: keymac[8:0] <= 9'h07b; + 9'h19a: keymac[8:0] <= 9'h07b; + 9'h19b: keymac[8:0] <= 9'h07b; + 9'h19c: keymac[8:0] <= 9'h07b; + 9'h19d: keymac[8:0] <= 9'h07b; + 9'h19e: keymac[8:0] <= 9'h07b; + 9'h19f: keymac[8:0] <= 9'h07b; + 9'h1a0: keymac[8:0] <= 9'h07b; + 9'h1a1: keymac[8:0] <= 9'h07b; + 9'h1a2: keymac[8:0] <= 9'h07b; + 9'h1a3: keymac[8:0] <= 9'h07b; + 9'h1a4: keymac[8:0] <= 9'h07b; + 9'h1a5: keymac[8:0] <= 9'h07b; + 9'h1a6: keymac[8:0] <= 9'h07b; + 9'h1a7: keymac[8:0] <= 9'h07b; + 9'h1a8: keymac[8:0] <= 9'h07b; + 9'h1a9: keymac[8:0] <= 9'h07b; + 9'h1aa: keymac[8:0] <= 9'h07b; + 9'h1ab: keymac[8:0] <= 9'h07b; + 9'h1ac: keymac[8:0] <= 9'h07b; + 9'h1ad: keymac[8:0] <= 9'h07b; + 9'h1ae: keymac[8:0] <= 9'h07b; + 9'h1af: keymac[8:0] <= 9'h07b; + 9'h1b0: keymac[8:0] <= 9'h07b; + 9'h1b1: keymac[8:0] <= 9'h07b; + 9'h1b2: keymac[8:0] <= 9'h07b; + 9'h1b3: keymac[8:0] <= 9'h07b; + 9'h1b4: keymac[8:0] <= 9'h07b; + 9'h1b5: keymac[8:0] <= 9'h07b; + 9'h1b6: keymac[8:0] <= 9'h07b; + 9'h1b7: keymac[8:0] <= 9'h07b; + 9'h1b8: keymac[8:0] <= 9'h07b; + 9'h1b9: keymac[8:0] <= 9'h07b; + 9'h1ba: keymac[8:0] <= 9'h07b; + 9'h1bb: keymac[8:0] <= 9'h07b; + 9'h1bc: keymac[8:0] <= 9'h07b; + 9'h1bd: keymac[8:0] <= 9'h07b; + 9'h1be: keymac[8:0] <= 9'h07b; + 9'h1bf: keymac[8:0] <= 9'h07b; + 9'h1c0: keymac[8:0] <= 9'h07b; + 9'h1c1: keymac[8:0] <= 9'h07b; + 9'h1c2: keymac[8:0] <= 9'h07b; + 9'h1c3: keymac[8:0] <= 9'h07b; + 9'h1c4: keymac[8:0] <= 9'h07b; + 9'h1c5: keymac[8:0] <= 9'h07b; + 9'h1c6: keymac[8:0] <= 9'h07b; + 9'h1c7: keymac[8:0] <= 9'h07b; + 9'h1c8: keymac[8:0] <= 9'h07b; + 9'h1c9: keymac[8:0] <= 9'h07b; + 9'h1ca: keymac[8:0] <= 9'h07b; + 9'h1cb: keymac[8:0] <= 9'h07b; + 9'h1cc: keymac[8:0] <= 9'h07b; + 9'h1cd: keymac[8:0] <= 9'h07b; + 9'h1ce: keymac[8:0] <= 9'h07b; + 9'h1cf: keymac[8:0] <= 9'h07b; + 9'h1d0: keymac[8:0] <= 9'h07b; + 9'h1d1: keymac[8:0] <= 9'h07b; + 9'h1d2: keymac[8:0] <= 9'h07b; + 9'h1d3: keymac[8:0] <= 9'h07b; + 9'h1d4: keymac[8:0] <= 9'h07b; + 9'h1d5: keymac[8:0] <= 9'h07b; + 9'h1d6: keymac[8:0] <= 9'h07b; + 9'h1d7: keymac[8:0] <= 9'h07b; + 9'h1d8: keymac[8:0] <= 9'h07b; + 9'h1d9: keymac[8:0] <= 9'h07b; + 9'h1da: keymac[8:0] <= 9'h07b; + 9'h1db: keymac[8:0] <= 9'h07b; + 9'h1dc: keymac[8:0] <= 9'h07b; + 9'h1dd: keymac[8:0] <= 9'h07b; + 9'h1de: keymac[8:0] <= 9'h07b; + 9'h1df: keymac[8:0] <= 9'h07b; + 9'h1e0: keymac[8:0] <= 9'h07b; //ps2 extended key(duplicate, see $e0) + 9'h1e1: keymac[8:0] <= 9'h07b; + 9'h1e2: keymac[8:0] <= 9'h07b; + 9'h1e3: keymac[8:0] <= 9'h07b; + 9'h1e4: keymac[8:0] <= 9'h07b; + 9'h1e5: keymac[8:0] <= 9'h07b; + 9'h1e6: keymac[8:0] <= 9'h07b; + 9'h1e7: keymac[8:0] <= 9'h07b; + 9'h1e8: keymac[8:0] <= 9'h07b; + 9'h1e9: keymac[8:0] <= 9'h07b; + 9'h1ea: keymac[8:0] <= 9'h07b; + 9'h1eb: keymac[8:0] <= 9'h07b; + 9'h1ec: keymac[8:0] <= 9'h07b; + 9'h1ed: keymac[8:0] <= 9'h07b; + 9'h1ee: keymac[8:0] <= 9'h07b; + 9'h1ef: keymac[8:0] <= 9'h07b; + 9'h1f0: keymac[8:0] <= 9'h07b; //ps2 release code(duplicate, see $f0) + 9'h1f1: keymac[8:0] <= 9'h07b; + 9'h1f2: keymac[8:0] <= 9'h07b; + 9'h1f3: keymac[8:0] <= 9'h07b; + 9'h1f4: keymac[8:0] <= 9'h07b; + 9'h1f5: keymac[8:0] <= 9'h07b; + 9'h1f6: keymac[8:0] <= 9'h07b; + 9'h1f7: keymac[8:0] <= 9'h07b; + 9'h1f8: keymac[8:0] <= 9'h07b; + 9'h1f9: keymac[8:0] <= 9'h07b; + 9'h1fa: keymac[8:0] <= 9'h07b; //ps2 ack code(duplicate see $fa) + 9'h1fb: keymac[8:0] <= 9'h07b; + 9'h1fc: keymac[8:0] <= 9'h07b; + 9'h1fd: keymac[8:0] <= 9'h07b; + 9'h1fe: keymac[8:0] <= 9'h07b; + 9'h1ff: keymac[8:0] <= 9'h07b; + endcase // case ({extended,ps2key[7:0]}) + keymac[7] <= keybreak; + end +endmodule diff --git a/cores/plus_too/ps2_mouse.v b/cores/plus_too/ps2_mouse.v index 3474f66..41cedfa 100644 --- a/cores/plus_too/ps2_mouse.v +++ b/cores/plus_too/ps2_mouse.v @@ -21,9 +21,7 @@ module ps2_mouse(input sysclk, output reg y1, output reg x2, output reg y2, - output reg button, - - output reg [15:0] debug + output reg button ); wire istrobe; wire [7:0] ibyte; @@ -39,7 +37,7 @@ module ps2_mouse(input sysclk, reg [9:0] yacc; reg xsign; reg ysign; - reg [12:0] clkdiv; + reg [11:0] clkdiv; wire tick; wire[1:0] dbg_lowstate; @@ -133,7 +131,10 @@ module ps2_mouse(input sysclk, next = ps2m_state_init; end end - ps2m_state_byte0: next = ps2m_state_byte1; + ps2m_state_byte0: + if(ibyte[3]) // bit 3 must be 1 + next = ps2m_state_byte1; + ps2m_state_byte1: next = ps2m_state_byte2; ps2m_state_byte2: next = ps2m_state_byte0; default: // shouldn't ever get into these states @@ -166,7 +167,8 @@ module ps2_mouse(input sysclk, if (reset) button <= 1; else if (istrobe && state == ps2m_state_byte0) - button <= ~ibyte[0]; + if(ibyte[3]) + button <= ~ibyte[0]; /* Clock divider to flush accumulators */ always@(posedge sysclk or posedge reset) @@ -202,8 +204,10 @@ module ps2_mouse(input sysclk, xsign <= 0; ysign <= 0; end else if (istrobe && state == ps2m_state_byte0) begin - xsign <= ibyte[4]; - ysign <= ibyte[5]; + if(ibyte[3]) begin + xsign <= ibyte[4]; + ysign <= ibyte[5]; + end end end @@ -218,7 +222,7 @@ module ps2_mouse(input sysclk, else /* Decrement */ if (tick && xacc != 0) - xacc <= xacc + { {9{~xsign}}, 1'b1 }; + xacc <= xacc + { {9{~xacc[9]}}, 1'b1 }; end end @@ -232,19 +236,7 @@ module ps2_mouse(input sysclk, else /* Decrement */ if (tick && yacc != 0) - yacc <= yacc + { {9{~ysign}}, 1'b1 }; - end - end - - /* Some debug signals for my own sanity */ - always@(posedge sysclk or posedge reset) begin - if (reset) - debug <= 0; - else begin - if (istrobe) - debug[15:8] <= ibyte; - debug[7:0] <= { ps2clk, ps2dat, dbg_lowstate, 1'b0, - state }; + yacc <= yacc + { {9{~yacc[9]}}, 1'b1 }; end end endmodule diff --git a/cores/plus_too/readme.md b/cores/plus_too/readme.md index 82930c1..1695485 100644 --- a/cores/plus_too/readme.md +++ b/cores/plus_too/readme.md @@ -15,11 +15,19 @@ itself. Major changes were: - ROM upload using the MISTs IO controller - Floppy image upload using the MISTs IO controller - Use of MiSTs on screen display for floppy image selection -- Use of MiSTS PS2 mouse emulation +- Use of MiSTs PS2 mouse emulation - Need to disable all parts dealing with mouse inialization Functional changes: - tg68k cpu core updated to latest version +- floppy disk images use 400k or 800k dsk format +- support for second floppy disk +- SDRAM clock reduced to 65MHz +- PS2 keyboard support +- removed debug overlay +- removed irq vector generation +- various timing simplifications +- fix mouse counter wrapping Binaries are available at the [binaries repository](https://github.com/mist-devel/mist-binaries/tree/master/cores/plus_too). diff --git a/cores/plus_too/scc.v b/cores/plus_too/scc.v index 70e9fee..df1822d 100644 --- a/cores/plus_too/scc.v +++ b/cores/plus_too/scc.v @@ -47,6 +47,7 @@ module scc(input sysclk, /* Register access is semi-insane */ reg [3:0] rindex; + reg [3:0] rindex_latch; wire wreg_a; wire wreg_b; wire wdata_a; @@ -139,23 +140,28 @@ module scc(input sysclk, assign rdata_a = cs & (~we) & (rs[1] | (rindex == 8)) & rs[0]; assign rdata_b = cs & (~we) & (rs[1] | (rindex == 8)) & ~rs[0]; + // make sure rindex changes after the cpu cycle has ended so + // read data is still stable while cpu advances + always@(negedge sysclk) + rindex <= rindex_latch; + /* Register index is set by a write to WR0 and reset * after any subsequent write. We ignore the side */ - always@(posedge sysclk or posedge reset) begin + always@(negedge sysclk or posedge reset) begin if (reset) - rindex <= 0; + rindex_latch <= 0; else if (cs && !rs[1]) begin /* Default, reset index */ - rindex <= 0; + rindex_latch <= 0; /* Write to WR0 */ if (we && rindex == 0) begin /* Get low index bits */ - rindex[2:0] <= wdata[2:0]; + rindex_latch[2:0] <= wdata[2:0]; /* Add point high */ - rindex[3] <= (wdata[5:3] == 3'b001); + rindex_latch[3] <= (wdata[5:3] == 3'b001); end end end @@ -173,7 +179,7 @@ module scc(input sysclk, /* WR1 * Reset: bit 5 and 2 unchanged */ - always@(posedge sysclk or posedge reset_hw) begin + always@(negedge sysclk or posedge reset_hw) begin if (reset_hw) wr1_a <= 0; else begin @@ -183,7 +189,7 @@ module scc(input sysclk, wr1_a <= wdata; end end - always@(posedge sysclk or posedge reset_hw) begin + always@(negedge sysclk or posedge reset_hw) begin if (reset_hw) wr1_b <= 0; else begin @@ -197,7 +203,7 @@ module scc(input sysclk, /* WR2 * Reset: unchanged */ - always@(posedge sysclk or posedge reset_hw) begin + always@(negedge sysclk or posedge reset_hw) begin if (reset_hw) wr2 <= 0; else if ((wreg_a || wreg_b) && rindex == 2) @@ -207,7 +213,7 @@ module scc(input sysclk, /* WR3 * Reset: bit 0 to 0, otherwise unchanged. */ - always@(posedge sysclk or posedge reset_hw) begin + always@(negedge sysclk or posedge reset_hw) begin if (reset_hw) wr3_a <= 0; else begin @@ -217,7 +223,7 @@ module scc(input sysclk, wr3_a <= wdata; end end - always@(posedge sysclk or posedge reset_hw) begin + always@(negedge sysclk or posedge reset_hw) begin if (reset_hw) wr3_b <= 0; else begin @@ -231,7 +237,7 @@ module scc(input sysclk, /* WR4 * Reset: Bit 2 to 1, otherwise unchanged */ - always@(posedge sysclk or posedge reset_hw) begin + always@(negedge sysclk or posedge reset_hw) begin if (reset_hw) wr4_a <= 0; else begin @@ -241,7 +247,7 @@ module scc(input sysclk, wr4_a <= wdata; end end - always@(posedge sysclk or posedge reset_hw) begin + always@(negedge sysclk or posedge reset_hw) begin if (reset_hw) wr4_b <= 0; else begin @@ -255,7 +261,7 @@ module scc(input sysclk, /* WR5 * Reset: Bits 7,4,3,2,1 to 0 */ - always@(posedge sysclk or posedge reset_hw) begin + always@(negedge sysclk or posedge reset_hw) begin if (reset_hw) wr5_a <= 0; else begin @@ -265,7 +271,7 @@ module scc(input sysclk, wr5_a <= wdata; end end - always@(posedge sysclk or posedge reset_hw) begin + always@(negedge sysclk or posedge reset_hw) begin if (reset_hw) wr5_b <= 0; else begin @@ -279,13 +285,13 @@ module scc(input sysclk, /* WR6 * Reset: Unchanged. */ - always@(posedge sysclk or posedge reset_hw) begin + always@(negedge sysclk or posedge reset_hw) begin if (reset_hw) wr6_a <= 0; else if (wreg_a && rindex == 6) wr6_a <= wdata; end - always@(posedge sysclk or posedge reset_hw) begin + always@(negedge sysclk or posedge reset_hw) begin if (reset_hw) wr6_b <= 0; else if (wreg_b && rindex == 6) @@ -295,13 +301,13 @@ module scc(input sysclk, /* WR7 * Reset: Unchanged. */ - always@(posedge sysclk or posedge reset_hw) begin + always@(negedge sysclk or posedge reset_hw) begin if (reset_hw) wr7_a <= 0; else if (wreg_a && rindex == 7) wr7_a <= wdata; end - always@(posedge sysclk or posedge reset_hw) begin + always@(negedge sysclk or posedge reset_hw) begin if (reset_hw) wr7_b <= 0; else if (wreg_b && rindex == 7) @@ -311,7 +317,7 @@ module scc(input sysclk, /* WR9. Special: top bits are reset, handled separately, bottom * bits are only reset by a hw reset */ - always@(posedge sysclk or posedge reset_hw) begin + always@(negedge sysclk or posedge reset_hw) begin if (reset_hw) wr9 <= 0; else if ((wreg_a || wreg_b) && rindex == 9) @@ -321,7 +327,7 @@ module scc(input sysclk, /* WR10 * Reset: all 0, except chanel reset retains 6 and 5 */ - always@(posedge sysclk or posedge reset) begin + always@(negedge sysclk or posedge reset) begin if (reset) wr10_a <= 0; else begin @@ -331,7 +337,7 @@ module scc(input sysclk, wr10_a <= wdata; end end - always@(posedge sysclk or posedge reset) begin + always@(negedge sysclk or posedge reset) begin if (reset) wr10_b <= 0; else begin @@ -345,13 +351,13 @@ module scc(input sysclk, /* WR11 * Reset: On full reset only, not channel reset */ - always@(posedge sysclk or posedge reset) begin + always@(negedge sysclk or posedge reset) begin if (reset) wr11_a <= 8'b00001000; else if (wreg_a && rindex == 11) wr11_a <= wdata; end - always@(posedge sysclk or posedge reset) begin + always@(negedge sysclk or posedge reset) begin if (reset) wr11_b <= 8'b00001000; else if (wreg_b && rindex == 11) @@ -361,13 +367,13 @@ module scc(input sysclk, /* WR12 * Reset: Unchanged */ - always@(posedge sysclk or posedge reset_hw) begin + always@(negedge sysclk or posedge reset_hw) begin if (reset_hw) wr12_a <= 0; else if (wreg_a && rindex == 12) wr12_a <= wdata; end - always@(posedge sysclk or posedge reset_hw) begin + always@(negedge sysclk or posedge reset_hw) begin if (reset_hw) wr12_b <= 0; else if (wreg_b && rindex == 12) @@ -377,13 +383,13 @@ module scc(input sysclk, /* WR13 * Reset: Unchanged */ - always@(posedge sysclk or posedge reset_hw) begin + always@(negedge sysclk or posedge reset_hw) begin if (reset_hw) wr13_a <= 0; else if (wreg_a && rindex == 13) wr13_a <= wdata; end - always@(posedge sysclk or posedge reset_hw) begin + always@(negedge sysclk or posedge reset_hw) begin if (reset_hw) wr13_b <= 0; else if (wreg_b && rindex == 13) @@ -395,7 +401,7 @@ module scc(input sysclk, * Chan reset also maitains bottom 2 bits, bit 4 also * reset to a different value */ - always@(posedge sysclk or posedge reset_hw) begin + always@(negedge sysclk or posedge reset_hw) begin if (reset_hw) wr14_a <= 0; else begin @@ -407,7 +413,7 @@ module scc(input sysclk, wr14_a <= wdata; end end - always@(posedge sysclk or posedge reset_hw) begin + always@(negedge sysclk or posedge reset_hw) begin if (reset_hw) wr14_b <= 0; else begin @@ -421,17 +427,14 @@ module scc(input sysclk, end /* WR15 */ - always@(posedge sysclk or posedge reset) begin - if (reset) + always@(negedge sysclk or posedge reset) begin + if (reset) begin wr15_a <= 8'b11111000; - else if (wreg_a && rindex == 15) - wr15_a <= wdata; - end - always@(posedge sysclk or posedge reset) begin - if (reset) wr15_b <= 8'b11111000; - else if (wreg_b && rindex == 15) - wr15_b <= wdata; + end else if (rindex == 15) begin + if(wreg_a) wr15_a <= wdata; + if(wreg_b) wr15_b <= wdata; + end end /* Read data mux */ diff --git a/cores/plus_too/sdram.v b/cores/plus_too/sdram.v index 69ea0a9..1aad3bb 100644 --- a/cores/plus_too/sdram.v +++ b/cores/plus_too/sdram.v @@ -33,7 +33,7 @@ module sdram ( // cpu/chipset interface input init, // init signal after FPGA config to initialize RAM - input clk_128, // sdram is accessed at 128MHz + input clk_64, // sdram is accessed at 64MHz input clk_8, // 8MHz chipset clock to which sdram state machine is synchonized input [15:0] din, // data input from chipset/cpu @@ -44,7 +44,7 @@ module sdram ( input we // cpu/chipset requests write ); -localparam RASCAS_DELAY = 3'd3; // tRCD=20ns -> 3 cycles@128MHz +localparam RASCAS_DELAY = 3'd2; // tRCD=20ns -> 3 cycles@128MHz localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8 localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved localparam CAS_LATENCY = 3'd3; // 2/3 allowed @@ -61,20 +61,20 @@ localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, B // The state machine runs at 128Mhz synchronous to the 8 Mhz chipset clock. // It wraps from T15 to T0 on the rising edge of clk_8 -localparam STATE_FIRST = 4'd0; // first state in cycle -localparam STATE_CMD_START = 4'd1; // state in which a new command can be started +localparam STATE_FIRST = 3'd0; // first state in cycle +localparam STATE_CMD_START = 3'd1; // state in which a new command can be started localparam STATE_CMD_CONT = STATE_CMD_START + RASCAS_DELAY; // command can be continued localparam STATE_READ = STATE_CMD_CONT + CAS_LATENCY + 4'd1; -localparam STATE_LAST = 4'd15; // last state in cycle +localparam STATE_LAST = 3'd7; // last state in cycle -reg [3:0] t; -always @(posedge clk_128) begin +reg [2:0] t; +always @(posedge clk_64) begin // 128Mhz counter synchronous to 8 Mhz clock // force counter to pass state 0 exactly after the rising edge of clk_8 if(((t == STATE_LAST) && ( clk_8 == 0)) || ((t == STATE_FIRST) && ( clk_8 == 1)) || ((t != STATE_LAST) && (t != STATE_FIRST))) - t <= t + 4'd1; + t <= t + 3'd1; end // --------------------------------------------------------------------- @@ -84,7 +84,7 @@ end // wait 1ms (32 8Mhz cycles) after FPGA config is done before going // into normal operation. Initialize the ram in the last 16 reset cycles (cycles 15-0) reg [4:0] reset; -always @(posedge clk_128) begin +always @(posedge clk_64) begin if(init) reset <= 5'h1f; else if((t == STATE_LAST) && (reset != 0)) reset <= reset - 5'd1; @@ -117,7 +117,7 @@ assign sd_we = sd_cmd[0]; assign sd_data = we?din:16'bZZZZZZZZZZZZZZZZ; assign dout = sd_data; -always @(posedge clk_128) begin +always @(posedge clk_64) begin sd_cmd <= CMD_INHIBIT; // default: idle if(reset != 0) begin diff --git a/cores/plus_too/testbench.v b/cores/plus_too/testbench.v deleted file mode 100644 index d1aa265..0000000 --- a/cores/plus_too/testbench.v +++ /dev/null @@ -1,81 +0,0 @@ -`timescale 1ns / 1ps - -//////////////////////////////////////////////////////////////////////////////// -// Company: -// Engineer: -// -// Create Date: 14:54:22 09/05/2011 -// Design Name: plusToo_top -// Module Name: C:/Users/steve/Documents/PlusToo/Verilog/testbench.v -// Project Name: plusToo -// Target Device: -// Tool versions: -// Description: -// -// Verilog Test Fixture created by ISE for module: plusToo_top -// -// Dependencies: -// -// Revision: -// Revision 0.01 - File Created -// Additional Comments: -// -//////////////////////////////////////////////////////////////////////////////// - -`define VIA_A_Data 24'hEFFFFE -`define VIA_A_Dir 24'hEFE9FE - -module testbench; - - // Inputs - reg clk50; - - // Outputs - wire hsync; - wire vsync; - wire [3:0] red; - wire [3:0] green; - wire [3:0] blue; - - // Instantiate the Unit Under Test (UUT) - plusToo_top uut ( - .clk50(clk50), - .hsync(hsync), - .vsync(vsync), - .red(red), - .green(green), - .blue(blue) - ); - - initial begin - clk50 = 1'b1; - uut.ac0.busCycle = 0; - uut.ac0.vt.xpos = 0; - uut.ac0.vt.ypos = 0; - uut.dc0.clkPhase = 0; - end - - always - #10 clk50 = ~clk50; - - always @(posedge uut.clk32) begin - if (uut.cpuAddr == `VIA_A_Data || - uut.cpuAddr == `VIA_A_Dir) begin - $display($time, " memory reference to VIA"); - end - if (uut.loadPixels == 1'b1 && uut.memoryDataInMux == 16'hBEEF) begin - $display($time, " loading bad pixel data"); - end - if (uut.cpuAddr == 24'h4001B8) begin - $display($time, " critical error"); - end - if (uut._cpuAS == 0 && - uut.cpuAddr >= 24'h402000 && - uut.cpuAddr < 24'h800000) begin - $display($time, " memory reference unimplemented ROM"); - $stop(); - end - end - -endmodule - diff --git a/cores/plus_too/via.v b/cores/plus_too/via.v index 1ab8583..5a24884 100644 --- a/cores/plus_too/via.v +++ b/cores/plus_too/via.v @@ -117,7 +117,12 @@ module via( output _irq, output [15:0] dataOut, output memoryOverlayOn, - output SEL // to IWM + output SEL, // to IWM + + input [7:0] kbd_in_data, + input kbd_in_strobe, + output [7:0] kbd_out_data, + output reg kbd_out_strobe ); wire [7:0] dataInHi = dataIn[15:8]; @@ -130,12 +135,44 @@ module via( reg [6:0] viaIFR; reg [6:0] viaIER; reg [7:0] viaACR; + reg [7:0] viaSR; reg [15:0] viaTimer1Count; reg [15:0] viaTimer1Latch; reg [15:0] viaTimer2Count; reg [7:0] viaTimer2LatchLow; reg viaTimer2Armed; + + // shift register can be written by CPU and by external source + /* Write to SR (including external input) */ + assign kbd_out_data = viaSR; + always @(negedge clk8 or negedge _reset) begin + if (_reset == 1'b0) + viaSR <= 8'b0; + else begin + if((selectVIA == 1'b1) && (_cpuUDS == 1'b0) && + (_cpuRW == 1'b0) && (cpuAddrRegHi == 4'hA)) + viaSR <= dataInHi; + + if (viaACR[4:2] == 3'b011 && kbd_in_strobe) + viaSR <= kbd_in_data; + end + end + + /* Generate sr_out_strobe */ + always @(negedge clk8 or negedge _reset) begin + if (_reset == 1'b0) + kbd_out_strobe <= 1'b0; + else begin + if((selectVIA == 1'b1) && (_cpuUDS == 1'b0) && + (_cpuRW == 1'b0) && (cpuAddrRegHi == 4'hA) && + (viaACR[4:2] == 3'b111)) + kbd_out_strobe <= 1; + else + kbd_out_strobe <= 0; + end + end + // divide by 10 clock divider for the VIA timers: 0.78336 MHz reg [3:0] clkDiv; always @(posedge clk8) begin @@ -148,13 +185,13 @@ module via( // store previous vblank value, for edge detection reg _lastVblank; - always @(posedge clk8) begin + always @(negedge clk8) begin _lastVblank <= _vblank; end - + // count vblanks, and set 1 second interrupt after 60 vblanks reg [5:0] vblankCount; - always @(posedge clk8) begin + always @(negedge clk8) begin if (_vblank == 1'b0 && _lastVblank == 1'b1) begin if (vblankCount != 59) begin vblankCount <= vblankCount + 1'b1; @@ -168,7 +205,7 @@ module via( // register write wire loadT2 = selectVIA == 1'b1 && _cpuUDS == 1'b0 && _cpuRW == 1'b0 && cpuAddrRegHi == 4'h9; - always @(posedge clk8 or negedge _reset) begin + always @(negedge clk8 or negedge _reset) begin if (_reset == 1'b0) begin viaB0DDR <= 1'b1; viaADataOut <= 8'b01111111; @@ -183,6 +220,8 @@ module via( viaTimer2Armed <= 0; end else begin +// kbd_out_strobe <= 1'b0; + if (selectVIA == 1'b1 && _cpuUDS == 1'b0) begin if (_cpuRW == 1'b0) begin // normal register writes @@ -208,6 +247,10 @@ module via( viaTimer2Armed = 1'b1; viaIFR[`INT_T2] <= 1'b0; end + 4'hA: begin // shift register + if( viaACR[4:2] == 3'b111 ) + viaIFR[`INT_KEYREADY] <= 1'b1; + end 4'hB: // Aux control register viaACR <= dataInHi; // 4'hC: ignore PCR @@ -231,6 +274,8 @@ module via( end 4'h8: // reading T2C-L clears the T2 interrupt flag viaIFR[`INT_T2] <= 1'b0; + 4'hA: // reading SR clears the SR interrupt flag + viaIFR[`INT_KEYREADY] <= 1'b0; 4'hF: begin // reading (and writing?) register A clears VBLANK and ONESEC interrupt flags viaIFR[`INT_ONESEC] <= 1'b0; viaIFR[`INT_VBLANK] <= 1'b0; @@ -252,49 +297,54 @@ module via( end viaTimer2Count <= viaTimer2Count - 1'b1; end + + // Shift in under control of external clock + if (viaACR[4:2] == 3'b011 && kbd_in_strobe) + viaIFR[`INT_KEYREADY] <= 1; + end end // register read always @(*) begin dataOutHi = 8'hBE; - - if (_cpuRW == 1'b1 && selectVIA == 1'b1 && _cpuUDS == 1'b0) begin - case (cpuAddrRegHi) - 4'h0: // B - // TODO: clear CB1 and CB2 interrupts - dataOutHi = { viaBDataOut[7], ~_hblank, mouseY2, mouseX2, mouseButton, viaBDataOut[2:1], viaB0DDR == 1'b1 ? viaBDataOut[0] : rtcData }; - 4'h2: // B DDR - dataOutHi = { 7'b1000011, viaB0DDR }; - 4'h3: // A DDR - dataOutHi = 8'b01111111; - 4'h4: // timer 1 count low - dataOutHi = viaTimer1Count[7:0]; - 4'h5: // timer 1 count high - dataOutHi = viaTimer1Count[15:8]; - 4'h6: // timer 1 latch low - dataOutHi = viaTimer1Latch[7:0]; - 4'h7: // timer 1 latch high - dataOutHi = viaTimer1Latch[15:8]; - 4'h8: // timer 2 count low - dataOutHi = viaTimer2Count[7:0]; - 4'h9: // timer 2 count high - dataOutHi = viaTimer2Count[15:8]; - 4'hB: // Aux control register - dataOutHi = viaACR; - 4'hC: // PCR - dataOutHi = 0; - 4'hD: // IFR - dataOutHi = { viaIFR & viaIER == 0 ? 1'b0 : 1'b1, viaIFR }; - 4'hE: // IER - dataOutHi = { 1'b1, viaIER }; - 4'hF: // A - // TODO: clear CA1 and CA2 interrupts - dataOutHi = { sccWReq, viaADataOut[6:0] }; - default: - dataOutHi = 8'hBE; - endcase - end + + case (cpuAddrRegHi) + 4'h0: // B + // TODO: clear CB1 and CB2 interrupts + dataOutHi = { viaBDataOut[7], ~_hblank, mouseY2, mouseX2, mouseButton, viaBDataOut[2:1], viaB0DDR == 1'b1 ? viaBDataOut[0] : rtcData }; + 4'h2: // B DDR + dataOutHi = { 7'b1000011, viaB0DDR }; + 4'h3: // A DDR + dataOutHi = 8'b01111111; + 4'h4: // timer 1 count low + dataOutHi = viaTimer1Count[7:0]; + 4'h5: // timer 1 count high + dataOutHi = viaTimer1Count[15:8]; + 4'h6: // timer 1 latch low + dataOutHi = viaTimer1Latch[7:0]; + 4'h7: // timer 1 latch high + dataOutHi = viaTimer1Latch[15:8]; + 4'h8: // timer 2 count low + dataOutHi = viaTimer2Count[7:0]; + 4'h9: // timer 2 count high + dataOutHi = viaTimer2Count[15:8]; + 4'hA: // shift register + dataOutHi = viaSR; + 4'hB: // Aux control register + dataOutHi = viaACR; + 4'hC: // PCR + dataOutHi = 0; + 4'hD: // IFR + dataOutHi = { viaIFR & viaIER == 0 ? 1'b0 : 1'b1, viaIFR }; + 4'hE: // IER + dataOutHi = { 1'b1, viaIER }; + 4'hF: // A + // TODO: clear CA1 and CA2 interrupts + dataOutHi = { sccWReq, viaADataOut[6:0] }; + default: + dataOutHi = 8'hBE; + endcase end assign memoryOverlayOn = viaADataOut[4]; diff --git a/cores/plus_too/videoTimer.v b/cores/plus_too/videoTimer.v index 3cf7e75..4ca4f05 100644 --- a/cores/plus_too/videoTimer.v +++ b/cores/plus_too/videoTimer.v @@ -7,8 +7,7 @@ module videoTimer( output reg vsync, output _hblank, output _vblank, - output loadNormalPixels, - output loadDebugPixels, + output loadPixels, output loadSound ); @@ -69,8 +68,7 @@ module videoTimer( (kVisibleHeightStart/2 * kVisibleWidth/2) + { ypos[9:1], xpos[6:2], 1'b0 }; - assign loadNormalPixels = _vblank == 1'b1 && _hblank == 1'b1 && busCycle == 2'b00; - assign loadDebugPixels = _vblank == 1'b0 && _hblank == 1'b1 && busCycle == 2'b00; + assign loadPixels = _vblank == 1'b1 && _hblank == 1'b1 && busCycle == 2'b00; assign loadSound = 1'b0; From 3033861e88f190308d8f5cd829c09ca69f8248c4 Mon Sep 17 00:00:00 2001 From: Till Harbaum Date: Mon, 26 Oct 2015 21:06:55 +0100 Subject: [PATCH 2/4] [Plus Too] Floppy dsk support and various other small improvements --- cores/plus_too/pll.qip | 4 ++++ 1 file changed, 4 insertions(+) create mode 100644 cores/plus_too/pll.qip diff --git a/cores/plus_too/pll.qip b/cores/plus_too/pll.qip new file mode 100644 index 0000000..afd958b --- /dev/null +++ b/cores/plus_too/pll.qip @@ -0,0 +1,4 @@ +set_global_assignment -name IP_TOOL_NAME "ALTPLL" +set_global_assignment -name IP_TOOL_VERSION "13.1" +set_global_assignment -name VERILOG_FILE [file join $::quartus(qip_path) "pll.v"] +set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "pll.ppf"] From d663fa9a480c215fc3e78dc3dcb4d1c584c75d55 Mon Sep 17 00:00:00 2001 From: Till Harbaum Date: Mon, 26 Oct 2015 21:13:19 +0100 Subject: [PATCH 3/4] [Plus Too] removed unused files --- cores/plus_too/ramAdapter.v | 18 ------------------ cores/plus_too/sdcard.v | 27 --------------------------- 2 files changed, 45 deletions(-) delete mode 100644 cores/plus_too/ramAdapter.v delete mode 100644 cores/plus_too/sdcard.v diff --git a/cores/plus_too/ramAdapter.v b/cores/plus_too/ramAdapter.v deleted file mode 100644 index 452a977..0000000 --- a/cores/plus_too/ramAdapter.v +++ /dev/null @@ -1,18 +0,0 @@ -module ramAdapter( - // CPU interface - input clk8, - input [20:0] addr, // word address - output [15:0] dataOut, - input _OE, - input _CS, - input _UDS, - input _LDS, - - // external interface to 8-bit Flash - output [21:0] flashAddr, // byte address - input [7:0] flashData, - output flashCE, - output flashOE -); - -endmodule diff --git a/cores/plus_too/sdcard.v b/cores/plus_too/sdcard.v deleted file mode 100644 index 070cd3d..0000000 --- a/cores/plus_too/sdcard.v +++ /dev/null @@ -1,27 +0,0 @@ -module sdcard( - input clk8, - input _reset, - input selectIWM -); - - spiMaster sdcard_intf( - // host interface - .clk_i(clk8), - .rst_i(), - .address_i(), // input [7:0] - .data_i(), // input [7:0] - .data_o(), // output [7:0] - .strobe_i(), // input - .we_i(), // input - .ack_o(), // output - - // SPI logic clock - spiSysClk(), - - //SPI bus - spiClkOut(), - spiDataIn(), - spiDataOut(), - spiCS_n()); - -endmodule From c7c69dc0999c3c3ba4ee252a20025f80b26f944e Mon Sep 17 00:00:00 2001 From: Till Harbaum Date: Tue, 27 Oct 2015 21:52:02 +0100 Subject: [PATCH 4/4] [Plus Too] Added basic audio support --- cores/plus_too/addrController_top.v | 80 ++- cores/plus_too/dataController_top.v | 49 +- cores/plus_too/data_io.v | 6 +- cores/plus_too/floppy.v | 6 +- cores/plus_too/plusToo_top.qsf | 871 ++++++++++++---------------- cores/plus_too/plusToo_top.v | 38 +- cores/plus_too/readme.md | 6 +- cores/plus_too/sigma_delta_dac.v | 129 ++++ cores/plus_too/via.v | 10 +- cores/plus_too/videoTimer.v | 5 +- 10 files changed, 657 insertions(+), 543 deletions(-) create mode 100644 cores/plus_too/sigma_delta_dac.v diff --git a/cores/plus_too/addrController_top.v b/cores/plus_too/addrController_top.v index 08c3a96..1224dec 100644 --- a/cores/plus_too/addrController_top.v +++ b/cores/plus_too/addrController_top.v @@ -35,10 +35,10 @@ module addrController_top( output _hblank, output _vblank, output loadPixels, - - // audio: + + input snd_alt, output loadSound, - + // misc input memoryOverlayOn, @@ -49,12 +49,45 @@ module addrController_top( output dskReadAckExt ); -assign dioBusControl = extraBusControl; + // -------------- audio engine (may be moved into seperate module) --------------- + assign loadSound = sndReadAck; + + localparam SIZE = 20'd67704; // 168*608/2 clk8 events per frame + localparam STEP = 20'd5920; // one step every 16*370 clk8 events + + reg [21:0] audioAddr; + reg [19:0] snd_div; + + reg sndReadAckD; + always @(negedge clk8) + sndReadAckD <= sndReadAck; + + reg vblankD, vblankD2; + always @(posedge clk8) begin + if(sndReadAckD) begin + vblankD <= _vblank; + vblankD2 <= vblankD; + + // falling adge of _vblank = begin of vblank phase + if(vblankD2 && !vblankD) begin + audioAddr <= snd_alt?22'h3FA100:22'h3FFD00; + snd_div <= 20'd0; + end else begin + if(snd_div >= SIZE-1) begin + snd_div <= snd_div - SIZE + STEP; + audioAddr <= audioAddr + 22'd2; + end else + snd_div <= snd_div + STEP; + end + end + end + + assign dioBusControl = extraBusControl; // interleaved RAM access for CPU and video reg [1:0] busCycle; always @(posedge clk8) - busCycle <= busCycle + 1'b1; + busCycle <= busCycle + 2'd1; // video controls memory bus during the first clock of the four-clock cycle assign videoBusControl = (busCycle == 2'b00); @@ -74,42 +107,44 @@ assign dioBusControl = extraBusControl; wire [21:0] videoAddr; // RAM/ROM control signals - wire videoControlActive = _hblank == 1'b1 || loadSound; + wire videoControlActive = _hblank; - assign _romOE = ~(extraBusControl || (cpuBusControl && selectROM == 1'b1 && _cpuRW == 1'b1)); -// assign _romOE = ~((videoBusControl && videoControlActive == 1'b0) || (cpuBusControl && selectROM == 1'b1 && _cpuRW == 1'b1)); + wire extraRomRead = dskReadAckInt || dskReadAckExt; + assign _romOE = ~(extraRomRead || (cpuBusControl && selectROM == 1'b1 && _cpuRW == 1'b1)); - assign _ramOE = ~((videoBusControl && videoControlActive == 1'b1) || + wire extraRamRead = sndReadAck; + assign _ramOE = ~((videoBusControl && videoControlActive == 1'b1) || (extraRamRead) || (cpuBusControl && selectRAM == 1'b1 && _cpuRW == 1'b1)); assign _ramWE = ~(cpuBusControl && selectRAM && _cpuRW == 1'b0); assign _memoryUDS = cpuBusControl ? _cpuUDS : 1'b0; assign _memoryLDS = cpuBusControl ? _cpuLDS : 1'b0; - wire [21:0] addrMux = videoBusControl ? videoAddr : cpuAddr[21:0]; + wire [21:0] addrMux = sndReadAck ? audioAddr : videoBusControl ? videoAddr : cpuAddr[21:0]; wire [21:0] macAddr; assign macAddr[15:0] = addrMux[15:0]; - // video always addresses ram - wire ram_access = (cpuBusControl && selectRAM) || videoBusControl; + // video and sound always addresses ram + wire ram_access = (cpuBusControl && selectRAM) || videoBusControl || sndReadAck; + wire rom_access = (cpuBusControl && selectROM); // simulate smaller RAM/ROM sizes - assign macAddr[16] = selectROM && configROMSize == 1'b0 ? 1'b0 : // force A16 to 0 for 64K ROM access + assign macAddr[16] = rom_access && configROMSize == 1'b0 ? 1'b0 : // force A16 to 0 for 64K ROM access addrMux[16]; assign macAddr[17] = ram_access && configRAMSize == 2'b00 ? 1'b0 : // force A17 to 0 for 128K RAM access - selectROM && configROMSize == 1'b1 ? 1'b0 : // force A17 to 0 for 128K ROM access - selectROM && configROMSize == 1'b0 ? 1'b1 : // force A17 to 1 for 64K ROM access (64K ROM image is at $20000) + rom_access && configROMSize == 1'b1 ? 1'b0 : // force A17 to 0 for 128K ROM access + rom_access && configROMSize == 1'b0 ? 1'b1 : // force A17 to 1 for 64K ROM access (64K ROM image is at $20000) addrMux[17]; assign macAddr[18] = ram_access && configRAMSize == 2'b00 ? 1'b0 : // force A18 to 0 for 128K RAM access - selectROM ? 1'b0 : // force A18 to 0 for ROM access + rom_access ? 1'b0 : // force A18 to 0 for ROM access addrMux[18]; assign macAddr[19] = ram_access && configRAMSize[1] == 1'b0 ? 1'b0 : // force A19 to 0 for 128K or 512K RAM access - selectROM ? 1'b0 : // force A19 to 0 for ROM access + rom_access ? 1'b0 : // force A19 to 0 for ROM access addrMux[19]; assign macAddr[20] = ram_access && configRAMSize != 2'b11 ? 1'b0 : // force A20 to 0 for all but 4MB RAM access - selectROM ? 1'b0 : // force A20 to 0 for ROM access + rom_access ? 1'b0 : // force A20 to 0 for ROM access addrMux[20]; assign macAddr[21] = ram_access && configRAMSize != 2'b11 ? 1'b0 : // force A21 to 0 for all but 4MB RAM access - selectROM ? 1'b0 : // force A21 to 0 for ROM access + rom_access ? 1'b0 : // force A21 to 0 for ROM access addrMux[21]; // allocate memory slots in the extra cycle @@ -118,9 +153,11 @@ assign dioBusControl = extraBusControl; if(busCycle == 2'b11) extra_slot_count <= extra_slot_count + 2'd1; - // loppy emulation gets extra slots 0 and 1 + // floppy emulation gets extra slots 0 and 1 assign dskReadAckInt = (extraBusControl == 1'b1) && (extra_slot_count == 0); assign dskReadAckExt = (extraBusControl == 1'b1) && (extra_slot_count == 1); + // audio gets extra slot 2 + assign sndReadAck = (extraBusControl == 1'b1) && (extra_slot_count == 2); assign memoryAddr = dskReadAckInt ? dskReadAddrInt + 22'h100000: // first dsk image at 1MB @@ -180,7 +217,6 @@ assign dioBusControl = extraBusControl; .vsync(vsync), ._hblank(_hblank), ._vblank(_vblank), - .loadPixels(loadPixels), - .loadSound(loadSound)); + .loadPixels(loadPixels)); endmodule diff --git a/cores/plus_too/dataController_top.v b/cores/plus_too/dataController_top.v index 3e5b39d..8042c89 100644 --- a/cores/plus_too/dataController_top.v +++ b/cores/plus_too/dataController_top.v @@ -47,10 +47,11 @@ module dataController_top( input _vblank, input loadPixels, - // audio: - input loadSound, - output sound, - + // audio + output [10:0] audioOut, // 8 bit audio + 3 bit volume + output snd_alt, + input loadSound, + // misc output memoryOverlayOn, input [1:0] insertDisk, @@ -63,11 +64,33 @@ module dataController_top( input dskReadAckExt ); + // add binary volume levels according to volume setting + assign audioOut = + (snd_vol[0]?audio_x1:11'd0) + + (snd_vol[1]?audio_x2:11'd0) + + (snd_vol[2]?audio_x4:11'd0); + + // three binary volume levels *1, *2 and *4 + wire [10:0] audio_x1 = { 3'b000, audio_latch }; + wire [10:0] audio_x2 = { 2'b00, audio_latch, 1'b0 }; + wire [10:0] audio_x4 = { 1'b0, audio_latch, 2'b00}; + + reg loadSoundD; + always @(negedge clk8) + loadSoundD <= loadSound; + + reg [7:0] audio_latch; + always @(posedge clk8) begin + if(loadSoundD) begin + if(snd_ena) audio_latch <= 8'h80; + else audio_latch <= memoryDataIn[15:8]; + end + end + // divide 32.5 MHz clock by four to get CPU clock reg [1:0] clkPhase; - always @(posedge clk32) begin + always @(posedge clk32) clkPhase <= clkPhase + 1'b1; - end assign clk8 = clkPhase[1]; // CPU reset generation @@ -103,10 +126,7 @@ module dataController_top( !_viaIrq?3'b110: !_sccIrq?3'b101: 3'b111; - - // Sound - assign sound = 0; - + // Serial port assign serialOut = 0; @@ -119,6 +139,10 @@ module dataController_top( // Memory-side assign memoryDataOut = cpuDataIn; + + wire [2:0] snd_vol; + wire snd_ena; + // VIA via v( .clk8(clk8), @@ -138,6 +162,11 @@ module dataController_top( .dataOut(viaDataOut), .memoryOverlayOn(memoryOverlayOn), .SEL(SEL), + + .snd_vol(snd_vol), + .snd_ena(snd_ena), + .snd_alt(snd_alt), + .kbd_in_data(kbd_in_data), .kbd_in_strobe(kbd_in_strobe), .kbd_out_data(kbd_out_data), diff --git a/cores/plus_too/data_io.v b/cores/plus_too/data_io.v index c1a3ffc..4b28b95 100644 --- a/cores/plus_too/data_io.v +++ b/cores/plus_too/data_io.v @@ -40,6 +40,10 @@ module data_io ( // spi client // ********************************************************************************* +// filter spi clock. the 8 bit gate delay is ~2.5ns in total +wire [7:0] spi_sck_D = { spi_sck_D[6:0], sck } /* synthesis keep */; +wire spi_sck = (spi_sck && spi_sck_D != 8'h00) || (!spi_sck && spi_sck_D == 8'hff); + // this core supports only the display related OSD commands // of the minimig reg [14:0] sbuf; @@ -58,7 +62,7 @@ assign downloading = downloading_reg; reg downloading_reg = 1'b0; // data_io has its own SPI interface to the io controller -always@(posedge sck, posedge ss) begin +always@(posedge spi_sck, posedge ss) begin if(ss == 1'b1) cnt <= 5'd0; else begin diff --git a/cores/plus_too/floppy.v b/cores/plus_too/floppy.v index 6dcffc6..bb9fcc5 100644 --- a/cores/plus_too/floppy.v +++ b/cores/plus_too/floppy.v @@ -106,10 +106,14 @@ module floppy( driveRegs[`DRIVE_REG_DIRTN] // step direction }; + reg dskReadAckD; + always @(negedge clk8) + dskReadAckD <= dskReadAck; + // latch incoming data reg [7:0] dskReadDataLatch; always @(posedge clk8) - if(dskReadAck) + if(dskReadAckD) dskReadDataLatch <= dskReadData; // generate glitch free data clock diff --git a/cores/plus_too/plusToo_top.qsf b/cores/plus_too/plusToo_top.qsf index 859fba9..4da4991 100644 --- a/cores/plus_too/plusToo_top.qsf +++ b/cores/plus_too/plusToo_top.qsf @@ -337,7 +337,6 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 8MA -to AUDIO_R set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to UART_RX -<<<<<<< HEAD set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0 set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "pll:cs0|c0" -section_id auto_signaltap_0 @@ -541,9 +540,24 @@ set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLE set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0 set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "addrController_top:ac0|_hblank" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "addrController_top:ac0|_memoryLDS" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "addrController_top:ac0|_memoryUDS" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "addrController_top:ac0|_hblank" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "addrController_top:ac0|_memoryLDS" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "addrController_top:ac0|_memoryUDS" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=128" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=128" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "addrController_top:ac0|_ramOE" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "addrController_top:ac0|_ramWE" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "addrController_top:ac0|_romOE" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "addrController_top:ac0|_vblank" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "addrController_top:ac0|_ramOE" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "addrController_top:ac0|_ramWE" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "addrController_top:ac0|_romOE" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "addrController_top:ac0|_vblank" -section_id auto_signaltap_0 +set_global_assignment -name VERILOG_FILE sigma_delta_dac.v set_global_assignment -name VERILOG_FILE floppy_track_encoder.v -======= ->>>>>>> 6a3164f3c71aa22fabf665c4838932b2343298ea set_global_assignment -name VERILOG_FILE ps2_kbd.v set_global_assignment -name VHDL_FILE TG68K_Pack.vhd set_global_assignment -name VHDL_FILE TG68KdotC_Kernel.vhd @@ -564,495 +578,370 @@ set_global_assignment -name VERILOG_FILE dataController_top.v set_global_assignment -name VERILOG_FILE videoTimer.v set_global_assignment -name VERILOG_FILE videoShifter.v set_global_assignment -name VERILOG_FILE plusToo_top.v -<<<<<<< HEAD set_global_assignment -name VERILOG_FILE floppy.v set_global_assignment -name SIGNALTAP_FILE stp1.stp set_global_assignment -name QIP_FILE pll.qip -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "addrController_top:ac0|_hblank" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "addrController_top:ac0|_memoryLDS" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "addrController_top:ac0|_memoryUDS" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "addrController_top:ac0|_hblank" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "addrController_top:ac0|_memoryLDS" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "addrController_top:ac0|_memoryUDS" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=128" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=128" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "addrController_top:ac0|_ramOE" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "addrController_top:ac0|_ramWE" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "addrController_top:ac0|_romOE" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "addrController_top:ac0|_vblank" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to "addrController_top:ac0|busCycle[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to "addrController_top:ac0|busCycle[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "addrController_top:ac0|_ramOE" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "addrController_top:ac0|_ramWE" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "addrController_top:ac0|_romOE" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "addrController_top:ac0|_vblank" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "addrController_top:ac0|busCycle[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "addrController_top:ac0|busCycle[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to "addrController_top:ac0|extra_slot_count[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to "addrController_top:ac0|extra_slot_count[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "addrController_top:ac0|extra_slot_count[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to "addrController_top:ac0|extra_slot_count[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAck" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[110] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[111] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[112] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[11]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[113] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[12]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[114] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[13]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[115] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[14]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[116] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[15]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[117] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[16]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[118] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[17]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[119] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[18]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[120] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[19]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[121] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[122] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[20]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[123] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[21]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[124] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[125] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[126] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[127] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[128] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[129] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[130] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[131] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[132] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[133] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[134] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[135] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[136] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[137] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[138] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAck" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[110] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[111] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[112] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[11]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[113] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[12]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[114] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[13]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[115] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[14]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[116] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[15]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[117] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[16]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[118] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[17]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[119] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[18]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[120] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[19]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[121] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[122] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[20]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[123] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[21]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[124] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[125] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[126] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[127] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[128] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[129] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[130] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[131] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|dskReadAddr[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[132] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[133] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[134] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[135] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[136] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[137] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[138] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to "addrController_top:ac0|videoBusControl" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to "clock325MHz:cs0|locked" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to "dataController_top:dc0|diskEject[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to "dataController_top:dc0|diskEject[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|diskEject" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[139] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskEject" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[140] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[141] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[142] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[143] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[144] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[145] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[146] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[147] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[148] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[149] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[150] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[151] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[152] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[153] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[154] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[155] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAck" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[156] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[157] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[158] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[11]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[159] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[12]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[160] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[13]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[161] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[14]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[162] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[15]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[163] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[16]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[164] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[17]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[165] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[18]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[166] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[19]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[167] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[168] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[20]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[169] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[21]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[170] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[171] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[172] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[173] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[174] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[175] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[176] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[177] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[178] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[179] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[180] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[181] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[182] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[183] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[184] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[185] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[186] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[187] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[188] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[189] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[190] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[191] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[192] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[193] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[194] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[195] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[196] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[197] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[198] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[199] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[200] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[201] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[202] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[203] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[204] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[205] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[206] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[207] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[208] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[209] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[210] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[211] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[212] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[213] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[214] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[215] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[216] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[217] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[218] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|clk" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[219] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[220] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[221] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[222] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[223] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[224] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[225] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[226] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[227] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[228] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[229] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[230] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[231] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[232] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[233] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[234] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[235] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[236] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[237] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[238] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[239] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[240] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[241] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[242] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[243] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[244] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[245] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|newByteReady" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[246] -to "data_io:data_io|addr[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[247] -to "data_io:data_io|addr[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[248] -to "data_io:data_io|addr[11]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[249] -to "data_io:data_io|addr[12]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[250] -to "data_io:data_io|addr[13]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[251] -to "data_io:data_io|addr[14]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[252] -to "data_io:data_io|addr[15]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[253] -to "data_io:data_io|addr[16]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[254] -to "data_io:data_io|addr[17]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[255] -to "data_io:data_io|addr[18]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[256] -to "data_io:data_io|addr[19]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[257] -to "data_io:data_io|addr[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[258] -to "data_io:data_io|addr[20]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[259] -to "data_io:data_io|addr[21]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[260] -to "data_io:data_io|addr[22]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[261] -to "data_io:data_io|addr[23]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[262] -to "data_io:data_io|addr[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[263] -to "data_io:data_io|addr[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[264] -to "data_io:data_io|addr[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[265] -to "data_io:data_io|addr[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[266] -to "data_io:data_io|addr[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[267] -to "data_io:data_io|addr[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[268] -to "data_io:data_io|addr[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[269] -to "data_io:data_io|addr[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[270] -to "data_io:data_io|downloading" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[271] -to "data_io:data_io|index[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[272] -to "data_io:data_io|index[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[273] -to "data_io:data_io|index[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[274] -to "data_io:data_io|index[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[275] -to "data_io:data_io|index[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[276] -to dsk_ext_ds -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[277] -to dsk_ext_ss -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[278] -to dsk_int_ds -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[279] -to dsk_int_ss -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[280] -to "sdram:sdram|addr[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[281] -to "sdram:sdram|addr[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[282] -to "sdram:sdram|addr[11]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[283] -to "sdram:sdram|addr[12]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[284] -to "sdram:sdram|addr[13]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[285] -to "sdram:sdram|addr[14]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[286] -to "sdram:sdram|addr[15]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[287] -to "sdram:sdram|addr[16]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[288] -to "sdram:sdram|addr[17]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[289] -to "sdram:sdram|addr[18]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[290] -to "sdram:sdram|addr[19]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[291] -to "sdram:sdram|addr[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[292] -to "sdram:sdram|addr[20]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[293] -to "sdram:sdram|addr[21]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[294] -to "sdram:sdram|addr[22]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[295] -to "sdram:sdram|addr[23]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[296] -to "sdram:sdram|addr[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[297] -to "sdram:sdram|addr[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[298] -to "sdram:sdram|addr[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[299] -to "sdram:sdram|addr[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[300] -to "sdram:sdram|addr[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[301] -to "sdram:sdram|addr[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[302] -to "sdram:sdram|addr[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[303] -to "sdram:sdram|addr[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[304] -to "sdram:sdram|dout[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[305] -to "sdram:sdram|dout[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[306] -to "sdram:sdram|dout[11]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[307] -to "sdram:sdram|dout[12]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[308] -to "sdram:sdram|dout[13]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[309] -to "sdram:sdram|dout[14]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[310] -to "sdram:sdram|dout[15]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[311] -to "sdram:sdram|dout[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[312] -to "sdram:sdram|dout[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[313] -to "sdram:sdram|dout[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[314] -to "sdram:sdram|dout[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[315] -to "sdram:sdram|dout[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[316] -to "sdram:sdram|dout[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[317] -to "sdram:sdram|dout[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[318] -to "sdram:sdram|dout[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[319] -to "sdram:sdram|dout[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[320] -to "sdram:sdram|sd_cas" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[321] -to "sdram:sdram|sd_cs" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[322] -to "sdram:sdram|sd_ras" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[323] -to "sdram:sdram|sd_we" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[324] -to "sdram:sdram|t[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[325] -to "sdram:sdram|t[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[326] -to "sdram:sdram|t[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[327] -to "sdram:sdram|we" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to "addrController_top:ac0|videoBusControl" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to "clock325MHz:cs0|locked" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to "dataController_top:dc0|diskEject[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to "dataController_top:dc0|diskEject[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to "dataController_top:dc0|iwm:i|floppy:floppyExt|diskEject" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[139] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskEject" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[140] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[141] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[142] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[143] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[144] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[145] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[146] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[147] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[148] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[149] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[150] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[151] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[152] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[153] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[154] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[155] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAck" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[156] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[157] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[158] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[11]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[159] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[12]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[160] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[13]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[161] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[14]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[162] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[15]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[163] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[16]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[164] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[17]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[165] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[18]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[166] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[19]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[167] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[168] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[20]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[169] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[21]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[170] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[171] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[172] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[173] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[174] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[175] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[176] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[177] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadAddr[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[178] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[179] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[180] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[181] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[182] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[183] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[184] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[185] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadDataLatch[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[186] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[187] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[188] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[189] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[190] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[191] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[192] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[193] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|dskReadData[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[194] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[195] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[196] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[197] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[198] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[199] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[200] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[201] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[202] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[203] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[204] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[205] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[206] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[207] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[208] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[209] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[210] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[211] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[212] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[213] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[214] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[215] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[216] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[217] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[218] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|clk" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[219] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[220] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[221] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[222] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[223] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[224] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[225] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[226] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[227] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[228] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[229] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[230] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[231] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[232] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[233] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[234] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[235] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[236] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[237] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[238] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[239] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[240] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[241] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[242] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[243] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[244] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|odata[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[245] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|newByteReady" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[246] -to "data_io:data_io|addr[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[247] -to "data_io:data_io|addr[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[248] -to "data_io:data_io|addr[11]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[249] -to "data_io:data_io|addr[12]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[250] -to "data_io:data_io|addr[13]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[251] -to "data_io:data_io|addr[14]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[252] -to "data_io:data_io|addr[15]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[253] -to "data_io:data_io|addr[16]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[254] -to "data_io:data_io|addr[17]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[255] -to "data_io:data_io|addr[18]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[256] -to "data_io:data_io|addr[19]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[257] -to "data_io:data_io|addr[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[258] -to "data_io:data_io|addr[20]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[259] -to "data_io:data_io|addr[21]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[260] -to "data_io:data_io|addr[22]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[261] -to "data_io:data_io|addr[23]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[262] -to "data_io:data_io|addr[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[263] -to "data_io:data_io|addr[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[264] -to "data_io:data_io|addr[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[265] -to "data_io:data_io|addr[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[266] -to "data_io:data_io|addr[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[267] -to "data_io:data_io|addr[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[268] -to "data_io:data_io|addr[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[269] -to "data_io:data_io|addr[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[270] -to "data_io:data_io|downloading" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[271] -to "data_io:data_io|index[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[272] -to "data_io:data_io|index[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[273] -to "data_io:data_io|index[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[274] -to "data_io:data_io|index[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[275] -to "data_io:data_io|index[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[276] -to dsk_ext_ds -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[277] -to dsk_ext_ss -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[278] -to dsk_int_ds -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[279] -to dsk_int_ss -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[280] -to "sdram:sdram|addr[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[281] -to "sdram:sdram|addr[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[282] -to "sdram:sdram|addr[11]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[283] -to "sdram:sdram|addr[12]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[284] -to "sdram:sdram|addr[13]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[285] -to "sdram:sdram|addr[14]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[286] -to "sdram:sdram|addr[15]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[287] -to "sdram:sdram|addr[16]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[288] -to "sdram:sdram|addr[17]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[289] -to "sdram:sdram|addr[18]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[290] -to "sdram:sdram|addr[19]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[291] -to "sdram:sdram|addr[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[292] -to "sdram:sdram|addr[20]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[293] -to "sdram:sdram|addr[21]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[294] -to "sdram:sdram|addr[22]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[295] -to "sdram:sdram|addr[23]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[296] -to "sdram:sdram|addr[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[297] -to "sdram:sdram|addr[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[298] -to "sdram:sdram|addr[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[299] -to "sdram:sdram|addr[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[300] -to "sdram:sdram|addr[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[301] -to "sdram:sdram|addr[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[302] -to "sdram:sdram|addr[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[303] -to "sdram:sdram|addr[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[304] -to "sdram:sdram|dout[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[305] -to "sdram:sdram|dout[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[306] -to "sdram:sdram|dout[11]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[307] -to "sdram:sdram|dout[12]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[308] -to "sdram:sdram|dout[13]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[309] -to "sdram:sdram|dout[14]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[310] -to "sdram:sdram|dout[15]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[311] -to "sdram:sdram|dout[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[312] -to "sdram:sdram|dout[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[313] -to "sdram:sdram|dout[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[314] -to "sdram:sdram|dout[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[315] -to "sdram:sdram|dout[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[316] -to "sdram:sdram|dout[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[317] -to "sdram:sdram|dout[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[318] -to "sdram:sdram|dout[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[319] -to "sdram:sdram|dout[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[320] -to "sdram:sdram|sd_cas" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[321] -to "sdram:sdram|sd_cs" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[322] -to "sdram:sdram|sd_ras" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[323] -to "sdram:sdram|sd_we" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[324] -to "sdram:sdram|t[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[325] -to "sdram:sdram|t[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[326] -to "sdram:sdram|t[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[327] -to "sdram:sdram|we" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=328" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=328" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=1005" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=61163" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=1089" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to "addrController_top:ac0|audioAddr[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to "addrController_top:ac0|audioAddr[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to "addrController_top:ac0|audioAddr[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to "addrController_top:ac0|audioAddr[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to "addrController_top:ac0|audioAddr[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to "addrController_top:ac0|audioAddr[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to "addrController_top:ac0|audioAddr[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to "addrController_top:ac0|audioAddr[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to "addrController_top:ac0|audioAddr[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to "addrController_top:ac0|audioAddr[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[110] -to "addrController_top:ac0|audioAddr[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[111] -to "addrController_top:ac0|audioAddr[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[112] -to "addrController_top:ac0|audioAddr[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[113] -to "addrController_top:ac0|audioAddr[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[114] -to "addrController_top:ac0|audioAddr[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[115] -to "addrController_top:ac0|audioAddr[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[116] -to "addrController_top:ac0|audioAddr[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[117] -to "addrController_top:ac0|audioAddr[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[118] -to "addrController_top:ac0|audioAddr[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[119] -to "addrController_top:ac0|audioAddr[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[120] -to "addrController_top:ac0|audioAddr[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[121] -to "addrController_top:ac0|audioAddr[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[122] -to "addrController_top:ac0|busCycle[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[123] -to "addrController_top:ac0|busCycle[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[124] -to "addrController_top:ac0|extra_slot_count[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[125] -to "addrController_top:ac0|extra_slot_count[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[126] -to "addrController_top:ac0|loadSound" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[127] -to "addrController_top:ac0|snd_alt" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[128] -to "addrController_top:ac0|snd_div[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[129] -to "addrController_top:ac0|snd_div[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[130] -to "addrController_top:ac0|snd_div[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[131] -to "addrController_top:ac0|snd_div[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[132] -to "addrController_top:ac0|snd_div[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[133] -to "addrController_top:ac0|snd_div[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[134] -to "addrController_top:ac0|snd_div[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[135] -to "addrController_top:ac0|snd_div[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[136] -to "addrController_top:ac0|snd_div[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[137] -to "addrController_top:ac0|snd_div[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[138] -to "addrController_top:ac0|videoBusControl" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[139] -to "clock325MHz:cs0|locked" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[140] -to "dataController_top:dc0|audioOut[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[141] -to "dataController_top:dc0|audioOut[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[142] -to "dataController_top:dc0|audioOut[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[143] -to "dataController_top:dc0|audioOut[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[144] -to "dataController_top:dc0|audioOut[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[145] -to "dataController_top:dc0|audioOut[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[146] -to "dataController_top:dc0|audioOut[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[147] -to "dataController_top:dc0|audioOut[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[148] -to "dataController_top:dc0|audioOut[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[149] -to "dataController_top:dc0|audioOut[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[150] -to "dataController_top:dc0|audioOut[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[151] -to "dataController_top:dc0|audio_latch[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[152] -to "dataController_top:dc0|audio_latch[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[153] -to "dataController_top:dc0|audio_latch[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[154] -to "dataController_top:dc0|audio_latch[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[155] -to "dataController_top:dc0|audio_latch[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[156] -to "dataController_top:dc0|audio_latch[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[157] -to "dataController_top:dc0|audio_latch[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[158] -to "dataController_top:dc0|audio_latch[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[159] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[160] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[161] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[162] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[163] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[164] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[165] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[166] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[167] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[168] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[169] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[170] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[171] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[172] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[173] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[174] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[175] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[176] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[177] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[178] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[179] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[180] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[181] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[182] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[183] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[184] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[185] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[186] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[187] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[188] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[189] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[190] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[191] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[192] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[193] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[194] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[195] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[196] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[197] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[198] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[199] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[200] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[201] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[202] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[203] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[204] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[205] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|clk" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[206] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[207] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[208] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[209] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[210] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[211] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[212] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[213] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[214] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[215] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[216] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[217] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[218] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[219] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[220] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[221] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[222] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[223] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[224] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|newByteReady" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[225] -to "dataController_top:dc0|snd_alt" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[226] -to "dataController_top:dc0|via:v|snd_ena" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[227] -to "dataController_top:dc0|via:v|snd_vol[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[228] -to "dataController_top:dc0|via:v|snd_vol[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[229] -to "dataController_top:dc0|via:v|snd_vol[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[230] -to "sdram:sdram|addr[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[231] -to "sdram:sdram|addr[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[232] -to "sdram:sdram|addr[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[233] -to "sdram:sdram|addr[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[234] -to "sdram:sdram|addr[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[235] -to "sdram:sdram|addr[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[236] -to "sdram:sdram|addr[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[237] -to "sdram:sdram|addr[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[238] -to "sdram:sdram|addr[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[239] -to "sdram:sdram|addr[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[240] -to "sdram:sdram|addr[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[241] -to "sdram:sdram|addr[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[242] -to "sdram:sdram|addr[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[243] -to "sdram:sdram|addr[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[244] -to "sdram:sdram|addr[22]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[245] -to "sdram:sdram|addr[23]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[246] -to "sdram:sdram|addr[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[247] -to "sdram:sdram|addr[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[248] -to "sdram:sdram|addr[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[249] -to "sdram:sdram|addr[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[250] -to "sdram:sdram|addr[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[251] -to "sdram:sdram|addr[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[252] -to "sdram:sdram|addr[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[253] -to "sdram:sdram|addr[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[254] -to "sdram:sdram|dout[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[255] -to "sdram:sdram|dout[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[256] -to "sdram:sdram|dout[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[257] -to "sdram:sdram|dout[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[258] -to "sdram:sdram|dout[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[259] -to "sdram:sdram|dout[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[260] -to "sdram:sdram|dout[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[261] -to "sdram:sdram|dout[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[262] -to "sdram:sdram|dout[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[263] -to "sdram:sdram|dout[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[264] -to "sdram:sdram|dout[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[265] -to "sdram:sdram|dout[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[266] -to "sdram:sdram|dout[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[267] -to "sdram:sdram|dout[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[268] -to "sdram:sdram|dout[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[269] -to "sdram:sdram|dout[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[270] -to "sdram:sdram|sd_cas" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[271] -to "sdram:sdram|sd_cs" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[272] -to "sdram:sdram|sd_ras" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[273] -to "sdram:sdram|sd_we" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[274] -to "sdram:sdram|t[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[275] -to "sdram:sdram|t[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[276] -to "sdram:sdram|t[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[277] -to "sdram:sdram|we" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "addrController_top:ac0|audioAddr[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "addrController_top:ac0|audioAddr[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "addrController_top:ac0|audioAddr[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to "addrController_top:ac0|audioAddr[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to "addrController_top:ac0|audioAddr[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to "addrController_top:ac0|audioAddr[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to "addrController_top:ac0|audioAddr[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to "addrController_top:ac0|audioAddr[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to "addrController_top:ac0|audioAddr[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to "addrController_top:ac0|audioAddr[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[110] -to "addrController_top:ac0|audioAddr[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[111] -to "addrController_top:ac0|audioAddr[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[112] -to "addrController_top:ac0|audioAddr[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[113] -to "addrController_top:ac0|audioAddr[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[114] -to "addrController_top:ac0|audioAddr[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[115] -to "addrController_top:ac0|audioAddr[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[116] -to "addrController_top:ac0|audioAddr[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[117] -to "addrController_top:ac0|audioAddr[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[118] -to "addrController_top:ac0|audioAddr[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[119] -to "addrController_top:ac0|audioAddr[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[120] -to "addrController_top:ac0|audioAddr[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[121] -to "addrController_top:ac0|audioAddr[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[122] -to "addrController_top:ac0|busCycle[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[123] -to "addrController_top:ac0|busCycle[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[124] -to "addrController_top:ac0|extra_slot_count[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[125] -to "addrController_top:ac0|extra_slot_count[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[126] -to "addrController_top:ac0|loadSound" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[127] -to "addrController_top:ac0|snd_alt" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[128] -to "addrController_top:ac0|snd_div[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[129] -to "addrController_top:ac0|snd_div[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[130] -to "addrController_top:ac0|snd_div[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[131] -to "addrController_top:ac0|snd_div[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[132] -to "addrController_top:ac0|snd_div[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[133] -to "addrController_top:ac0|snd_div[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[134] -to "addrController_top:ac0|snd_div[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[135] -to "addrController_top:ac0|snd_div[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[136] -to "addrController_top:ac0|snd_div[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[137] -to "addrController_top:ac0|snd_div[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[138] -to "addrController_top:ac0|videoBusControl" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[139] -to "clock325MHz:cs0|locked" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[140] -to "dataController_top:dc0|audioOut[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[141] -to "dataController_top:dc0|audioOut[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[142] -to "dataController_top:dc0|audioOut[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[143] -to "dataController_top:dc0|audioOut[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[144] -to "dataController_top:dc0|audioOut[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[145] -to "dataController_top:dc0|audioOut[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[146] -to "dataController_top:dc0|audioOut[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[147] -to "dataController_top:dc0|audioOut[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[148] -to "dataController_top:dc0|audioOut[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[149] -to "dataController_top:dc0|audioOut[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[150] -to "dataController_top:dc0|audioOut[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[151] -to "dataController_top:dc0|audio_latch[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[152] -to "dataController_top:dc0|audio_latch[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[153] -to "dataController_top:dc0|audio_latch[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[154] -to "dataController_top:dc0|audio_latch[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[155] -to "dataController_top:dc0|audio_latch[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[156] -to "dataController_top:dc0|audio_latch[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[157] -to "dataController_top:dc0|audio_latch[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[158] -to "dataController_top:dc0|audio_latch[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[159] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[160] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[161] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[162] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[163] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[164] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[165] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskDataByteTimer[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[166] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[167] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[168] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[169] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[170] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[171] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[172] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[173] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|diskImageData[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[174] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[175] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[176] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[177] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[178] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[179] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[180] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|driveTrack[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[181] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[182] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[183] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[184] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[185] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[186] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[187] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[188] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c1[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[189] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[190] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[191] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[192] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[193] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[194] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[195] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[196] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c2[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[197] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[198] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[199] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[200] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[201] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[202] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[203] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[204] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|c3[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[205] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|clk" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[206] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[207] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[208] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[209] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[210] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[211] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[212] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[213] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[214] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[215] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|count[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[216] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[217] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[218] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[219] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[220] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[221] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[222] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[223] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|floppy_track_encoder:enc|data_latch[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[224] -to "dataController_top:dc0|iwm:i|floppy:floppyInt|newByteReady" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[225] -to "dataController_top:dc0|snd_alt" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[226] -to "dataController_top:dc0|via:v|snd_ena" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[227] -to "dataController_top:dc0|via:v|snd_vol[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[228] -to "dataController_top:dc0|via:v|snd_vol[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[229] -to "dataController_top:dc0|via:v|snd_vol[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[230] -to "sdram:sdram|addr[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[231] -to "sdram:sdram|addr[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[232] -to "sdram:sdram|addr[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[233] -to "sdram:sdram|addr[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[234] -to "sdram:sdram|addr[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[235] -to "sdram:sdram|addr[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[236] -to "sdram:sdram|addr[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[237] -to "sdram:sdram|addr[16]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[238] -to "sdram:sdram|addr[17]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[239] -to "sdram:sdram|addr[18]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[240] -to "sdram:sdram|addr[19]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[241] -to "sdram:sdram|addr[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[242] -to "sdram:sdram|addr[20]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[243] -to "sdram:sdram|addr[21]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[244] -to "sdram:sdram|addr[22]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[245] -to "sdram:sdram|addr[23]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[246] -to "sdram:sdram|addr[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[247] -to "sdram:sdram|addr[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[248] -to "sdram:sdram|addr[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[249] -to "sdram:sdram|addr[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[250] -to "sdram:sdram|addr[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[251] -to "sdram:sdram|addr[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[252] -to "sdram:sdram|addr[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[253] -to "sdram:sdram|addr[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[254] -to "sdram:sdram|dout[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[255] -to "sdram:sdram|dout[10]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[256] -to "sdram:sdram|dout[11]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[257] -to "sdram:sdram|dout[12]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[258] -to "sdram:sdram|dout[13]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[259] -to "sdram:sdram|dout[14]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[260] -to "sdram:sdram|dout[15]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[261] -to "sdram:sdram|dout[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[262] -to "sdram:sdram|dout[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[263] -to "sdram:sdram|dout[3]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[264] -to "sdram:sdram|dout[4]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[265] -to "sdram:sdram|dout[5]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[266] -to "sdram:sdram|dout[6]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[267] -to "sdram:sdram|dout[7]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[268] -to "sdram:sdram|dout[8]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[269] -to "sdram:sdram|dout[9]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[270] -to "sdram:sdram|sd_cas" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[271] -to "sdram:sdram|sd_cs" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[272] -to "sdram:sdram|sd_ras" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[273] -to "sdram:sdram|sd_we" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[274] -to "sdram:sdram|t[0]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[275] -to "sdram:sdram|t[1]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[276] -to "sdram:sdram|t[2]" -section_id auto_signaltap_0 +set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[277] -to "sdram:sdram|we" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=278" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=278" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=855" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=42733" -section_id auto_signaltap_0 +set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=17167" -section_id auto_signaltap_0 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp -======= -set_global_assignment -name VERILOG_FILE debugPanel.v -set_global_assignment -name VERILOG_FILE fontGen.v -set_global_assignment -name VERILOG_FILE floppy.v -set_global_assignment -name SIGNALTAP_FILE stp1.stp -set_global_assignment -name QIP_FILE pll.qip -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top ->>>>>>> 6a3164f3c71aa22fabf665c4838932b2343298ea +set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp \ No newline at end of file diff --git a/cores/plus_too/plusToo_top.v b/cores/plus_too/plusToo_top.v index 2d16956..0892aca 100644 --- a/cores/plus_too/plusToo_top.v +++ b/cores/plus_too/plusToo_top.v @@ -1,6 +1,6 @@ // PlusToo_top for the MIST FPGA board -module plusToo_top( +module plusToo_top( // clock inputs input wire [ 2-1:0] CLOCK_27, // 27 MHz // LED outputs @@ -198,10 +198,14 @@ assign SDRAM_CLK = !clk64; wire [15:0] memoryDataOut; // peripherals - wire loadSound, loadPixels, pixelOut, _hblank, _vblank; + wire loadPixels, pixelOut, _hblank, _vblank; wire memoryOverlayOn, selectSCC, selectIWM, selectVIA; wire [15:0] dataControllerDataOut; + // audio + wire snd_alt; + wire loadSound; + // floppy disk image interface wire dskReadAckInt; wire [21:0] dskReadAddrInt; @@ -299,9 +303,11 @@ assign SDRAM_CLK = !clk64; ._hblank(_hblank), ._vblank(_vblank), .loadPixels(loadPixels), - .loadSound(loadSound), .memoryOverlayOn(memoryOverlayOn), + .snd_alt(snd_alt), + .loadSound(loadSound), + .dskReadAddrInt(dskReadAddrInt), .dskReadAckInt(dskReadAckInt), .dskReadAddrExt(dskReadAddrExt), @@ -325,7 +331,16 @@ assign SDRAM_CLK = !clk64; else if(rst_cnt != 0) rst_cnt <= rst_cnt - 16'd1; end - + + wire [10:0] audio; + sigma_delta_dac dac ( + .clk ( clk32 ), + .ldatasum ( { audio, 3'h0 } ), + .rdatasum ( { audio, 3'h0 } ), + .left ( AUDIO_L ), + .right ( AUDIO_R ) + ); + dataController_top dc0( .clk32(clk32), .clk8(clk8), @@ -345,21 +360,30 @@ assign SDRAM_CLK = !clk64; .videoBusControl(videoBusControl), .memoryDataOut(memoryDataOut), .memoryDataIn(sdram_do), + + // peripherals .keyClk(keyClk), .keyData(keyData), .mouseClk(mouseClk), .mouseData(mouseData), .serialIn(serialIn), + + // video ._hblank(_hblank), ._vblank(_vblank), .pixelOut(pixelOut), - .loadPixels(loadPixels), - .loadSound(loadSound), + .loadPixels(loadPixels), + .memoryOverlayOn(memoryOverlayOn), + + .audioOut(audio), + .snd_alt(snd_alt), + .loadSound(loadSound), + + // floppy disk interface .insertDisk( { dsk_ext_ins, dsk_int_ins} ), .diskSides( { dsk_ext_ds, dsk_int_ds} ), .diskEject(diskEject), - .dskReadAddrInt(dskReadAddrInt), .dskReadAckInt(dskReadAckInt), .dskReadAddrExt(dskReadAddrExt), diff --git a/cores/plus_too/readme.md b/cores/plus_too/readme.md index 35e8ff7..55090ad 100644 --- a/cores/plus_too/readme.md +++ b/cores/plus_too/readme.md @@ -21,7 +21,6 @@ itself. Major changes were: Functional changes: - tg68k cpu core updated to latest version -<<<<<<< HEAD - floppy disk images use 400k or 800k dsk format - support for second floppy disk - SDRAM clock reduced to 65MHz @@ -30,9 +29,6 @@ Functional changes: - removed irq vector generation - various timing simplifications - fix mouse counter wrapping -======= -- Keyboard support -- Cleaned up overall timing ->>>>>>> 6a3164f3c71aa22fabf665c4838932b2343298ea +- Basic sound support Binaries are available at the [binaries repository](https://github.com/mist-devel/mist-binaries/tree/master/cores/plus_too). diff --git a/cores/plus_too/sigma_delta_dac.v b/cores/plus_too/sigma_delta_dac.v new file mode 100644 index 0000000..b0085de --- /dev/null +++ b/cores/plus_too/sigma_delta_dac.v @@ -0,0 +1,129 @@ +// sigmadelta.v +// two channel second order sigma delta dac +// taken from Minimig + +// audio data processing +// stereo sigma/delta bitstream modulator +module sigma_delta_dac ( + input clk, // bus clock + input [14:0] ldatasum, // left channel data + input [14:0] rdatasum, // right channel data + output reg left=0, // left bitstream output + output reg right=0 // right bitsteam output +); + +//-------------------------------------------------------------------------------------- + +// local signals +localparam DW = 15; +localparam CW = 2; +localparam RW = 4; +localparam A1W = 2; +localparam A2W = 5; + +wire [DW+2+0 -1:0] sd_l_er0, sd_r_er0; +reg [DW+2+0 -1:0] sd_l_er0_prev=0, sd_r_er0_prev=0; +wire [DW+A1W+2-1:0] sd_l_aca1, sd_r_aca1; +wire [DW+A2W+2-1:0] sd_l_aca2, sd_r_aca2; +reg [DW+A1W+2-1:0] sd_l_ac1=0, sd_r_ac1=0; +reg [DW+A2W+2-1:0] sd_l_ac2=0, sd_r_ac2=0; +wire [DW+A2W+3-1:0] sd_l_quant, sd_r_quant; + +// LPF noise LFSR +reg [24-1:0] seed1 = 24'h654321; +reg [19-1:0] seed2 = 19'h12345; +reg [24-1:0] seed_sum=0, seed_prev=0, seed_out=0; +always @ (posedge clk) begin + if (&seed1) + seed1 <= #1 24'h654321; + else + seed1 <= #1 {seed1[22:0], ~(seed1[23] ^ seed1[22] ^ seed1[21] ^ seed1[16])}; +end +always @ (posedge clk) begin + if (&seed2) + seed2 <= #1 19'h12345; + else + seed2 <= #1 {seed2[17:0], ~(seed2[18] ^ seed2[17] ^ seed2[16] ^ seed2[13] ^ seed2[0])}; +end +always @ (posedge clk) begin + seed_sum <= #1 seed1 + {5'b0, seed2}; + seed_prev <= #1 seed_sum; + seed_out <= #1 seed_sum - seed_prev; +end + +// linear interpolate +localparam ID=4; // counter size, also 2^ID = interpolation rate +reg [ID+0-1:0] int_cnt = 0; +always @ (posedge clk) int_cnt <= #1 int_cnt + 'd1; + +reg [DW+0-1:0] ldata_cur=0, ldata_prev=0; +reg [DW+0-1:0] rdata_cur=0, rdata_prev=0; +wire [DW+1-1:0] ldata_step, rdata_step; +reg [DW+ID-1:0] ldata_int=0, rdata_int=0; +wire [DW+0-1:0] ldata_int_out, rdata_int_out; +assign ldata_step = {ldata_cur[DW-1], ldata_cur} - {ldata_prev[DW-1], ldata_prev}; // signed subtract +assign rdata_step = {rdata_cur[DW-1], rdata_cur} - {rdata_prev[DW-1], rdata_prev}; // signed subtract +always @ (posedge clk) begin + if (~|int_cnt) begin + ldata_prev <= #1 ldata_cur; + ldata_cur <= #1 ldatasum; //{~ldatasum[DW-1], ldatasum[DW-2:0]}; // convert to offset binary, samples no longer signed! + rdata_prev <= #1 rdata_cur; + rdata_cur <= #1 rdatasum; //{~rdatasum[DW-1], rdatasum[DW-2:0]}; // convert to offset binary, samples no longer signed! + ldata_int <= #1 {ldata_cur[DW-1], ldata_cur, {ID{1'b0}}}; + rdata_int <= #1 {rdata_cur[DW-1], rdata_cur, {ID{1'b0}}}; + end else begin + ldata_int <= #1 ldata_int + {{ID{ldata_step[DW+1-1]}}, ldata_step}; + rdata_int <= #1 rdata_int + {{ID{rdata_step[DW+1-1]}}, rdata_step}; + end +end +assign ldata_int_out = ldata_int[DW+ID-1:ID]; +assign rdata_int_out = rdata_int[DW+ID-1:ID]; + +// input gain x3 +wire [DW+2-1:0] ldata_gain, rdata_gain; +assign ldata_gain = {ldata_int_out[DW-1], ldata_int_out, 1'b0} + {{(2){ldata_int_out[DW-1]}}, ldata_int_out}; +assign rdata_gain = {rdata_int_out[DW-1], rdata_int_out, 1'b0} + {{(2){rdata_int_out[DW-1]}}, rdata_int_out}; + +/* +// random dither to 15 bits +reg [DW-1:0] ldata=0, rdata=0; +always @ (posedge clk) begin + ldata <= #1 ldata_gain[DW+2-1:2] + ( (~(&ldata_gain[DW+2-1-1:2]) && (ldata_gain[1:0] > seed_out[1:0])) ? 15'd1 : 15'd0 ); + rdata <= #1 rdata_gain[DW+2-1:2] + ( (~(&ldata_gain[DW+2-1-1:2]) && (ldata_gain[1:0] > seed_out[1:0])) ? 15'd1 : 15'd0 ); +end +*/ + +// accumulator adders +assign sd_l_aca1 = {{(A1W){ldata_gain[DW+2-1]}}, ldata_gain} - {{(A1W){sd_l_er0[DW+2-1]}}, sd_l_er0} + sd_l_ac1; +assign sd_r_aca1 = {{(A1W){rdata_gain[DW+2-1]}}, rdata_gain} - {{(A1W){sd_r_er0[DW+2-1]}}, sd_r_er0} + sd_r_ac1; + +assign sd_l_aca2 = {{(A2W-A1W){sd_l_aca1[DW+A1W+2-1]}}, sd_l_aca1} - {{(A2W){sd_l_er0[DW+2-1]}}, sd_l_er0} - {{(A2W+1){sd_l_er0_prev[DW+2-1]}}, sd_l_er0_prev[DW+2-1:1]} + sd_l_ac2; +assign sd_r_aca2 = {{(A2W-A1W){sd_r_aca1[DW+A1W+2-1]}}, sd_r_aca1} - {{(A2W){sd_r_er0[DW+2-1]}}, sd_r_er0} - {{(A2W+1){sd_r_er0_prev[DW+2-1]}}, sd_r_er0_prev[DW+2-1:1]} + sd_r_ac2; + +// accumulators +always @ (posedge clk) begin + sd_l_ac1 <= #1 sd_l_aca1; + sd_r_ac1 <= #1 sd_r_aca1; + sd_l_ac2 <= #1 sd_l_aca2; + sd_r_ac2 <= #1 sd_r_aca2; +end + +// value for quantizaton +assign sd_l_quant = {sd_l_ac2[DW+A2W+2-1], sd_l_ac2} + {{(DW+A2W+3-RW){seed_out[RW-1]}}, seed_out[RW-1:0]}; +assign sd_r_quant = {sd_r_ac2[DW+A2W+2-1], sd_r_ac2} + {{(DW+A2W+3-RW){seed_out[RW-1]}}, seed_out[RW-1:0]}; + +// error feedback +assign sd_l_er0 = sd_l_quant[DW+A2W+3-1] ? {1'b1, {(DW+2-1){1'b0}}} : {1'b0, {(DW+2-1){1'b1}}}; +assign sd_r_er0 = sd_r_quant[DW+A2W+3-1] ? {1'b1, {(DW+2-1){1'b0}}} : {1'b0, {(DW+2-1){1'b1}}}; +always @ (posedge clk) begin + sd_l_er0_prev <= #1 (&sd_l_er0) ? sd_l_er0 : sd_l_er0+1; + sd_r_er0_prev <= #1 (&sd_r_er0) ? sd_r_er0 : sd_r_er0+1; +end + +// output +always @ (posedge clk) begin + left <= #1 (~|ldata_gain) ? ~left : ~sd_l_er0[DW+2-1]; + right <= #1 (~|rdata_gain) ? ~right : ~sd_r_er0[DW+2-1]; +end + +endmodule diff --git a/cores/plus_too/via.v b/cores/plus_too/via.v index 5a24884..c96fb47 100644 --- a/cores/plus_too/via.v +++ b/cores/plus_too/via.v @@ -118,6 +118,10 @@ module via( output [15:0] dataOut, output memoryOverlayOn, output SEL, // to IWM + + output snd_ena, + output snd_alt, + output [2:0] snd_vol, input [7:0] kbd_in_data, input kbd_in_strobe, @@ -220,8 +224,6 @@ module via( viaTimer2Armed <= 0; end else begin -// kbd_out_strobe <= 1'b0; - if (selectVIA == 1'b1 && _cpuUDS == 1'b0) begin if (_cpuRW == 1'b0) begin // normal register writes @@ -347,6 +349,10 @@ module via( endcase end + assign snd_vol = viaADataOut[2:0]; + assign snd_alt = !viaADataOut[3]; + assign snd_ena = viaBDataOut[7]; + assign memoryOverlayOn = viaADataOut[4]; assign SEL = viaADataOut[5]; diff --git a/cores/plus_too/videoTimer.v b/cores/plus_too/videoTimer.v index 4ca4f05..11f86ba 100644 --- a/cores/plus_too/videoTimer.v +++ b/cores/plus_too/videoTimer.v @@ -7,8 +7,7 @@ module videoTimer( output reg vsync, output _hblank, output _vblank, - output loadPixels, - output loadSound + output loadPixels ); // timing data from http://tinyvga.com/vga-timing/1024x768@60Hz @@ -69,7 +68,5 @@ module videoTimer( { ypos[9:1], xpos[6:2], 1'b0 }; assign loadPixels = _vblank == 1'b1 && _hblank == 1'b1 && busCycle == 2'b00; - - assign loadSound = 1'b0; endmodule