diff --git a/cores/nes/mist/NES_mist.v b/cores/nes/mist/NES_mist.v index dc0b7b8..65bbd80 100644 --- a/cores/nes/mist/NES_mist.v +++ b/cores/nes/mist/NES_mist.v @@ -141,28 +141,29 @@ parameter CONF_STR = { parameter CONF_STR_LEN = 8+25+9+10+9; wire [7:0] status; wire scandoubler_disable; +wire ps2_kbd_clk, ps2_kbd_data; user_io #(.STRLEN(CONF_STR_LEN)) user_io( - .conf_str ( CONF_STR ), + .conf_str(CONF_STR), // the spi interface - .SPI_CLK (SPI_SCK ), - .SPI_SS_IO (CONF_DATA0 ), - .SPI_MISO (SPI_DO ), // tristate handling inside user_io - .SPI_MOSI (SPI_DI ), + .SPI_SCK(SPI_SCK), + .CONF_DATA0(CONF_DATA0), + .SPI_DO(SPI_DO), // tristate handling inside user_io + .SPI_DI(SPI_DI), - .SWITCHES (switches ), - .BUTTONS (buttons ), + .switches(switches), + .buttons(buttons), .scandoubler_disable(scandoubler_disable), - .JOY0 (joyA ), - .JOY1 (joyB ), + .joystick_0(joyA), + .joystick_1(joyB), - .status (status ), + .status(status), - .clk (1'b0 ), // should be 10-16kHz for ps2 clock - .ps2_data ( ), - .ps2_clk ( ) + .ps2_clk(ps2_clk), // should be 10-16kHz for ps2 clock + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data) ); // if "Start" or "Select" are selected from the menu keep them set for half a second @@ -186,10 +187,10 @@ wire strt = (start_cnt != 0); wire sel = (select_cnt != 0); wire [7:0] nes_joy_A = { joyB[0], joyB[1], joyB[2], joyB[3], - joyB[7] | strt, joyB[6] | sel, joyB[5], joyB[4] }; + joyB[7] | strt, joyB[6] | sel, joyB[5], joyB[4] } | kbd_joy0; wire [7:0] nes_joy_B = { joyA[0], joyA[1], joyA[2], joyA[3], - joyA[7], joyA[6], joyA[5], joyA[4] }; - + joyA[7], joyA[6], joyA[5], joyA[4] } | kbd_joy1; + wire clock_locked; wire clk85; clk clock_21mhz(.inclk0(CLOCK_27[0]), .c0(clk85), .c1(SDRAM_CLK), .locked(clock_locked)); @@ -213,10 +214,11 @@ wire [7:0] nes_joy_B = { joyA[0], joyA[1], joyA[2], joyA[3], init_reset <= 1'b0; end - reg [1:0] clkcnt; + reg [12:0] clkcnt; always @(posedge clk85) clkcnt <= clkcnt + 2'd1; wire clk = clkcnt[1]; + wire ps2_clk = clkcnt[12]; // Loader @@ -391,5 +393,18 @@ assign VGA_VS = scandoubler_disable ? 1'b1 : nes_vs; ); assign LED = ~downloading; + +wire [7:0] kbd_joy0; +wire [7:0] kbd_joy1; + +keyboard keyboard ( + .clk(clk), + .reset(reset_nes), + .ps2_kbd_clk(ps2_kbd_clk), + .ps2_kbd_data(ps2_kbd_data), + + .joystick_0(kbd_joy0), + .joystick_1(kbd_joy1) +); endmodule diff --git a/cores/nes/mist/keyboard.v b/cores/nes/mist/keyboard.v new file mode 100644 index 0000000..19f5b8e --- /dev/null +++ b/cores/nes/mist/keyboard.v @@ -0,0 +1,72 @@ + + +module keyboard +( + input clk, + input reset, + input ps2_kbd_clk, + input ps2_kbd_data, + + output [7:0] joystick_0, + output [7:0] joystick_1 +); + +reg pressed; +reg e0; +wire [7:0] keyb_data; +wire keyb_valid; + +// PS/2 interface +ps2_intf ps2( + clk, + !reset, + + ps2_kbd_clk, + ps2_kbd_data, + + // Byte-wide data interface - only valid for one clock + // so must be latched externally if required + keyb_data, + keyb_valid +); + +reg joy_num; +reg [7:0] buttons; +assign joystick_0 = joy_num ? 7'b0 : buttons; +assign joystick_1 = joy_num ? buttons : 7'b0; + +always @(posedge reset or posedge clk) begin + + if(reset) begin + pressed <= 1'b1; + e0 <= 1'b0; + end else begin + if (keyb_valid) begin + if (keyb_data == 8'HE0) + e0 <=1'b1; + else if (keyb_data == 8'HF0) + pressed <= 1'b0; + else begin + case({e0, keyb_data}) + 9'H016: if(pressed) joy_num <= 1'b0; // 1 + 9'H01E: if(pressed) joy_num <= 1'b1; // 2 + + 9'H175: buttons[4] <= pressed; // arrow up + 9'H172: buttons[5] <= pressed; // arrow down + 9'H16B: buttons[6] <= pressed; // arrow left + 9'H174: buttons[7] <= pressed; // arrow right + + 9'H029: buttons[0] <= pressed; // Space + 9'H011: buttons[1] <= pressed; // Left Alt + 9'H00d: buttons[2] <= pressed; // Tab + 9'H076: buttons[3] <= pressed; // Escape + endcase; + + pressed <= 1'b1; + e0 <= 1'b0; + end + end + end +end + +endmodule diff --git a/cores/nes/mist/ps2_intf.v b/cores/nes/mist/ps2_intf.v new file mode 100644 index 0000000..f128cda --- /dev/null +++ b/cores/nes/mist/ps2_intf.v @@ -0,0 +1,141 @@ +// ZX Spectrum for Altera DE1 +// +// Copyright (c) 2009-2011 Mike Stirling +// +// All rights reserved +// +// Redistribution and use in source and synthezised forms, with or without +// modification, are permitted provided that the following conditions are met: +// +// * Redistributions of source code must retain the above copyright notice, +// this list of conditions and the following disclaimer. +// +// * Redistributions in synthesized form must reproduce the above copyright +// notice, this list of conditions and the following disclaimer in the +// documentation and/or other materials provided with the distribution. +// +// * Neither the name of the author nor the names of other contributors may +// be used to endorse or promote products derived from this software without +// specific prior written agreement from the author. +// +// * License is granted for non-commercial use only. A fee may not be charged +// for redistributions as source code or in synthesized/hardware form without +// specific prior written agreement from the author. +// +// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, +// THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR +// PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE +// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +// POSSIBILITY OF SUCH DAMAGE. +// + +// PS/2 interface (input only) +// Based loosely on ps2_ctrl.vhd (c) ALSE. http://www.alse-fr.com + +// This is input-only for the time being +module ps2_intf #(parameter filter_length=8)( + input CLK, + input nRESET, + + // PS/2 interface (could be bi-dir) + input PS2_CLK, + input PS2_DATA, + + // Byte-wide data interface - only valid for one clock + // so must be latched externally if required + output reg [7:0] DATA, + output reg VALID, + output reg ERROR +); + + reg [filter_length-1:0] clk_filter; + + reg ps2_clk_in; + reg ps2_dat_in; + // Goes high when a clock falling edge is detected + reg clk_edge; + reg [3:0] bit_count; + reg [8:0] shiftreg; + reg parity; + // Register input signals + + always @(negedge nRESET or posedge CLK) + if (!nRESET) begin + ps2_clk_in <= 1'b1; + ps2_dat_in <= 1'b1; + clk_filter <= 8'b11111111; + clk_edge <= 1'b0; + end else begin + // Register inputs (and filter clock) + ps2_dat_in <= PS2_DATA; + clk_filter <= {PS2_CLK, clk_filter[filter_length-1:1]}; + clk_edge <= 1'b0; + + if (clk_filter) + // Filtered clock is high + ps2_clk_in <= 1'b1; + else begin + // Filter clock is low, check for edge + if (ps2_clk_in) clk_edge <= 1'b1; + ps2_clk_in <= 1'b0; + end + end + + // Shift in keyboard data + always @(negedge nRESET or posedge CLK) begin + if (!nRESET) begin + bit_count <= 4'd0; + shiftreg <= 9'd0; + parity <= 1'b0; + DATA <= 8'd0; + VALID <= 1'b0; + ERROR <= 1'b0; + end else begin + // Clear flags + VALID <= 1'b0; + ERROR <= 1'b0; + + if (clk_edge) begin + // We have a new bit from the keyboard for processing + if (bit_count == 4'd0) begin + // Idle state, check for start bit (0) only and don't + // start counting bits until we get it + parity <= 1'b0; + if (!ps2_dat_in) bit_count <= bit_count + 4'd1; // This is a start bit + end else begin + // Running. 8-bit data comes in LSb first followed by + // a single stop bit (1) + if (bit_count < 4'd10) begin + // Shift in data and parity (9 bits) + bit_count <= bit_count + 4'd1; + shiftreg <= {ps2_dat_in, shiftreg[8:1]}; + parity <= parity ^ ps2_dat_in; // Calculate parity + end else if (ps2_dat_in) begin + // Valid stop bit received + bit_count <= 4'd0; // back to idle + if (parity) begin + // Parity correct, submit data to host + DATA <= shiftreg[7:0]; + VALID <= 1'b1; + end else begin + // Error + ERROR <= 1'b1; + end + end + else begin + // Invalid stop bit + bit_count <= 4'd0; // back to idle + ERROR <= 1'b1; + end + end + end + end + end + +endmodule diff --git a/cores/nes/mist/user_io.v b/cores/nes/mist/user_io.v index 00c2aa2..ee5baa5 100644 --- a/cores/nes/mist/user_io.v +++ b/cores/nes/mist/user_io.v @@ -21,168 +21,379 @@ // // parameter STRLEN and the actual length of conf_str have to match - + module user_io #(parameter STRLEN=0) ( input [(8*STRLEN)-1:0] conf_str, - input SPI_CLK, - input SPI_SS_IO, - output reg SPI_MISO, - input SPI_MOSI, + input SPI_SCK, + input CONF_DATA0, + output reg SPI_DO, + input SPI_DI, - output [7:0] JOY0, - output [7:0] JOY1, - output [1:0] BUTTONS, - output [1:0] SWITCHES, - output scandoubler_disable, + output reg [7:0] joystick_0, + output reg [7:0] joystick_1, + output reg [15:0] joystick_analog_0, + output reg [15:0] joystick_analog_1, + output [1:0] buttons, + output [1:0] switches, + output scandoubler_disable, - output reg [7:0] status, - - input clk, - output ps2_clk, - output reg ps2_data + output reg [7:0] status, + + // connection to sd card emulation + input [31:0] sd_lba, + input sd_rd, + input sd_wr, + output reg sd_ack, + input sd_conf, + input sd_sdhc, + output reg [7:0] sd_dout, + output reg sd_dout_strobe, + input [7:0] sd_din, + output reg sd_din_strobe, + output sd_mounted, + + + // ps2 keyboard emulation + input ps2_clk, // 12-16khz provided by core + output ps2_kbd_clk, + output reg ps2_kbd_data, + output ps2_mouse_clk, + output reg ps2_mouse_data, + + // serial com port + input [7:0] serial_data, + input serial_strobe ); -reg [6:0] sbuf; -reg [7:0] cmd; -reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... -reg [7:0] byte_cnt; // counts bytes -reg [7:0] joystick0; -reg [7:0] joystick1; -reg [4:0] but_sw; +reg [6:0] sbuf; +reg [7:0] cmd; +reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... +reg [7:0] byte_cnt; // counts bytes +reg [7:0] but_sw; +reg [2:0] stick_idx; -assign JOY0 = joystick0; -assign JOY1 = joystick1; -assign BUTTONS = but_sw[1:0]; -assign SWITCHES = but_sw[3:2]; +reg mount_strobe = 1'b0; +assign sd_mounted = mount_strobe; + +assign buttons = but_sw[1:0]; +assign switches = but_sw[3:2]; assign scandoubler_disable = but_sw[4]; +wire [7:0] dout = { sbuf, SPI_DI}; + // this variant of user_io is for 8 bit cores (type == a4) only wire [7:0] core_type = 8'ha4; +// command byte read by the io controller +wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; + // drive MISO only when transmitting core id -always@(negedge SPI_CLK or posedge SPI_SS_IO) begin - if(SPI_SS_IO == 1) begin - SPI_MISO <= 1'bZ; +always@(negedge SPI_SCK or posedge CONF_DATA0) begin + if(CONF_DATA0 == 1) begin + SPI_DO <= 1'bZ; end else begin + // first byte returned is always core type, further bytes are // command dependent if(byte_cnt == 0) begin - SPI_MISO <= core_type[~bit_cnt]; + SPI_DO <= core_type[~bit_cnt]; + end else begin + // reading serial fifo + if(cmd == 8'h1b) begin + // send alternating flag byte and data + if(byte_cnt[0]) SPI_DO <= serial_out_status[~bit_cnt]; + else SPI_DO <= serial_out_byte[~bit_cnt]; + end + // reading config string - if(cmd == 8'h14) begin + else if(cmd == 8'h14) begin // returning a byte from string if(byte_cnt < STRLEN + 1) - SPI_MISO <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; + SPI_DO <= conf_str[{STRLEN - byte_cnt,~bit_cnt}]; else - SPI_MISO <= 1'b0; + SPI_DO <= 1'b0; end + + // reading sd card status + else if(cmd == 8'h16) begin + if(byte_cnt == 1) + SPI_DO <= sd_cmd[~bit_cnt]; + else if((byte_cnt >= 2) && (byte_cnt < 6)) + SPI_DO <= sd_lba[{5-byte_cnt, ~bit_cnt}]; + else + SPI_DO <= 1'b0; + end + + // reading sd card write data + else if(cmd == 8'h18) + SPI_DO <= sd_din[~bit_cnt]; + + else + SPI_DO <= 1'b0; end end end -// 8 byte fifo to store ps2 bytes +// ---------------- PS2 --------------------- + +// 8 byte fifos to store ps2 bytes localparam PS2_FIFO_BITS = 3; -reg [7:0] ps2_fifo [(2**PS2_FIFO_BITS)-1:0]; -reg [PS2_FIFO_BITS-1:0] ps2_wptr; -reg [PS2_FIFO_BITS-1:0] ps2_rptr; + +// keyboard +reg [7:0] ps2_kbd_fifo [(2**PS2_FIFO_BITS)-1:0]; +reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr; +reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr; // ps2 transmitter state machine -reg [3:0] ps2_tx_state; -reg [7:0] ps2_tx_byte; -reg ps2_parity; +reg [3:0] ps2_kbd_tx_state; +reg [7:0] ps2_kbd_tx_byte; +reg ps2_kbd_parity; -assign ps2_clk = clk || (ps2_tx_state == 0); +assign ps2_kbd_clk = ps2_clk || (ps2_kbd_tx_state == 0); // ps2 transmitter // Takes a byte from the FIFO and sends it in a ps2 compliant serial format. -reg ps2_r_inc; -always@(posedge clk) begin - ps2_r_inc <= 1'b0; +reg ps2_kbd_r_inc; +always@(posedge ps2_clk) begin + ps2_kbd_r_inc <= 1'b0; - if(ps2_r_inc) - ps2_rptr <= ps2_rptr + 1; + if(ps2_kbd_r_inc) + ps2_kbd_rptr <= ps2_kbd_rptr + 3'd1; // transmitter is idle? - if(ps2_tx_state == 0) begin + if(ps2_kbd_tx_state == 0) begin // data in fifo present? - if(ps2_wptr != ps2_rptr) begin + if(ps2_kbd_wptr != ps2_kbd_rptr) begin // load tx register from fifo - ps2_tx_byte <= ps2_fifo[ps2_rptr]; - ps2_r_inc <= 1'b1; + ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr]; + ps2_kbd_r_inc <= 1'b1; // reset parity - ps2_parity <= 1'b1; + ps2_kbd_parity <= 1'b1; // start transmitter - ps2_tx_state <= 4'd1; + ps2_kbd_tx_state <= 4'd1; // put start bit on data line - ps2_data <= 1'b0; // start bit is 0 + ps2_kbd_data <= 1'b0; // start bit is 0 end end else begin // transmission of 8 data bits - if((ps2_tx_state >= 1)&&(ps2_tx_state < 9)) begin - ps2_data <= ps2_tx_byte[0]; // data bits - ps2_tx_byte[6:0] <= ps2_tx_byte[7:1]; // shift down - if(ps2_tx_byte[0]) - ps2_parity <= !ps2_parity; + if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin + ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits + ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down + if(ps2_kbd_tx_byte[0]) + ps2_kbd_parity <= !ps2_kbd_parity; end // transmission of parity - if(ps2_tx_state == 9) - ps2_data <= ps2_parity; + if(ps2_kbd_tx_state == 9) + ps2_kbd_data <= ps2_kbd_parity; // transmission of stop bit - if(ps2_tx_state == 10) - ps2_data <= 1'b1; // stop bit is 1 + if(ps2_kbd_tx_state == 10) + ps2_kbd_data <= 1'b1; // stop bit is 1 // advance state machine - if(ps2_tx_state < 11) - ps2_tx_state <= ps2_tx_state + 4'd1; + if(ps2_kbd_tx_state < 11) + ps2_kbd_tx_state <= ps2_kbd_tx_state + 4'd1; else - ps2_tx_state <= 4'd0; + ps2_kbd_tx_state <= 4'd0; + + end +end + +// mouse +reg [7:0] ps2_mouse_fifo [(2**PS2_FIFO_BITS)-1:0]; +reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr; +reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr; + +// ps2 transmitter state machine +reg [3:0] ps2_mouse_tx_state; +reg [7:0] ps2_mouse_tx_byte; +reg ps2_mouse_parity; + +assign ps2_mouse_clk = ps2_clk || (ps2_mouse_tx_state == 0); + +// ps2 transmitter +// Takes a byte from the FIFO and sends it in a ps2 compliant serial format. +reg ps2_mouse_r_inc; +always@(posedge ps2_clk) begin + ps2_mouse_r_inc <= 1'b0; + + if(ps2_mouse_r_inc) + ps2_mouse_rptr <= ps2_mouse_rptr + 3'd1; + + // transmitter is idle? + if(ps2_mouse_tx_state == 0) begin + // data in fifo present? + if(ps2_mouse_wptr != ps2_mouse_rptr) begin + // load tx register from fifo + ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr]; + ps2_mouse_r_inc <= 1'b1; + + // reset parity + ps2_mouse_parity <= 1'b1; + + // start transmitter + ps2_mouse_tx_state <= 4'd1; + + // put start bit on data line + ps2_mouse_data <= 1'b0; // start bit is 0 + end + end else begin + + // transmission of 8 data bits + if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin + ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits + ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down + if(ps2_mouse_tx_byte[0]) + ps2_mouse_parity <= !ps2_mouse_parity; + end + + // transmission of parity + if(ps2_mouse_tx_state == 9) + ps2_mouse_data <= ps2_mouse_parity; + + // transmission of stop bit + if(ps2_mouse_tx_state == 10) + ps2_mouse_data <= 1'b1; // stop bit is 1 + + // advance state machine + if(ps2_mouse_tx_state < 11) + ps2_mouse_tx_state <= ps2_mouse_tx_state + 4'd1; + else + ps2_mouse_tx_state <= 4'd0; end end -// SPI receiver -always@(posedge SPI_CLK or posedge SPI_SS_IO) begin +// fifo to receive serial data from core to be forwarded to io controller - if(SPI_SS_IO == 1) begin +// 16 byte fifo to store serial bytes +localparam SERIAL_OUT_FIFO_BITS = 6; +reg [7:0] serial_out_fifo [(2**SERIAL_OUT_FIFO_BITS)-1:0]; +reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_wptr; +reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_rptr; + +wire serial_out_data_available = serial_out_wptr != serial_out_rptr; +wire [7:0] serial_out_byte = serial_out_fifo[serial_out_rptr] /* synthesis keep */; +wire [7:0] serial_out_status = { 7'b1000000, serial_out_data_available}; + +// status[0] is reset signal from io controller and is thus used to flush +// the fifo +always @(posedge serial_strobe or posedge status[0]) begin + if(status[0] == 1) begin + serial_out_wptr <= 0; + end else begin + serial_out_fifo[serial_out_wptr] <= serial_data; + serial_out_wptr <= serial_out_wptr + 6'd1; + end +end + +always@(negedge SPI_SCK or posedge status[0]) begin + if(status[0] == 1) begin + serial_out_rptr <= 0; + end else begin + if((byte_cnt != 0) && (cmd == 8'h1b)) begin + // read last bit -> advance read pointer + if((bit_cnt == 7) && !byte_cnt[0] && serial_out_data_available) + serial_out_rptr <= serial_out_rptr + 6'd1; + end + end +end + +// SPI receiver +always@(posedge SPI_SCK or posedge CONF_DATA0) begin + + if(CONF_DATA0 == 1) begin bit_cnt <= 3'd0; byte_cnt <= 8'd0; + sd_ack <= 1'b0; + sd_dout_strobe <= 1'b0; + sd_din_strobe <= 1'b0; end else begin - sbuf[6:0] <= { sbuf[5:0], SPI_MOSI }; + sd_dout_strobe <= 1'b0; + sd_din_strobe <= 1'b0; + + sbuf <= dout[6:0]; bit_cnt <= bit_cnt + 3'd1; - if(bit_cnt == 7) byte_cnt <= byte_cnt + 8'd1; // finished reading command byte if(bit_cnt == 7) begin - if(byte_cnt == 0) - cmd <= { sbuf, SPI_MOSI}; + if(byte_cnt != 8'd255) byte_cnt <= byte_cnt + 8'd1; + if(byte_cnt == 0) begin + cmd <= dout; + + // fetch first byte when sectore FPGA->IO command has been seen + if(dout == 8'h18) + sd_din_strobe <= 1'b1; + + if((dout == 8'h17) || (dout == 8'h18)) + sd_ack <= 1'b1; - if(byte_cnt != 0) begin - if(cmd == 8'h01) - but_sw <= { sbuf[3:0], SPI_MOSI }; + mount_strobe <= 1'b0; + + end else begin + + case(cmd) + // buttons and switches + 8'h01: but_sw <= dout; + 8'h02: joystick_0 <= dout; + 8'h03: joystick_1 <= dout; - if(cmd == 8'h02) - joystick0 <= { sbuf, SPI_MOSI }; - - if(cmd == 8'h03) - joystick1 <= { sbuf, SPI_MOSI }; - - if(cmd == 8'h05) begin - // store incoming keyboard bytes in - ps2_fifo[ps2_wptr] <= { sbuf, SPI_MOSI }; - ps2_wptr <= ps2_wptr + 1; - end + // store incoming ps2 mouse bytes + 8'h04: begin + ps2_mouse_fifo[ps2_mouse_wptr] <= dout; + ps2_mouse_wptr <= ps2_mouse_wptr + 3'd1; + end + + // store incoming ps2 keyboard bytes + 8'h05: begin + ps2_kbd_fifo[ps2_kbd_wptr] <= dout; + ps2_kbd_wptr <= ps2_kbd_wptr + 3'd1; + end - if(cmd == 8'h15) begin - status <= { sbuf[4:0], SPI_MOSI }; - end + 8'h15: status <= dout; + + // send SD config IO -> FPGA + // flag that download begins + // sd card knows data is config if sd_dout_strobe is asserted + // with sd_ack still being inactive (low) + 8'h19, + // send sector IO -> FPGA + // flag that download begins + 8'h17: begin + sd_dout <= dout; + sd_dout_strobe <= 1'b1; + end + + // send sector FPGA -> IO + 8'h18: sd_din_strobe <= 1'b1; + + // joystick analog + 8'h1a: begin + // first byte is joystick index + if(byte_cnt == 1) stick_idx <= dout[2:0]; + else if(byte_cnt == 2) begin + // second byte is x axis + if(stick_idx == 0) joystick_analog_0[15:8] <= dout; + else if(stick_idx == 1) joystick_analog_1[15:8] <= dout; + end else if(byte_cnt == 3) begin + // third byte is y axis + if(stick_idx == 0) joystick_analog_0[7:0] <= dout; + else if(stick_idx == 1) joystick_analog_1[7:0] <= dout; + end + end + + // notify image selection + 8'h1c: mount_strobe <= 1'b1; + + default: ; + endcase end end end diff --git a/cores/nes/nes.qsf b/cores/nes/nes.qsf index 306bc79..ebdc399 100644 --- a/cores/nes/nes.qsf +++ b/cores/nes/nes.qsf @@ -1,305 +1,307 @@ -# Copyright (C) 1991-2007 Altera Corporation -# Your use of Altera Corporation's design tools, logic functions -# and other software and tools, and its AMPP partner logic -# functions, and any output files from any of the foregoing -# (including device programming or simulation files), and any -# associated documentation or information are expressly subject -# to the terms and conditions of the Altera Program License -# Subscription Agreement, Altera MegaCore Function License -# Agreement, or other applicable license agreement, including, -# without limitation, that your use is for the sole purpose of -# programming logic devices manufactured by Altera and sold by -# Altera or its authorized distributors. Please refer to the -# applicable agreement for further details. - - -# If this file doesn't exist, and for assignments not listed, see file -# assignment_defaults.qdf - -# Altera recommends that you do not modify this file. This -# file is updated automatically by the Quartus II software -# and any changes you make may be lost or overwritten. - - -set_global_assignment -name FAMILY "Cyclone III" -set_global_assignment -name DEVICE EP3C25E144C8 -set_global_assignment -name TOP_LEVEL_ENTITY NES_mist -set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2 -set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:27:29 OCTOBER 30, 2007" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 -set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace -set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 -set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" -set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" -set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF -set_global_assignment -name FITTER_EFFORT "FAST FIT" -set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4 -set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" -set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" -set_global_assignment -name GENERATE_RBF_FILE ON -set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON -set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" - -set_location_assignment PIN_7 -to LED -set_location_assignment PIN_22 -to CLOCK_50[0] -set_location_assignment PIN_23 -to CLOCK_50[1] -set_location_assignment PIN_128 -to CLOCK_32[0] -set_location_assignment PIN_129 -to CLOCK_32[1] -set_location_assignment PIN_54 -to CLOCK_27[0] -set_location_assignment PIN_55 -to CLOCK_27[1] -set_location_assignment PIN_144 -to VGA_R[5] -set_location_assignment PIN_143 -to VGA_R[4] -set_location_assignment PIN_142 -to VGA_R[3] -set_location_assignment PIN_141 -to VGA_R[2] -set_location_assignment PIN_137 -to VGA_R[1] -set_location_assignment PIN_135 -to VGA_R[0] -set_location_assignment PIN_133 -to VGA_B[5] -set_location_assignment PIN_132 -to VGA_B[4] -set_location_assignment PIN_125 -to VGA_B[3] -set_location_assignment PIN_121 -to VGA_B[2] -set_location_assignment PIN_120 -to VGA_B[1] -set_location_assignment PIN_115 -to VGA_B[0] -set_location_assignment PIN_114 -to VGA_G[5] -set_location_assignment PIN_113 -to VGA_G[4] -set_location_assignment PIN_112 -to VGA_G[3] -set_location_assignment PIN_111 -to VGA_G[2] -set_location_assignment PIN_110 -to VGA_G[1] -set_location_assignment PIN_106 -to VGA_G[0] -set_location_assignment PIN_136 -to VGA_VS -set_location_assignment PIN_119 -to VGA_HS -set_location_assignment PIN_65 -to AUDIO_L -set_location_assignment PIN_80 -to AUDIO_R -set_location_assignment PIN_46 -to UART_TX -set_location_assignment PIN_31 -to UART_RX -set_location_assignment PIN_105 -to SPI_DO -set_location_assignment PIN_88 -to SPI_DI -set_location_assignment PIN_126 -to SPI_SCK -set_location_assignment PIN_127 -to SPI_SS2 -set_location_assignment PIN_91 -to SPI_SS3 -set_location_assignment PIN_90 -to SPI_SS4 -set_location_assignment PIN_13 -to CONF_DATA0 - -set_location_assignment PIN_49 -to SDRAM_A[0] -set_location_assignment PIN_44 -to SDRAM_A[1] -set_location_assignment PIN_42 -to SDRAM_A[2] -set_location_assignment PIN_39 -to SDRAM_A[3] -set_location_assignment PIN_4 -to SDRAM_A[4] -set_location_assignment PIN_6 -to SDRAM_A[5] -set_location_assignment PIN_8 -to SDRAM_A[6] -set_location_assignment PIN_10 -to SDRAM_A[7] -set_location_assignment PIN_11 -to SDRAM_A[8] -set_location_assignment PIN_28 -to SDRAM_A[9] -set_location_assignment PIN_50 -to SDRAM_A[10] -set_location_assignment PIN_30 -to SDRAM_A[11] -set_location_assignment PIN_32 -to SDRAM_A[12] -set_location_assignment PIN_83 -to SDRAM_DQ[0] -set_location_assignment PIN_79 -to SDRAM_DQ[1] -set_location_assignment PIN_77 -to SDRAM_DQ[2] -set_location_assignment PIN_76 -to SDRAM_DQ[3] -set_location_assignment PIN_72 -to SDRAM_DQ[4] -set_location_assignment PIN_71 -to SDRAM_DQ[5] -set_location_assignment PIN_69 -to SDRAM_DQ[6] -set_location_assignment PIN_68 -to SDRAM_DQ[7] -set_location_assignment PIN_86 -to SDRAM_DQ[8] -set_location_assignment PIN_87 -to SDRAM_DQ[9] -set_location_assignment PIN_98 -to SDRAM_DQ[10] -set_location_assignment PIN_99 -to SDRAM_DQ[11] -set_location_assignment PIN_100 -to SDRAM_DQ[12] -set_location_assignment PIN_101 -to SDRAM_DQ[13] -set_location_assignment PIN_103 -to SDRAM_DQ[14] -set_location_assignment PIN_104 -to SDRAM_DQ[15] -set_location_assignment PIN_58 -to SDRAM_BA[0] -set_location_assignment PIN_51 -to SDRAM_BA[1] -set_location_assignment PIN_85 -to SDRAM_DQMH -set_location_assignment PIN_67 -to SDRAM_DQML -set_location_assignment PIN_60 -to SDRAM_nRAS -set_location_assignment PIN_64 -to SDRAM_nCAS -set_location_assignment PIN_66 -to SDRAM_nWE -set_location_assignment PIN_59 -to SDRAM_nCS -set_location_assignment PIN_33 -to SDRAM_CKE -set_location_assignment PIN_43 -to SDRAM_CLK - -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED -set_global_assignment -name SMART_RECOMPILE ON -set_global_assignment -name ENABLE_SIGNALTAP OFF -set_global_assignment -name USE_SIGNALTAP_FILE mist/stp.stp -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON -set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL -set_global_assignment -name FMAX_REQUIREMENT "114 MHz" -set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF -set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 -set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 -set_global_assignment -name USE_CONFIGURATION_DEVICE ON -set_global_assignment -name TPD_REQUIREMENT "2 ns" -set_global_assignment -name TSU_REQUIREMENT "2 ns" -set_global_assignment -name TCO_REQUIREMENT "2 ns" -set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF -set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF -set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION OFF -set_global_assignment -name AUTO_RAM_RECOGNITION ON -set_global_assignment -name AUTO_ROM_RECOGNITION ON -set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON - -set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON -set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF -set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF - -set_global_assignment -name PROJECT_OUTPUT_DIRECTORY out -set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 4.0 -set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 4.0 -set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY OFF - -set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF -set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise -set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise -set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall - - - - - - -set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" -set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" -set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top -set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top -set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[0] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[1] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[2] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[3] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[4] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[5] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[6] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[7] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[8] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[9] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[10] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[11] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[12] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[13] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[14] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[15] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[0] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[1] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[2] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[3] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[4] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[5] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[6] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[7] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[8] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[9] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[10] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[11] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[12] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1] -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE -set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS -set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[0] -set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[1] -set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[2] -set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[3] -set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[4] -set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[5] -set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[6] -set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[7] -set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[8] -set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[9] -set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[10] -set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[11] -set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12] -set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13] -set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14] -set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15] -set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[0] -set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[1] -set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[2] -set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[3] -set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[4] -set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[5] -set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[6] -set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[7] -set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[8] -set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[9] -set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[10] -set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[11] -set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[12] -set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[13] -set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[14] -set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[15] -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk_8 -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk_128 -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to SDRAM_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to SPI_SCK -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[0] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[1] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[2] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[3] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[4] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[5] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[6] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[7] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[8] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[9] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[10] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[11] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[12] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[0] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[1] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[2] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[3] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[4] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[5] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[6] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[7] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[8] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[9] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[10] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[11] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[12] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[13] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[14] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[15] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[0] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[1] -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQML -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQMH -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nRAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCAS -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nWE -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCS -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CKE -set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CLK -set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk_32 -set_global_assignment -name VERILOG_FILE mist/sigma_delta_dac.v -set_global_assignment -name VERILOG_FILE mist/data_io.v -set_global_assignment -name VERILOG_FILE mist/sdram.v -set_global_assignment -name VERILOG_FILE mist/user_io.v -set_global_assignment -name VERILOG_FILE mist/osd.v -set_global_assignment -name QIP_FILE mist/clk.qip -set_global_assignment -name VERILOG_FILE src/compat.v -set_global_assignment -name VERILOG_FILE src/ppu.v -set_global_assignment -name VERILOG_FILE src/mmu.v -set_global_assignment -name VERILOG_FILE src/cpu.v -set_global_assignment -name VERILOG_FILE src/vga.v -set_global_assignment -name VERILOG_FILE mist/NES_mist.v -set_global_assignment -name VERILOG_FILE src/nes.v -set_global_assignment -name VERILOG_FILE src/MicroCode.v -set_global_assignment -name VERILOG_FILE src/hq2x.v -set_global_assignment -name VERILOG_FILE src/dsp.v -set_global_assignment -name VERILOG_FILE src/apu.v -set_global_assignment -name SIGNALTAP_FILE mist/stp.stp +# Copyright (C) 1991-2007 Altera Corporation +# Your use of Altera Corporation's design tools, logic functions +# and other software and tools, and its AMPP partner logic +# functions, and any output files from any of the foregoing +# (including device programming or simulation files), and any +# associated documentation or information are expressly subject +# to the terms and conditions of the Altera Program License +# Subscription Agreement, Altera MegaCore Function License +# Agreement, or other applicable license agreement, including, +# without limitation, that your use is for the sole purpose of +# programming logic devices manufactured by Altera and sold by +# Altera or its authorized distributors. Please refer to the +# applicable agreement for further details. + + +# If this file doesn't exist, and for assignments not listed, see file +# assignment_defaults.qdf + +# Altera recommends that you do not modify this file. This +# file is updated automatically by the Quartus II software +# and any changes you make may be lost or overwritten. + + +set_global_assignment -name FAMILY "Cyclone III" +set_global_assignment -name DEVICE EP3C25E144C8 +set_global_assignment -name TOP_LEVEL_ENTITY NES_mist +set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2 +set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:27:29 OCTOBER 30, 2007" +set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace +set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 +set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" +set_global_assignment -name POWER_BOARD_THERMAL_MODEL "NONE (CONSERVATIVE)" +set_global_assignment -name OPTIMIZE_HOLD_TIMING OFF +set_global_assignment -name FITTER_EFFORT "FAST FIT" +set_global_assignment -name STRATIX_CONFIGURATION_DEVICE EPCS4 +set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_ASDO_AFTER_CONFIGURATION "AS INPUT TRI-STATED" +set_global_assignment -name CYCLONEIII_CONFIGURATION_SCHEME "PASSIVE SERIAL" +set_global_assignment -name GENERATE_RBF_FILE ON +set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON +set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" + +set_location_assignment PIN_7 -to LED +set_location_assignment PIN_22 -to CLOCK_50[0] +set_location_assignment PIN_23 -to CLOCK_50[1] +set_location_assignment PIN_128 -to CLOCK_32[0] +set_location_assignment PIN_129 -to CLOCK_32[1] +set_location_assignment PIN_54 -to CLOCK_27[0] +set_location_assignment PIN_55 -to CLOCK_27[1] +set_location_assignment PIN_144 -to VGA_R[5] +set_location_assignment PIN_143 -to VGA_R[4] +set_location_assignment PIN_142 -to VGA_R[3] +set_location_assignment PIN_141 -to VGA_R[2] +set_location_assignment PIN_137 -to VGA_R[1] +set_location_assignment PIN_135 -to VGA_R[0] +set_location_assignment PIN_133 -to VGA_B[5] +set_location_assignment PIN_132 -to VGA_B[4] +set_location_assignment PIN_125 -to VGA_B[3] +set_location_assignment PIN_121 -to VGA_B[2] +set_location_assignment PIN_120 -to VGA_B[1] +set_location_assignment PIN_115 -to VGA_B[0] +set_location_assignment PIN_114 -to VGA_G[5] +set_location_assignment PIN_113 -to VGA_G[4] +set_location_assignment PIN_112 -to VGA_G[3] +set_location_assignment PIN_111 -to VGA_G[2] +set_location_assignment PIN_110 -to VGA_G[1] +set_location_assignment PIN_106 -to VGA_G[0] +set_location_assignment PIN_136 -to VGA_VS +set_location_assignment PIN_119 -to VGA_HS +set_location_assignment PIN_65 -to AUDIO_L +set_location_assignment PIN_80 -to AUDIO_R +set_location_assignment PIN_46 -to UART_TX +set_location_assignment PIN_31 -to UART_RX +set_location_assignment PIN_105 -to SPI_DO +set_location_assignment PIN_88 -to SPI_DI +set_location_assignment PIN_126 -to SPI_SCK +set_location_assignment PIN_127 -to SPI_SS2 +set_location_assignment PIN_91 -to SPI_SS3 +set_location_assignment PIN_90 -to SPI_SS4 +set_location_assignment PIN_13 -to CONF_DATA0 + +set_location_assignment PIN_49 -to SDRAM_A[0] +set_location_assignment PIN_44 -to SDRAM_A[1] +set_location_assignment PIN_42 -to SDRAM_A[2] +set_location_assignment PIN_39 -to SDRAM_A[3] +set_location_assignment PIN_4 -to SDRAM_A[4] +set_location_assignment PIN_6 -to SDRAM_A[5] +set_location_assignment PIN_8 -to SDRAM_A[6] +set_location_assignment PIN_10 -to SDRAM_A[7] +set_location_assignment PIN_11 -to SDRAM_A[8] +set_location_assignment PIN_28 -to SDRAM_A[9] +set_location_assignment PIN_50 -to SDRAM_A[10] +set_location_assignment PIN_30 -to SDRAM_A[11] +set_location_assignment PIN_32 -to SDRAM_A[12] +set_location_assignment PIN_83 -to SDRAM_DQ[0] +set_location_assignment PIN_79 -to SDRAM_DQ[1] +set_location_assignment PIN_77 -to SDRAM_DQ[2] +set_location_assignment PIN_76 -to SDRAM_DQ[3] +set_location_assignment PIN_72 -to SDRAM_DQ[4] +set_location_assignment PIN_71 -to SDRAM_DQ[5] +set_location_assignment PIN_69 -to SDRAM_DQ[6] +set_location_assignment PIN_68 -to SDRAM_DQ[7] +set_location_assignment PIN_86 -to SDRAM_DQ[8] +set_location_assignment PIN_87 -to SDRAM_DQ[9] +set_location_assignment PIN_98 -to SDRAM_DQ[10] +set_location_assignment PIN_99 -to SDRAM_DQ[11] +set_location_assignment PIN_100 -to SDRAM_DQ[12] +set_location_assignment PIN_101 -to SDRAM_DQ[13] +set_location_assignment PIN_103 -to SDRAM_DQ[14] +set_location_assignment PIN_104 -to SDRAM_DQ[15] +set_location_assignment PIN_58 -to SDRAM_BA[0] +set_location_assignment PIN_51 -to SDRAM_BA[1] +set_location_assignment PIN_85 -to SDRAM_DQMH +set_location_assignment PIN_67 -to SDRAM_DQML +set_location_assignment PIN_60 -to SDRAM_nRAS +set_location_assignment PIN_64 -to SDRAM_nCAS +set_location_assignment PIN_66 -to SDRAM_nWE +set_location_assignment PIN_59 -to SDRAM_nCS +set_location_assignment PIN_33 -to SDRAM_CKE +set_location_assignment PIN_43 -to SDRAM_CLK + +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED +set_global_assignment -name SMART_RECOMPILE ON +set_global_assignment -name ENABLE_SIGNALTAP OFF +set_global_assignment -name USE_SIGNALTAP_FILE mist/stp.stp +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL +set_global_assignment -name FMAX_REQUIREMENT "114 MHz" +set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING OFF +set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 +set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 +set_global_assignment -name USE_CONFIGURATION_DEVICE ON +set_global_assignment -name TPD_REQUIREMENT "2 ns" +set_global_assignment -name TSU_REQUIREMENT "2 ns" +set_global_assignment -name TCO_REQUIREMENT "2 ns" +set_global_assignment -name ALLOW_POWER_UP_DONT_CARE OFF +set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS OFF +set_global_assignment -name AUTO_RAM_TO_LCELL_CONVERSION OFF +set_global_assignment -name AUTO_RAM_RECOGNITION ON +set_global_assignment -name AUTO_ROM_RECOGNITION ON +set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON + +set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON +set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA OFF +set_global_assignment -name PHYSICAL_SYNTHESIS_MAP_LOGIC_TO_MEMORY_FOR_AREA OFF + +set_global_assignment -name PROJECT_OUTPUT_DIRECTORY out +set_global_assignment -name PLACEMENT_EFFORT_MULTIPLIER 4.0 +set_global_assignment -name ROUTER_EFFORT_MULTIPLIER 4.0 +set_global_assignment -name CYCLONEII_M4K_COMPATIBILITY OFF + +set_global_assignment -name CRC_ERROR_OPEN_DRAIN OFF +set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO" +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -rise +set_global_assignment -name OUTPUT_IO_TIMING_NEAR_END_VMEAS "HALF VCCIO" -fall +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -rise +set_global_assignment -name OUTPUT_IO_TIMING_FAR_END_VMEAS "HALF SIGNAL SWING" -fall + + + + + + +set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region" +set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region" +set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top +set_global_assignment -name PARTITION_COLOR 2147039 -section_id Top +set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[0] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[1] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[2] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[3] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[4] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[5] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[6] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[7] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[8] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[9] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[10] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[11] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[12] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[13] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[14] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQ[15] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[0] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[1] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[2] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[3] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[4] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[5] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[6] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[7] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[8] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[9] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[10] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[11] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_A[12] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[0] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_BA[1] +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQMH +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_DQML +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nRAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCAS +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nWE +set_instance_assignment -name FAST_OUTPUT_REGISTER ON -to SDRAM_nCS +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[0] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[1] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[2] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[3] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[4] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[5] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[6] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[7] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[8] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[9] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[10] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[11] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[12] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[13] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[14] +set_instance_assignment -name FAST_OUTPUT_ENABLE_REGISTER ON -to SDRAM_DQ[15] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[0] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[1] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[2] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[3] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[4] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[5] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[6] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[7] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[8] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[9] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[10] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[11] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[12] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[13] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[14] +set_instance_assignment -name FAST_INPUT_REGISTER ON -to SDRAM_DQ[15] +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk_8 +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk_128 +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to SDRAM_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to SPI_SCK +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_A[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[2] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[3] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[4] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[5] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[6] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[7] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[8] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[9] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[10] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[11] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[12] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[13] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[14] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQ[15] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[0] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_BA[1] +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQML +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_DQMH +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nRAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCAS +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nWE +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_nCS +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CKE +set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to SDRAM_CLK +set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk_32 +set_global_assignment -name VERILOG_FILE mist/ps2_intf.v +set_global_assignment -name VERILOG_FILE mist/keyboard.v +set_global_assignment -name VERILOG_FILE mist/sigma_delta_dac.v +set_global_assignment -name VERILOG_FILE mist/data_io.v +set_global_assignment -name VERILOG_FILE mist/sdram.v +set_global_assignment -name VERILOG_FILE mist/user_io.v +set_global_assignment -name VERILOG_FILE mist/osd.v +set_global_assignment -name QIP_FILE mist/clk.qip +set_global_assignment -name VERILOG_FILE src/compat.v +set_global_assignment -name VERILOG_FILE src/ppu.v +set_global_assignment -name VERILOG_FILE src/mmu.v +set_global_assignment -name VERILOG_FILE src/cpu.v +set_global_assignment -name VERILOG_FILE src/vga.v +set_global_assignment -name VERILOG_FILE mist/NES_mist.v +set_global_assignment -name VERILOG_FILE src/nes.v +set_global_assignment -name VERILOG_FILE src/MicroCode.v +set_global_assignment -name VERILOG_FILE src/hq2x.v +set_global_assignment -name VERILOG_FILE src/dsp.v +set_global_assignment -name VERILOG_FILE src/apu.v +set_global_assignment -name SIGNALTAP_FILE mist/stp.stp set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file