diff --git a/cores/mist/data_io.v b/cores/mist/data_io.v
index a7a0aee..a3759cc 100644
--- a/cores/mist/data_io.v
+++ b/cores/mist/data_io.v
@@ -48,9 +48,9 @@ assign addr = addrR[22:0] - ((cmd == 2)?23'b1:23'b0);
 always @(posedge clk_8) begin
 	// start io transfers clock cycles after bus_cycle 0 
         // (after the cpu cycle)
-	writeD <= write && ((bus_cycle == 0) || writeD);
+	writeD <= write && ((bus_cycle == 3) || writeD);
 	writeD2 <= writeD;
-	readD <= read && ((bus_cycle == 0) || readD);
+	readD <= read && ((bus_cycle == 3) || readD);
 	readD2 <= readD;
 
 	if(reset)
diff --git a/cores/mist/dma.v b/cores/mist/dma.v
index a8a2d3a..bc1204e 100644
--- a/cores/mist/dma.v
+++ b/cores/mist/dma.v
@@ -104,7 +104,7 @@ assign dma_status = { 14'd0, !(scnt == 0), 1'b1 };   // bit 0 = 1: DMA_OK
 reg [15:0] motor_on;
 
 always @(sel, rw, addr, mode, base, fdc_data, fdc_sector, fdc_status, fdc_track,
-	dma_status, scnt, acsi_target) begin
+	dma_status, scnt, acsi_target, acsi_busy) begin
 	dout = 16'h0000;
 
 	if(sel && rw) begin
@@ -123,7 +123,8 @@ always @(sel, rw, addr, mode, base, fdc_data, fdc_sector, fdc_status, fdc_track,
 			end
 			if(mode[3] == 1'b1) begin
 				// acsi status register  [3]==1 -> BUSY
-				dout = { 8'h00, acsi_target, 5'h00 }; // status "ok"
+//				dout = { 8'h00, acsi_target, 1'b0, acsi_busy, 3'h0 }; // status "ok"
+				dout = { 8'h00, 3'b000, 1'b0, acsi_busy, 3'h0 }; // status "ok"
 			end
 		end
 
diff --git a/cores/mist/mist_top.v b/cores/mist/mist_top.v
index f1703c7..69df83e 100644
--- a/cores/mist/mist_top.v
+++ b/cores/mist/mist_top.v
@@ -114,12 +114,14 @@ end
 		
 // no tristate busses exist inside the FPGA. so bus request doesn't do
 // much more than halting the cpu by suppressing dtack
-wire br = dma_br;   // dma is only other bus master (yet)
+wire br = dma_br && (tg68_cpustate[1:0] == 2'b00) ;   // dma is only other bus master (yet)
 wire dma_br;
 
+// dma_br may come at any time. Make sure the real br comes not before the end 
+// of the instruction
+
 // request interrupt ack from mfp for IPL == 6
-wire mfp_iack;
-assign mfp_iack = cpu_cycle && cpu2iack && address_strobe && (tg68_adr[3:1] == 3'b110);
+wire mfp_iack = cpu_cycle && cpu2iack && address_strobe && (tg68_adr[3:1] == 3'b110);
 
 // the tg68k core with the wrapper of the minimig doesn't support non-autovector
 // interrupts. Also the existing support for them inside the tg68 kernel is/was broken.
@@ -434,7 +436,7 @@ wire           tg68_cpuena;
 // wire [  2-1:0] cpu_config;
 // wire [  6-1:0] memcfg;
 wire [ 32-1:0] tg68_cad;
-wire [  6-1:0] tg68_cpustate;
+wire [  6-1:0] tg68_cpustate /* synthesis noprune */;
 wire           tg68_cdma;
 wire           tg68_clds;
 wire           tg68_cuds;
@@ -589,10 +591,9 @@ wire cpu2iack = (tg68_adr[23:4] == 20'hfffff);
 reg address_strobe;
 always @(posedge clk_8)
 //	address_strobe <= (video_cycle) && (~tg68_lds || ~tg68_uds);
-	address_strobe <= video_cycle && ~tg68_as;
+	address_strobe <= video_cycle && ~tg68_as && !br;
 
 // generate dtack (for st ram only and rom), TODO: no dtack for rom write
-// assign tg68_dtack = ~(((cpu2mem && address_strobe && cpu_cycle) || io_dtack ) && !br);
 assign tg68_dtack = ~(((cpu2mem && address_strobe) || io_dtack ) && !br);
 
 wire ram_oe = video_cycle?~video_read: