From bb0141b3a83d5c9518d6acff9d647611c701503b Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi Date: Tue, 5 Mar 2019 15:57:36 +0100 Subject: [PATCH] [Archie] Silence warnings --- .../archie/fpga/mist/archimedes_mist_top.qsf | 2 -- cores/archie/fpga/mist/archimedes_mist_top.v | 4 +-- cores/archie/fpga/mist/data_io.v | 2 +- cores/archie/rtl/fdc1772.v | 20 +++++------ cores/archie/rtl/floppy.v | 36 +++++++++---------- cores/archie/rtl/ioc.v | 4 +-- cores/archie/rtl/latches.v | 2 +- cores/archie/rtl/memc.v | 12 +++++-- cores/archie/rtl/sdram/sdram_top.v | 11 +++--- 9 files changed, 47 insertions(+), 46 deletions(-) diff --git a/cores/archie/fpga/mist/archimedes_mist_top.qsf b/cores/archie/fpga/mist/archimedes_mist_top.qsf index 41fb7d2..96b2512 100644 --- a/cores/archie/fpga/mist/archimedes_mist_top.qsf +++ b/cores/archie/fpga/mist/archimedes_mist_top.qsf @@ -201,8 +201,6 @@ set_global_assignment -name VERILOG_FILE ../../rtl/ioc_irq.v set_global_assignment -name VERILOG_FILE ../../rtl/ioc.v set_global_assignment -name VERILOG_FILE ../../rtl/amber/a23_barrel_shift.v set_global_assignment -name VERILOG_FILE ../../rtl/memc_translator.v -set_global_assignment -name VERILOG_FILE ../../rtl/gdb/slgdb_debug.v -set_global_assignment -name VERILOG_FILE ../../sw/testdata/screenbox.v set_global_assignment -name VERILOG_FILE ../../rtl/vidc_fifo.v set_global_assignment -name VERILOG_FILE ../../rtl/vidc_timing.v set_global_assignment -name VERILOG_FILE ../../rtl/vidc.v diff --git a/cores/archie/fpga/mist/archimedes_mist_top.v b/cores/archie/fpga/mist/archimedes_mist_top.v index 41830bd..901d5b9 100644 --- a/cores/archie/fpga/mist/archimedes_mist_top.v +++ b/cores/archie/fpga/mist/archimedes_mist_top.v @@ -237,7 +237,7 @@ end wire [5:0] osd_r_o, osd_g_o, osd_b_o; -osd #(0,0,4) OSD ( +osd #(10'd0,10'd0,4) OSD ( .clk_sys ( clk_pix ), // spi for OSD @@ -331,7 +331,7 @@ user_io user_io( .img_size ( img_size ) ); -data_io # ( .START_ADDR(26'h40_0000) ) +data_io # ( .START_ADDR(24'h40_0000) ) DATA_IO ( .sck ( SPI_SCK ), .ss ( SPI_SS2 ), diff --git a/cores/archie/fpga/mist/data_io.v b/cores/archie/fpga/mist/data_io.v index acd48d6..c06514a 100644 --- a/cores/archie/fpga/mist/data_io.v +++ b/cores/archie/fpga/mist/data_io.v @@ -126,7 +126,7 @@ always @(posedge clk) begin end else if (spi_receiver_strobeD ^ spi_receiver_strobe) begin if(~&abyte_cnt) - abyte_cnt <= abyte_cnt + 8'd1; + abyte_cnt <= abyte_cnt + 1'd1; if(!abyte_cnt) begin acmd <= spi_byte_in; diff --git a/cores/archie/rtl/fdc1772.v b/cores/archie/rtl/fdc1772.v index 661998f..269fc83 100644 --- a/cores/archie/rtl/fdc1772.v +++ b/cores/archie/rtl/fdc1772.v @@ -75,10 +75,10 @@ reg [1:0] floppy_ready = 0; reg [1:0] floppy_wp = 1; wire floppy_present = (floppy_drive == 4'b1110)?floppy_ready[0]: - (floppy_drive == 4'b1101)?floppy_ready[1]:0; + (floppy_drive == 4'b1101)?floppy_ready[1]:1'b0; wire floppy_write_protected = (floppy_drive == 4'b1110)?floppy_wp[0]: - (floppy_drive == 4'b1101)?floppy_wp[1]:1; + (floppy_drive == 4'b1101)?floppy_wp[1]:1'b1; always @(posedge clkcpu) begin reg [1:0] img_mountedD; @@ -319,7 +319,7 @@ wire fd_track0 = (fd_track == 0); // reached full speed for 5 rotations (800ms spin-up time + 5*200ms = // 1.8sec) If the floppy is idle for 10 rotations (2 sec) then the // motor is switched off again -localparam MOTOR_IDLE_COUNTER = 10; +localparam MOTOR_IDLE_COUNTER = 4'd10; reg [3:0] motor_timeout_index; reg indexD; reg busy; @@ -406,7 +406,7 @@ always @(posedge clkcpu) begin // all type 1 commands are step commands and step_to has been set if(fd_track == step_to) begin busy <= 1'b0; // done if reached track 0 - motor_timeout_index <= MOTOR_IDLE_COUNTER - 1; + motor_timeout_index <= MOTOR_IDLE_COUNTER - 1'd1; irq_set <= 1'b1; // emit irq when command done end else begin // do the step @@ -430,7 +430,7 @@ always @(posedge clkcpu) begin if(!floppy_present) begin // no image selected -> send irq immediately busy <= 1'b0; - motor_timeout_index <= MOTOR_IDLE_COUNTER - 1; + motor_timeout_index <= MOTOR_IDLE_COUNTER - 1'd1; irq_set <= 1'b1; // emit irq when command done end else begin // read sector @@ -447,7 +447,7 @@ always @(posedge clkcpu) begin if(data_transfer_done) begin busy <= 1'b0; - motor_timeout_index <= MOTOR_IDLE_COUNTER - 1; + motor_timeout_index <= MOTOR_IDLE_COUNTER - 1'd1; irq_set <= 1'b1; // emit irq when command done end end @@ -458,7 +458,7 @@ always @(posedge clkcpu) begin if (data_transfer_done) sd_card_write <= 1; if (sd_card_done) begin busy <= 1'b0; - motor_timeout_index <= MOTOR_IDLE_COUNTER - 1; + motor_timeout_index <= MOTOR_IDLE_COUNTER - 1'd1; irq_set <= 1'b1; // emit irq when command done end end @@ -470,7 +470,7 @@ always @(posedge clkcpu) begin if(!floppy_present) begin // no image selected -> send irq immediately busy <= 1'b0; - motor_timeout_index <= MOTOR_IDLE_COUNTER - 1; + motor_timeout_index <= MOTOR_IDLE_COUNTER - 1'd1; irq_set <= 1'b1; // emit irq when command done end else begin // read address @@ -481,7 +481,7 @@ always @(posedge clkcpu) begin if(data_transfer_done) begin busy <= 1'b0; - motor_timeout_index <= MOTOR_IDLE_COUNTER - 1; + motor_timeout_index <= MOTOR_IDLE_COUNTER - 1'd1; irq_set <= 1'b1; // emit irq when command done end end @@ -692,7 +692,7 @@ localparam FDC_REG_SECTOR = 2; localparam FDC_REG_DATA = 3; // CPU register read -always @(wb_stb, wb_cyc, wb_adr, wb_we) begin +always @(*) begin wb_dat_o = 8'h00; if(wb_stb && wb_cyc && !wb_we) begin diff --git a/cores/archie/rtl/floppy.v b/cores/archie/rtl/floppy.v index a9832a2..caee1d4 100644 --- a/cores/archie/rtl/floppy.v +++ b/cores/archie/rtl/floppy.v @@ -43,19 +43,19 @@ assign sector_hdr = (sec_state == SECTOR_STATE_HDR); assign sector_data = (sec_state == SECTOR_STATE_DATA); // a standard DD floppy has a data rate of 250kBit/s and rotates at 300RPM -localparam RATE = 250000; -localparam RPM = 300; -localparam STEPBUSY = 18; // 18ms after step data can be read -localparam SPINUP = 500; // drive spins up in up to 800ms -localparam SPINDOWN = 300; // GUESSED: drive spins down in 300ms -localparam INDEX_PULSE_LEN = 5; // fd1036 data sheet says 1~8ms -localparam SECTOR_HDR_LEN = 6; // GUESSED: Sector header is 6 bytes -localparam TRACKS = 85; // max allowed track +localparam RATE = 20'd250000; +localparam RPM = 10'd300; +localparam STEPBUSY = 8'd18; // 18ms after step data can be read +localparam SPINUP = 10'd500; // drive spins up in up to 800ms +localparam SPINDOWN = 10'd300; // GUESSED: drive spins down in 300ms +localparam INDEX_PULSE_LEN = 4'd5; // fd1036 data sheet says 1~8ms +localparam SECTOR_HDR_LEN = 4'd6; // GUESSED: Sector header is 6 bytes +localparam TRACKS = 8'd85; // max allowed track // Archimedes specific values -localparam SECTOR_LEN = 1024; // Default sector size is 1k on Archie ... -localparam SPT = 5; // ... with 5 sectors per track -localparam SECTOR_BASE = 0; // number of first sector on track (archie 0, dos 1) +localparam SECTOR_LEN = 11'd1024; // Default sector size is 1k on Archie ... +localparam SPT = 4'd5; // ... with 5 sectors per track +localparam SECTOR_BASE = 4'd0; // number of first sector on track (archie 0, dos 1) // number of physical bytes per track localparam BPT = RATE*60/(8*RPM); @@ -85,7 +85,7 @@ end // ======================= track handling ========================= // ================================================================ -localparam STEP_BUSY_CLKS = (SYS_CLK/1000)*STEPBUSY; // steprate is in ms +localparam[19:0] STEP_BUSY_CLKS = (SYS_CLK/1000)*STEPBUSY; // steprate is in ms assign track = current_track; reg [6:0] current_track = 7'd0; @@ -139,7 +139,7 @@ reg [3:0] current_sector = SECTOR_BASE; always @(posedge clk) begin if (byte_clk_en) begin if(index_pulse_start) begin - sec_byte_cnt <= SECTOR_GAP_LEN-1; + sec_byte_cnt <= SECTOR_GAP_LEN-1'd1; sec_state <= SECTOR_STATE_GAP; // track starts with gap current_sector <= start_sector; // track starts with sector 1 end else begin @@ -147,17 +147,17 @@ always @(posedge clk) begin case(sec_state) SECTOR_STATE_GAP: begin sec_state <= SECTOR_STATE_HDR; - sec_byte_cnt <= SECTOR_HDR_LEN-1; + sec_byte_cnt <= SECTOR_HDR_LEN-1'd1; end SECTOR_STATE_HDR: begin sec_state <= SECTOR_STATE_DATA; - sec_byte_cnt <= SECTOR_LEN-1; + sec_byte_cnt <= SECTOR_LEN-1'd1; end SECTOR_STATE_DATA: begin sec_state <= SECTOR_STATE_GAP; - sec_byte_cnt <= SECTOR_GAP_LEN-1; + sec_byte_cnt <= SECTOR_GAP_LEN-1'd1; if(current_sector == SECTOR_BASE+SPT-1) current_sector <= SECTOR_BASE; else @@ -191,7 +191,7 @@ always @(posedge clk) begin byte_cnt <= 0; index_pulse_start <= 1'b1; end else - byte_cnt <= byte_cnt + 1; + byte_cnt <= byte_cnt + 1'd1; end end @@ -203,7 +203,7 @@ reg [2:0] clk_cnt2; always @(posedge clk) begin byte_clk_en <= 0; if (data_clk_en) begin - clk_cnt2 <= clk_cnt2 + 1; + clk_cnt2 <= clk_cnt2 + 1'd1; if (clk_cnt2 == 3'b011) byte_clk_en <= 1; end end diff --git a/cores/archie/rtl/ioc.v b/cores/archie/rtl/ioc.v index 6a12bb2..6dc8f25 100644 --- a/cores/archie/rtl/ioc.v +++ b/cores/archie/rtl/ioc.v @@ -254,8 +254,8 @@ always @(posedge clkcpu) begin end // increment the clock counters. - clk2m_count <= clk2m_count + 'd1; - clk8m_count <= clk8m_count + 'd1; + clk2m_count <= clk2m_count + 1'd1; + clk8m_count <= clk8m_count + 1'd1; if (write_request & ctrl_selected) begin diff --git a/cores/archie/rtl/latches.v b/cores/archie/rtl/latches.v index e954830..f8d46b8 100644 --- a/cores/archie/rtl/latches.v +++ b/cores/archie/rtl/latches.v @@ -99,7 +99,7 @@ assign floppy_density = ext_latch_b[1]; assign floppy_reset = ext_latch_b[3]; assign wb_dat_o = wb_adr == 14'h001e ? {3'b011, joy0} : - wb_adr == 14'h001f ? {3'b011, joy1} : 32'hFFFFFFFF; + wb_adr == 14'h001f ? {3'b011, joy1} : 8'hFF; assign baseclk = ext_latch_c[1:0]; assign syncpol = ext_latch_c[3:2]; diff --git a/cores/archie/rtl/memc.v b/cores/archie/rtl/memc.v index d53733c..ecb6180 100644 --- a/cores/archie/rtl/memc.v +++ b/cores/archie/rtl/memc.v @@ -127,6 +127,12 @@ localparam REG_SendN = 3'b101; localparam REG_Sptr = 3'b110; localparam REG_Ctrl = 3'b111; +wire table_valid; +wire err; +wire memw; +wire logcs; +wire vidc_cs; +wire mem_virtual; wire[25:0] phys_address; memc_translator PAGETABLES( @@ -332,12 +338,12 @@ always @(posedge clkcpu) begin if ((vidak & vid_load) == 1'b1) begin // advance the pointer to the next location. - vid_address <= vid_address + 4; + vid_address <= vid_address + 4'd4; end else if ((vidak & cur_load) == 1'b1) begin // advance the cursor pointer to the next location. - cur_address <= cur_address + 4; + cur_address <= cur_address + 4'd4; end @@ -358,7 +364,7 @@ always @(posedge clkcpu) begin if ((sndak & snd_load) == 1'b1) begin // advance the pointer to the next location. - snd_sptr <= snd_sptr + 4; + snd_sptr <= snd_sptr + 4'd4; end end else begin diff --git a/cores/archie/rtl/sdram/sdram_top.v b/cores/archie/rtl/sdram/sdram_top.v index 31668a3..4ffd4aa 100644 --- a/cores/archie/rtl/sdram/sdram_top.v +++ b/cores/archie/rtl/sdram/sdram_top.v @@ -79,9 +79,6 @@ reg [3:0] sd_cmd = 4'd0; // current command sent to sd ram reg [9:0] sd_refresh = 10'd0; reg sd_auto_refresh = 1'b0; -wire sd_reading; -wire sd_writing; - initial begin t = 4'd0; reset = 5'h1f; @@ -331,10 +328,10 @@ always @(posedge wb_clk) begin end -assign burst_mode = wb_cti == 3'b010; -assign can_burst = wb_adr[2] === 1'b0; -assign sd_reading = sd_stb & sd_cyc & ~sd_we; -assign sd_writing = sd_stb & sd_cyc & sd_we; +wire burst_mode = wb_cti == 3'b010; +wire can_burst = wb_adr[2] === 1'b0; +wire sd_reading = sd_stb & sd_cyc & ~sd_we; +wire sd_writing = sd_stb & sd_cyc & sd_we; // drive control signals according to current command assign sd_cs_n = sd_cmd[3];