diff --git a/cores/archie/rtl/vidc_dmachannel.v b/cores/archie/rtl/vidc_dmachannel.v
index 849e116..b684351 100644
--- a/cores/archie/rtl/vidc_dmachannel.v
+++ b/cores/archie/rtl/vidc_dmachannel.v
@@ -93,10 +93,11 @@ vidc_fifo #(.FIFO_SIZE(FIFO_SIZE)) VIDEO_FIFO(
 // DMA interface control
 // this is in the cpu clock domain. 
 always @(posedge clkcpu) begin
-
+	reg rstD, rstD2;
 	ak_r	<=	ak;
-
-	if (rst == 1'b1) begin
+	rstD <= rst;
+	rstD2 <= rstD;
+	if (rstD2 == 1'b1) begin
 	
 		// do reset logic 
 		dma_count 	<= 2'd0;	
diff --git a/cores/archie/rtl/vidc_fifo.v b/cores/archie/rtl/vidc_fifo.v
index b5c0456..1c0e92f 100644
--- a/cores/archie/rtl/vidc_fifo.v
+++ b/cores/archie/rtl/vidc_fifo.v
@@ -75,11 +75,14 @@ end
 reg [BYTE_WIDTH-1:0] rd_ptr_r;
 
 always @(posedge wr_clk) begin
+	reg rstD, rstD2;
 
 	rd_ptr_r	<= rd_ptr;
 	space 		<= {rd_ptr_r[BYTE_WIDTH-1:2]} - wr_ptr;
+	rstD <= rst;
+	rstD2 <= rstD;
 	
-	if (rst) begin
+	if (rstD2) begin
 
 		wr_ptr 	<= 'd0;
 		full   	<= 1'b0;
@@ -108,8 +111,12 @@ wire [7:0] q;
 
 always @(posedge rd_clk) begin
 
+    reg rstD, rstD2;
+
+    rstD <= rst;
+	rstD2 <= rstD;
 	if(rd_ce) begin
-		if (rst) begin
+		if (rstD2) begin
 		
 			rd_ptr <= 'd0;
 			dout <= 8'd0;