From be20434625ddc82f76de0a192c2c14c8fad1096e Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi Date: Sat, 9 Nov 2019 15:35:15 +0100 Subject: [PATCH] NES: use dedicated PLL output for SDRAM_CLK --- cores/nes/mist/NES_mist.v | 3 +- cores/nes/mist/clk.v | 82 +++++++++++----------------------- cores/nes/mist/constraints.sdc | 14 +++--- cores/nes/nes.qsf | 6 ++- 4 files changed, 40 insertions(+), 65 deletions(-) diff --git a/cores/nes/mist/NES_mist.v b/cores/nes/mist/NES_mist.v index d6309a7..b7453f1 100644 --- a/cores/nes/mist/NES_mist.v +++ b/cores/nes/mist/NES_mist.v @@ -216,7 +216,8 @@ wire [7:0] nes_joy_B = (reset_nes || osd_visible) ? 8'd0 : wire clock_locked; wire clk85; wire clk; - clk clock_21mhz(.inclk0(CLOCK_27[0]), .c0(clk85), .c1(SDRAM_CLK), .c2(clk), .locked(clock_locked)); + clk clock_21mhz(.inclk0(CLOCK_27[0]), .c0(clk85), .c1(clk), .locked(clock_locked)); + assign SDRAM_CLK = clk85; // reset after download reg [7:0] download_reset_cnt; diff --git a/cores/nes/mist/clk.v b/cores/nes/mist/clk.v index 9f2e0f0..b3ac9fd 100644 --- a/cores/nes/mist/clk.v +++ b/cores/nes/mist/clk.v @@ -14,7 +14,7 @@ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 13.1.4 Build 182 03/12/2014 SJ Web Edition +// 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition // ************************************************************ @@ -40,30 +40,26 @@ module clk ( inclk0, c0, c1, - c2, locked); input inclk0; output c0; output c1; - output c2; output locked; wire [4:0] sub_wire0; wire sub_wire2; - wire [0:0] sub_wire7 = 1'h0; - wire [2:2] sub_wire4 = sub_wire0[2:2]; + wire [0:0] sub_wire6 = 1'h0; wire [0:0] sub_wire3 = sub_wire0[0:0]; wire [1:1] sub_wire1 = sub_wire0[1:1]; wire c1 = sub_wire1; wire locked = sub_wire2; wire c0 = sub_wire3; - wire c2 = sub_wire4; - wire sub_wire5 = inclk0; - wire [1:0] sub_wire6 = {sub_wire7, sub_wire5}; + wire sub_wire4 = inclk0; + wire [1:0] sub_wire5 = {sub_wire6, sub_wire4}; altpll altpll_component ( - .inclk (sub_wire6), + .inclk (sub_wire5), .clk (sub_wire0), .locked (sub_wire2), .activeclock (), @@ -102,18 +98,14 @@ module clk ( .vcounderrange ()); defparam altpll_component.bandwidth_type = "AUTO", - altpll_component.clk0_divide_by = 2250, + altpll_component.clk0_divide_by = 11, altpll_component.clk0_duty_cycle = 50, - altpll_component.clk0_multiply_by = 7159, + altpll_component.clk0_multiply_by = 35, altpll_component.clk0_phase_shift = "0", - altpll_component.clk1_divide_by = 2250, + altpll_component.clk1_divide_by = 44, altpll_component.clk1_duty_cycle = 50, - altpll_component.clk1_multiply_by = 7159, - altpll_component.clk1_phase_shift = "-1500", - altpll_component.clk2_divide_by = 44, - altpll_component.clk2_duty_cycle = 50, - altpll_component.clk2_multiply_by = 35, - altpll_component.clk2_phase_shift = "0", + altpll_component.clk1_multiply_by = 35, + altpll_component.clk1_phase_shift = "0", altpll_component.compensate_clock = "CLK0", altpll_component.inclk0_input_frequency = 37037, altpll_component.intended_device_family = "Cyclone III", @@ -148,7 +140,7 @@ module clk ( altpll_component.port_scanwrite = "PORT_UNUSED", altpll_component.port_clk0 = "PORT_USED", altpll_component.port_clk1 = "PORT_USED", - altpll_component.port_clk2 = "PORT_USED", + altpll_component.port_clk2 = "PORT_UNUSED", altpll_component.port_clk3 = "PORT_UNUSED", altpll_component.port_clk4 = "PORT_UNUSED", altpll_component.port_clk5 = "PORT_UNUSED", @@ -187,15 +179,12 @@ endmodule // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" -// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1" -// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "44" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "11" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "44" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" // Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" -// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "85.907997" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "85.907997" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "21.477272" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "85.909088" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "21.477272" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -217,33 +206,25 @@ endmodule // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" -// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps" // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" // Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" -// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0" -// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" -// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1" -// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "35" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "35" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "35" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "85.90800000" // Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "85.90800000" -// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "100.00000000" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" -// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "0" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" -// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz" // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-1500.00000000" -// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" -// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ps" // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" @@ -267,32 +248,25 @@ endmodule // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" // Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" -// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1" // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: USE_CLK0 STRING "1" // Retrieval info: PRIVATE: USE_CLK1 STRING "1" -// Retrieval info: PRIVATE: USE_CLK2 STRING "1" // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" // Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" -// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0" // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" -// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "2250" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "11" // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "7159" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "35" // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "2250" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "44" // Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "7159" -// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-1500" -// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "44" -// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "35" -// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "35" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" @@ -326,7 +300,7 @@ endmodule // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED" +// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED" @@ -345,14 +319,12 @@ endmodule // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" // Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" -// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2" // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" // Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0 // Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 // Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 -// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 // Retrieval info: GEN_FILE: TYPE_NORMAL clk.v TRUE // Retrieval info: GEN_FILE: TYPE_NORMAL clk.ppf TRUE @@ -360,6 +332,6 @@ endmodule // Retrieval info: GEN_FILE: TYPE_NORMAL clk.cmp FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL clk.bsf FALSE // Retrieval info: GEN_FILE: TYPE_NORMAL clk_inst.v FALSE -// Retrieval info: GEN_FILE: TYPE_NORMAL clk_bb.v TRUE +// Retrieval info: GEN_FILE: TYPE_NORMAL clk_bb.v FALSE // Retrieval info: LIB_FILE: altera_mf // Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/cores/nes/mist/constraints.sdc b/cores/nes/mist/constraints.sdc index e0d6b5f..08394d9 100644 --- a/cores/nes/mist/constraints.sdc +++ b/cores/nes/mist/constraints.sdc @@ -73,11 +73,11 @@ set_input_delay -clock [get_clocks {clock_21mhz|altpll_component|auto_generated| set_output_delay -clock [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] set_output_delay -clock [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[0]}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] -set_output_delay -clock [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[1]}] -max 1.5 [get_ports SDRAM_CLK] -set_output_delay -clock [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[1]}] -min -0.8 [get_ports SDRAM_CLK] +set_output_delay -clock [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_ports SDRAM_CLK] +set_output_delay -clock [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[0]}] -min -0.8 [get_ports SDRAM_CLK] -set_output_delay -clock [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[2]}] -max 0 [get_ports {VGA_*}] -set_output_delay -clock [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[2]}] -min -5 [get_ports {VGA_*}] +set_output_delay -clock [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[1]}] -max 0 [get_ports {VGA_*}] +set_output_delay -clock [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[1]}] -min -5 [get_ports {VGA_*}] #************************************************************** # Set Clock Groups @@ -98,11 +98,11 @@ set_false_path -to [get_ports {LED}] # Set Multicycle Path #************************************************************** -set_multicycle_path -from [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[0]}] -setup 4 -set_multicycle_path -from [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[0]}] -hold 4 +set_multicycle_path -from [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[0]}] -setup 2 +set_multicycle_path -from [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {clock_21mhz|altpll_component|auto_generated|pll1|clk[0]}] -hold 1 set_multicycle_path -to {VGA_*[*]} -setup 2 -set_multicycle_path -to {VGA_*[*]} -hold 2 +set_multicycle_path -to {VGA_*[*]} -hold 1 #************************************************************** # Set Maximum Delay diff --git a/cores/nes/nes.qsf b/cores/nes/nes.qsf index d4fba6a..6ba0bf9 100644 --- a/cores/nes/nes.qsf +++ b/cores/nes/nes.qsf @@ -26,7 +26,7 @@ set_global_assignment -name DEVICE EP3C25E144C8 set_global_assignment -name TOP_LEVEL_ENTITY NES_mist set_global_assignment -name ORIGINAL_QUARTUS_VERSION 7.2 set_global_assignment -name PROJECT_CREATION_TIME_DATE "22:27:29 OCTOBER 30, 2007" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26" set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_palace set_global_assignment -name DEVICE_FILTER_PIN_COUNT 144 set_global_assignment -name POWER_PRESET_COOLING_SOLUTION "NO HEAT SINK WITH STILL AIR" @@ -310,4 +310,6 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_VS set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_R[*] set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_G[*] set_instance_assignment -name CURRENT_STRENGTH_NEW "MAXIMUM CURRENT" -to VGA_B[*] -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top + +set_location_assignment PLL_1 -to clock_21mhz|altpll_component|auto_generated|pll1 +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file