From be41c2d93652112d17e23dbf6a120fe073c792e0 Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi Date: Sun, 17 May 2020 20:00:53 +0200 Subject: [PATCH] Archie: use double clock for scandoubler 16MHz mode scandoubled doesn't look good with 3x16 MHz clock --- .../archie/fpga/mist/archimedes_mist_top.sdc | 3 + cores/archie/fpga/mist/archimedes_mist_top.v | 33 ++++---- cores/archie/fpga/mist/pll_vidc.ppf | 1 + cores/archie/fpga/mist/pll_vidc.v | 82 +++++++++++++------ cores/archie/fpga/mist/pll_vidc_24.mif | 82 +++++++++---------- cores/archie/fpga/mist/pll_vidc_25.mif | 58 ++++++------- cores/archie/fpga/mist/pll_vidc_36.mif | 16 ++-- 7 files changed, 156 insertions(+), 119 deletions(-) diff --git a/cores/archie/fpga/mist/archimedes_mist_top.sdc b/cores/archie/fpga/mist/archimedes_mist_top.sdc index d27ec51..b0ba48b 100644 --- a/cores/archie/fpga/mist/archimedes_mist_top.sdc +++ b/cores/archie/fpga/mist/archimedes_mist_top.sdc @@ -51,6 +51,7 @@ set sdram_clk "CLOCKS|altpll_component|auto_generated|pll1|clk[3]" set mem_clk "CLOCKS|altpll_component|auto_generated|pll1|clk[1]" set sys_clk "CLOCKS|altpll_component|auto_generated|pll1|clk[0]" set vidc_clk "CLOCKS_VIDC|altpll_component|auto_generated|pll1|clk[0]" +set vidc2x_clk "CLOCKS_VIDC|altpll_component|auto_generated|pll1|clk[1]" #************************************************************** # Set Clock Latency @@ -87,7 +88,9 @@ set_output_delay -clock [get_clocks $vidc_clk] -min -5 [get_ports {VGA_*}] set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks {CLOCKS|*}] set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks $vidc_clk] +set_clock_groups -asynchronous -group [get_clocks {SPI_SCK}] -group [get_clocks $vidc2x_clk] set_clock_groups -asynchronous -group [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[*]}] -group [get_clocks $vidc_clk] +set_clock_groups -asynchronous -group [get_clocks {CLOCKS|altpll_component|auto_generated|pll1|clk[*]}] -group [get_clocks $vidc2x_clk] #************************************************************** # Set False Path diff --git a/cores/archie/fpga/mist/archimedes_mist_top.v b/cores/archie/fpga/mist/archimedes_mist_top.v index 208e153..93f6fc2 100644 --- a/cores/archie/fpga/mist/archimedes_mist_top.v +++ b/cores/archie/fpga/mist/archimedes_mist_top.v @@ -67,6 +67,7 @@ wire kbd_in_strobe; // generated clocks wire clk_pix; +wire clk_vid; wire ce_pix; wire clk_sys /* synthesis keep */ ; wire clk_mem /* synthesis keep */ ; @@ -117,7 +118,8 @@ clockgen CLOCKS( pll_vidc CLOCKS_VIDC( .inclk0 (CLOCK_27[0]), - .c0 (clk_pix), + .c0 (clk_pix), // 2x VIDC pixel clock (48, 50, 76 MHz); + .c1 (clk_vid), // 4x VIDC pixel clock for scandoubler use (24MHz mode => 96 MHz), otherwise 2x pixel clock .areset(pll_areset), .scanclk(pll_scanclk), .scandata(pll_scandata), @@ -246,23 +248,26 @@ wire back_porch_n = (pixbaseclk_select[0] == pixbaseclk_select[1]) ? &pix_ always @(posedge clk_pix) begin - hs_adj <= core_hs; - vs_adj <= core_vs; - if (~back_porch_n) pix_cnt <= pix_cnt + 1'd1; if (~hs_adj) pix_cnt <= 0; - if (back_porch_n) begin - r_adj <= core_r; - g_adj <= core_g; - b_adj <= core_b; - end else - { r_adj, g_adj, b_adj } <= 12'h0; + + if (ce_pix) begin + hs_adj <= core_hs; + vs_adj <= core_vs; + + if (back_porch_n) begin + r_adj <= core_r; + g_adj <= core_g; + b_adj <= core_b; + end else + { r_adj, g_adj, b_adj } <= 12'h0; + end end wire scandoubler_en = ~scandoubler_disable && pixbaseclk_select[0] == pixbaseclk_select[1]; -mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(10)) mist_video ( - .clk_sys ( clk_pix ), +mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(12)) mist_video ( + .clk_sys ( clk_vid ), // OSD SPI interface .SPI_SCK ( SPI_SCK ), @@ -273,7 +278,7 @@ mist_video #(.COLOR_DEPTH(4), .SD_HCNT_WIDTH(10)) mist_video ( .scanlines ( 2'b00 ), // non-scandoubled pixel clock divider 0 - clk_sys/4, 1 - clk_sys/2 - .ce_divider ( 1'b0 ), + .ce_divider ( 1'b1 ), // 0 = HVSync 31KHz, 1 = CSync 15KHz .scandoubler_disable ( ~scandoubler_en ), @@ -431,7 +436,7 @@ wire reset = ~ram_ready | ~rom_ready; archimedes_top ARCHIMEDES( .CLKCPU_I ( clk_sys ), - .CLKPIX_I ( clk_pix ), // pixel clock for OSD + .CLKPIX_I ( clk_pix ), // 2xVIDC clock .CEPIX_O ( ce_pix ), .RESET_I ( reset ), diff --git a/cores/archie/fpga/mist/pll_vidc.ppf b/cores/archie/fpga/mist/pll_vidc.ppf index ce19074..f702f22 100644 --- a/cores/archie/fpga/mist/pll_vidc.ppf +++ b/cores/archie/fpga/mist/pll_vidc.ppf @@ -9,6 +9,7 @@ + diff --git a/cores/archie/fpga/mist/pll_vidc.v b/cores/archie/fpga/mist/pll_vidc.v index b985b75..4595860 100644 --- a/cores/archie/fpga/mist/pll_vidc.v +++ b/cores/archie/fpga/mist/pll_vidc.v @@ -14,7 +14,7 @@ // ************************************************************ // THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! // -// 13.1.4 Build 182 03/12/2014 SJ Web Edition +// 13.1.4 Build 182 03/12/2014 Patches 4.26 SJ Web Edition // ************************************************************ @@ -44,6 +44,7 @@ module pll_vidc ( scanclkena, scandata, c0, + c1, locked, scandataout, scandone); @@ -55,6 +56,7 @@ module pll_vidc ( input scanclkena; input scandata; output c0; + output c1; output locked; output scandataout; output scandone; @@ -70,29 +72,31 @@ module pll_vidc ( `endif wire [4:0] sub_wire0; - wire sub_wire2; wire sub_wire3; wire sub_wire4; - wire [0:0] sub_wire7 = 1'h0; - wire [0:0] sub_wire1 = sub_wire0[0:0]; - wire c0 = sub_wire1; - wire scandataout = sub_wire2; - wire scandone = sub_wire3; - wire locked = sub_wire4; - wire sub_wire5 = inclk0; - wire [1:0] sub_wire6 = {sub_wire7, sub_wire5}; + wire sub_wire5; + wire [0:0] sub_wire8 = 1'h0; + wire [0:0] sub_wire2 = sub_wire0[0:0]; + wire [1:1] sub_wire1 = sub_wire0[1:1]; + wire c1 = sub_wire1; + wire c0 = sub_wire2; + wire scandataout = sub_wire3; + wire scandone = sub_wire4; + wire locked = sub_wire5; + wire sub_wire6 = inclk0; + wire [1:0] sub_wire7 = {sub_wire8, sub_wire6}; altpll altpll_component ( .areset (areset), .configupdate (configupdate), - .inclk (sub_wire6), + .inclk (sub_wire7), .scanclk (scanclk), .scanclkena (scanclkena), .scandata (scandata), .clk (sub_wire0), - .scandataout (sub_wire2), - .scandone (sub_wire3), - .locked (sub_wire4), + .scandataout (sub_wire3), + .scandone (sub_wire4), + .locked (sub_wire5), .activeclock (), .clkbad (), .clkena ({6{1'b1}}), @@ -122,10 +126,14 @@ module pll_vidc ( .vcounderrange ()); defparam altpll_component.bandwidth_type = "LOW", - altpll_component.clk0_divide_by = 3, + altpll_component.clk0_divide_by = 9, altpll_component.clk0_duty_cycle = 50, - altpll_component.clk0_multiply_by = 8, + altpll_component.clk0_multiply_by = 16, altpll_component.clk0_phase_shift = "0", + altpll_component.clk1_divide_by = 9, + altpll_component.clk1_duty_cycle = 50, + altpll_component.clk1_multiply_by = 32, + altpll_component.clk1_phase_shift = "0", altpll_component.compensate_clock = "CLK0", altpll_component.inclk0_input_frequency = 37037, altpll_component.intended_device_family = "Cyclone III", @@ -159,7 +167,7 @@ module pll_vidc ( altpll_component.port_scanread = "PORT_UNUSED", altpll_component.port_scanwrite = "PORT_UNUSED", altpll_component.port_clk0 = "PORT_USED", - altpll_component.port_clk1 = "PORT_UNUSED", + altpll_component.port_clk1 = "PORT_USED", altpll_component.port_clk2 = "PORT_UNUSED", altpll_component.port_clk3 = "PORT_UNUSED", altpll_component.port_clk4 = "PORT_UNUSED", @@ -176,7 +184,7 @@ module pll_vidc ( altpll_component.port_extclk3 = "PORT_UNUSED", altpll_component.self_reset_on_loss_lock = "ON", altpll_component.width_clock = 5, - altpll_component.scan_chain_mif_file = "pll_vidc_36.mif"; + altpll_component.scan_chain_mif_file = "pll_vidc_24.mif"; endmodule @@ -200,9 +208,12 @@ endmodule // Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0" // Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "c0" // Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8" -// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "9" +// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9" // Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "72.000000" +// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000" +// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "96.000000" // Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" // Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" // Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -223,18 +234,26 @@ endmodule // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available" // Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0" // Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps" // Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any" // Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0" -// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1" +// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0" +// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "16" +// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "32" // Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0" -// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "72.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000" +// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "96.00000000" // Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" +// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" // Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" +// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz" // Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" +// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "0.00000000" // Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" // Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" +// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" // Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1" // Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1" @@ -245,7 +264,7 @@ endmodule // Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0" // Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0" // Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0" -// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_vidc_36.mif" +// Retrieval info: PRIVATE: RECONFIG_FILE STRING "pll_vidc_24.mif" // Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "1" // Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "1" @@ -257,19 +276,26 @@ endmodule // Retrieval info: PRIVATE: SPREAD_USE STRING "0" // Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "1" // Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" +// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1" // Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1" // Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1" // Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" // Retrieval info: PRIVATE: USE_CLK0 STRING "1" +// Retrieval info: PRIVATE: USE_CLK1 STRING "1" // Retrieval info: PRIVATE: USE_CLKENA0 STRING "0" +// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0" // Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0" // Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0" // Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all // Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "LOW" -// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "3" +// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "9" // Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" -// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "8" +// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "16" // Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" +// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "9" +// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" +// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "32" +// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0" // Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" // Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" @@ -302,7 +328,7 @@ endmodule // Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED" -// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_UNUSED" +// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED" // Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED" @@ -319,10 +345,11 @@ endmodule // Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED" // Retrieval info: CONSTANT: SELF_RESET_ON_LOSS_LOCK STRING "ON" // Retrieval info: CONSTANT: WIDTH_CLOCK NUMERIC "5" -// Retrieval info: CONSTANT: scan_chain_mif_file STRING "pll_vidc_36.mif" +// Retrieval info: CONSTANT: scan_chain_mif_file STRING "pll_vidc_24.mif" // Retrieval info: USED_PORT: @clk 0 0 5 0 OUTPUT_CLK_EXT VCC "@clk[4..0]" // Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset" // Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0" +// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1" // Retrieval info: USED_PORT: configupdate 0 0 0 0 INPUT GND "configupdate" // Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0" // Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked" @@ -339,6 +366,7 @@ endmodule // Retrieval info: CONNECT: @scanclkena 0 0 0 0 scanclkena 0 0 0 0 // Retrieval info: CONNECT: @scandata 0 0 0 0 scandata 0 0 0 0 // Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0 +// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1 // Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0 // Retrieval info: CONNECT: scandataout 0 0 0 0 @scandataout 0 0 0 0 // Retrieval info: CONNECT: scandone 0 0 0 0 @scandone 0 0 0 0 diff --git a/cores/archie/fpga/mist/pll_vidc_24.mif b/cores/archie/fpga/mist/pll_vidc_24.mif index cab0eb4..8a68abb 100644 --- a/cores/archie/fpga/mist/pll_vidc_24.mif +++ b/cores/archie/fpga/mist/pll_vidc_24.mif @@ -18,7 +18,7 @@ -- Device Speed Grade: 8 -- PLL Scan Chain: Fast PLL (144 bits) -- File Name: /home/gyuri/git/mist-board/cores/archie/fpga/mist/pll_vidc_24.mif --- Generated: Fri Feb 22 22:07:56 2019 +-- Generated: Sun May 17 18:31:26 2020 WIDTH=1; DEPTH=144; @@ -31,12 +31,12 @@ CONTENT BEGIN 1 : 0; -- Reserved Bits = 0 (1 bit(s)) 2 : 0; -- Loop Filter Capacitance = 0 (2 bit(s)) (Setting 0) 3 : 0; - 4 : 1; -- Loop Filter Resistance = 27 (5 bit(s)) (Setting 27) + 4 : 0; -- Loop Filter Resistance = 8 (5 bit(s)) (Setting 8) 5 : 1; 6 : 0; - 7 : 1; - 8 : 1; - 9 : 0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2) + 7 : 0; + 8 : 0; + 9 : 1; -- VCO Post Scale = 1 (1 bit(s)) (VCO post-scale divider counter value = 1) 10 : 0; -- Reserved Bits = 0 (5 bit(s)) 11 : 0; 12 : 0; @@ -45,77 +45,77 @@ CONTENT BEGIN 15 : 0; -- Charge Pump Current = 1 (3 bit(s)) (Setting 1) 16 : 0; 17 : 1; - 18 : 1; -- N counter: Bypass = 1 (1 bit(s)) - 19 : 0; -- N counter: High Count = 0 (8 bit(s)) + 18 : 0; -- N counter: Bypass = 0 (1 bit(s)) + 19 : 0; -- N counter: High Count = 3 (8 bit(s)) 20 : 0; 21 : 0; 22 : 0; 23 : 0; 24 : 0; - 25 : 0; - 26 : 0; - 27 : 0; -- N counter: Odd Division = 0 (1 bit(s)) - 28 : 0; -- N counter: Low Count = 0 (8 bit(s)) + 25 : 1; + 26 : 1; + 27 : 1; -- N counter: Odd Division = 1 (1 bit(s)) + 28 : 0; -- N counter: Low Count = 2 (8 bit(s)) 29 : 0; 30 : 0; 31 : 0; 32 : 0; 33 : 0; - 34 : 0; + 34 : 1; 35 : 0; 36 : 0; -- M counter: Bypass = 0 (1 bit(s)) - 37 : 0; -- M counter: High Count = 8 (8 bit(s)) - 38 : 0; - 39 : 0; - 40 : 0; - 41 : 1; - 42 : 0; + 37 : 0; -- M counter: High Count = 116 (8 bit(s)) + 38 : 1; + 39 : 1; + 40 : 1; + 41 : 0; + 42 : 1; 43 : 0; 44 : 0; - 45 : 0; -- M counter: Odd Division = 0 (1 bit(s)) - 46 : 0; -- M counter: Low Count = 8 (8 bit(s)) - 47 : 0; - 48 : 0; - 49 : 0; - 50 : 1; + 45 : 1; -- M counter: Odd Division = 1 (1 bit(s)) + 46 : 0; -- M counter: Low Count = 115 (8 bit(s)) + 47 : 1; + 48 : 1; + 49 : 1; + 50 : 0; 51 : 0; - 52 : 0; - 53 : 0; + 52 : 1; + 53 : 1; 54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s)) - 55 : 0; -- clk0 counter: High Count = 5 (8 bit(s)) + 55 : 0; -- clk0 counter: High Count = 13 (8 bit(s)) 56 : 0; 57 : 0; 58 : 0; - 59 : 0; + 59 : 1; 60 : 1; 61 : 0; 62 : 1; - 63 : 1; -- clk0 counter: Odd Division = 1 (1 bit(s)) - 64 : 0; -- clk0 counter: Low Count = 4 (8 bit(s)) + 63 : 0; -- clk0 counter: Odd Division = 0 (1 bit(s)) + 64 : 0; -- clk0 counter: Low Count = 13 (8 bit(s)) 65 : 0; 66 : 0; 67 : 0; - 68 : 0; + 68 : 1; 69 : 1; 70 : 0; - 71 : 0; - 72 : 1; -- clk1 counter: Bypass = 1 (1 bit(s)) - 73 : 0; -- clk1 counter: High Count = 0 (8 bit(s)) + 71 : 1; + 72 : 0; -- clk1 counter: Bypass = 0 (1 bit(s)) + 73 : 0; -- clk1 counter: High Count = 7 (8 bit(s)) 74 : 0; 75 : 0; 76 : 0; 77 : 0; - 78 : 0; - 79 : 0; - 80 : 0; - 81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s)) - 82 : 0; -- clk1 counter: Low Count = 0 (8 bit(s)) + 78 : 1; + 79 : 1; + 80 : 1; + 81 : 1; -- clk1 counter: Odd Division = 1 (1 bit(s)) + 82 : 0; -- clk1 counter: Low Count = 6 (8 bit(s)) 83 : 0; 84 : 0; 85 : 0; 86 : 0; - 87 : 0; - 88 : 0; + 87 : 1; + 88 : 1; 89 : 0; 90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s)) 91 : 0; -- clk2 counter: High Count = 0 (8 bit(s)) diff --git a/cores/archie/fpga/mist/pll_vidc_25.mif b/cores/archie/fpga/mist/pll_vidc_25.mif index 5fdb190..db5f1c1 100644 --- a/cores/archie/fpga/mist/pll_vidc_25.mif +++ b/cores/archie/fpga/mist/pll_vidc_25.mif @@ -18,7 +18,7 @@ -- Device Speed Grade: 8 -- PLL Scan Chain: Fast PLL (144 bits) -- File Name: /home/gyuri/git/mist-board/cores/archie/fpga/mist/pll_vidc_25.mif --- Generated: Sat Feb 23 00:00:38 2019 +-- Generated: Sun May 17 02:52:17 2020 WIDTH=1; DEPTH=144; @@ -36,7 +36,7 @@ CONTENT BEGIN 6 : 0; 7 : 0; 8 : 0; - 9 : 0; -- VCO Post Scale = 0 (1 bit(s)) (VCO post-scale divider counter value = 2) + 9 : 1; -- VCO Post Scale = 1 (1 bit(s)) (VCO post-scale divider counter value = 1) 10 : 0; -- Reserved Bits = 0 (5 bit(s)) 11 : 0; 12 : 0; @@ -64,59 +64,59 @@ CONTENT BEGIN 34 : 1; 35 : 0; 36 : 0; -- M counter: Bypass = 0 (1 bit(s)) - 37 : 0; -- M counter: High Count = 56 (8 bit(s)) - 38 : 0; + 37 : 0; -- M counter: High Count = 107 (8 bit(s)) + 38 : 1; 39 : 1; - 40 : 1; + 40 : 0; 41 : 1; 42 : 0; - 43 : 0; - 44 : 0; - 45 : 0; -- M counter: Odd Division = 0 (1 bit(s)) - 46 : 0; -- M counter: Low Count = 56 (8 bit(s)) - 47 : 0; + 43 : 1; + 44 : 1; + 45 : 1; -- M counter: Odd Division = 1 (1 bit(s)) + 46 : 0; -- M counter: Low Count = 106 (8 bit(s)) + 47 : 1; 48 : 1; - 49 : 1; + 49 : 0; 50 : 1; 51 : 0; - 52 : 0; + 52 : 1; 53 : 0; 54 : 0; -- clk0 counter: Bypass = 0 (1 bit(s)) - 55 : 0; -- clk0 counter: High Count = 6 (8 bit(s)) + 55 : 0; -- clk0 counter: High Count = 12 (8 bit(s)) 56 : 0; 57 : 0; 58 : 0; - 59 : 0; + 59 : 1; 60 : 1; - 61 : 1; + 61 : 0; 62 : 0; - 63 : 0; -- clk0 counter: Odd Division = 0 (1 bit(s)) - 64 : 0; -- clk0 counter: Low Count = 6 (8 bit(s)) + 63 : 1; -- clk0 counter: Odd Division = 1 (1 bit(s)) + 64 : 0; -- clk0 counter: Low Count = 11 (8 bit(s)) 65 : 0; 66 : 0; 67 : 0; - 68 : 0; - 69 : 1; + 68 : 1; + 69 : 0; 70 : 1; - 71 : 0; - 72 : 1; -- clk1 counter: Bypass = 1 (1 bit(s)) - 73 : 0; -- clk1 counter: High Count = 0 (8 bit(s)) + 71 : 1; + 72 : 0; -- clk1 counter: Bypass = 0 (1 bit(s)) + 73 : 0; -- clk1 counter: High Count = 12 (8 bit(s)) 74 : 0; 75 : 0; 76 : 0; - 77 : 0; - 78 : 0; + 77 : 1; + 78 : 1; 79 : 0; 80 : 0; - 81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s)) - 82 : 0; -- clk1 counter: Low Count = 0 (8 bit(s)) + 81 : 1; -- clk1 counter: Odd Division = 1 (1 bit(s)) + 82 : 0; -- clk1 counter: Low Count = 11 (8 bit(s)) 83 : 0; 84 : 0; 85 : 0; - 86 : 0; + 86 : 1; 87 : 0; - 88 : 0; - 89 : 0; + 88 : 1; + 89 : 1; 90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s)) 91 : 0; -- clk2 counter: High Count = 0 (8 bit(s)) 92 : 0; diff --git a/cores/archie/fpga/mist/pll_vidc_36.mif b/cores/archie/fpga/mist/pll_vidc_36.mif index 03d819a..932d6f7 100644 --- a/cores/archie/fpga/mist/pll_vidc_36.mif +++ b/cores/archie/fpga/mist/pll_vidc_36.mif @@ -18,7 +18,7 @@ -- Device Speed Grade: 8 -- PLL Scan Chain: Fast PLL (144 bits) -- File Name: /home/gyuri/git/mist-board/cores/archie/fpga/mist/pll_vidc_36.mif --- Generated: Sat Feb 23 00:01:12 2019 +-- Generated: Sun May 17 02:54:24 2020 WIDTH=1; DEPTH=144; @@ -99,22 +99,22 @@ CONTENT BEGIN 69 : 1; 70 : 0; 71 : 0; - 72 : 1; -- clk1 counter: Bypass = 1 (1 bit(s)) - 73 : 0; -- clk1 counter: High Count = 0 (8 bit(s)) + 72 : 0; -- clk1 counter: Bypass = 0 (1 bit(s)) + 73 : 0; -- clk1 counter: High Count = 5 (8 bit(s)) 74 : 0; 75 : 0; 76 : 0; 77 : 0; - 78 : 0; + 78 : 1; 79 : 0; - 80 : 0; - 81 : 0; -- clk1 counter: Odd Division = 0 (1 bit(s)) - 82 : 0; -- clk1 counter: Low Count = 0 (8 bit(s)) + 80 : 1; + 81 : 1; -- clk1 counter: Odd Division = 1 (1 bit(s)) + 82 : 0; -- clk1 counter: Low Count = 4 (8 bit(s)) 83 : 0; 84 : 0; 85 : 0; 86 : 0; - 87 : 0; + 87 : 1; 88 : 0; 89 : 0; 90 : 1; -- clk2 counter: Bypass = 1 (1 bit(s))