diff --git a/cores/spectrum/clocks.vhd b/cores/spectrum/clocks.vhd index 3c342e8..db58775 100755 --- a/cores/spectrum/clocks.vhd +++ b/cores/spectrum/clocks.vhd @@ -57,39 +57,64 @@ port ( -- 1.75 MHz clock enable (1 in 8) for data_io CLKEN_DIO : out std_logic; -- 14 MHz clock enable (out of phase with CPU) - CLKEN_VID : out std_logic + CLKEN_VID : out std_logic; + -- clock reference for sdram to sync onto + CLK_REF : out std_logic ); end clocks; --- Clock enables for uncontended VRAM access --- 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 --- CPU VID VID VID VID CPU VID VID VID VID --- DIO MEM PSG - architecture clocks_arch of clocks is signal counter : unsigned(3 downto 0); signal mreq_D : std_logic; begin - -- X000 - -- CPU may used 1000 state only if it doesn't use the memory bus - CLKEN_CPU <= '1' when (counter = "1000" and mreq_D = '0') - or counter = "0000" else '0'; - -- 1000 - CLKEN_DIO <= '1' when counter = "1101" else '0'; - -- 1001 - CLKEN_MEM <= '1' when counter = "1001" else '0'; - -- XXX1 - CLKEN_VID <= '1' when counter(0) = '1' else '0'; - -- 1111 - CLKEN_PSG <= '1' when counter = "1111" else '0'; + process(CLK) begin + if rising_edge(CLK) then + if counter(1) = '1' then + CLK_REF <= '1'; + else + CLK_REF <= '0'; + end if; + end if; + end process; - process(nRESET,CLK) - begin + process(nRESET,CLK) begin if nRESET = '0' then counter <= (others => '0'); elsif falling_edge(CLK) then counter <= counter + 1; mreq_D <= MREQ; + + if counter(0) = '1' then + CLKEN_VID <= '1'; + else + CLKEN_VID <= '0'; + end if; + + if (counter = "1000") then --1111/1000 + CLKEN_PSG <= '1'; + else + CLKEN_PSG <= '0'; + end if; + + if (counter = "1011") or (counter = "1100") or(counter = "1101") then + CLKEN_DIO <= '1'; + else + CLKEN_DIO <= '0'; + end if; + + if (counter = "0111") or (counter = "1000") or (counter = "1001") then + CLKEN_MEM <= '1'; + else + CLKEN_MEM <= '0'; + end if; + + if ((counter = "0111") and (MREQ = '0')) or (counter = "1111") then +-- if ( counter = "1111" ) then + CLKEN_CPU <= '1'; + else + CLKEN_CPU <= '0'; + end if; + end if; end process; end clocks_arch; diff --git a/cores/spectrum/pll_main.vhd b/cores/spectrum/pll_main.vhd index d975595..4f677c1 100755 --- a/cores/spectrum/pll_main.vhd +++ b/cores/spectrum/pll_main.vhd @@ -150,12 +150,12 @@ BEGIN bandwidth_type => "AUTO", clk0_divide_by => 27, clk0_duty_cycle => 50, - clk0_multiply_by => 112, + clk0_multiply_by => 56, clk0_phase_shift => "0", clk1_divide_by => 27, clk1_duty_cycle => 50, - clk1_multiply_by => 112, - clk1_phase_shift => "-1500", + clk1_multiply_by => 56, + clk1_phase_shift => "-2500", compensate_clock => "CLK0", inclk0_input_frequency => 37037, intended_device_family => "Cyclone III", @@ -241,8 +241,8 @@ END SYN; -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "9" -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000" -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "112.000000" --- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "112.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "56.000000" +-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "56.000000" -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0" -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0" -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1" @@ -270,8 +270,8 @@ END SYN; -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "40" -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "40" -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1" --- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "112.00000000" --- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "112.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "56.00000000" +-- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "56.00000000" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1" -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz" @@ -279,7 +279,7 @@ END SYN; -- Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "1" -- Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000" --- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-1500.00000000" +-- Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-2500.00000000" -- Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg" -- Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ps" @@ -301,7 +301,7 @@ END SYN; -- Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0" -- Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000" -- Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz" --- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500" +-- Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.000" -- Retrieval info: PRIVATE: SPREAD_USE STRING "0" -- Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0" -- Retrieval info: PRIVATE: STICKY_CLK0 STRING "1" @@ -319,12 +319,12 @@ END SYN; -- Retrieval info: CONSTANT: BANDWIDTH_TYPE STRING "AUTO" -- Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "27" -- Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "112" +-- Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "56" -- Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0" -- Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "27" -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50" --- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "112" --- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-1500" +-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "56" +-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-2500" -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0" -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "37037" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" @@ -391,7 +391,7 @@ END SYN; -- Retrieval info: GEN_FILE: TYPE_NORMAL pll_main.ppf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL pll_main.inc FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL pll_main.cmp FALSE --- Retrieval info: GEN_FILE: TYPE_NORMAL pll_main.bsf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL pll_main.bsf FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL pll_main_inst.vhd FALSE -- Retrieval info: LIB_FILE: altera_mf -- Retrieval info: CBX_MODULE_PREFIX: ON diff --git a/cores/spectrum/sdram.v b/cores/spectrum/sdram.v index ef192f7..3faa550 100644 --- a/cores/spectrum/sdram.v +++ b/cores/spectrum/sdram.v @@ -24,9 +24,9 @@ module sdram ( // interface to the MT48LC16M16 chip inout [15:0] sd_data, // 16 bit bidirectional data bus - output [12:0] sd_addr, // 13 bit multiplexed address bus - output [1:0] sd_dqm, // two byte masks - output [1:0] sd_ba, // two banks + output reg [12:0] sd_addr, // 13 bit multiplexed address bus + output reg [1:0] sd_dqm, // two byte masks + output reg [1:0] sd_ba, // two banks output sd_cs, // a single chip select output sd_we, // write enable output sd_ras, // row address select @@ -38,7 +38,7 @@ module sdram ( input clkref, // reference clock to sync to input [7:0] din, // data input from chipset/cpu - output [7:0] dout, // data output to chipset/cpu + output [7:0] dout, // data output to chipset/cpu input [24:0] addr, // 25 bit byte address input oe, // cpu/chipset requests read input we // cpu/chipset requests write @@ -47,7 +47,7 @@ module sdram ( // falling edge on oe/we/rfsh starts state machine // no burst configured -localparam RASCAS_DELAY = 3'd3; // tRCD=20ns -> 3 cycles@128MHz +localparam RASCAS_DELAY = 3'd3; // tRCD=20ns -> 2 cycles@56MHz localparam BURST_LENGTH = 3'b000; // 000=1, 001=2, 010=4, 011=8 localparam ACCESS_TYPE = 1'b0; // 0=sequential, 1=interleaved localparam CAS_LATENCY = 3'd3; // 2/3 allowed @@ -62,18 +62,18 @@ localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, B // --------------------------------------------------------------------- localparam STATE_IDLE = 3'd0; // first state in cycle -localparam STATE_CMD_START = 3'd1; // state in which a new command can be started +localparam STATE_CMD_START = 3'd0; // state in which a new command can be started localparam STATE_CMD_CONT = STATE_CMD_START + RASCAS_DELAY; // 4 command can be continued localparam STATE_LAST = 3'd7; // last state in cycle reg [2:0] q /* synthesis noprune */; always @(posedge clk) begin - // 112Mhz counter synchronous to 14 Mhz clock + // 56Mhz counter synchronous to 7 Mhz clkref // force counter to pass state 5->6 exactly after the rising edge of clkref // since clkref is two clocks early - if(((q == 5) && ( clkref == 0)) || - ((q == 6) && ( clkref == 1)) || - ((q != 5) && (q != 6))) + if(((q == 0) && ( clkref == 0)) || + ((q == 7) && ( clkref == 1)) || + ((q != 0) && (q != 7))) q <= q + 3'd1; end @@ -105,7 +105,7 @@ localparam CMD_PRECHARGE = 4'b0010; localparam CMD_AUTO_REFRESH = 4'b0001; localparam CMD_LOAD_MODE = 4'b0000; -wire [3:0] sd_cmd; // current command sent to sd ram +reg [3:0] sd_cmd; // current command sent to sd ram // drive control signals according to current command assign sd_cs = sd_cmd[3]; @@ -119,37 +119,54 @@ assign sd_we = sd_cmd[0]; // at a time when writing assign sd_data = we?{din, din}:16'bZZZZZZZZZZZZZZZZ; -//reg addr0; -//always @(posedge clk) -// if((q == 1) && oe) addr0 <= addr[0]; - -//assign dout = addr0?sd_data[7:0]:sd_data[15:8]; +// assign dout = addr[0]?sd_data[7:0]:sd_data[15:8]; assign dout = sd_data[7:0]; -wire [3:0] reset_cmd = - ((q == STATE_CMD_START) && (reset == 13))?CMD_PRECHARGE: - ((q == STATE_CMD_START) && (reset == 2))?CMD_LOAD_MODE: - CMD_INHIBIT; - -wire [3:0] run_cmd = - ((we || oe) && (q == STATE_CMD_START))?CMD_ACTIVE: - (we && (q == STATE_CMD_CONT ))?CMD_WRITE: - (!we && oe && (q == STATE_CMD_CONT ))?CMD_READ: - (!we && !oe && (q == STATE_CMD_START))?CMD_AUTO_REFRESH: - CMD_INHIBIT; +always @(posedge clk) begin + sd_cmd <= CMD_INHIBIT; // default: idle -assign sd_cmd = (reset != 0)?reset_cmd:run_cmd; + if(reset != 0) begin + // initialization takes place at the end of the reset phase + if(q == STATE_CMD_START) begin -wire [12:0] reset_addr = (reset == 13)?13'b0010000000000:MODE; + if(reset == 13) begin + sd_cmd <= CMD_PRECHARGE; + sd_addr[10] <= 1'b1; // precharge all banks + end + + if(reset == 2) begin + sd_cmd <= CMD_LOAD_MODE; + sd_addr <= MODE; + end + + end + end else begin + // normal operation + + // ------------------- cpu/chipset read/write ---------------------- + if(we || oe) begin -wire [12:0] run_addr = - (q == STATE_CMD_START)?addr[20:8]:{ 4'b0010, addr[23], addr[7:0]}; - -assign sd_addr = (reset != 0)?reset_addr:run_addr; - -assign sd_ba = addr[22:21]; - -//assign sd_dqm = we?{ addr[0], ~addr[0] }:2'b00; -assign sd_dqm = 2'b00; + // RAS phase + if(q == STATE_CMD_START) begin + sd_cmd <= CMD_ACTIVE; + sd_addr <= addr[21:9]; + sd_ba <= addr[23:22]; + sd_dqm <= 2'b00; + end + + // CAS phase + if(q == STATE_CMD_CONT) begin + sd_cmd <= we?CMD_WRITE:CMD_READ; + sd_addr <= { 4'b0010, addr[8:0] }; // auto precharge + end + end + + // ------------------------ no access -------------------------- + else begin + if(q == STATE_CMD_START) + sd_cmd <= CMD_AUTO_REFRESH; + end + end +end endmodule diff --git a/cores/spectrum/spectrum.qsf b/cores/spectrum/spectrum.qsf index c79582b..9be3e9f 100755 --- a/cores/spectrum/spectrum.qsf +++ b/cores/spectrum/spectrum.qsf @@ -154,7 +154,7 @@ set_global_assignment -name ENABLE_NCE_PIN OFF set_global_assignment -name ENABLE_BOOT_SEL_PIN OFF set_global_assignment -name USE_CONFIGURATION_DEVICE OFF set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO" -set_global_assignment -name ENABLE_SIGNALTAP ON +set_global_assignment -name ENABLE_SIGNALTAP OFF set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top @@ -293,34 +293,8 @@ set_global_assignment -name ALLOW_POWER_UP_DONT_CARE ON set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON set_global_assignment -name OPTIMIZE_HOLD_TIMING "ALL PATHS" set_global_assignment -name OPTIMIZE_MULTI_CORNER_TIMING ON -set_global_assignment -name FITTER_EFFORT "FAST FIT" -set_global_assignment -name SLD_NODE_CREATOR_ID 110 -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_ENTITY_NAME sld_signaltap -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_clk -to "pll_main:pll|altpll:altpll_component|pll_main_altpll:auto_generated|wire_pll1_clk[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[0] -to SDRAM_nCAS -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[1] -to SDRAM_nCS -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[2] -to SDRAM_nRAS -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[3] -to SDRAM_nWE -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[0] -to SDRAM_nCAS -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[1] -to SDRAM_nCS -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[2] -to SDRAM_nRAS -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[3] -to SDRAM_nWE -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_RAM_BLOCK_TYPE=AUTO" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_INFO=805334528" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_POWER_UP_TRIGGER=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STORAGE_QUALIFIER_INVERSION_MASK_LENGTH=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SEGMENT_SIZE=512" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ATTRIBUTE_MEM_MODE=OFF" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_FLOW_USE_GENERATED=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_STATE_BITS=11" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_BUFFER_FULL_STOP=1" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_CURRENT_RESOURCE_WIDTH=1" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL=1" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_SAMPLE_DEPTH=512" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_IN_ENABLED=0" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ADVANCED_TRIGGER_ENTITY=basic,1," -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_LEVEL_PIPELINE=1" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_ENABLE_ADVANCED_TRIGGER=0" -section_id auto_signaltap_0 +set_global_assignment -name FITTER_EFFORT "AUTO FIT" +set_global_assignment -name VERILOG_FILE sdram.v set_global_assignment -name VERILOG_FILE spi.v set_global_assignment -name VERILOG_FILE sd_card.v set_global_assignment -name VERILOG_FILE sigma_delta_dac.v @@ -347,300 +321,4 @@ set_global_assignment -name QIP_FILE rom48.qip set_global_assignment -name QIP_FILE rom128.qip set_global_assignment -name VERILOG_FILE tape.v set_global_assignment -name VERILOG_FILE divmmc.v -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[4] -to "T80se:cpu|IORQ_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[5] -to "T80se:cpu|RESET_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[4] -to "T80se:cpu|IORQ_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[5] -to "T80se:cpu|RESET_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[6] -to "T80se:cpu|T80:u0|PC[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[7] -to "T80se:cpu|T80:u0|PC[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[8] -to "T80se:cpu|T80:u0|PC[11]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[9] -to "T80se:cpu|T80:u0|PC[12]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[10] -to "T80se:cpu|T80:u0|PC[13]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[11] -to "T80se:cpu|T80:u0|PC[14]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[12] -to "T80se:cpu|T80:u0|PC[15]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[13] -to "T80se:cpu|T80:u0|PC[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[14] -to "T80se:cpu|T80:u0|PC[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[15] -to "T80se:cpu|T80:u0|PC[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[16] -to "T80se:cpu|T80:u0|PC[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[17] -to "T80se:cpu|T80:u0|PC[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[18] -to "T80se:cpu|T80:u0|PC[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[19] -to "T80se:cpu|T80:u0|PC[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[20] -to "T80se:cpu|T80:u0|PC[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[21] -to "T80se:cpu|T80:u0|PC[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[22] -to "T80se:cpu|WAIT_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[23] -to "clocks:clken|CLKEN_CPU" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[24] -to "clocks:clken|CLKEN_DIO" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[25] -to "clocks:clken|CLKEN_MEM" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[26] -to "clocks:clken|CLKEN_PSG" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[27] -to "clocks:clken|CLKEN_VID" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[28] -to "divmmc:dmmc|a[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[29] -to "divmmc:dmmc|a[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[30] -to "divmmc:dmmc|a[11]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[31] -to "divmmc:dmmc|a[12]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[32] -to "divmmc:dmmc|a[13]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[33] -to "divmmc:dmmc|a[14]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[34] -to "divmmc:dmmc|a[15]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[35] -to "divmmc:dmmc|a[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[36] -to "divmmc:dmmc|a[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[37] -to "divmmc:dmmc|a[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[38] -to "divmmc:dmmc|a[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[39] -to "divmmc:dmmc|a[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[40] -to "divmmc:dmmc|a[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[41] -to "divmmc:dmmc|a[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[42] -to "divmmc:dmmc|a[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[43] -to "divmmc:dmmc|a[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[44] -to "divmmc:dmmc|acc_cnt[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[45] -to "divmmc:dmmc|acc_cnt[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[46] -to "divmmc:dmmc|acc_cnt[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[47] -to "divmmc:dmmc|acc_cnt[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[48] -to "divmmc:dmmc|acc_cnt[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[49] -to "divmmc:dmmc|acc_cnt[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[50] -to "divmmc:dmmc|acc_cnt[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[51] -to "divmmc:dmmc|acc_cnt[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[52] -to "divmmc:dmmc|ctrl[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[53] -to "divmmc:dmmc|ctrl[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[54] -to "divmmc:dmmc|ctrl[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[55] -to "divmmc:dmmc|ctrl[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[56] -to "divmmc:dmmc|ctrl[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[57] -to "divmmc:dmmc|ctrl[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[58] -to "divmmc:dmmc|ctrl[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[59] -to "divmmc:dmmc|ctrl[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[60] -to "divmmc:dmmc|din[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[61] -to "divmmc:dmmc|din[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[62] -to "divmmc:dmmc|din[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[63] -to "divmmc:dmmc|din[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[64] -to "divmmc:dmmc|din[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[65] -to "divmmc:dmmc|din[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[66] -to "divmmc:dmmc|din[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[67] -to "divmmc:dmmc|din[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[68] -to "divmmc:dmmc|enable" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[69] -to "divmmc:dmmc|m1_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[70] -to "divmmc:dmmc|m1_trigger" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[71] -to "divmmc:dmmc|mreq_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[72] -to "divmmc:dmmc|paged_in" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[73] -to "divmmc:dmmc|rd_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[74] -to "divmmc:dmmc|sd_cs" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[75] -to "divmmc:dmmc|sd_miso" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[76] -to "divmmc:dmmc|sd_mosi" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[77] -to "divmmc:dmmc|sd_sck" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[78] -to "divmmc:dmmc|spi:mi_spi|data_from_spi[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[79] -to "divmmc:dmmc|spi:mi_spi|data_from_spi[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[80] -to "divmmc:dmmc|spi:mi_spi|data_from_spi[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[81] -to "divmmc:dmmc|spi:mi_spi|data_from_spi[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[82] -to "divmmc:dmmc|spi:mi_spi|data_from_spi[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[83] -to "divmmc:dmmc|spi:mi_spi|data_from_spi[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[84] -to "divmmc:dmmc|spi:mi_spi|data_from_spi[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[85] -to "divmmc:dmmc|spi:mi_spi|data_from_spi[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[86] -to "divmmc:dmmc|spi:mi_spi|data_to_cpu[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[87] -to "divmmc:dmmc|spi:mi_spi|data_to_cpu[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[88] -to "divmmc:dmmc|spi:mi_spi|data_to_cpu[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[89] -to "divmmc:dmmc|spi:mi_spi|data_to_cpu[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[90] -to "divmmc:dmmc|spi:mi_spi|data_to_cpu[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[91] -to "divmmc:dmmc|spi:mi_spi|data_to_cpu[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[92] -to "divmmc:dmmc|spi:mi_spi|data_to_cpu[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[93] -to "divmmc:dmmc|spi:mi_spi|data_to_cpu[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[94] -to "divmmc:dmmc|spi:mi_spi|data_to_spi[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[95] -to "divmmc:dmmc|spi:mi_spi|data_to_spi[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[96] -to "divmmc:dmmc|spi:mi_spi|data_to_spi[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[97] -to "divmmc:dmmc|spi:mi_spi|data_to_spi[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[98] -to "divmmc:dmmc|spi:mi_spi|data_to_spi[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[99] -to "divmmc:dmmc|spi:mi_spi|data_to_spi[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[100] -to "divmmc:dmmc|spi:mi_spi|data_to_spi[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[101] -to "divmmc:dmmc|spi:mi_spi|data_to_spi[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[102] -to "divmmc:dmmc|wr_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[103] -to mem_do[0] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[104] -to mem_do[1] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[105] -to mem_do[2] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[106] -to mem_do[3] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[107] -to mem_do[4] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[108] -to mem_do[5] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[109] -to mem_do[6] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[110] -to mem_do[7] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[111] -to psg_enable -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[112] -to rom_dl -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[113] -to rom_enable -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[114] -to "sdram:sdr|din[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[115] -to "sdram:sdr|din[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[116] -to "sdram:sdr|din[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[117] -to "sdram:sdr|din[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[118] -to "sdram:sdr|din[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[119] -to "sdram:sdr|din[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[120] -to "sdram:sdr|din[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[121] -to "sdram:sdr|din[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[122] -to "sdram:sdr|dout[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[123] -to "sdram:sdr|dout[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[124] -to "sdram:sdr|dout[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[125] -to "sdram:sdr|dout[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[126] -to "sdram:sdr|dout[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[127] -to "sdram:sdr|dout[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[128] -to "sdram:sdr|dout[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[129] -to "sdram:sdr|dout[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[130] -to sdram_oe -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[131] -to sdram_we -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[132] -to "tape:tape_I|downloading" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[133] -to ula_enable -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[134] -to divmmc_enable -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_trigger_in[135] -to page_rom_sel -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[6] -to "T80se:cpu|T80:u0|PC[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[7] -to "T80se:cpu|T80:u0|PC[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[8] -to "T80se:cpu|T80:u0|PC[11]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[9] -to "T80se:cpu|T80:u0|PC[12]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[10] -to "T80se:cpu|T80:u0|PC[13]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[11] -to "T80se:cpu|T80:u0|PC[14]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[12] -to "T80se:cpu|T80:u0|PC[15]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[13] -to "T80se:cpu|T80:u0|PC[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[14] -to "T80se:cpu|T80:u0|PC[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[15] -to "T80se:cpu|T80:u0|PC[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[16] -to "T80se:cpu|T80:u0|PC[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[17] -to "T80se:cpu|T80:u0|PC[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[18] -to "T80se:cpu|T80:u0|PC[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[19] -to "T80se:cpu|T80:u0|PC[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[20] -to "T80se:cpu|T80:u0|PC[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[21] -to "T80se:cpu|T80:u0|PC[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[22] -to "T80se:cpu|WAIT_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[23] -to "clocks:clken|CLKEN_CPU" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[24] -to "clocks:clken|CLKEN_DIO" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[25] -to "clocks:clken|CLKEN_MEM" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[26] -to "clocks:clken|CLKEN_PSG" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[27] -to "clocks:clken|CLKEN_VID" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[28] -to "divmmc:dmmc|a[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[29] -to "divmmc:dmmc|a[10]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[30] -to "divmmc:dmmc|a[11]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[31] -to "divmmc:dmmc|a[12]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[32] -to "divmmc:dmmc|a[13]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[33] -to "divmmc:dmmc|a[14]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[34] -to "divmmc:dmmc|a[15]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[35] -to "divmmc:dmmc|a[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[36] -to "divmmc:dmmc|a[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[37] -to "divmmc:dmmc|a[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[38] -to "divmmc:dmmc|a[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[39] -to "divmmc:dmmc|a[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[40] -to "divmmc:dmmc|a[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[41] -to "divmmc:dmmc|a[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[42] -to "divmmc:dmmc|a[8]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[43] -to "divmmc:dmmc|a[9]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[44] -to "divmmc:dmmc|acc_cnt[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[45] -to "divmmc:dmmc|acc_cnt[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[46] -to "divmmc:dmmc|acc_cnt[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[47] -to "divmmc:dmmc|acc_cnt[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[48] -to "divmmc:dmmc|acc_cnt[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[49] -to "divmmc:dmmc|acc_cnt[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[50] -to "divmmc:dmmc|acc_cnt[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[51] -to "divmmc:dmmc|acc_cnt[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[52] -to "divmmc:dmmc|ctrl[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[53] -to "divmmc:dmmc|ctrl[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[54] -to "divmmc:dmmc|ctrl[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[55] -to "divmmc:dmmc|ctrl[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[56] -to "divmmc:dmmc|ctrl[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[57] -to "divmmc:dmmc|ctrl[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[58] -to "divmmc:dmmc|ctrl[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[59] -to "divmmc:dmmc|ctrl[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[60] -to "divmmc:dmmc|din[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[61] -to "divmmc:dmmc|din[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[62] -to "divmmc:dmmc|din[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[63] -to "divmmc:dmmc|din[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[64] -to "divmmc:dmmc|din[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[65] -to "divmmc:dmmc|din[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[66] -to "divmmc:dmmc|din[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[67] -to "divmmc:dmmc|din[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[68] -to "divmmc:dmmc|enable" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[69] -to "divmmc:dmmc|m1_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[70] -to "divmmc:dmmc|m1_trigger" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[71] -to "divmmc:dmmc|mreq_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[72] -to "divmmc:dmmc|paged_in" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[73] -to "divmmc:dmmc|rd_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[74] -to "divmmc:dmmc|sd_cs" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[75] -to "divmmc:dmmc|sd_miso" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[76] -to "divmmc:dmmc|sd_mosi" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[77] -to "divmmc:dmmc|sd_sck" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[78] -to "divmmc:dmmc|spi:mi_spi|data_from_spi[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[79] -to "divmmc:dmmc|spi:mi_spi|data_from_spi[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[80] -to "divmmc:dmmc|spi:mi_spi|data_from_spi[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[81] -to "divmmc:dmmc|spi:mi_spi|data_from_spi[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[82] -to "divmmc:dmmc|spi:mi_spi|data_from_spi[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[83] -to "divmmc:dmmc|spi:mi_spi|data_from_spi[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[84] -to "divmmc:dmmc|spi:mi_spi|data_from_spi[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[85] -to "divmmc:dmmc|spi:mi_spi|data_from_spi[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[86] -to "divmmc:dmmc|spi:mi_spi|data_to_cpu[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[87] -to "divmmc:dmmc|spi:mi_spi|data_to_cpu[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[88] -to "divmmc:dmmc|spi:mi_spi|data_to_cpu[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[89] -to "divmmc:dmmc|spi:mi_spi|data_to_cpu[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[90] -to "divmmc:dmmc|spi:mi_spi|data_to_cpu[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[91] -to "divmmc:dmmc|spi:mi_spi|data_to_cpu[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[92] -to "divmmc:dmmc|spi:mi_spi|data_to_cpu[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[93] -to "divmmc:dmmc|spi:mi_spi|data_to_cpu[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[94] -to "divmmc:dmmc|spi:mi_spi|data_to_spi[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[95] -to "divmmc:dmmc|spi:mi_spi|data_to_spi[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[96] -to "divmmc:dmmc|spi:mi_spi|data_to_spi[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[97] -to "divmmc:dmmc|spi:mi_spi|data_to_spi[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[98] -to "divmmc:dmmc|spi:mi_spi|data_to_spi[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[99] -to "divmmc:dmmc|spi:mi_spi|data_to_spi[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[100] -to "divmmc:dmmc|spi:mi_spi|data_to_spi[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[101] -to "divmmc:dmmc|spi:mi_spi|data_to_spi[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[102] -to "divmmc:dmmc|wr_n" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[103] -to mem_do[0] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[104] -to mem_do[1] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[105] -to mem_do[2] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[106] -to mem_do[3] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[107] -to mem_do[4] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[108] -to mem_do[5] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[109] -to mem_do[6] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[110] -to mem_do[7] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[111] -to psg_enable -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[112] -to rom_dl -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[113] -to rom_enable -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[114] -to "sdram:sdr|din[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[115] -to "sdram:sdr|din[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[116] -to "sdram:sdr|din[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[117] -to "sdram:sdr|din[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[118] -to "sdram:sdr|din[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[119] -to "sdram:sdr|din[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[120] -to "sdram:sdr|din[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[121] -to "sdram:sdr|din[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[122] -to "sdram:sdr|dout[0]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[123] -to "sdram:sdr|dout[1]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[124] -to "sdram:sdr|dout[2]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[125] -to "sdram:sdr|dout[3]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[126] -to "sdram:sdr|dout[4]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[127] -to "sdram:sdr|dout[5]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[128] -to "sdram:sdr|dout[6]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[129] -to "sdram:sdr|dout[7]" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[130] -to sdram_addr[0] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[131] -to sdram_addr[10] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[132] -to sdram_addr[11] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[133] -to sdram_addr[12] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[134] -to sdram_addr[13] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[135] -to sdram_addr[14] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[136] -to sdram_addr[15] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[137] -to sdram_addr[16] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[138] -to sdram_addr[17] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[139] -to sdram_addr[18] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[140] -to sdram_addr[19] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[141] -to sdram_addr[1] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[142] -to sdram_addr[20] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[143] -to sdram_addr[21] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[144] -to sdram_addr[22] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[145] -to sdram_addr[23] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[146] -to sdram_addr[24] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[147] -to sdram_addr[2] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[148] -to sdram_addr[3] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[149] -to sdram_addr[4] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[150] -to sdram_addr[5] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[151] -to sdram_addr[6] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[152] -to sdram_addr[7] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[153] -to sdram_addr[8] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[154] -to sdram_addr[9] -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[155] -to sdram_oe -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[156] -to sdram_we -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[157] -to "tape:tape_I|downloading" -section_id auto_signaltap_0 -set_instance_assignment -name CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[158] -to ula_enable -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[159] -to divmmc_enable -section_id auto_signaltap_0 -set_instance_assignment -name POST_FIT_CONNECT_TO_SLD_NODE_ENTITY_PORT acq_data_in[160] -to page_rom_sel -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_DATA_BITS=161" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_TRIGGER_BITS=136" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_INVERSION_MASK_LENGTH=431" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_LOWORD=55689" -section_id auto_signaltap_0 -set_global_assignment -name SLD_NODE_PARAMETER_ASSIGNMENT "SLD_NODE_CRC_HIWORD=63638" -section_id auto_signaltap_0 -set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top -set_global_assignment -name SLD_FILE db/stp1_auto_stripped.stp \ No newline at end of file +set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/cores/spectrum/spectrum_mist.vhd b/cores/spectrum/spectrum_mist.vhd index a5c714d..6eaf7ca 100755 --- a/cores/spectrum/spectrum_mist.vhd +++ b/cores/spectrum/spectrum_mist.vhd @@ -141,7 +141,9 @@ port ( -- 1.75 MHz clock enable (1 in 8) CLKEN_DIO : out std_logic; -- 14 MHz clock enable (out of phase with CPU) - CLKEN_VID : out std_logic + CLKEN_VID : out std_logic; + -- SDRAM reference clock to sync onto + CLK_REF : out std_logic ); end component; @@ -606,8 +608,7 @@ signal divmmc_conmem : std_logic; signal key_f11 : std_logic; -- Master clock - 28 MHz -signal clk112 : std_logic; -signal clk_div : unsigned(1 downto 0); +signal clk56 : std_logic; signal pll_locked : std_logic; signal clock : std_logic; signal audio_clock : std_logic; @@ -621,6 +622,7 @@ signal cpu_clken : std_logic; signal mem_clken : std_logic; signal dio_clken : std_logic; signal vid_clken : std_logic; +signal clk_ref : std_logic; -- Address decoding signal ula_enable : std_logic; -- all even IO addresses @@ -685,7 +687,6 @@ signal ula_ram_page : std_logic_vector(2 downto 0); -- ULA video signals signal vid_a : std_logic_vector(12 downto 0); -signal vid_di : std_logic_vector(7 downto 0); signal vid_rd_n : std_logic; signal vid_wait_n : std_logic; signal vid_r_out : std_logic_vector(3 downto 0); @@ -723,19 +724,17 @@ begin pll: pll_main port map ( '0', CLOCK_27(0), - clk112, + clk56, SDRAM_CLK, pll_locked ); - -- generate 28Mhz system clock from 112MHz main clock by dividing it by 4 - process(clk112) + -- generate 28Mhz system clock from 56MHz main clock by dividing it by 2 + process(clk56) begin - if rising_edge(clk112) then - clk_div <= clk_div + 1; + if rising_edge(clk56) then + clock <= not clock; end if; - - clock <= clk_div(1); end process; -- Clock enable logic @@ -747,7 +746,8 @@ begin cpu_clken, mem_clken, dio_clken, - vid_clken + vid_clken, + clk_ref ); -- SDRAM @@ -757,7 +757,7 @@ begin SDRAM_nCS, SDRAM_BA, SDRAM_nWE, SDRAM_NRAS, SDRAM_nCAS, -- System - clk112, vid_clken, not pll_locked, + clk56, clk_ref, not pll_locked, -- cpu interface sdram_di, sdram_do, @@ -771,7 +771,7 @@ begin -- embedded rom rom: rom128 port map ( rom_addr(14 downto 0), - mem_clken, + psg_clken, -- psg_clken is in the middle of a cpu cycle rom_do ); @@ -831,7 +831,7 @@ begin process(clock) begin if rising_edge(clock) then - if dio_clken = '1' then + if dio_clken = '1' and ioctl_cycle = '0' then if ioctl_ram_wr = '1' then ioctl_ram_wr <= '0'; ioctl_used <= '1'; @@ -1036,7 +1036,7 @@ begin end if; -- make sure cpu runs synchronous to bus state machine - if rising_edge(psg_clken) then + if rising_edge(mem_clken) then if reset_cnt = 0 then reset_n <= '1'; else @@ -1073,7 +1073,8 @@ begin -- ROM is enabled between 0x0000 and 0x3fff except in +3 special mode rom_enable <= (not cpu_mreq_n) and not (plus3_special or cpu_a(15) or cpu_a(14)); -- RAM is enabled for any memory request when ROM isn't enabled - ram_enable <= not (cpu_mreq_n or rom_enable); + ram_enable <= (not cpu_mreq_n and not rom_enable); + ram_page_128k: if model /= 2 generate -- 128K has pageable RAM at 0xc000 ram_page <= @@ -1131,6 +1132,7 @@ begin -- Otherwise access the internal ROM "000000" & cpu_a(13 downto 0); end generate; + rom_128k: if model = 1 generate -- DIVMMC low mapping (0x0000 - 0x1fff) divmmc_lo_addr <= "000000" & cpu_a(12 downto 0) when @@ -1150,6 +1152,7 @@ begin -- Otherwise access the internal ROMs "00000" & page_rom_sel & cpu_a(13 downto 0); end generate; + rom_plus3: if model = 2 generate -- DIVMMC low mapping (0x0000 - 0x1fff) divmmc_lo_addr <= "000000" & cpu_a(12 downto 0) when @@ -1171,9 +1174,6 @@ begin "0000" & plus3_page(1) & page_rom_sel & cpu_a(13 downto 0); end generate; - -- SRAM bus - vid_di <= sdram_do; - -- first 1MB of sdram are used as ram, second 1MB sdram are used as rom -- and after that starts tape buffer cpu_addr <= "0" & ram_addr when ram_enable = '1' else "1" & rom_addr; @@ -1295,7 +1295,9 @@ begin zx_green <= vid_g_out & "00"; zx_blue <= vid_b_out & "00"; VGA_HS <= vid_hcsync_n; - VGA_VS <= vid_vsync_n; + -- when scandoubler is disabled a csync is fed into hsync and + -- vsync is used as a rgb switch signal + VGA_VS <= '1' when scandoubler_disable = '1' else vid_vsync_n; -- route video through osd osd_d : osd diff --git a/cores/spectrum/video.vhd b/cores/spectrum/video.vhd index 1c2189a..d2517bc 100755 --- a/cores/spectrum/video.vhd +++ b/cores/spectrum/video.vhd @@ -124,7 +124,7 @@ begin -- Output syncs -- drive VSYNC to 1 in PAL mode for Minimig VGA cable - nVSYNC <= '1' when VGA = '0' else not vsync; + nVSYNC <= not vsync; nHSYNC <= not hsync; nCSYNC <= not (vsync xor hsync); -- Combined HSYNC/CSYNC. Feeds HSYNC to VGA HSYNC in VGA mode, @@ -237,6 +237,21 @@ begin pixels <= (others => '0'); attr <= (others => '0'); elsif rising_edge(CLK) and CLKEN = '1' then + + -- TH + -- activate nVID_RD in advance of pixel and attribute read so data + -- is present in time. This is needed for the SDRAM which is operated at + -- much lower speed than the orignal SRAM in the DE1/DE2 + if blanking='0' and + ((hcounter(3 downto 1) = "111") or + (hcounter(3 downto 1) = "000") or + (hcounter(3 downto 1) = "001") or + (hcounter(3 downto 1) = "010")) then + nVID_RD <= '0'; + else + nVID_RD <= '1'; + end if; + -- Most functions are only performed when hcounter(0) is clear. -- This is the 'half' bit inserted to allow for scan-doubled VGA output. -- In VGA mode the counter will be stepped through the even values only, @@ -260,7 +275,7 @@ begin -- first and third pixel of every 8. This splits a picture/attribute -- fetch pair across two CPU cycles in PAL mode, or both in one cycle -- in VGA mode - nVID_RD <= '0'; +--TH nVID_RD <= '0'; else -- STORE if hcounter(2) = '0' then @@ -271,10 +286,10 @@ begin attr <= VID_D_IN; end if; - nVID_RD <= '1'; - end if; +-- TH nVID_RD <= '1'; + end if; end if; - + -- Delay horizontal picture enable until the end of the first fetch cycle -- This also allows for the re-registration of the outputs if hcounter(9) = '0' and hcounter(2 downto 1) = "11" then