From c54bc6e582e9835c19c605153f63b73eb524da40 Mon Sep 17 00:00:00 2001
From: Gyorgy Szombathelyi <gyurco@freemail.hu>
Date: Tue, 29 Jan 2019 10:19:14 +0100
Subject: [PATCH] [C64] CIA: selectable old and new CIA versions

---
 cores/c64/rtl/fpga64_sid_iec.vhd | 7 ++++++-
 cores/c64/rtl/mist/c64_mist.vhd  | 2 ++
 cores/c64/rtl/mos6526.v          | 5 +++--
 cores/c64/rtl/mos6526.vhd        | 1 +
 4 files changed, 12 insertions(+), 3 deletions(-)

diff --git a/cores/c64/rtl/fpga64_sid_iec.vhd b/cores/c64/rtl/fpga64_sid_iec.vhd
index 7a9fa96..38c169c 100644
--- a/cores/c64/rtl/fpga64_sid_iec.vhd
+++ b/cores/c64/rtl/fpga64_sid_iec.vhd
@@ -108,7 +108,10 @@ entity fpga64_sid_iec is
 		iec_clk_i	: in  std_logic;
 		iec_atn_o	: out std_logic;
 --		iec_atn_i	: in  std_logic;
-		
+
+		-- CIA
+		cia_mode    : in std_logic;
+
 		disk_num    : out std_logic_vector(7 downto 0);
 
 		c64rom_addr : in std_logic_vector(13 downto 0);
@@ -619,6 +622,7 @@ div1m: process(clk32)				-- this process devides 32 MHz to 1MHz (for the SID)
 -- -----------------------------------------------------------------------
 	cia1: mos6526
 		port map (
+			mode => cia_mode,
 			clk => clk32,
             phi2 => enableCia,
             res_n => not reset,
@@ -645,6 +649,7 @@ div1m: process(clk32)				-- this process devides 32 MHz to 1MHz (for the SID)
 
 	cia2: mos6526
 		port map (
+			mode => cia_mode,
 			clk => clk32,
             phi2 => enableCia,
             res_n => not reset,
diff --git a/cores/c64/rtl/mist/c64_mist.vhd b/cores/c64/rtl/mist/c64_mist.vhd
index bf78c3a..7dbdb53 100644
--- a/cores/c64/rtl/mist/c64_mist.vhd
+++ b/cores/c64/rtl/mist/c64_mist.vhd
@@ -134,6 +134,7 @@ constant CONF_STR : string :=
 	"OD,SID,6581,8580;"&
 	"O3,Joysticks,normal,swapped;"&
 	"O6,Audio filter,On,Off;"&
+	"O4,CIA Model,6256,8521;"&
 --	"OB,BIOS,C64,C64GS;" &
 	"T5,Reset & Detach Cartridge;";
 
@@ -842,6 +843,7 @@ begin
 		iec_data_i => c64_iec_data_i,
 		iec_clk_i  => c64_iec_clk_i,
 --		iec_atn_i  => not c64_iec_atn_i,
+		cia_mode => status(4),
 		disk_num => open,
 		c64rom_addr => ioctl_addr(13 downto 0),
 		c64rom_data => ioctl_data,
diff --git a/cores/c64/rtl/mos6526.v b/cores/c64/rtl/mos6526.v
index 01ede2b..d4cd9ca 100644
--- a/cores/c64/rtl/mos6526.v
+++ b/cores/c64/rtl/mos6526.v
@@ -5,6 +5,7 @@
 // TODO: check if Flag and Serial port interrupts are still working
 
 module mos6526 (
+  input  wire       mode, // 0 - 6526 "old", 1 - 8521 "new"
   input  wire       clk,
   input  wire       phi2,
   input  wire       res_n,
@@ -492,11 +493,11 @@ always @(posedge clk) begin
     int_reset <= 0;
     if (!cs_n && rw && rs == 4'hd) int_reset <= 1;
 
-    if (phi2) begin
+    if (phi2 | mode) begin
       imr <= imr_reg[7] ? imr | imr_reg[4:0] : imr & ~imr_reg[4:0];
       irq_n <= irq_n ? ~|(imr & icr) : irq_n;
-      if (int_reset) irq_n <= 1;
     end
+    if (phi2 & int_reset) irq_n <= 1;
   end
 end
 
diff --git a/cores/c64/rtl/mos6526.vhd b/cores/c64/rtl/mos6526.vhd
index af92849..1585df6 100644
--- a/cores/c64/rtl/mos6526.vhd
+++ b/cores/c64/rtl/mos6526.vhd
@@ -4,6 +4,7 @@ use IEEE.std_logic_1164.all;
 package mos6526 is
 component mos6526
     PORT (
+	mode     : in  std_logic; -- '0' - 6256, '1' - 8521
 	clk      : in  std_logic;
 	phi2     : in  std_logic;
 	res_n    : in  std_logic;