diff --git a/cores/c16/sdram.v b/cores/c16/sdram.v
index e32e095..3930658 100644
--- a/cores/c16/sdram.v
+++ b/cores/c16/sdram.v
@@ -46,7 +46,7 @@ module sdram (
 );
 
 // no burst configured
-localparam RASCAS_DELAY   = 3'd2;   // tRCD>=20ns -> 2 cycles@64MHz
+localparam RASCAS_DELAY   = 3'd1;   // tRCD>=20ns -> 1 cycle@32MHz
 localparam BURST_LENGTH   = 3'b000; // 000=none, 001=2, 010=4, 011=8
 localparam ACCESS_TYPE    = 1'b0;   // 0=sequential, 1=interleaved
 localparam CAS_LATENCY    = 3'd2;   // 2/3 allowed
@@ -61,7 +61,7 @@ localparam MODE = { 3'b000, NO_WRITE_BURST, OP_MODE, CAS_LATENCY, ACCESS_TYPE, B
 
 localparam STATE_IDLE      = 4'd0;    // first state in cycle
 localparam STATE_CMD_START = 4'd1;    // state in which a new command can be started
-localparam STATE_CMD_CONT  = STATE_CMD_START  + RASCAS_DELAY - 1'd1; // 2 command can be continued
+localparam STATE_CMD_CONT  = STATE_CMD_START  + RASCAS_DELAY; // 2 command can be continued
 localparam STATE_DATA_READY= STATE_CMD_CONT + CAS_LATENCY + 1'd1;
 localparam STATE_LAST      = 4'd7;   // last state in cycle