From c8d2bb5c00a820f50ae78f7b8cf7ee280e1ba2fe Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi Date: Sun, 24 Feb 2019 00:21:28 +0100 Subject: [PATCH] [Archie] Use only one clock in the FDC --- cores/archie/rtl/fdc1772.v | 83 ++++++++++++++++---------------------- cores/archie/rtl/floppy.v | 47 +++++++++++++-------- 2 files changed, 64 insertions(+), 66 deletions(-) diff --git a/cores/archie/rtl/fdc1772.v b/cores/archie/rtl/fdc1772.v index 74ddee7..03b8add 100644 --- a/cores/archie/rtl/fdc1772.v +++ b/cores/archie/rtl/fdc1772.v @@ -92,9 +92,9 @@ always @(posedge clkcpu) wire irq_clr = !floppy_reset || cpu_read_status; -always @(posedge irq_set or posedge irq_clr) begin +always @(posedge clkcpu or posedge irq_clr) begin if(irq_clr) irq <= 1'b0; - else irq <= 1'b1; + else if(irq_set) irq <= 1'b1; end assign floppy_firq = irq; @@ -106,12 +106,12 @@ reg cpu_read_data; always @(posedge clkcpu) cpu_read_data <= wb_stb && wb_cyc && !wb_we && (wb_adr[3:2] == FDC_REG_DATA); - + wire drq_clr = !floppy_reset || cpu_read_data; - -always @(posedge drq_set or posedge drq_clr) begin + +always @(posedge clkcpu or posedge drq_clr) begin if(drq_clr) drq <= 1'b0; - else drq <= 1'b1; + else if(drq_set) drq <= 1'b1; end assign floppy_drq = drq; @@ -131,9 +131,9 @@ wire fd0_sector_hdr; wire fd0_sector_data; wire fd0_dclk; -floppy floppy0 ( - .clk ( clk8m_en ), - +floppy #(.SYS_CLK(32000000)) floppy0 ( + .clk ( clkcpu ), + // control signals into floppy .select (!floppy_drive[0] ), .motor_on ( motor_on ), @@ -141,7 +141,7 @@ floppy floppy0 ( .step_out ( step_out ), // status signals generated by floppy - .dclk ( fd0_dclk ), + .dclk_en ( fd0_dclk ), .track ( fd0_track ), .sector ( fd0_sector ), .sector_hdr ( fd0_sector_hdr ), @@ -161,9 +161,9 @@ wire fd1_sector_hdr; wire fd1_sector_data; wire fd1_dclk; -floppy floppy1 ( - .clk ( clk8m_en ), - +floppy #(.SYS_CLK(32000000)) floppy1 ( + .clk ( clkcpu ), + // control signals into floppy .select (!floppy_drive[1] ), .motor_on ( motor_on ), @@ -171,7 +171,7 @@ floppy floppy1 ( .step_out ( step_out ), // status signals generated by floppy - .dclk ( fd1_dclk ), + .dclk_en ( fd1_dclk ), .track ( fd1_track ), .sector ( fd1_sector ), .sector_hdr ( fd1_sector_hdr ), @@ -191,9 +191,9 @@ wire fd2_sector_hdr; wire fd2_sector_data; wire fd2_dclk; -floppy floppy2 ( - .clk ( clk8m_en ), - +floppy #(.SYS_CLK(32000000)) floppy2 ( + .clk ( clkcpu ), + // control signals into floppy .select (!floppy_drive[2] ), .motor_on ( motor_on ), @@ -201,7 +201,7 @@ floppy floppy2 ( .step_out ( step_out ), // status signals generated by floppy - .dclk ( fd2_dclk ), + .dclk_en ( fd2_dclk ), .track ( fd2_track ), .sector ( fd2_sector ), .sector_hdr ( fd2_sector_hdr ), @@ -221,9 +221,9 @@ wire fd3_sector_hdr; wire fd3_sector_data; wire fd3_dclk; -floppy floppy3 ( - .clk ( clk8m_en ), - +floppy #(.SYS_CLK(32000000)) floppy3 ( + .clk ( clkcpu ), + // control signals into floppy .select (!floppy_drive[3] ), .motor_on ( motor_on ), @@ -231,7 +231,7 @@ floppy floppy3 ( .step_out ( step_out ), // status signals generated by floppy - .dclk ( fd3_dclk ), + .dclk_en ( fd3_dclk ), .track ( fd3_track ), .sector ( fd3_sector ), .sector_hdr ( fd3_sector_hdr ), @@ -280,7 +280,7 @@ wire fd_sector_data = (!floppy_drive[0])?fd0_sector_data: (!floppy_drive[3])?fd3_sector_data: 1'b0; -wire fd_dclk = (!floppy_drive[0])?fd0_dclk: +wire fd_dclk_en = (!floppy_drive[0])?fd0_dclk: (!floppy_drive[1])?fd1_dclk: (!floppy_drive[2])?fd2_dclk: (!floppy_drive[3])?fd3_dclk: @@ -329,7 +329,8 @@ reg [15:0] step_rate_cnt; wire step_busy = (step_rate_cnt != 0); reg [7:0] step_to; -always @(posedge clk8m_en) begin +always @(posedge clkcpu) begin + irq_set <= 0; if(!floppy_reset) begin motor_on <= 1'b0; busy <= 1'b0; @@ -338,7 +339,7 @@ always @(posedge clk8m_en) begin irq_set <= 1'b0; data_read_start_set <= 1'b0; data_read_done_clr <= 1'b0; - end else begin + end else if (clk8m_en) begin irq_set <= 1'b0; data_read_start_set <= 1'b0; data_read_done_clr <= 1'b0; @@ -473,20 +474,9 @@ end // floppy delivers data at a floppy generated rate (usually 250kbit/s), so the start and stop // signals need to be passed forth and back from cpu clock domain to floppy data clock domain reg data_read_start_set; -reg data_read_start_clr; -reg data_read_start; -always @(posedge data_read_start_set or posedge data_read_start_clr) begin - if(data_read_start_clr) data_read_start <= 1'b0; - else data_read_start <= 1'b1; -end -reg data_read_done_set; reg data_read_done_clr; reg data_read_done; -always @(posedge data_read_done_set or posedge data_read_done_clr) begin - if(data_read_done_clr) data_read_done <= 1'b0; - else data_read_done <= 1'b1; -end // ==================================== FIFO ================================== @@ -498,11 +488,11 @@ reg [10:0] fifo_wptr; // -------------------- data write ----------------------- -always @(posedge dio_in_strobe or posedge cmd_rx) begin +always @(posedge clkcpu or posedge cmd_rx) begin if(cmd_rx) fifo_wptr <= 11'd0; else begin - if(fifo_wptr != 11'd1024) begin + if(dio_in_strobe && (fifo_wptr != 11'd1024)) begin fifo[fifo_wptr] <= dio_in; fifo_wptr <= fifo_wptr + 11'd1; end @@ -511,20 +501,18 @@ end // -------------------- data read ----------------------- -reg dclkD, dclkD2; reg [10:0] data_read_cnt; always @(posedge clkcpu) begin + reg data_read_start_setD; // reset fifo read pointer on reception of a new command if(cmd_rx) fifo_rptr <= 11'd0; - data_read_start_clr <= 1'b0; - data_read_done_set <= 1'b0; drq_set <= 1'b0; - + if (data_read_done_clr) data_read_done <= 0; + data_read_start_setD <= data_read_start_set; // received request to read data - if(data_read_start) begin - data_read_start_clr <= 1'b1; + if(~data_read_start_setD & data_read_start_set) begin // read_address command has 6 data bytes if(cmd[7:4] == 4'b1100) @@ -535,10 +523,7 @@ always @(posedge clkcpu) begin data_read_cnt <= 11'd1024+11'd1; end - // rising edge of floppy data clock (fd_dclk) - dclkD <= fd_dclk; - dclkD2 <= dclkD; - if(dclkD && !dclkD2) begin + if(fd_dclk_en) begin if(data_read_cnt != 0) begin if(data_read_cnt != 1) begin drq_set <= 1'b1; @@ -567,7 +552,7 @@ always @(posedge clkcpu) begin // count down and stop after last byte data_read_cnt <= data_read_cnt - 11'd1; if(data_read_cnt == 1) - data_read_done_set <= 1'b1; + data_read_done <= 1'b1; end end end diff --git a/cores/archie/rtl/floppy.v b/cores/archie/rtl/floppy.v index dc87f5b..a9832a2 100644 --- a/cores/archie/rtl/floppy.v +++ b/cores/archie/rtl/floppy.v @@ -25,7 +25,7 @@ module floppy ( input step_in, input step_out, - output dclk, // data clock + output dclk_en, // data clock enable output [6:0] track, // number of track under head output [3:0] sector, // number of sector under head, 0 = no sector output sector_hdr, // valid sector header under head @@ -37,7 +37,7 @@ module floppy ( // The sysclock is the value all floppy timings are derived from. // Default: 8 MHz -localparam SYS_CLK = 8000000; +parameter SYS_CLK = 8000000; assign sector_hdr = (sec_state == SECTOR_STATE_HDR); assign sector_data = (sec_state == SECTOR_STATE_DATA); @@ -70,7 +70,7 @@ assign ready = select && (rate == RATE) && (step_busy == 0); // Index pulse generation. Pulse starts with the begin of index_pulse_start // and lasts INDEX_PULSE_CYCLES system clock cycles localparam INDEX_PULSE_CYCLES = INDEX_PULSE_LEN * SYS_CLK / 1000; -reg [15:0] index_pulse_cnt; +reg [18:0] index_pulse_cnt; always @(posedge clk) begin if(index_pulse_start && (index_pulse_cnt == INDEX_PULSE_CYCLES-1)) begin index <= 1'b0; @@ -92,7 +92,7 @@ reg [6:0] current_track = 7'd0; reg step_inD; reg step_outD; -reg [17:0] step_busy; +reg [19:0] step_busy; always @(posedge clk) begin step_inD <= step_in; @@ -136,7 +136,8 @@ reg [1:0] sec_state; reg [9:0] sec_byte_cnt; // counting bytes within sectors reg [3:0] current_sector = SECTOR_BASE; -always @(posedge byte_clk) begin +always @(posedge clk) begin + if (byte_clk_en) begin if(index_pulse_start) begin sec_byte_cnt <= SECTOR_GAP_LEN-1; sec_state <= SECTOR_STATE_GAP; // track starts with gap @@ -170,6 +171,8 @@ always @(posedge byte_clk) begin end else sec_byte_cnt <= sec_byte_cnt - 10'd1; end + + end end // ================================================================ @@ -179,24 +182,31 @@ end // An ed floppy at 300rpm with 1MBit/s has max 31.250 bytes/track // thus we need to support up to 31250 events reg [14:0] byte_cnt; -reg index_pulse_start; -always @(posedge byte_clk) begin - index_pulse_start <= 1'b0; +reg index_pulse_start; +always @(posedge clk) begin + if (byte_clk_en) begin + index_pulse_start <= 1'b0; - if(byte_cnt == BPT-1) begin - byte_cnt <= 0; - index_pulse_start <= 1'b1; - end else - byte_cnt <= byte_cnt + 1; + if(byte_cnt == BPT-1) begin + byte_cnt <= 0; + index_pulse_start <= 1'b1; + end else + byte_cnt <= byte_cnt + 1; + end end // Make byte clock from bit clock. // When a DD disk spins at 300RPM every 32us a byte passes the disk head -assign dclk = byte_clk; -wire byte_clk = clk_cnt2[2]; +assign dclk_en = byte_clk_en; +reg byte_clk_en; reg [2:0] clk_cnt2; -always @(posedge data_clk) - clk_cnt2 <= clk_cnt2 + 1; +always @(posedge clk) begin + byte_clk_en <= 0; + if (data_clk_en) begin + clk_cnt2 <= clk_cnt2 + 1; + if (clk_cnt2 == 3'b011) byte_clk_en <= 1; + end +end // ================================================================ // ===================== SPIN VIRTUAL DISK ======================== @@ -246,11 +256,14 @@ end // speed and reaches the full rate when the disk rotates at 300RPM. No // valid data can be read until the disk has reached it's full speed. reg data_clk; +reg data_clk_en; reg [31:0] clk_cnt; always @(posedge clk) begin + data_clk_en <= 0; if(clk_cnt + rate > SYS_CLK/2) begin clk_cnt <= clk_cnt - (SYS_CLK/2 - rate); data_clk <= !data_clk; + if (~data_clk) data_clk_en <= 1; end else clk_cnt <= clk_cnt + rate; end