From cb13fcef8d89a397a4e4a701d0d5ed7bbc6f33a7 Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi Date: Tue, 22 Oct 2019 19:55:27 +0200 Subject: [PATCH] Archie: use 2 deterministic places for requesting new data in VIDC --- cores/archie/rtl/vidc_dmachannel.v | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cores/archie/rtl/vidc_dmachannel.v b/cores/archie/rtl/vidc_dmachannel.v index 0773e71..0ae5425 100644 --- a/cores/archie/rtl/vidc_dmachannel.v +++ b/cores/archie/rtl/vidc_dmachannel.v @@ -116,7 +116,7 @@ end // TODO: use bits 4 and 5 of fifo control register for requesting new data to the video fifo. // But the RAM timing is so different from the original machine that it won't be useful -assign fifo_can_load = ~stall && ((!FIFO4WORDS && wrusedw <= 4) || (FIFO4WORDS && wrusedw == 0)); +assign fifo_can_load = ~stall && ((!FIFO4WORDS && wrusedw == 4) || wrusedw == 0); assign busy = load; endmodule