diff --git a/cores/mist/mfp_timer.v b/cores/mist/mfp_timer.v
index 6bc245f..b9943ec 100644
--- a/cores/mist/mfp_timer.v
+++ b/cores/mist/mfp_timer.v
@@ -51,7 +51,7 @@ always @(posedge XCLK_I) begin
 	if(RST === 1'b1) 
       prescaler_counter <= 8'd0;
 	else begin
-		if(prescaler_counter >= prescaler)
+ 		if(prescaler_counter >= prescaler-1)
 			prescaler_counter <= 8'd0;
 		else
 			prescaler_counter <= prescaler_counter + 8'd1;
diff --git a/cores/mist/mist_top.v b/cores/mist/mist_top.v
index ec2de5b..474d235 100644
--- a/cores/mist/mist_top.v
+++ b/cores/mist/mist_top.v
@@ -1,7 +1,7 @@
 /********************************************/
 /*                                          */
 /********************************************/
-
+ 
 module mist_top ( 
   // clock inputsxque	
   input wire [ 2-1:0] 	CLOCK_27, // 27 MHz
@@ -1008,6 +1008,10 @@ wire MEM14M  = (system_ctrl[3:1] == 3'd5);
 // rom is also at 0x000000 to 0x000007
 wire cpu2lowrom = (tg68_adr[23:3] == 21'd0);
 
+// the viking card has ram at 0xc00000 only in st/ste/mega ste mode. In STEroids the
+// video memory is at 0xe80000 and is always enabled
+wire viking_at_c0 = viking_enable && !steroids;
+
 // ordinary ram from 0x000000 to 0x400000, more if enabled
 wire cpu2ram = (!cpu2lowrom) && (
 								  (tg68_adr[23:22] == 2'b00)     ||  // ordinary 4MB
@@ -1015,7 +1019,7 @@ wire cpu2ram = (!cpu2lowrom) && (
 	(MEM14M            && ((tg68_adr[23:22] == 2'b10)     ||  // 12MB
 	                       (tg68_adr[23:21] == 3'b110)))  ||  // 14MB
 	(steroids          &&  (tg68_adr[23:19] == 5'b11101)) ||  // 512k at $e80000 for STEroids
-	(viking_enable     &&  (tg68_adr[23:18] == 6'b110000))    // 256k at 0xc00000 for viking card
+	(viking_at_c0      &&  (tg68_adr[23:18] == 6'b110000))    // 256k at 0xc00000 for viking card
 );
 
 // 256k tos from 0xe00000 to 0xe40000
diff --git a/cores/mist/user_io.v b/cores/mist/user_io.v
index bf7e553..3ca5f63 100644
--- a/cores/mist/user_io.v
+++ b/cores/mist/user_io.v
@@ -57,6 +57,10 @@ module user_io(
 		output [1:0]     SWITCHES
 );
 
+// filter spi clock. the 8 bit gate delay is ~2.5ns in total
+wire [7:0] spi_sck_D = { spi_sck_D[6:0], SPI_CLK } /* synthesis keep */;
+wire spi_sck = (spi_sck && spi_sck_D != 8'h00) || (!spi_sck && spi_sck_D == 8'hff);
+
 	reg [1:0] 			byte_cnt;
    reg [6:0]         sbuf;
    reg [7:0]         cmd;
@@ -69,7 +73,7 @@ module user_io(
 	assign BUTTONS = but_sw[1:0];
 	assign SWITCHES = but_sw[3:2];
    
-   always@(negedge SPI_CLK) begin
+   always@(negedge spi_sck) begin
       if(bit_cnt <= 7)
 		  SPI_MISO <= CORE_TYPE[7-bit_cnt];
 		else begin
@@ -115,7 +119,7 @@ module user_io(
 		end
 	end
 		
-   always@(posedge SPI_CLK, posedge SPI_SS_IO) begin
+   always@(posedge spi_sck, posedge SPI_SS_IO) begin
 		if(SPI_SS_IO == 1) begin
         bit_cnt <= 4'd0;
 		  byte_cnt <= 2'd0;