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Ethernec work started
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harbaum
parent
279329ede0
commit
d047f3fa05
@ -1,117 +0,0 @@
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module dongle (
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// cpu register interface
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input clk,
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input sel,
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input cpu_as, // cpu_cycle && as
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input uds,
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input rw,
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input [14:0] addr,
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output reg [7:0] dout,
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output present
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);
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assign present = 1'b0; // 0 = deactivate dongle
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// ------------------------------------------------------------------------------------
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// ------------------------------------ CUBASE 2 DONGLE -------------------------------
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// ------------------------------------------------------------------------------------
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reg [15:8] d;
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reg [15:8] next_d;
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// read
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always @(sel, uds, rw, d) begin
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dout = 8'd0;
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if(sel && ~uds && rw)
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dout = d;
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end
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wire [8:1] a = addr[7:0];
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// special addresses:
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// a[8:1] = 8'b11011000,0 -> 0x1b0 clear all
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// a[8:1] = 8'bxxx00xx0,0 -> a5+a4+a1 = 0 sets all, incl. $0c
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// update register in the middle of the transfer
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always @(negedge clk) begin
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if(cpu_as && ~uds) begin
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next_d[15] <= !(( a[8] & a[7] & !a[6] & a[5] & a[4] & !a[3] & !a[2] & !a[1]) |
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(!d[15] & !d[14] & !d[13] & !d[12] & !d[11] & d[10] & !d[9] & a[4] ) |
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( d[14] & d[12] & d[10] & a[1]) |
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( d[13] & !d[10] & a[4] ) |
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( !d[14] & !d[10] & a[1]) |
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( d[15] & !d[10] & a[4] ) |
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( !d[12] & !d[10] & a[1]) |
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(!d[8] & a[5] ));
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next_d[14] <= !(( a[8] & a[7] & !a[6] & a[5] & a[4] & !a[3] & !a[2] & !a[1]) |
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(!d[15] & !d[14] & !d[13] & !d[12] & !d[11] & !d[10] & !d[9] & d[8] & a[4] ) |
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( d[14] & d[12] & d[10] & d[8] & a[1]) |
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( !d[10] & !d[8] & a[1]) |
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( !d[12] & !d[8] & a[1]) |
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( d[15] & !d[8] & a[4] ) |
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( !d[14] & !d[8] & a[1]) |
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(!d[15] & a[5] ));
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next_d[13] <= !(( a[8] & a[7] & !a[6] & a[5] & a[4] & !a[3] & !a[2] & !a[1]) |
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(d[15]&d[14]&d[13]&d[12]&d[11]&d[10]&d[8]&a[1]) |
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(!d[15]&!d[13]&d[11]&a[4]) |
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(d[13]&!d[11]&a[4]) |
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(!d[12]&!d[11]&a[1]) |
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(d[15]&!d[11]&a[4]) |
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(!d[14]&!d[11]&a[1]) |
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(!d[9]&a[5]));
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next_d[12] <= !(( a[8] & a[7] & !a[6] & a[5] & a[4] & !a[3] & !a[2] & !a[1]) |
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(d[15]&d[14]&d[13]&d[12]&d[10]&d[8]&a[1]) |
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(!d[13]&!d[10]&a[1]) |
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(!d[15]&d[13]&a[4]) |
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(!d[13]&!d[12]&a[1]) |
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(d[15]&!d[13]&a[4]) |
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(!d[14]&!d[13]&a[1]) |
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(!d[11]&a[5]));
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next_d[11] <= !(( a[8] & a[7] & !a[6] & a[5] & a[4] & !a[3] & !a[2] & !a[1]) |
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(d[15]&d[14]&d[12]&d[10]&d[8]&a[1]) |
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(!d[15]&!d[8]&a[1]) |
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(!d[15]&!d[10]&a[1]) |
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(!d[15]&!d[12]&a[1]) |
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(!d[15]&!d[14]&a[1]) |
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(d[15]&a[4]) |
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(!d[13]&a[5]));
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next_d[10] <= !(( a[8] & a[7] & !a[6] & a[5] & a[4] & !a[3] & !a[2] & !a[1]) |
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(d[15]&d[14]&d[13]&d[12]&d[11]&d[10]&d[9]&d[8]&a[1]) |
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(!d[15]&!d[13]&!d[11]&d[9]&a[4]) |
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(d[11]&!d[9]&a[4]) |
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(d[13]&!d[9]&a[4]) |
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(d[15]&!d[9]&a[4]) |
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(!d[14]&!d[9]&a[1]) |
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(!d[14]&a[5]));
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next_d[9] <= !(( a[8] & a[7] & !a[6] & a[5] & a[4] & !a[3] & !a[2] & !a[1]) |
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(!d[15]&d[14]&!d[13]&!d[11]&!d[9]&a[4]) |
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(!d[14]&d[9]&a[4]) |
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(!d[14]&d[11]&a[4]) |
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(!d[14]&d[13]&a[4]) |
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(d[15]&!d[14]&a[4]) |
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(d[14]&a[1]) |
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(!d[12]&a[5]));
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next_d[8] <= !(( a[8] & a[7] & !a[6] & a[5] & a[4] & !a[3] & !a[2] & !a[1]) |
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(!d[15]&!d[14]&!d[13]&d[12]&!d[11]&!d[9]&a[4]) |
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(d[14]&d[12]&a[1]) |
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(!d[12]&d[11]&a[4]) |
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(d[13]&!d[12]&a[4]) |
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(d[15]&!d[12]&a[4]) |
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(!d[14]&!d[12]&a[1]) |
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(!d[10]&a[5]));
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end
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end
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always @(posedge clk)
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d <= next_d;
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endmodule
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@ -308,7 +308,7 @@ set_instance_assignment -name GLOBAL_SIGNAL "GLOBAL CLOCK" -to clk_32
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set_global_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION ON
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set_global_assignment -name VERILOG_FILE cache.v
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set_global_assignment -name VERILOG_FILE dongle.v
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set_global_assignment -name VERILOG_FILE ethernec.v
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set_global_assignment -name VERILOG_FILE mfp_timer.v
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set_global_assignment -name VHDL_FILE vol_table_array.vhd
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set_global_assignment -name VHDL_FILE YM2149_volmix.vhd
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@ -2,7 +2,7 @@
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/* */
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/********************************************/
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module mist_top (
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module mist_top (
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// clock inputsxque
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input wire [ 2-1:0] CLOCK_27, // 27 MHz
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// LED outputs
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@ -54,7 +54,8 @@ wire [15:0] video_adj;
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// generate dtack for all implemented peripherals
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wire io_dtack = vreg_sel || mmu_sel || mfp_sel || mfp_iack ||
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acia_sel || psg_sel || dma_sel || auto_iack || blitter_sel ||
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ste_joy_sel || ste_dma_snd_sel || mste_ctrl_sel || vme_sel || dongle_sel;
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ste_joy_sel || ste_dma_snd_sel || mste_ctrl_sel || vme_sel ||
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rom_sel[1] || rom_sel[0];
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// the original tg68k did not contain working support for bus fault exceptions. While earlier
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// TOS versions cope with that, TOS versions with blitter support need this to work as this is
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@ -122,7 +123,7 @@ always @(negedge clk_8)
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if(video_cycle)
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br <= data_io_br || blitter_br;
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`endif
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// request interrupt ack from mfp for IPL == 6
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wire mfp_iack = cpu_cycle && cpu2iack && tg68_as && (tg68_adr[3:1] == 3'b110);
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@ -146,10 +147,14 @@ wire [7:0] auto_vector = auto_vector_vbi | auto_vector_hbi;
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// $ffff8e00 - $ffff8e0f - VME (only fake implementation)
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wire io_sel = cpu_cycle && cpu2io && tg68_as ;
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// dongle interface at $fb0000 - $fbffff
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wire dongle_sel = dongle_present && cpu_cycle && tg68_as && tg68_rw && (tg68_adr[23:16] == 8'hfb);
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wire [7:0] dongle_data_out;
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// TODO: from sysconfig
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wire ethernec_present = 1'b1;
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// romport interface at $fa0000 - $fbffff
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wire rom_sel_all = ethernec_present && cpu_cycle && tg68_as && tg68_rw && ({tg68_adr[23:17], 1'b0} == 8'hfa);
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wire [1:0] rom_sel = { rom_sel_all && tg68_adr[16], rom_sel_all && !tg68_adr[16] };
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wire [15:0] rom_data_out;
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// mmu 8 bit interface at $ff8000 - $ff8001
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wire mmu_sel = io_sel && ({tg68_adr[15:1], 1'd0} == 16'h8000);
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@ -197,10 +202,10 @@ wire dma_sel = io_sel && ({tg68_adr[15:4], 4'd0} == 16'h8600);
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wire [15:0] dma_data_out;
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// de-multiplex the various io data output ports into one
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wire [7:0] io_data_out_8u = acia_data_out | psg_data_out | dongle_data_out;
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wire [7:0] io_data_out_8u = acia_data_out | psg_data_out;
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wire [7:0] io_data_out_8l = mmu_data_out | mfp_data_out | auto_vector | mste_ctrl_data_out;
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wire [15:0] io_data_out = vreg_data_out | dma_data_out | blitter_data_out |
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ste_joy_data_out | ste_dma_snd_data_out |
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ste_joy_data_out | ste_dma_snd_data_out | rom_data_out |
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{8'h00, io_data_out_8l} | {io_data_out_8u, 8'h00};
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wire init = ~pll_locked;
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@ -391,16 +396,13 @@ ste_joystick ste_joystick (
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.dout (ste_joy_data_out),
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);
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wire dongle_present; // true if the dongle modules contains functonality
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dongle dongle (
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ethernec ethernec (
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.clk (clk_8 ),
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.sel (dongle_sel ),
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.present (dongle_present),
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.sel (rom_sel ),
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.addr (tg68_adr[15:1]),
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.cpu_as (cpu_cycle && tg68_as && !br),
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.lds (tg68_lds ),
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.uds (tg68_uds ),
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.rw (tg68_rw ),
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.dout (dongle_data_out)
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.dout (rom_data_out)
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);
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wire [22:0] ste_dma_snd_addr;
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@ -944,8 +946,7 @@ wire cpu2tos192k = (tg68_adr[23:17] == 7'b1111110) ||
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(tg68_adr[23:16] == 8'b11111110);
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// 128k cartridge from 0xfa0000 to 0xfbffff
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wire cpu2cart = (tg68_adr[23:16] == 8'hfa) ||
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((tg68_adr[23:16] == 8'hfb) && !dongle_present); // include fb0000 only if no dongle present
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wire cpu2cart = ({tg68_adr[23:17], 1'b0} == 8'hfa) && !ethernec_present;
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// all rom areas
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wire cpu2rom = cpu2lowrom || cpu2tos192k || cpu2tos256k || cpu2cart;
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