diff --git a/cores/c64/C64_mist.srf b/cores/c64/C64_mist.srf deleted file mode 100644 index cf803e2..0000000 --- a/cores/c64/C64_mist.srf +++ /dev/null @@ -1,6 +0,0 @@ -{ "" "" "" "Verilog HDL macro warning at hq2x.sv(26): overriding existing definition for macro \"BITS_TO_FIT\", which was defined in \"rtl/scandoubler.v\", line 109" { } { } 0 10274 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL warning at hq2x.sv(247): extended using \"x\" or \"z\"" { } { } 0 10273 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "Verilog HDL information at scandoubler.v(102): always construct contains both blocking and non-blocking assignments" { } { } 0 10268 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "2 hierarchies have connectivity warnings - see the Connectivity Checks report folder" { } { } 0 12241 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 10230 "" 0 0 "Quartus II" 0 -1 0 ""} -{ "" "" "" "*" { } { } 0 332060 "" 0 0 "Quartus II" 0 -1 0 ""} diff --git a/cores/c64/rtl/mist/c64_mist.vhd b/cores/c64/rtl/mist/c64_mist.vhd index 8d81d92..46fdb1e 100644 --- a/cores/c64/rtl/mist/c64_mist.vhd +++ b/cores/c64/rtl/mist/c64_mist.vhd @@ -102,31 +102,6 @@ component sdram is port ); end component; -component sram is port -( - init : in std_logic; - clk : in std_logic; - SDRAM_DQ : inout std_logic_vector(15 downto 0); - SDRAM_A : out std_logic_vector(12 downto 0); - SDRAM_DQML : out std_logic; - SDRAM_DQMH : out std_logic; - SDRAM_BA : out std_logic_vector(1 downto 0); - SDRAM_nCS : out std_logic; - SDRAM_nWE : out std_logic; - SDRAM_nRAS : out std_logic; - SDRAM_nCAS : out std_logic; - SDRAM_CKE : out std_logic; - - wtbt : in std_logic_vector(1 downto 0); - addr : in std_logic_vector(24 downto 0); - dout : out std_logic_vector(15 downto 0); - din : in std_logic_vector(15 downto 0); - we : in std_logic; - rd : in std_logic; - ready : out std_logic -); -end component; - constant CONF_STR : string := "C64;;"& "S,D64,Mount Disk;"& @@ -218,9 +193,7 @@ component data_io port ( clk_sys : in std_logic; SPI_SCK, SPI_SS2, SPI_DI :in std_logic; - ioctl_force_erase : in std_logic; ioctl_download : out std_logic; - ioctl_erasing : out std_logic; ioctl_index : out std_logic_vector(7 downto 0); ioctl_wr : out std_logic; ioctl_addr : out std_logic_vector(24 downto 0); @@ -347,8 +320,6 @@ end component cartridge; signal ioctl_load_addr : std_logic_vector(24 downto 0); signal ioctl_ram_wr: std_logic; signal ioctl_iec_cycle_used: std_logic; - signal ioctl_force_erase: std_logic; - signal ioctl_erasing: std_logic; signal ioctl_download: std_logic; signal c64_addr: std_logic_vector(15 downto 0); signal c64_data_in: std_logic_vector(7 downto 0); @@ -622,8 +593,6 @@ begin st_ntsc <= status(2); st_reset <= status(0); - ioctl_force_erase <= '0'; - data_io_d: data_io port map ( clk_sys => clk_c64, @@ -632,8 +601,6 @@ begin SPI_DI => SPI_DI, ioctl_download => ioctl_download, - ioctl_force_erase => ioctl_force_erase, - ioctl_erasing => ioctl_erasing, ioctl_index => ioctl_index, ioctl_wr => ioctl_wr, ioctl_addr => ioctl_addr, @@ -884,16 +851,16 @@ begin pll_scanclkena => pll_scanclkena, pll_scandata => pll_scandata, pll_scandataout => pll_scandataout, - pll_scandone => pll_scandone, + pll_scandone => pll_scandone, read_param => '0', - reconfig => pll_reconfig, + reconfig => pll_reconfig, reset => pll_reconfig_reset, reset_rom_address => '0', rom_address_out => pll_rom_address, rom_data_in => pll_rom_q, write_from_rom => pll_write_from_rom, write_param => '0', - write_rom_ena => pll_write_rom_ena + write_rom_ena => pll_write_rom_ena ); process(clk32) @@ -1134,7 +1101,7 @@ begin end process; -- connect user port - process (pa2_out, pb_out, joyC_c64, joyD_c64, uart_rxD2, st_user_port_uart) + process (pa2_out, pb_out, joyC_c64, joyD_c64, uart_rxD2, st_user_port_uart, cass_motor) begin pa2_in <= pa2_out; if st_user_port_uart = '0' then @@ -1179,8 +1146,8 @@ begin disk_readonly <= st_disk_readonly; - c64_iec_data_i <= c1541_iec_data_o; - c64_iec_clk_i <= c1541_iec_clk_o; + c64_iec_data_i <= c1541_iec_data_o; + c64_iec_clk_i <= c1541_iec_clk_o; c1541_iec_atn_i <= c64_iec_atn_o; c1541_iec_data_i <= c64_iec_data_o; diff --git a/cores/c64/rtl/mist/data_io.v b/cores/c64/rtl/mist/data_io.v index aa56a89..2c29c87 100644 --- a/cores/c64/rtl/mist/data_io.v +++ b/cores/c64/rtl/mist/data_io.v @@ -31,9 +31,7 @@ module data_io input SPI_DI, // ARM -> FPGA download - input ioctl_force_erase, output reg ioctl_download = 0, // signal indicating an active download - output reg ioctl_erasing = 0, // signal indicating an active erase output reg [7:0] ioctl_index, // menu index used to upload the file output reg ioctl_wr = 0, output reg [24:0] ioctl_addr, @@ -95,19 +93,13 @@ always@(posedge SPI_SCK, posedge SPI_SS2) begin rclk <= 1; end - // expose file (menu) index - if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; + // expose file (menu) index + if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; end end -reg [24:0] erase_mask; -wire [24:0] next_erase = (ioctl_addr + 1'd1) & erase_mask; - always@(posedge clk_sys) begin reg rclkD, rclkD2; - reg old_force = 0; - reg [6:0] erase_clk_div; - reg [24:0] end_addr; rclkD <= rclk; rclkD2 <= rclkD; @@ -119,30 +111,6 @@ always@(posedge clk_sys) begin ioctl_wr <= 1; end - if(ioctl_download) begin - old_force <= 0; - ioctl_erasing <= 0; - end else begin - - old_force <= ioctl_force_erase; - if(ioctl_force_erase & ~old_force) begin - ioctl_addr <= 'h1FFFF; - erase_mask <= 'h1FFFF; - end_addr <= 'h10002; - erase_clk_div <= 1; - ioctl_erasing <= 1; - end else if(ioctl_erasing) begin - erase_clk_div <= erase_clk_div + 1'd1; - if(!erase_clk_div) begin - if(next_erase == end_addr) ioctl_erasing <= 0; - else begin - ioctl_addr <= next_erase; - ioctl_dout <= 0; - ioctl_wr <= 1; - end - end - end - end end endmodule \ No newline at end of file