diff --git a/cores/c64/C64_mist.qsf b/cores/c64/C64_mist.qsf index cff9bc3..63b23f7 100644 --- a/cores/c64/C64_mist.qsf +++ b/cores/c64/C64_mist.qsf @@ -126,7 +126,7 @@ set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 # Analysis & Synthesis Assignments # ================================ -set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE SPEED +set_global_assignment -name CYCLONEII_OPTIMIZATION_TECHNIQUE BALANCED set_global_assignment -name FAMILY "Cyclone III" set_global_assignment -name TOP_LEVEL_ENTITY c64_mist set_global_assignment -name DEVICE_FILTER_PACKAGE TQFP @@ -166,7 +166,7 @@ set_global_assignment -name USE_CONFIGURATION_DEVICE OFF # SignalTap II Assignments # ======================== set_global_assignment -name ENABLE_SIGNALTAP OFF -set_global_assignment -name USE_SIGNALTAP_FILE stp1.stp +set_global_assignment -name USE_SIGNALTAP_FILE output_files/sid.stp # Power Estimation Assignments # ============================ @@ -320,6 +320,10 @@ set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to CONF_DATA0 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top set_global_assignment -name PARTITION_FITTER_PRESERVATION_LEVEL PLACEMENT_AND_ROUTING -section_id Top set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top +set_global_assignment -name VERILOG_FILE rtl/sid8580/sid_voice.v +set_global_assignment -name VERILOG_FILE rtl/sid8580/sid_filters.v +set_global_assignment -name VERILOG_FILE rtl/sid8580/sid_envelope.v +set_global_assignment -name VERILOG_FILE rtl/sid8580/sid8580.v set_global_assignment -name VERILOG_FILE rtl/mist/sigma_delta_dac.v set_global_assignment -name SYSTEMVERILOG_FILE rtl/mist/video_mixer.sv set_global_assignment -name VERILOG_FILE rtl/mist/user_io.v @@ -359,10 +363,6 @@ set_global_assignment -name VHDL_FILE rtl/sid/oscillator.vhd set_global_assignment -name VHDL_FILE rtl/sid/my_math_pkg.vhd set_global_assignment -name VHDL_FILE rtl/sid/mult_acc.vhd set_global_assignment -name VHDL_FILE rtl/sid/adsr_multi.vhd -set_global_assignment -name SYSTEMVERILOG_FILE rtl/sid8580/sid_voice.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/sid8580/sid_filters.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/sid8580/sid_envelope.sv -set_global_assignment -name SYSTEMVERILOG_FILE rtl/sid8580/sid8580.sv set_global_assignment -name VHDL_FILE rtl/c1541/via6522.vhd set_global_assignment -name VHDL_FILE rtl/c1541/spram.vhd set_global_assignment -name VHDL_FILE rtl/c1541/spi_controller.vhd @@ -375,4 +375,6 @@ set_global_assignment -name VHDL_FILE rtl/t65/T65_Pack.vhd set_global_assignment -name VHDL_FILE rtl/t65/T65_MCode.vhd set_global_assignment -name VHDL_FILE rtl/t65/T65_ALU.vhd set_global_assignment -name VHDL_FILE rtl/t65/T65.vhd +set_global_assignment -name AUTO_SHIFT_REGISTER_RECOGNITION OFF +set_global_assignment -name SIGNALTAP_FILE output_files/sid.stp set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/cores/c64/rtl/c1541/c1541_sd.vhd b/cores/c64/rtl/c1541/c1541_sd.vhd index 6f29f65..1fe44ae 100644 --- a/cores/c64/rtl/c1541/c1541_sd.vhd +++ b/cores/c64/rtl/c1541/c1541_sd.vhd @@ -110,6 +110,9 @@ signal track_modified : std_logic; signal sector_offset : std_logic; signal save_track_stage : std_logic_vector(3 downto 0); +signal wps_flag : std_logic; +signal change_timer : integer; + signal dbg_sector : std_logic_vector(4 downto 0); signal dbg_adr_fetch : std_logic_vector(15 downto 0); @@ -172,7 +175,7 @@ begin freq => freq, -- motor frequency sync_n => sync_n, -- reading SYNC bytes byte_n => byte_n, -- byte ready - wps_n => not disk_readonly, -- write-protect sense (0 = protected) + wps_n => not wps_flag, -- write-protect sense (0 = protected) tr00_sense_n => '1', -- track 0 sense (unused?) act => act, -- activity LED @@ -266,7 +269,22 @@ port map -- -- dbg_state => dbg_sd_state --); - + +wps_flag <= disk_readonly when change_timer = 0 else not disk_readonly; + +process (clk32,reset) +begin + if reset = '1' then + change_timer <= 0; + elsif rising_edge(clk32) then + if disk_change = '1' then + change_timer <= 1000000; + elsif change_timer /= 0 then + change_timer <= change_timer - 1; + end if; + end if; +end process; + process (clk32) begin if rising_edge(clk32) then diff --git a/cores/c64/rtl/fpga64_sid_iec.vhd b/cores/c64/rtl/fpga64_sid_iec.vhd index e06f151..89bae2d 100644 --- a/cores/c64/rtl/fpga64_sid_iec.vhd +++ b/cores/c64/rtl/fpga64_sid_iec.vhd @@ -97,9 +97,10 @@ entity fpga64_sid_iec is --Connector to the SID SIDclk : buffer std_logic; still : out unsigned(15 downto 0); - audio_data : out std_logic_vector(17 downto 0); + audio_data_l: out std_logic_vector(17 downto 0); + audio_data_r: out std_logic_vector(17 downto 0); extfilter_en: in std_logic; - sid_ver : in std_logic; + sid_mode : in std_logic_vector(1 downto 0); -- IEC iec_data_o : out std_logic; @@ -189,6 +190,7 @@ architecture rtl of fpga64_sid_iec is signal sid_do : std_logic_vector(7 downto 0); signal sid_do6581 : std_logic_vector(7 downto 0); signal sid_do8580 : std_logic_vector(7 downto 0); + signal second_sid_en: std_logic; -- CIA signals signal enableCia : std_logic; @@ -262,7 +264,8 @@ architecture rtl of fpga64_sid_iec is signal restore_key : std_logic; signal clk_1MHz : std_logic_vector(31 downto 0); - signal voice_volume : signed(17 downto 0); + signal voice_l : signed(17 downto 0); + signal voice_r : signed(17 downto 0); signal pot_x : std_logic_vector(7 downto 0); signal pot_y : std_logic_vector(7 downto 0); signal audio_8580 : std_logic_vector(15 downto 0); @@ -270,8 +273,9 @@ architecture rtl of fpga64_sid_iec is component sid8580 port ( reset : in std_logic; - clk : in std_logic; - ce_1m : in std_logic; + cs : in std_logic; + clk32 : in std_logic; + clk_1MHz : in std_logic; we : in std_logic; addr : in std_logic_vector(4 downto 0); data_in : in std_logic_vector(7 downto 0); @@ -570,18 +574,29 @@ div1m: process(clk32) -- this process devides 32 MHz to 1MHz (for the SID) end if; end process; - audio_data <= std_logic_vector(voice_volume) when sid_ver='0' else (audio_8580 & "00"); - sid_do <= sid_do6581 when sid_ver='0' else sid_do8580; + audio_data_l <= std_logic_vector(voice_l) when sid_mode(1)='0' else + (audio_8580 & "00"); + audio_data_r <= std_logic_vector(voice_l) when sid_mode="00" else + std_logic_vector(voice_r) when sid_mode="01" else + (audio_8580 & "00"); + sid_do <= sid_do6581 when sid_mode(1)='0' else sid_do8580; pot_x <= X"FF" when ((cia1_pao(7) and JoyA(5)) or (cia1_pao(6) and JoyB(5))) = '0' else X"00"; pot_y <= X"FF" when ((cia1_pao(7) and JoyA(6)) or (cia1_pao(6) and JoyB(6))) = '0' else X"00"; + second_sid_en <= '0' when sid_mode(0) = '0' else + '1' when cpuAddr(11 downto 8) = x"4" and cpuAddr(5) = '1' else -- D420 + '1' when cpuAddr(11 downto 8) = x"5" else -- D500 + '0'; sid_6581: entity work.sid_top + generic map ( + g_num_voices => 16 + ) port map ( clock => clk32, reset => reset, - addr => "000" & cpuAddr(4 downto 0), + addr => second_sid_en & "00" & cpuAddr(4 downto 0), wren => pulseWrRam and phi0_cpu and cs_sid, wdata => std_logic_vector(cpuDo), rdata => sid_do6581, @@ -595,16 +610,17 @@ div1m: process(clk32) -- this process devides 32 MHz to 1MHz (for the SID) extfilter_en => extfilter_en, start_iter => clk_1MHz(31), - sample_left => voice_volume, - sample_right => open + sample_left => voice_l, + sample_right => voice_r ); sid_8580 : sid8580 port map ( reset => reset, - clk => clk32, - ce_1m => clk_1MHz(31), - we => pulseWrRam and phi0_cpu and cs_sid, + clk32 => clk32, + clk_1MHz => clk_1MHz(31), + cs => cs_sid, + we => pulseWrRam and phi0_cpu, addr => std_logic_vector(cpuAddr(4 downto 0)), data_in => std_logic_vector(cpuDo), data_out => sid_do8580, @@ -612,7 +628,7 @@ div1m: process(clk32) -- this process devides 32 MHz to 1MHz (for the SID) pot_y => pot_y, audio_data => audio_8580, extfilter_en => extfilter_en -); +); -- ----------------------------------------------------------------------- -- CIAs diff --git a/cores/c64/rtl/mist/c64_mist.vhd b/cores/c64/rtl/mist/c64_mist.vhd index 7dbdb53..7093efa 100644 --- a/cores/c64/rtl/mist/c64_mist.vhd +++ b/cores/c64/rtl/mist/c64_mist.vhd @@ -128,10 +128,10 @@ constant CONF_STR : string := "F,CRT,Load Cartridge;" &--3 -- "F,TAP,Load File;"&--4 -- "F,T64,Load File;"&--5 - "OE,Disk Write,Enable,Disable;"& + "OF,Disk Write,Enable,Disable;"& "O2,Video standard,PAL,NTSC;"& "O8A,Scandoubler Fx,None,HQ2x-320,HQ2x-160,CRT 25%,CRT 50%;"& - "OD,SID,6581,8580;"& + "ODE,SID,6581 Mono,6581 Stereo,8580;"& "O3,Joysticks,normal,swapped;"& "O6,Audio filter,On,Off;"& "O4,CIA Model,6256,8521;"& @@ -436,7 +436,8 @@ end component cartridge; signal hsync_out : std_logic; signal vsync_out : std_logic; - signal audio_data : std_logic_vector(17 downto 0); + signal audio_data_l : std_logic_vector(17 downto 0); + signal audio_data_r : std_logic_vector(17 downto 0); signal reset_counter : integer; signal reset_n : std_logic; @@ -780,14 +781,14 @@ begin ce => sdram_ce ); - dac : sigma_delta_dac - port map ( - clk => clk32, - ldatasum => audio_data(17 downto 3), - rdatasum => audio_data(17 downto 3), + dac : sigma_delta_dac + port map ( + clk => clk32, + ldatasum => audio_data_l(17 downto 3), + rdatasum => audio_data_r(17 downto 3), aleft => AUDIO_L, aright => AUDIO_R - ); + ); fpga64 : entity work.fpga64_sid_iec @@ -834,9 +835,10 @@ begin SIDclk => open, still => open, idle => idle, - audio_data => audio_data, + audio_data_l => audio_data_l, + audio_data_r => audio_data_r, extfilter_en => not status(6), - sid_ver => status(13), + sid_mode => status(14 downto 13), iec_data_o => c64_iec_data_o, iec_atn_o => c64_iec_atn_o, iec_clk_o => c64_iec_clk_o, @@ -852,7 +854,7 @@ begin reset_key => reset_key ); - disk_readonly <= status(14); + disk_readonly <= status(15); c64_iec_data_i <= c1541_iec_data_o; c64_iec_clk_i <= c1541_iec_clk_o; diff --git a/cores/c64/rtl/mos6526.v b/cores/c64/rtl/mos6526.v index d4cd9ca..7f44a03 100644 --- a/cores/c64/rtl/mos6526.v +++ b/cores/c64/rtl/mos6526.v @@ -96,15 +96,10 @@ always @(posedge clk) begin 4'h5: db_out <= timer_a[15:8]; 4'h6: db_out <= timer_b[ 7:0]; 4'h7: db_out <= timer_b[15:8]; - 4'h8: db_out <= tod_latched ? - {4'h0, tod_latch[3:0]} : {4'h0, tod_10ths}; - 4'h9: db_out <= tod_latched ? - {1'b0, tod_latch[10:4]} : {1'b0, tod_sec}; - 4'ha: db_out <= tod_latched ? - {1'b0, tod_latch[17:11]} : {1'b0, tod_min}; - 4'hb: db_out <= tod_latched ? - {tod_latch[23], 2'h0, tod_latch[22:18]} : - {tod_hr[5], 2'h0, tod_hr[4:0]}; + 4'h8: db_out <= {4'h0, tod_latch[3:0]}; + 4'h9: db_out <= {1'b0, tod_latch[10:4]}; + 4'ha: db_out <= {1'b0, tod_latch[17:11]}; + 4'hb: db_out <= {tod_latch[23], 2'h0, tod_latch[22:18]}; 4'hc: db_out <= sdr; 4'hd: db_out <= {~irq_n, 2'b00, icr}; 4'he: db_out <= {cra[7:5], 1'b0, cra[3:0]}; @@ -310,17 +305,31 @@ always @(posedge clk) begin tod_latched <= 1'b0; icr[2] <= 1'b0; end + else if (!cs_n && rw) + case (rs) + 4'h8: tod_latched <= 1'b0; + 4'hb: tod_latched <= 1'b1; + default: tod_latched <= tod_latched; + endcase else if (!cs_n && !rw) case (rs) 4'h8: if (crb[7]) tod_alarm[3:0] <= db_in[3:0]; - else tod_10ths <= db_in[3:0]; + else begin + tod_run <= 1'b1; + tod_10ths <= db_in[3:0]; + end 4'h9: if (crb[7]) tod_alarm[10:4] <= db_in[6:0]; else tod_sec <= db_in[6:0]; 4'ha: if (crb[7]) tod_alarm[17:11] <= db_in[6:0]; else tod_min <= db_in[6:0]; 4'hb: if (crb[7]) tod_alarm[23:18] <= {db_in[7], db_in[4:0]}; - else tod_hr <= {db_in[7], db_in[4:0]}; + else begin + tod_run <= 1'b0; + if (db_in[4:0] == 5'h12) tod_hr <= {~db_in[7], db_in[4:0]}; + else tod_hr <= {db_in[7], db_in[4:0]}; + end default: begin + tod_run <= tod_run; tod_10ths <= tod_10ths; tod_sec <= tod_sec; tod_min <= tod_min; @@ -328,19 +337,6 @@ always @(posedge clk) begin tod_alarm <= tod_alarm; end endcase - if (!cs_n) - if (rs == 4'h8) - if (!rw) tod_run <= !crb[7] ? 1'b1 : tod_run; - else begin - tod_latched <= 1'b0; - tod_latch <= 24'h000000; - end - else if (rs == 4'hb) - if (!rw) tod_run <= !crb[7] ? 1'b0 : tod_run; - else begin - tod_latched <= 1'b1; - tod_latch <= {tod_hr, tod_min, tod_sec, tod_10ths}; - end tod_prev <= tod; tod_tick <= 1'b0; if (tod_run) begin @@ -370,19 +366,11 @@ always @(posedge clk) begin tod_hr[3:0] <= tod_hr[3:0] + 1'b1; end if (tod_hr[3:0] == 4'h9 && tod_min == 7'h59 && tod_sec == 7'h59) begin - tod_hr[3:0] <= 4'h0; - tod_hr[4] <= tod_hr[4] + 1'b1; + tod_hr[4] <= 1'b1; + tod_hr[3:0] <= tod_hr[4] ? tod_hr[3:0] + 1'b1 : 4'h0; end if (tod_min == 7'h59 && tod_sec == 7'h59) - if (tod_hr[4:0] == 5'h11) - if (!tod_hr[5]) begin - tod_hr[5] <= ~tod_hr[5]; - tod_hr[3:0] <= tod_hr[3:0] + 1'b1; - end - else begin - tod_hr[5] <= ~tod_hr[5]; - tod_hr[4:0] <= 5'h00; - end + if (tod_hr[4:0] == 5'h11) tod_hr[5] <= ~tod_hr[5]; else if (tod_hr[4:0] == 5'h12) tod_hr[4:0] <= 5'h01; end end @@ -390,6 +378,7 @@ always @(posedge clk) begin else tod_count <= 3'h0; if (phi2) begin + if (!tod_latched) tod_latch <= {tod_hr, tod_min, tod_sec, tod_10ths}; if ({tod_hr, tod_min, tod_sec, tod_10ths} == tod_alarm) begin tod_alarm_reg <= 1'b1; icr[2] <= !tod_alarm_reg ? 1'b1 : icr[2]; diff --git a/cores/c64/rtl/sid8580/sid8580.sv b/cores/c64/rtl/sid8580/sid8580.sv deleted file mode 100644 index 6d3e3e3..0000000 --- a/cores/c64/rtl/sid8580/sid8580.sv +++ /dev/null @@ -1,228 +0,0 @@ - -module sid8580 -( - input reset, - - input clk, - input ce_1m, - - input we, - input [4:0] addr, - input [7:0] data_in, - output [ 7:0] data_out, - - input [7:0] pot_x, - input [7:0] pot_y, - - input extfilter_en, - output [15:0] audio_data -); - -// Internal Signals -reg [7:0] Voice_1_Freq_lo; -reg [7:0] Voice_1_Freq_hi; -reg [7:0] Voice_1_Pw_lo; -reg [3:0] Voice_1_Pw_hi; -reg [7:0] Voice_1_Control; -reg [7:0] Voice_1_Att_dec; -reg [7:0] Voice_1_Sus_Rel; - -reg [7:0] Voice_2_Freq_lo; -reg [7:0] Voice_2_Freq_hi; -reg [7:0] Voice_2_Pw_lo; -reg [3:0] Voice_2_Pw_hi; -reg [7:0] Voice_2_Control; -reg [7:0] Voice_2_Att_dec; -reg [7:0] Voice_2_Sus_Rel; - -reg [7:0] Voice_3_Freq_lo; -reg [7:0] Voice_3_Freq_hi; -reg [7:0] Voice_3_Pw_lo; -reg [3:0] Voice_3_Pw_hi; -reg [7:0] Voice_3_Control; -reg [7:0] Voice_3_Att_dec; -reg [7:0] Voice_3_Sus_Rel; - -reg [7:0] Filter_Fc_lo; -reg [7:0] Filter_Fc_hi; -reg [7:0] Filter_Res_Filt; -reg [7:0] Filter_Mode_Vol; - -wire [7:0] Misc_Osc3_Random; -wire [7:0] Misc_Env3; - -reg [7:0] do_buf; -reg [7:0] sidrandom; - -wire [11:0] voice_1; -wire [11:0] voice_2; -wire [11:0] voice_3; -wire [17:0] voice_mixed; -reg [17:0] voice_volume; - -wire voice_1_PA_MSB; -wire voice_2_PA_MSB; -wire voice_3_PA_MSB; - -wire [18:0] filtered_audio; -wire [17:0] unsigned_audio; -wire [18:0] unsigned_filt; - -localparam DC_offset = 14'b00111111111111; - -// Voice 1 Instantiation -sid_voice v1 -( - .clock(clk), - .ce_1m(ce_1m), - .reset(reset), - .freq_lo(Voice_1_Freq_lo), - .freq_hi(Voice_1_Freq_hi), - .pw_lo(Voice_1_Pw_lo), - .pw_hi(Voice_1_Pw_hi), - .control(Voice_1_Control), - .att_dec(Voice_1_Att_dec), - .sus_rel(Voice_1_Sus_Rel), - .osc_msb_in(voice_3_PA_MSB), - .osc_msb_out(voice_1_PA_MSB), - .signal_out(voice_1) -); - -// Voice 2 Instantiation -sid_voice v2 -( - .clock(clk), - .ce_1m(ce_1m), - .reset(reset), - .freq_lo(Voice_2_Freq_lo), - .freq_hi(Voice_2_Freq_hi), - .pw_lo(Voice_2_Pw_lo), - .pw_hi(Voice_2_Pw_hi), - .control(Voice_2_Control), - .att_dec(Voice_2_Att_dec), - .sus_rel(Voice_2_Sus_Rel), - .osc_msb_in(voice_1_PA_MSB), - .osc_msb_out(voice_2_PA_MSB), - .signal_out(voice_2) -); - -// Voice 3 Instantiation -sid_voice v3 -( - .clock(clk), - .ce_1m(ce_1m), - .reset(reset), - .freq_lo(Voice_3_Freq_lo), - .freq_hi(Voice_3_Freq_hi), - .pw_lo(Voice_3_Pw_lo), - .pw_hi(Voice_3_Pw_hi), - .control(Voice_3_Control), - .att_dec(Voice_3_Att_dec), - .sus_rel(Voice_3_Sus_Rel), - .osc_msb_in(voice_2_PA_MSB), - .osc_msb_out(voice_3_PA_MSB), - .signal_out(voice_3), - .osc_out(Misc_Osc3_Random), - .env_out(Misc_Env3) -); - -// Filter Instantiation -sid_filters filters -( - .clk(clk), - .rst(reset), - .Fc_lo(Filter_Fc_lo), - .Fc_hi(Filter_Fc_hi), - .Res_Filt(Filter_Res_Filt), - .Mode_Vol(Filter_Mode_Vol), - .voice1(voice_1), - .voice2(voice_2), - .voice3(voice_3), - .input_valid(ce_1m), - .ext_in(12'hfff), - .sound(audio_data), - .extfilter_en(extfilter_en) -); - -assign data_out = do_buf; -//assign audio_data = {1'b0, (filtered_audio[18:5] + 14'b1000000000000000)}; -//assign unsigned_filt = filtered_audio + 19'b1000000000000000000; -//assign unsigned_audio = unsigned_filt[18:1]; -//assign audio_data = filtered_audio[18:3];// + 15'h4000;//{1'b0, unsigned_audio[17:1]}; - -reg [7:0] last_wr; -always @(*) begin - case (addr) - 5'h19: do_buf = pot_x; - 5'h1a: do_buf = pot_y; - 5'h1b: do_buf = Misc_Osc3_Random; - 5'h1c: do_buf = Misc_Env3; - default: do_buf = last_wr; - endcase -end - - -// Register Decoding -always @(posedge clk) begin - if (reset) begin - Voice_1_Freq_lo <= 0; - Voice_1_Freq_hi <= 0; - Voice_1_Pw_lo <= 0; - Voice_1_Pw_hi <= 0; - Voice_1_Control <= 0; - Voice_1_Att_dec <= 0; - Voice_1_Sus_Rel <= 0; - Voice_2_Freq_lo <= 0; - Voice_2_Freq_hi <= 0; - Voice_2_Pw_lo <= 0; - Voice_2_Pw_hi <= 0; - Voice_2_Control <= 0; - Voice_2_Att_dec <= 0; - Voice_2_Sus_Rel <= 0; - Voice_3_Freq_lo <= 0; - Voice_3_Freq_hi <= 0; - Voice_3_Pw_lo <= 0; - Voice_3_Pw_hi <= 0; - Voice_3_Control <= 0; - Voice_3_Att_dec <= 0; - Voice_3_Sus_Rel <= 0; - Filter_Fc_lo <= 0; - Filter_Fc_hi <= 0; - Filter_Res_Filt <= 0; - Filter_Mode_Vol <= 0; - end - else begin - if (we) begin - last_wr <= data_in; - case (addr) - 5'h00: Voice_1_Freq_lo <= data_in; - 5'h01: Voice_1_Freq_hi <= data_in; - 5'h02: Voice_1_Pw_lo <= data_in; - 5'h03: Voice_1_Pw_hi <= data_in[3:0]; - 5'h04: Voice_1_Control <= data_in; - 5'h05: Voice_1_Att_dec <= data_in; - 5'h06: Voice_1_Sus_Rel <= data_in; - 5'h07: Voice_2_Freq_lo <= data_in; - 5'h08: Voice_2_Freq_hi <= data_in; - 5'h09: Voice_2_Pw_lo <= data_in; - 5'h0a: Voice_2_Pw_hi <= data_in[3:0]; - 5'h0b: Voice_2_Control <= data_in; - 5'h0c: Voice_2_Att_dec <= data_in; - 5'h0d: Voice_2_Sus_Rel <= data_in; - 5'h0e: Voice_3_Freq_lo <= data_in; - 5'h0f: Voice_3_Freq_hi <= data_in; - 5'h10: Voice_3_Pw_lo <= data_in; - 5'h11: Voice_3_Pw_hi <= data_in[3:0]; - 5'h12: Voice_3_Control <= data_in; - 5'h13: Voice_3_Att_dec <= data_in; - 5'h14: Voice_3_Sus_Rel <= data_in; - 5'h15: Filter_Fc_lo <= data_in; - 5'h16: Filter_Fc_hi <= data_in; - 5'h17: Filter_Res_Filt <= data_in; - 5'h18: Filter_Mode_Vol <= data_in; - endcase - end - end -end - -endmodule diff --git a/cores/c64/rtl/sid8580/sid8580.v b/cores/c64/rtl/sid8580/sid8580.v new file mode 100644 index 0000000..f594c76 --- /dev/null +++ b/cores/c64/rtl/sid8580/sid8580.v @@ -0,0 +1,253 @@ +module sid8580 (clk_1MHz, clk32, reset, cs, we, addr, data_in, data_out, + pot_x, pot_y, audio_data, extfilter_en); + +// Input Ports +input wire [0:0] clk_1MHz; +input wire [0:0] clk32; +input wire [0:0] reset; +input wire [0:0] cs; +input wire [0:0] we; +input wire [4:0] addr; +input wire [7:0] data_in; +input wire [7:0] pot_x; +input wire [7:0] pot_y; +input wire [0:0] extfilter_en; + +// Output Ports +output wire [ 7:0] data_out; +output wire [15:0] audio_data; + +// Internal Signals +reg [7:0] Voice_1_Freq_lo; +reg [7:0] Voice_1_Freq_hi; +reg [7:0] Voice_1_Pw_lo; +reg [3:0] Voice_1_Pw_hi; +reg [7:0] Voice_1_Control; +reg [7:0] Voice_1_Att_dec; +reg [7:0] Voice_1_Sus_Rel; + +reg [7:0] Voice_2_Freq_lo; +reg [7:0] Voice_2_Freq_hi; +reg [7:0] Voice_2_Pw_lo; +reg [3:0] Voice_2_Pw_hi; +reg [7:0] Voice_2_Control; +reg [7:0] Voice_2_Att_dec; +reg [7:0] Voice_2_Sus_Rel; + +reg [7:0] Voice_3_Freq_lo; +reg [7:0] Voice_3_Freq_hi; +reg [7:0] Voice_3_Pw_lo; +reg [3:0] Voice_3_Pw_hi; +reg [7:0] Voice_3_Control; +reg [7:0] Voice_3_Att_dec; +reg [7:0] Voice_3_Sus_Rel; + +reg [7:0] Filter_Fc_lo; +reg [7:0] Filter_Fc_hi; +reg [7:0] Filter_Res_Filt; +reg [7:0] Filter_Mode_Vol; + +wire [7:0] Misc_Osc3_Random; +wire [7:0] Misc_Env3; + +reg [7:0] Ext_hi; +reg [3:0] Ext_lo; + +reg [7:0] do_buf; +reg [7:0] sidrandom; + +wire [11:0] voice_1; +wire [11:0] voice_2; +wire [11:0] voice_3; +wire [17:0] voice_mixed; +reg [17:0] voice_volume; + +wire [ 0:0] voice_1_PA_MSB; +wire [ 0:0] voice_2_PA_MSB; +wire [ 0:0] voice_3_PA_MSB; + +wire [18:0] filtered_audio; +reg [ 0:0] tick_q1; +reg [ 0:0] tick_q2; +reg [ 0:0] input_valid; +wire [17:0] unsigned_audio; +wire [18:0] unsigned_filt; +reg [ 0:0] ff1; + +localparam DC_offset = 14'b00111111111111; + +// Voice 1 Instantiation +sid_voice v1 (.clock(clk_1MHz), .reset(reset), + .freq_lo(Voice_1_Freq_lo), .freq_hi(Voice_1_Freq_hi), + .pw_lo(Voice_1_Pw_lo), .pw_hi(Voice_1_Pw_hi), + .control(Voice_1_Control), + .att_dec(Voice_1_Att_dec), .sus_rel(Voice_1_Sus_Rel), + .osc_msb_in(voice_3_PA_MSB), .osc_msb_out(voice_1_PA_MSB), + .signal_out(voice_1)); + +// Voice 2 Instantiation +sid_voice v2 (.clock(clk_1MHz), .reset(reset), + .freq_lo(Voice_2_Freq_lo), .freq_hi(Voice_2_Freq_hi), + .pw_lo(Voice_2_Pw_lo), .pw_hi(Voice_2_Pw_hi), + .control(Voice_2_Control), + .att_dec(Voice_2_Att_dec), .sus_rel(Voice_2_Sus_Rel), + .osc_msb_in(voice_1_PA_MSB), .osc_msb_out(voice_2_PA_MSB), + .signal_out(voice_2)); + +// Voice 3 Instantiation +sid_voice v3 (.clock(clk_1MHz), .reset(reset), + .freq_lo(Voice_3_Freq_lo), .freq_hi(Voice_3_Freq_hi), + .pw_lo(Voice_3_Pw_lo), .pw_hi(Voice_3_Pw_hi), + .control(Voice_3_Control), + .att_dec(Voice_3_Att_dec), .sus_rel(Voice_3_Sus_Rel), + .osc_msb_in(voice_2_PA_MSB), .osc_msb_out(voice_3_PA_MSB), + .signal_out(voice_3), .osc_out(Misc_Osc3_Random), + .env_out(Misc_Env3)); + +// Filter Instantiation +sid_filters filters (.clk(clk32), .rst(reset), + .Fc_lo(Filter_Fc_lo), .Fc_hi(Filter_Fc_hi), + .Res_Filt(Filter_Res_Filt), .Mode_Vol(Filter_Mode_Vol), + .voice1(voice_1), .voice2(voice_2), + .voice3(voice_3), .input_valid(input_valid), + .ext_in(12'hfff), .sound(audio_data), + .extfilter_en(extfilter_en)); + +assign data_out = do_buf; +//assign audio_data = {1'b0, (filtered_audio[18:5] + 14'b1000000000000000)}; +//assign unsigned_filt = filtered_audio + 19'b1000000000000000000; +//assign unsigned_audio = unsigned_filt[18:1]; +//assign audio_data = filtered_audio[18:3];// + 15'h4000;//{1'b0, unsigned_audio[17:1]}; + +// Toggle Flip Flop +always @(posedge clk_1MHz) +begin + if (reset) + ff1 <= 1'b0; + else + ff1 <= ~ff1; +end + +always @(posedge clk32) +begin + input_valid <= (tick_q1 != tick_q2) ? 1'b1 : 1'b0; + tick_q1 <= ff1; + tick_q2 <= tick_q1; +end + +reg [7:0] last_wr; + +// Register Decoding +always @(posedge clk32) +begin + if (reset) + begin + Voice_1_Freq_lo <= 8'h00; + Voice_1_Freq_hi <= 8'h00; + Voice_1_Pw_lo <= 8'h00; + Voice_1_Pw_hi <= 4'h0; + Voice_1_Control <= 8'h00; + Voice_1_Att_dec <= 8'h00; + Voice_1_Sus_Rel <= 8'h00; + Voice_2_Freq_lo <= 8'h00; + Voice_2_Freq_hi <= 8'h00; + Voice_2_Pw_lo <= 8'h00; + Voice_2_Pw_hi <= 4'h0; + Voice_2_Control <= 8'h00; + Voice_2_Att_dec <= 8'h00; + Voice_2_Sus_Rel <= 8'h00; + Voice_3_Freq_lo <= 8'h00; + Voice_3_Freq_hi <= 8'h00; + Voice_3_Pw_lo <= 8'h00; + Voice_3_Pw_hi <= 4'h0; + Voice_3_Control <= 8'h00; + Voice_3_Att_dec <= 8'h00; + Voice_3_Sus_Rel <= 8'h00; + Filter_Fc_lo <= 8'h00; + Filter_Fc_hi <= 8'h00; + Filter_Res_Filt <= 8'h00; + Filter_Mode_Vol <= 8'h00; + Ext_hi <= 8'h00; + Ext_lo <= 4'h0; + end + else + begin + Voice_1_Freq_lo <= Voice_1_Freq_lo; + Voice_1_Freq_hi <= Voice_1_Freq_hi; + Voice_1_Pw_lo <= Voice_1_Pw_lo; + Voice_1_Pw_hi <= Voice_1_Pw_hi; + Voice_1_Control <= Voice_1_Control; + Voice_1_Att_dec <= Voice_1_Att_dec; + Voice_1_Sus_Rel <= Voice_1_Sus_Rel; + Voice_2_Freq_lo <= Voice_2_Freq_lo; + Voice_2_Freq_hi <= Voice_2_Freq_hi; + Voice_2_Pw_lo <= Voice_2_Pw_lo; + Voice_2_Pw_hi <= Voice_2_Pw_hi; + Voice_2_Control <= Voice_2_Control; + Voice_2_Att_dec <= Voice_2_Att_dec; + Voice_2_Sus_Rel <= Voice_2_Sus_Rel; + Voice_3_Freq_lo <= Voice_3_Freq_lo; + Voice_3_Freq_hi <= Voice_3_Freq_hi; + Voice_3_Pw_lo <= Voice_3_Pw_lo; + Voice_3_Pw_hi <= Voice_3_Pw_hi; + Voice_3_Control <= Voice_3_Control; + Voice_3_Att_dec <= Voice_3_Att_dec; + Voice_3_Sus_Rel <= Voice_3_Sus_Rel; + Filter_Fc_lo <= Filter_Fc_lo; + Filter_Fc_hi <= Filter_Fc_hi; + Filter_Res_Filt <= Filter_Res_Filt; + Filter_Mode_Vol <= Filter_Mode_Vol; + Ext_hi <= Ext_hi; + Ext_lo <= Ext_lo; + do_buf <= 8'h00; + end + if (cs) + begin + if (we) + begin + last_wr <= data_in; + case (addr) + 5'h00: Voice_1_Freq_lo <= data_in; + 5'h01: Voice_1_Freq_hi <= data_in; + 5'h02: Voice_1_Pw_lo <= data_in; + 5'h03: Voice_1_Pw_hi <= data_in[3:0]; + 5'h04: Voice_1_Control <= data_in; + 5'h05: Voice_1_Att_dec <= data_in; + 5'h06: Voice_1_Sus_Rel <= data_in; + 5'h07: Voice_2_Freq_lo <= data_in; + 5'h08: Voice_2_Freq_hi <= data_in; + 5'h09: Voice_2_Pw_lo <= data_in; + 5'h0a: Voice_2_Pw_hi <= data_in[3:0]; + 5'h0b: Voice_2_Control <= data_in; + 5'h0c: Voice_2_Att_dec <= data_in; + 5'h0d: Voice_2_Sus_Rel <= data_in; + 5'h0e: Voice_3_Freq_lo <= data_in; + 5'h0f: Voice_3_Freq_hi <= data_in; + 5'h10: Voice_3_Pw_lo <= data_in; + 5'h11: Voice_3_Pw_hi <= data_in[3:0]; + 5'h12: Voice_3_Control <= data_in; + 5'h13: Voice_3_Att_dec <= data_in; + 5'h14: Voice_3_Sus_Rel <= data_in; + 5'h15: Filter_Fc_lo <= data_in; + 5'h16: Filter_Fc_hi <= data_in; + 5'h17: Filter_Res_Filt <= data_in; + 5'h18: Filter_Mode_Vol <= data_in; + 5'h19: Ext_lo <= data_in[3:0]; + 5'h1a: Ext_hi <= data_in; + default:; + endcase + end + else + begin + case (addr) + 5'h19: do_buf <= pot_x; + 5'h1a: do_buf <= pot_y; + 5'h1b: do_buf <= Misc_Osc3_Random; + 5'h1c: do_buf <= Misc_Env3; + default: do_buf <= last_wr; + endcase + end + end +end + +endmodule diff --git a/cores/c64/rtl/sid8580/sid_envelope.sv b/cores/c64/rtl/sid8580/sid_envelope.sv deleted file mode 100644 index 451aeba..0000000 --- a/cores/c64/rtl/sid8580/sid_envelope.sv +++ /dev/null @@ -1,178 +0,0 @@ - -module sid_envelope -( - input clock, - input ce_1m, - - input reset, - input gate, - input [ 7:0] att_dec, - input [ 7:0] sus_rel, - - output reg [7:0] envelope -); - -// Internal Signals -reg [ 1:0] state; -reg gate_edge; -reg [14:0] rate_counter; -reg [14:0] rate_period; -wire [14:0] adsrtable [0:15]; -reg [ 7:0] exponential_counter; -reg [ 7:0] exponential_counter_period; -reg hold_zero; -reg envelope_pipeline; - -`define ST_ATTACK 2'b00 -`define ST_DEC_SUS 2'b01 -`define ST_RELEASE 2'b10 - -assign adsrtable[4'h0] = 15'h007f; -assign adsrtable[4'h1] = 15'h3000; -assign adsrtable[4'h2] = 15'h1e00; -assign adsrtable[4'h3] = 15'h0660; -assign adsrtable[4'h4] = 15'h0182; -assign adsrtable[4'h5] = 15'h5573; -assign adsrtable[4'h6] = 15'h000e; -assign adsrtable[4'h7] = 15'h3805; -assign adsrtable[4'h8] = 15'h2424; -assign adsrtable[4'h9] = 15'h2220; -assign adsrtable[4'ha] = 15'h090c; -assign adsrtable[4'hb] = 15'h0ecd; -assign adsrtable[4'hc] = 15'h010e; -assign adsrtable[4'hd] = 15'h23f7; -assign adsrtable[4'he] = 15'h5237; -assign adsrtable[4'hf] = 15'h64a8; - -// State Logic -always @(posedge clock) begin - if (reset) - state <= `ST_RELEASE; - else if(ce_1m) begin - if (gate_edge != gate) - if (gate) state <= `ST_ATTACK; - else state <= `ST_RELEASE; - - if (((rate_counter == rate_period) && - (state == `ST_ATTACK || - (exponential_counter + 1'b1) == exponential_counter_period) && - (!hold_zero))) - case (state) - `ST_ATTACK: if (envelope + 1'b1 == 8'hff) state <= `ST_DEC_SUS; - endcase - end -end - -// Gate Switch Detection -always @(posedge clock) begin - if (reset) gate_edge <= 1'b0; - else if(ce_1m) begin - if (gate_edge != gate) gate_edge <= gate; - end -end - -// Envelope -always @(posedge clock) begin - if (reset) - envelope <= 8'h00; - else if(ce_1m) begin - if (envelope_pipeline) envelope <= envelope - 1'b1; - if (((rate_counter == rate_period) && - (state == `ST_ATTACK || - (exponential_counter + 1'b1) == exponential_counter_period) && - (!hold_zero))) - case (state) - `ST_ATTACK: envelope <= envelope + 1'b1; - `ST_DEC_SUS: if (envelope != {2{sus_rel[7:4]}} && exponential_counter_period == 1) envelope <= envelope - 1'b1; - `ST_RELEASE: if (exponential_counter_period == 1) envelope <= envelope - 1'b1; - endcase - end -end - -// Envelope Pipeline -always @(posedge clock) begin - if (reset) - envelope_pipeline <= 1'b0; - else if(ce_1m) begin - if (gate_edge != gate) - if (gate) envelope_pipeline <= 1'b0; - if (envelope_pipeline) envelope_pipeline <= 1'b0; - if (((rate_counter == rate_period) && - (state == `ST_ATTACK || - (exponential_counter + 1'b1) == exponential_counter_period) && - (!hold_zero))) - case (state) - `ST_DEC_SUS: if (envelope != {2{sus_rel[7:4]}} && exponential_counter_period != 1) envelope_pipeline <= 1'b1; - `ST_RELEASE: if(exponential_counter_period != 1) envelope_pipeline <= 1'b1; - endcase - end -end - -// Exponential Counter -always @(posedge clock) begin - if (reset) - exponential_counter <= 8'h00; - else if(ce_1m) begin - if (rate_counter == rate_period) begin - exponential_counter <= exponential_counter + 1'b1; - if (state == `ST_ATTACK || (exponential_counter + 1'b1) == exponential_counter_period) exponential_counter <= 8'h00; - end - end -end - -// Exponential Counter Period -always @(posedge clock) begin - if (reset) begin - hold_zero <= 1'b1; - exponential_counter_period <= 8'h00; - end - else if(ce_1m) begin - if (gate_edge != gate) if (gate) hold_zero <= 1'b0; - if ((envelope_pipeline) || ((rate_counter == rate_period) && - (state == `ST_ATTACK || - (exponential_counter + 1'b1) == exponential_counter_period) && - (!hold_zero))) - begin - case (state == `ST_ATTACK ? envelope + 1'b1 : envelope - 1'b1) - 8'hff: exponential_counter_period <= 8'd1; - 8'h5d: exponential_counter_period <= 8'd2; - 8'h36: exponential_counter_period <= 8'd4; - 8'h1a: exponential_counter_period <= 8'd8; - 8'h0e: exponential_counter_period <= 8'd16; - 8'h06: exponential_counter_period <= 8'd30; - 8'h00: begin - exponential_counter_period <= 8'd1; - hold_zero <= 1'b1; - end - endcase - end - end -end - -// Rate Counter -always @(posedge clock) begin - if (reset) rate_counter <= 15'h7fff; - else if(ce_1m) begin - if (rate_counter == rate_period) rate_counter <= 15'h7fff; - else rate_counter <= {rate_counter[1] ^ rate_counter[0], rate_counter[14:1]}; - end -end - -// Rate Period -always @(posedge clock) begin - if (reset) - rate_period <= adsrtable[sus_rel[3:0]]; - else if(ce_1m) begin - if (gate_edge != gate) begin - if (gate) rate_period <= adsrtable[att_dec[7:4]]; - else rate_period <= adsrtable[sus_rel[3:0]]; - end - case (state) - `ST_ATTACK: rate_period <= adsrtable[att_dec[7:4]]; - `ST_DEC_SUS: rate_period <= adsrtable[att_dec[3:0]]; - default: rate_period <= adsrtable[sus_rel[3:0]]; - endcase - end -end - -endmodule diff --git a/cores/c64/rtl/sid8580/sid_envelope.v b/cores/c64/rtl/sid8580/sid_envelope.v new file mode 100644 index 0000000..332270a --- /dev/null +++ b/cores/c64/rtl/sid8580/sid_envelope.v @@ -0,0 +1,232 @@ +module sid_envelope (clock, reset, gate, att_dec, sus_rel, envelope); + +// Input Signals +input wire [ 0:0] clock; +input wire [ 0:0] reset; +input wire [ 0:0] gate; +input wire [ 7:0] att_dec; +input wire [ 7:0] sus_rel; + +// Output Signals +output reg [7:0] envelope; + +// Internal Signals +reg [ 1:0] state; +reg [ 0:0] gate_edge; +reg [14:0] rate_counter; +reg [14:0] rate_period; +wire [14:0] adsrtable [0:15]; +reg [ 7:0] exponential_counter; +reg [ 7:0] exponential_counter_period; +reg [ 0:0] hold_zero; +reg [ 0:0] envelope_pipeline; + +`define ST_ATTACK 2'b00 +`define ST_DEC_SUS 2'b01 +`define ST_RELEASE 2'b10 + +assign adsrtable[4'h0] = 15'h007f; +assign adsrtable[4'h1] = 15'h3000; +assign adsrtable[4'h2] = 15'h1e00; +assign adsrtable[4'h3] = 15'h0660; +assign adsrtable[4'h4] = 15'h0182; +assign adsrtable[4'h5] = 15'h5573; +assign adsrtable[4'h6] = 15'h000e; +assign adsrtable[4'h7] = 15'h3805; +assign adsrtable[4'h8] = 15'h2424; +assign adsrtable[4'h9] = 15'h2220; +assign adsrtable[4'ha] = 15'h090c; +assign adsrtable[4'hb] = 15'h0ecd; +assign adsrtable[4'hc] = 15'h010e; +assign adsrtable[4'hd] = 15'h23f7; +assign adsrtable[4'he] = 15'h5237; +assign adsrtable[4'hf] = 15'h64a8; + +// State Logic +always @(posedge clock) +begin + if (reset) + state <= `ST_RELEASE; + else + begin + if (gate_edge != gate) + if (gate) + state <= `ST_ATTACK; + else + state <= `ST_RELEASE; + if (((rate_counter == rate_period) && + (state == `ST_ATTACK || + (exponential_counter + 1'b1) == exponential_counter_period) && + (!hold_zero))) + case (state) + `ST_ATTACK: + if (envelope + 1'b1 == 8'hff) + state <= `ST_DEC_SUS; + default: + ; + endcase + end +end + +// Gate Switch Detection +always @(posedge clock) +begin + if (reset) + gate_edge <= 1'b0; + else + if (gate_edge != gate) + gate_edge <= gate; +end + +// Envelope +always @(posedge clock) +begin + if (reset) + envelope <= 8'h00; + else + begin + if (envelope_pipeline) + envelope <= envelope - 1'b1; + if (((rate_counter == rate_period) && + (state == `ST_ATTACK || + (exponential_counter + 1'b1) == exponential_counter_period) && + (!hold_zero))) + case (state) + `ST_ATTACK: + envelope <= envelope + 1'b1; + `ST_DEC_SUS: + if (envelope != {2{sus_rel[7:4]}} && + exponential_counter_period == 1) + envelope <= envelope - 1'b1; + `ST_RELEASE: + if (exponential_counter_period == 1) + envelope <= envelope - 1'b1; + endcase + end +end + +// Envelope Pipeline +always @(posedge clock) +begin + if (reset) + envelope_pipeline <= 1'b0; + else + begin + if (gate_edge != gate) + if (gate) + envelope_pipeline <= 1'b0; + if (envelope_pipeline) + envelope_pipeline <= 1'b0; + if (((rate_counter == rate_period) && + (state == `ST_ATTACK || + (exponential_counter + 1'b1) == exponential_counter_period) && + (!hold_zero))) + case (state) + `ST_DEC_SUS: + if (envelope != {2{sus_rel[7:4]}} && + exponential_counter_period != 1) + envelope_pipeline <= 1'b1; + `ST_RELEASE: + if(exponential_counter_period != 1) + envelope_pipeline <= 1'b1; + default: + ; + endcase + end +end + +// Exponential Counter +always @(posedge clock) +begin + if (reset) + exponential_counter <= 8'h00; + else + begin + if (rate_counter == rate_period) + begin + exponential_counter <= exponential_counter + 1'b1; + if (state == `ST_ATTACK || + (exponential_counter + 1'b1) == exponential_counter_period) + exponential_counter <= 8'h00; + end + end +end + +// Exponential Counter Period +always @(posedge clock) +begin + if (reset) + begin + hold_zero <= 1'b1; + exponential_counter_period <= 8'h00; + end + else + begin + if (gate_edge != gate) + if (gate) + hold_zero <= 1'b0; + if ((envelope_pipeline) || ((rate_counter == rate_period) && + (state == `ST_ATTACK || + (exponential_counter + 1'b1) == exponential_counter_period) && + (!hold_zero))) + begin + case (state == `ST_ATTACK ? envelope + 1'b1 : envelope - 1'b1) + 8'hff: + exponential_counter_period <= 8'd1; + 8'h5d: + exponential_counter_period <= 8'd2; + 8'h36: + exponential_counter_period <= 8'd4; + 8'h1a: + exponential_counter_period <= 8'd8; + 8'h0e: + exponential_counter_period <= 8'd16; + 8'h06: + exponential_counter_period <= 8'd30; + 8'h00: + begin + exponential_counter_period <= 8'd1; + hold_zero <= 1'b1; + end + default: + ; + endcase + end + end +end + +// Rate Counter +always @(posedge clock) +begin + if (reset || rate_counter == rate_period) + rate_counter <= 15'h7fff; + else + rate_counter <= {rate_counter[1] ^ rate_counter[0], rate_counter[14:1]}; +end + +// Rate Period +always @(posedge clock) +begin + if (reset) + rate_period <= adsrtable[sus_rel[3:0]]; + else + begin + if (gate_edge != gate) + begin + if (gate) + rate_period <= adsrtable[att_dec[7:4]]; + else + rate_period <= adsrtable[sus_rel[3:0]]; + end + case (state) + `ST_ATTACK: + rate_period <= adsrtable[att_dec[7:4]]; + `ST_DEC_SUS: + rate_period <= adsrtable[att_dec[3:0]]; + default: + rate_period <= adsrtable[sus_rel[3:0]]; + endcase + end +end + +endmodule diff --git a/cores/c64/rtl/sid8580/sid_filters.sv b/cores/c64/rtl/sid8580/sid_filters.sv deleted file mode 100644 index aed096c..0000000 --- a/cores/c64/rtl/sid8580/sid_filters.sv +++ /dev/null @@ -1,129 +0,0 @@ - -module sid_filters -( - input clk, - input rst, - input [ 7:0] Fc_lo, - input [ 7:0] Fc_hi, - input [ 7:0] Res_Filt, - input [ 7:0] Mode_Vol, - input [11:0] voice1, - input [11:0] voice2, - input [11:0] voice3, - input input_valid, - input [11:0] ext_in, - input extfilter_en, - - output reg [15:0] sound -); - -reg signed [17:0] Vhp; -reg signed [17:0] Vbp; -reg signed [17:0] w0; -reg signed [17:0] q; - -wire [10:0] divmul[16]; -assign divmul[0] = 1448; -assign divmul[1] = 1328; -assign divmul[2] = 1218; -assign divmul[3] = 1117; -assign divmul[4] = 1024; -assign divmul[5] = 939; -assign divmul[6] = 861; -assign divmul[7] = 790; -assign divmul[8] = 724; -assign divmul[9] = 664; -assign divmul[10] = 609; -assign divmul[11] = 558; -assign divmul[12] = 512; -assign divmul[13] = 470; -assign divmul[14] = 431; -assign divmul[15] = 395; - -wire [35:0] mul1 = w0 * Vhp; -wire [35:0] mul2 = w0 * Vbp; -wire [35:0] mul3 = q * Vbp; -wire [35:0] mul4 = 18'd82355 * ({Fc_hi, Fc_lo[2:0]} + 1'b1); - -// Filter -always @(posedge clk) begin - reg [17:0] dVbp; - reg [17:0] Vlp; - reg [17:0] dVlp; - reg [17:0] Vi; - reg [17:0] Vnf; - reg [17:0] Vf; - reg [21:0] mulr; - reg [3:0] state; - - if (rst) begin - state <= 0; - Vlp <= 0; - Vbp <= 0; - Vhp <= 0; - end - else begin - case (state) - 0: if (input_valid) begin - if(mulr[21] == mulr[20]) sound <= mulr[20:5]; - state <= state + 1'd1; - Vi <= 0; - Vnf <= 0; - end - 1: state <= state + 1'd1; - 2: begin - state <= state + 1'd1; - w0 <= {mul4[35], mul4[28:12]}; - if (Res_Filt[0]) Vi <= Vi + (voice1 << 2); - else Vnf <= Vnf + (voice1 << 2); - end - 3: begin - state <= state + 1'd1; - if (Res_Filt[1]) Vi <= Vi + (voice2 << 2); - else Vnf <= Vnf + (voice2 << 2); - end - 4: begin - state <= state + 1'd1; - if (Res_Filt[2]) Vi <= Vi + (voice3 << 2); - else if (!Mode_Vol[7]) Vnf <= Vnf + (voice3 << 2); - dVbp <= {mul1[35], mul1[35:19]}; - end - 5: begin - state <= state + 1'd1; - if (Res_Filt[3]) Vi <= Vi + (ext_in << 2); - else Vnf <= Vnf + (ext_in << 2); - dVlp <= {mul2[35], mul2[35:19]}; - Vbp <= Vbp - dVbp; - q <= divmul[Res_Filt[7:4]]; - end - 6: begin - state <= state + 1'd1; - Vlp <= Vlp - dVlp; - Vf <= (Mode_Vol[5]) ? Vbp : 18'h00000; - end - 7: begin - state <= state + 1'd1; - Vhp <= {mul3[35], mul3[26:10]} - Vlp; - if(Mode_Vol[4]) Vf <= Vf + Vlp; - end - 8: begin - state <= state + 1'd1; - Vhp <= Vhp - Vi; - end - 9: begin - state <= state + 1'd1; - if(Mode_Vol[6]) Vf <= Vf + Vhp; - end - 10: begin - state <= state + 1'd1; - Vf <= (extfilter_en) ? {~Vf + 1'b1} + Vnf : Vi + Vnf; - end - 11: begin - state <= 0; - mulr <= Vf * Mode_Vol[3:0]; - end - endcase - end -end - -endmodule diff --git a/cores/c64/rtl/sid8580/sid_filters.v b/cores/c64/rtl/sid8580/sid_filters.v new file mode 100644 index 0000000..7eba3a9 --- /dev/null +++ b/cores/c64/rtl/sid8580/sid_filters.v @@ -0,0 +1,184 @@ +module sid_filters (clk, rst, Fc_lo, Fc_hi, Res_Filt, Mode_Vol, + voice1, voice2, voice3, input_valid, ext_in, sound, extfilter_en); + +// Input Signals +input wire [ 0:0] clk; +input wire [ 0:0] rst; +input wire [ 7:0] Fc_lo; +input wire [ 7:0] Fc_hi; +input wire [ 7:0] Res_Filt; +input wire [ 7:0] Mode_Vol; +input wire [11:0] voice1; +input wire [11:0] voice2; +input wire [11:0] voice3; +input wire [ 0:0] input_valid; +input wire [11:0] ext_in; +input wire [ 0:0] extfilter_en; + +// Output Signals +output reg [15:0] sound; + +// Internal Signals +reg signed [17:0] mula; +reg signed [17:0] mulb; +reg [35:0] mulr; +reg [ 0:0] mulen; + +wire [35:0] mul1; +wire [35:0] mul2; +wire [35:0] mul3; +wire [35:0] mul4; + +wire [10:0] divmul [0:15]; + +reg signed [17:0] Vhp; +reg signed [17:0] Vbp; +reg [17:0] dVbp; +reg [17:0] Vlp; +reg [17:0] dVlp; +reg [17:0] Vi; +reg [17:0] Vnf; +reg [17:0] Vf; +reg signed [17:0] w0; +reg signed [17:0] q; +reg [ 3:0] state; + +assign divmul[4'h0] = 11'd1448; +assign divmul[4'h1] = 11'd1328; +assign divmul[4'h2] = 11'd1218; +assign divmul[4'h3] = 11'd1117; +assign divmul[4'h4] = 11'd1024; +assign divmul[4'h5] = 11'd939; +assign divmul[4'h6] = 11'd861; +assign divmul[4'h7] = 11'd790; +assign divmul[4'h8] = 11'd724; +assign divmul[4'h9] = 11'd664; +assign divmul[4'ha] = 11'd609; +assign divmul[4'hb] = 11'd558; +assign divmul[4'hc] = 11'd512; +assign divmul[4'hd] = 11'd470; +assign divmul[4'he] = 11'd431; +assign divmul[4'hf] = 11'd395; + +// Multiplier +always @(posedge clk) +begin + if (mulen) + mulr <= mula * mulb; +end + +assign mul1 = w0 * Vhp; +assign mul2 = w0 * Vbp; +assign mul3 = q * Vbp; +assign mul4 = 18'd82355 * ({Fc_hi, Fc_lo[2:0]} + 1'b1); + +// Filter +always @(posedge clk) +begin + if (rst) + begin + state <= 4'h0; + Vlp <= 18'h00000; + Vbp <= 18'h00000; + Vhp <= 18'h00000; + end + else + begin + mula <= 18'h00000; + mulb <= 18'h00000; + mulen <= 1'b0; + case (state) + 4'h0: + begin + if (input_valid) + begin + state <= 4'h1; + Vi <= 18'h00000; + Vnf <= 18'h00000; + end + end + 4'h1: + begin + state <= 4'h2; + w0 <= {mul4[35], mul4[28:12]}; + if (Res_Filt[0]) + Vi <= Vi + (voice1 << 2); + else + Vnf <= Vnf + (voice1 << 2); + end + 4'h2: + begin + state <= 4'h3; + if (Res_Filt[1]) + Vi <= Vi + (voice2 << 2); + else + Vnf <= Vnf + (voice2 << 2); + end + 4'h3: + begin + state <= 4'h4; + if (Res_Filt[2]) + Vi <= Vi + (voice3 << 2); + else + if (!Mode_Vol[7]) + Vnf <= Vnf + (voice3 << 2); + dVbp <= {mul1[35], mul1[35:19]}; + end + 4'h4: + begin + state <= 4'h5; + if (Res_Filt[3]) + Vi <= Vi + (ext_in << 2); + else + Vnf <= Vnf + (ext_in << 2); + dVlp <= {mul2[35], mul2[35:19]}; + Vbp <= Vbp - dVbp; + q <= divmul[Res_Filt[7:4]]; + end + 4'h5: + begin + state <= 4'h6; + Vlp <= Vlp - dVlp; + Vf <= (Mode_Vol[5]) ? Vbp : 18'h00000; + end + 4'h6: + begin + state <= 4'h7; + Vhp <= {mul3[35], mul3[26:10]} - Vlp; + Vf <= (Mode_Vol[4]) ? Vf + Vlp : Vf; + end + 4'h7: + begin + state <= 4'h8; + Vhp <= Vhp - Vi; + end + 4'h8: + begin + state <= 4'h9; + Vf <= (Mode_Vol[6]) ? Vf + Vhp : Vf; + end + 4'h9: + begin + state <= 4'ha; + //Vf <= {~Vf + 1'b1} + Vnf; + Vf <= (extfilter_en) ? {~Vf + 1'b1} + Vnf : Vi + Vnf; + end + 4'ha: + begin + state <= 4'hb; + mulen <= 1'b1; + mula <= Vf; + mulb <= Mode_Vol[3:0]; + end + 4'hb: + begin + state <= 4'h0; + sound <= (mulr[21] != mulr[20]) ? sound : mulr[20:5]; + end + default: + ; + endcase + end +end + +endmodule diff --git a/cores/c64/rtl/sid8580/sid_voice.sv b/cores/c64/rtl/sid8580/sid_voice.sv deleted file mode 100644 index d12c826..0000000 --- a/cores/c64/rtl/sid8580/sid_voice.sv +++ /dev/null @@ -1,353 +0,0 @@ - -// altera message_off 10030 -module sid_voice -( - input clock, - input ce_1m, - input reset, - input [7:0] freq_lo, - input [7:0] freq_hi, - input [7:0] pw_lo, - input [3:0] pw_hi, - input [7:0] control, - input [7:0] att_dec, - input [7:0] sus_rel, - input osc_msb_in, - - output osc_msb_out, - output [11:0] signal_out, - output [ 7:0] osc_out, - output [ 7:0] env_out -); - -// Internal Signals -reg [23:0] oscillator; -reg osc_edge; -reg osc_msb_in_prv; -reg [11:0] triangle; -reg [11:0] sawtooth; -reg [11:0] pulse; -reg [11:0] noise; -reg [22:0] lfsr_noise; -wire [ 7:0] envelope; -reg [11:0] wave_out; -reg [19:0] dca_out; - -`define noise_ctrl control[7] -`define pulse_ctrl control[6] -`define saw_ctrl control[5] -`define tri_ctrl control[4] -`define test_ctrl control[3] -`define ringmod_ctrl control[2] -`define sync_ctrl control[1] - -// Signal Assignments -assign osc_msb_out = oscillator[23]; -assign signal_out = dca_out[19:8]; -assign osc_out = wave_out[11:4]; -assign env_out = envelope; - -// Digital Controlled Amplifier -always @(posedge clock) if(ce_1m) dca_out <= wave_out * envelope; - -// Envelope Instantiation -sid_envelope adsr -( - .clock(clock), - .ce_1m(ce_1m), - .reset(reset), - .gate(control[0]), - .att_dec(att_dec), - .sus_rel(sus_rel), - .envelope(envelope) -); - -// Phase Accumulating Oscillator -always @(posedge clock) begin - if(ce_1m) begin - osc_msb_in_prv <= osc_msb_in; - if (reset || `test_ctrl || ((`sync_ctrl) && (!osc_msb_in) && (osc_msb_in != osc_msb_in_prv))) - oscillator <= 0; - else - oscillator <= oscillator + {freq_hi, freq_lo}; - end -end - -// Waveform Generator -always @(posedge clock) begin - if (reset) begin - triangle <= 0; - sawtooth <= 0; - pulse <= 0; - noise <= 0; - osc_edge <= 0; - lfsr_noise <= 23'h7fffff; - end - else if(ce_1m) begin - triangle <= (`ringmod_ctrl) ? - {({11{osc_msb_in}} ^ {{11{oscillator[23]}}}) ^ oscillator[22:12], 1'b0} : - {{11{oscillator[23]}} ^ oscillator[22:12], 1'b0}; - - sawtooth <= oscillator[23:12]; - - pulse <= (`test_ctrl) ? 12'hfff : - (oscillator[23:12] >= {pw_hi, pw_lo}) ? {12{1'b1}} : - {12{1'b0}}; - - noise <= {lfsr_noise[21], lfsr_noise[19], lfsr_noise[15], - lfsr_noise[12], lfsr_noise[10], lfsr_noise[6], - lfsr_noise[3], lfsr_noise[1], 4'b0000}; - - osc_edge <= (oscillator[19] && !osc_edge) ? 1'b1 : - (!oscillator[19] && osc_edge) ? 1'b0 : - osc_edge; - - lfsr_noise <= (oscillator[19] && !osc_edge) ? - {lfsr_noise[21:0], (lfsr_noise[22] | `test_ctrl) ^ lfsr_noise[17]} : - lfsr_noise; - end -end - -// Waveform Output Selector -always @(*) begin - case (control[7:4]) - 4'b0001: wave_out = triangle; - 4'b0010: wave_out = sawtooth; - 4'b0011: wave_out = {wave__st[sawtooth], 4'b0000}; - 4'b0100: wave_out = pulse; - 4'b0101: wave_out = {wave_p_t[triangle[11:1]], 4'b0000} & pulse; - 4'b0110: wave_out = {wave_ps_[sawtooth], 4'b0000} & pulse; - 4'b0111: wave_out = {wave_pst[sawtooth], 4'b0000} & pulse; - 4'b1000: wave_out = noise; - default: wave_out = 0; - endcase -end - -// -// convert combinatorial logic to ROM (Sorgelig) -// - -reg [7:0] wave__st[4096]; -reg [7:0] wave_p_t[2048]; -reg [7:0] wave_ps_[4096]; -reg [7:0] wave_pst[4096]; - -initial begin - integer i; - for(i = 0; i<4096; i=i+1) wave__st[i] = - (i < 'h07e) ? 8'h00 : (i < 'h080) ? 8'h03 : (i < 'h0fc) ? 8'h00 : (i < 'h100) ? 8'h07 : - (i < 'h17e) ? 8'h00 : (i < 'h180) ? 8'h03 : (i < 'h1f8) ? 8'h00 : (i < 'h1fc) ? 8'h0e : - (i < 'h200) ? 8'h0f : (i < 'h27e) ? 8'h00 : (i < 'h280) ? 8'h03 : (i < 'h2fc) ? 8'h00 : - (i < 'h300) ? 8'h07 : (i < 'h37e) ? 8'h00 : (i < 'h380) ? 8'h03 : (i < 'h3bf) ? 8'h00 : - (i < 'h3c0) ? 8'h01 : (i < 'h3f0) ? 8'h00 : (i < 'h3f8) ? 8'h1c : (i < 'h3fa) ? 8'h1e : - (i < 'h400) ? 8'h1f : (i < 'h47e) ? 8'h00 : (i < 'h480) ? 8'h03 : (i < 'h4fc) ? 8'h00 : - (i < 'h500) ? 8'h07 : (i < 'h57e) ? 8'h00 : (i < 'h580) ? 8'h03 : (i < 'h5f8) ? 8'h00 : - (i < 'h5fc) ? 8'h0e : (i < 'h5ff) ? 8'h0f : (i < 'h600) ? 8'h1f : (i < 'h67e) ? 8'h00 : - (i < 'h680) ? 8'h03 : (i < 'h6fc) ? 8'h00 : (i < 'h700) ? 8'h07 : (i < 'h77e) ? 8'h00 : - (i < 'h780) ? 8'h03 : (i < 'h7bf) ? 8'h00 : (i < 'h7c0) ? 8'h01 : (i < 'h7e0) ? 8'h00 : - (i < 'h7f0) ? 8'h38 : (i < 'h7f7) ? 8'h3c : (i < 'h7f8) ? 8'h3e : (i < 'h800) ? 8'h7f : - (i < 'h87e) ? 8'h00 : (i < 'h880) ? 8'h03 : (i < 'h8fc) ? 8'h00 : (i < 'h900) ? 8'h07 : - (i < 'h97e) ? 8'h00 : (i < 'h980) ? 8'h03 : (i < 'h9f8) ? 8'h00 : (i < 'h9fc) ? 8'h0e : - (i < 'ha00) ? 8'h0f : (i < 'ha7e) ? 8'h00 : (i < 'ha80) ? 8'h03 : (i < 'hafc) ? 8'h00 : - (i < 'hb00) ? 8'h07 : (i < 'hb7e) ? 8'h00 : (i < 'hb80) ? 8'h03 : (i < 'hbbf) ? 8'h00 : - (i < 'hbc0) ? 8'h01 : (i < 'hbf0) ? 8'h00 : (i < 'hbf8) ? 8'h1c : (i < 'hbfa) ? 8'h1e : - (i < 'hbfe) ? 8'h1f : (i < 'hc00) ? 8'h3f : (i < 'hc7e) ? 8'h00 : (i < 'hc80) ? 8'h03 : - (i < 'hcfc) ? 8'h00 : (i < 'hd00) ? 8'h07 : (i < 'hd7e) ? 8'h00 : (i < 'hd80) ? 8'h03 : - (i < 'hdbf) ? 8'h00 : (i < 'hdc0) ? 8'h01 : (i < 'hdf8) ? 8'h00 : (i < 'hdfc) ? 8'h0e : - (i < 'hdfe) ? 8'h0f : (i < 'he00) ? 8'h1f : (i < 'he7c) ? 8'h00 : (i < 'he7d) ? 8'h80 : - (i < 'he7e) ? 8'h00 : (i < 'he80) ? 8'h83 : (i < 'hefc) ? 8'h80 : (i < 'heff) ? 8'h87 : - (i < 'hf00) ? 8'h8f : (i < 'hf01) ? 8'hc0 : (i < 'hf03) ? 8'he0 : (i < 'hf05) ? 8'hc0 : - (i < 'hf09) ? 8'he0 : (i < 'hf11) ? 8'hc0 : (i < 'hf13) ? 8'he0 : (i < 'hf18) ? 8'hc0 : - (i < 'hf19) ? 8'he0 : (i < 'hf21) ? 8'hc0 : (i < 'hf23) ? 8'he0 : (i < 'hf25) ? 8'hc0 : - (i < 'hf2b) ? 8'he0 : (i < 'hf2c) ? 8'hc0 : (i < 'hf2d) ? 8'he0 : (i < 'hf2e) ? 8'hc0 : - (i < 'hf7e) ? 8'he0 : (i < 'hf80) ? 8'he3 : (i < 'hfbf) ? 8'hf0 : (i < 'hfc0) ? 8'hf1 : - (i < 'hfe0) ? 8'hf8 : (i < 'hff0) ? 8'hfc : (i < 'hff8) ? 8'hfe : 8'hff; - - for(i = 0; i<2048; i=i+1) wave_p_t[i] = - (i < 'h0ff) ? 8'h00 : (i < 'h100) ? 8'h07 : (i < 'h1fb) ? 8'h00 : (i < 'h1fc) ? 8'h1c : - (i < 'h1fd) ? 8'h00 : (i < 'h1fe) ? 8'h3c : (i < 'h200) ? 8'h3f : (i < 'h2fd) ? 8'h00 : - (i < 'h2fe) ? 8'h0c : (i < 'h2ff) ? 8'h5e : (i < 'h300) ? 8'h5f : (i < 'h377) ? 8'h00 : - (i < 'h378) ? 8'h40 : (i < 'h37b) ? 8'h00 : (i < 'h37d) ? 8'h40 : (i < 'h37f) ? 8'h60 : - (i < 'h380) ? 8'h6f : (i < 'h39f) ? 8'h00 : (i < 'h3a0) ? 8'h40 : (i < 'h3ae) ? 8'h00 : - (i < 'h3b0) ? 8'h40 : (i < 'h3b3) ? 8'h00 : (i < 'h3b7) ? 8'h40 : (i < 'h3b8) ? 8'h60 : - (i < 'h3ba) ? 8'h40 : (i < 'h3be) ? 8'h60 : (i < 'h3bf) ? 8'h70 : (i < 'h3c0) ? 8'h77 : - (i < 'h3c5) ? 8'h00 : (i < 'h3cd) ? 8'h40 : (i < 'h3d0) ? 8'h60 : (i < 'h3d3) ? 8'h40 : - (i < 'h3d7) ? 8'h60 : (i < 'h3d8) ? 8'h70 : (i < 'h3db) ? 8'h60 : (i < 'h3de) ? 8'h70 : - (i < 'h3df) ? 8'h78 : (i < 'h3e0) ? 8'h7b : (i < 'h3e3) ? 8'h60 : (i < 'h3e4) ? 8'h70 : - (i < 'h3e5) ? 8'h60 : (i < 'h3eb) ? 8'h70 : (i < 'h3ef) ? 8'h78 : (i < 'h3f0) ? 8'h7c : - (i < 'h3f3) ? 8'h78 : (i < 'h3f4) ? 8'h7c : (i < 'h3f5) ? 8'h78 : (i < 'h3f7) ? 8'h7c : - (i < 'h3f8) ? 8'h7e : (i < 'h3f9) ? 8'h7c : (i < 'h3fb) ? 8'h7e : (i < 'h400) ? 8'h7f : - (i < 'h47f) ? 8'h00 : (i < 'h480) ? 8'h80 : (i < 'h4bd) ? 8'h00 : (i < 'h4c0) ? 8'h80 : - (i < 'h4cf) ? 8'h00 : (i < 'h4d0) ? 8'h80 : (i < 'h4d7) ? 8'h00 : (i < 'h4d8) ? 8'h80 : - (i < 'h4da) ? 8'h00 : (i < 'h4e0) ? 8'h80 : (i < 'h4e3) ? 8'h00 : (i < 'h4fe) ? 8'h80 : - (i < 'h4ff) ? 8'h8e : (i < 'h500) ? 8'h9f : (i < 'h51f) ? 8'h00 : (i < 'h520) ? 8'h80 : - (i < 'h52b) ? 8'h00 : (i < 'h52c) ? 8'h80 : (i < 'h52d) ? 8'h00 : (i < 'h530) ? 8'h80 : - (i < 'h532) ? 8'h00 : (i < 'h540) ? 8'h80 : (i < 'h543) ? 8'h00 : (i < 'h544) ? 8'h80 : - (i < 'h545) ? 8'h00 : (i < 'h57f) ? 8'h80 : (i < 'h580) ? 8'haf : (i < 'h5bb) ? 8'h80 : - (i < 'h5bf) ? 8'ha0 : (i < 'h5c0) ? 8'hb7 : (i < 'h5cf) ? 8'h80 : (i < 'h5d0) ? 8'ha0 : - (i < 'h5d6) ? 8'h80 : (i < 'h5db) ? 8'ha0 : (i < 'h5dc) ? 8'hb0 : (i < 'h5dd) ? 8'ha0 : - (i < 'h5df) ? 8'hb0 : (i < 'h5e0) ? 8'hbb : (i < 'h5e6) ? 8'ha0 : (i < 'h5e8) ? 8'hb0 : - (i < 'h5e9) ? 8'ha0 : (i < 'h5eb) ? 8'hb0 : (i < 'h5ec) ? 8'hb8 : (i < 'h5ed) ? 8'hb0 : - (i < 'h5ef) ? 8'hb8 : (i < 'h5f0) ? 8'hbc : (i < 'h5f1) ? 8'hb0 : (i < 'h5f5) ? 8'hb8 : - (i < 'h5f7) ? 8'hbc : (i < 'h5f8) ? 8'hbe : (i < 'h5fa) ? 8'hbc : (i < 'h5fb) ? 8'hbe : - (i < 'h5fc) ? 8'hbf : (i < 'h5fd) ? 8'hbe : (i < 'h600) ? 8'hbf : (i < 'h63e) ? 8'h80 : - (i < 'h640) ? 8'hc0 : (i < 'h657) ? 8'h80 : (i < 'h658) ? 8'hc0 : (i < 'h65a) ? 8'h80 : - (i < 'h660) ? 8'hc0 : (i < 'h663) ? 8'h80 : (i < 'h664) ? 8'hc0 : (i < 'h665) ? 8'h80 : - (i < 'h67f) ? 8'hc0 : (i < 'h680) ? 8'hcf : (i < 'h686) ? 8'h80 : (i < 'h689) ? 8'hc0 : - (i < 'h68a) ? 8'h80 : (i < 'h6bf) ? 8'hc0 : (i < 'h6c0) ? 8'hd7 : (i < 'h6dd) ? 8'hc0 : - (i < 'h6df) ? 8'hd0 : (i < 'h6e0) ? 8'hd9 : (i < 'h6e7) ? 8'hc0 : (i < 'h6e8) ? 8'hd0 : - (i < 'h6e9) ? 8'hc0 : (i < 'h6ed) ? 8'hd0 : (i < 'h6ef) ? 8'hd8 : (i < 'h6f0) ? 8'hdc : - (i < 'h6f2) ? 8'hd0 : (i < 'h6f5) ? 8'hd8 : (i < 'h6f7) ? 8'hdc : (i < 'h6f8) ? 8'hde : - (i < 'h6fa) ? 8'hdc : (i < 'h6fb) ? 8'hde : (i < 'h6fc) ? 8'hdf : (i < 'h6fd) ? 8'hde : - (i < 'h700) ? 8'hdf : (i < 'h71b) ? 8'hc0 : (i < 'h71c) ? 8'he0 : (i < 'h71d) ? 8'hc0 : - (i < 'h720) ? 8'he0 : (i < 'h727) ? 8'hc0 : (i < 'h728) ? 8'he0 : (i < 'h72a) ? 8'hc0 : - (i < 'h73f) ? 8'he0 : (i < 'h740) ? 8'he7 : (i < 'h75f) ? 8'he0 : (i < 'h760) ? 8'he8 : - (i < 'h76e) ? 8'he0 : (i < 'h76f) ? 8'he8 : (i < 'h770) ? 8'hec : (i < 'h773) ? 8'he0 : - (i < 'h776) ? 8'he8 : (i < 'h777) ? 8'hec : (i < 'h778) ? 8'hee : (i < 'h77b) ? 8'hec : - (i < 'h77d) ? 8'hee : (i < 'h780) ? 8'hef : (i < 'h78d) ? 8'he0 : (i < 'h790) ? 8'hf0 : - (i < 'h792) ? 8'he0 : (i < 'h7af) ? 8'hf0 : (i < 'h7b0) ? 8'hf4 : (i < 'h7b7) ? 8'hf0 : - (i < 'h7b8) ? 8'hf4 : (i < 'h7b9) ? 8'hf0 : (i < 'h7bb) ? 8'hf4 : (i < 'h7bd) ? 8'hf6 : - (i < 'h7c0) ? 8'hf7 : (i < 'h7c3) ? 8'hf0 : (i < 'h7c4) ? 8'hf8 : (i < 'h7c5) ? 8'hf0 : - (i < 'h7db) ? 8'hf8 : (i < 'h7dd) ? 8'hfa : (i < 'h7e0) ? 8'hfb : (i < 'h7e1) ? 8'hf8 : - (i < 'h7ed) ? 8'hfc : (i < 'h7f0) ? 8'hfd : (i < 'h7f8) ? 8'hfe : 8'hff; - - for(i = 0; i<4096; i=i+1) wave_ps_[i] = - (i < 'h07f) ? 8'h00 : (i < 'h080) ? 8'h03 : (i < 'h0bf) ? 8'h00 : (i < 'h0c0) ? 8'h01 : - (i < 'h0ff) ? 8'h00 : (i < 'h100) ? 8'h0f : (i < 'h17f) ? 8'h00 : (i < 'h180) ? 8'h07 : - (i < 'h1bf) ? 8'h00 : (i < 'h1c0) ? 8'h03 : (i < 'h1df) ? 8'h00 : (i < 'h1e0) ? 8'h01 : - (i < 'h1fd) ? 8'h00 : (i < 'h1ff) ? 8'h07 : (i < 'h200) ? 8'h1f : (i < 'h27f) ? 8'h00 : - (i < 'h280) ? 8'h03 : (i < 'h2bf) ? 8'h00 : (i < 'h2c0) ? 8'h03 : (i < 'h2df) ? 8'h00 : - (i < 'h2e0) ? 8'h01 : (i < 'h2fe) ? 8'h00 : (i < 'h2ff) ? 8'h01 : (i < 'h300) ? 8'h0f : - (i < 'h33f) ? 8'h00 : (i < 'h340) ? 8'h01 : (i < 'h37f) ? 8'h00 : (i < 'h380) ? 8'h17 : - (i < 'h3bf) ? 8'h00 : (i < 'h3c0) ? 8'h3b : (i < 'h3df) ? 8'h00 : (i < 'h3e0) ? 8'h3d : - (i < 'h3ef) ? 8'h00 : (i < 'h3f0) ? 8'h3e : (i < 'h3f7) ? 8'h00 : (i < 'h3f8) ? 8'h3f : - (i < 'h3f9) ? 8'h00 : (i < 'h3fa) ? 8'h0c : (i < 'h3fb) ? 8'h1c : (i < 'h3fc) ? 8'h3f : - (i < 'h3fd) ? 8'h1e : (i < 'h400) ? 8'h3f : (i < 'h47f) ? 8'h00 : (i < 'h480) ? 8'h03 : - (i < 'h4bf) ? 8'h00 : (i < 'h4c0) ? 8'h01 : (i < 'h4ff) ? 8'h00 : (i < 'h500) ? 8'h0f : - (i < 'h53f) ? 8'h00 : (i < 'h540) ? 8'h01 : (i < 'h57f) ? 8'h00 : (i < 'h580) ? 8'h07 : - (i < 'h5bf) ? 8'h00 : (i < 'h5c0) ? 8'h0b : (i < 'h5df) ? 8'h00 : (i < 'h5e0) ? 8'h0a : - (i < 'h5ef) ? 8'h00 : (i < 'h5f0) ? 8'h5e : (i < 'h5f7) ? 8'h00 : (i < 'h5f8) ? 8'h5f : - (i < 'h5fb) ? 8'h00 : (i < 'h5fc) ? 8'h5f : (i < 'h5fd) ? 8'h0c : (i < 'h600) ? 8'h5f : - (i < 'h63f) ? 8'h00 : (i < 'h640) ? 8'h01 : (i < 'h67f) ? 8'h00 : (i < 'h680) ? 8'h47 : - (i < 'h6bf) ? 8'h00 : (i < 'h6c0) ? 8'h43 : (i < 'h6df) ? 8'h00 : (i < 'h6e0) ? 8'h65 : - (i < 'h6ef) ? 8'h00 : (i < 'h6f0) ? 8'h6e : (i < 'h6f7) ? 8'h00 : (i < 'h6f8) ? 8'h6f : - (i < 'h6f9) ? 8'h00 : (i < 'h6fb) ? 8'h40 : (i < 'h6fc) ? 8'h6f : (i < 'h6fd) ? 8'h40 : - (i < 'h700) ? 8'h6f : (i < 'h73f) ? 8'h00 : (i < 'h740) ? 8'h63 : (i < 'h75e) ? 8'h00 : - (i < 'h75f) ? 8'h40 : (i < 'h760) ? 8'h61 : (i < 'h767) ? 8'h00 : (i < 'h768) ? 8'h40 : - (i < 'h76b) ? 8'h00 : (i < 'h76c) ? 8'h40 : (i < 'h76d) ? 8'h00 : (i < 'h76f) ? 8'h40 : - (i < 'h770) ? 8'h70 : (i < 'h772) ? 8'h00 : (i < 'h777) ? 8'h40 : (i < 'h778) ? 8'h70 : - (i < 'h779) ? 8'h40 : (i < 'h77b) ? 8'h60 : (i < 'h77c) ? 8'h77 : (i < 'h77d) ? 8'h60 : - (i < 'h780) ? 8'h77 : (i < 'h78f) ? 8'h00 : (i < 'h790) ? 8'h40 : (i < 'h796) ? 8'h00 : - (i < 'h797) ? 8'h40 : (i < 'h798) ? 8'h60 : (i < 'h799) ? 8'h00 : (i < 'h79b) ? 8'h40 : - (i < 'h79c) ? 8'h60 : (i < 'h79d) ? 8'h40 : (i < 'h79f) ? 8'h60 : (i < 'h7a0) ? 8'h79 : - (i < 'h7a1) ? 8'h00 : (i < 'h7a7) ? 8'h40 : (i < 'h7a8) ? 8'h60 : (i < 'h7ab) ? 8'h40 : - (i < 'h7af) ? 8'h60 : (i < 'h7b0) ? 8'h78 : (i < 'h7b1) ? 8'h40 : (i < 'h7b7) ? 8'h60 : - (i < 'h7b8) ? 8'h78 : (i < 'h7b9) ? 8'h60 : (i < 'h7bb) ? 8'h70 : (i < 'h7bc) ? 8'h78 : - (i < 'h7bd) ? 8'h70 : (i < 'h7be) ? 8'h79 : (i < 'h7c0) ? 8'h7b : (i < 'h7c7) ? 8'h60 : - (i < 'h7c8) ? 8'h70 : (i < 'h7cb) ? 8'h60 : (i < 'h7cc) ? 8'h70 : (i < 'h7cd) ? 8'h60 : - (i < 'h7cf) ? 8'h70 : (i < 'h7d0) ? 8'h7c : (i < 'h7d1) ? 8'h60 : (i < 'h7d7) ? 8'h70 : - (i < 'h7d8) ? 8'h7c : (i < 'h7d9) ? 8'h70 : (i < 'h7db) ? 8'h78 : (i < 'h7dc) ? 8'h7c : - (i < 'h7dd) ? 8'h78 : (i < 'h7df) ? 8'h7c : (i < 'h7e0) ? 8'h7d : (i < 'h7e1) ? 8'h70 : - (i < 'h7e7) ? 8'h78 : (i < 'h7e8) ? 8'h7c : (i < 'h7e9) ? 8'h78 : (i < 'h7eb) ? 8'h7c : - (i < 'h7ec) ? 8'h7e : (i < 'h7ed) ? 8'h7c : (i < 'h7f0) ? 8'h7e : (i < 'h7f3) ? 8'h7c : - (i < 'h7f5) ? 8'h7e : (i < 'h7f8) ? 8'h7f : (i < 'h7f9) ? 8'h7e : (i < 'h7ff) ? 8'h7f : - (i < 'h800) ? 8'hff : (i < 'h87f) ? 8'h00 : (i < 'h880) ? 8'h03 : (i < 'h8bf) ? 8'h00 : - (i < 'h8c0) ? 8'h01 : (i < 'h8ff) ? 8'h00 : (i < 'h900) ? 8'h8f : (i < 'h93f) ? 8'h00 : - (i < 'h940) ? 8'h01 : (i < 'h97f) ? 8'h00 : (i < 'h980) ? 8'h87 : (i < 'h9bf) ? 8'h00 : - (i < 'h9c0) ? 8'h83 : (i < 'h9de) ? 8'h00 : (i < 'h9df) ? 8'h80 : (i < 'h9e0) ? 8'h8d : - (i < 'h9e7) ? 8'h00 : (i < 'h9e8) ? 8'h80 : (i < 'h9eb) ? 8'h00 : (i < 'h9ec) ? 8'h80 : - (i < 'h9ed) ? 8'h00 : (i < 'h9ef) ? 8'h80 : (i < 'h9f0) ? 8'h8e : (i < 'h9f3) ? 8'h00 : - (i < 'h9f7) ? 8'h80 : (i < 'h9f8) ? 8'h8f : (i < 'h9fb) ? 8'h80 : (i < 'h9fc) ? 8'h9f : - (i < 'h9fd) ? 8'h80 : (i < 'ha00) ? 8'h9f : (i < 'ha3f) ? 8'h00 : (i < 'ha40) ? 8'h01 : - (i < 'ha6f) ? 8'h00 : (i < 'ha70) ? 8'h80 : (i < 'ha77) ? 8'h00 : (i < 'ha78) ? 8'h80 : - (i < 'ha7b) ? 8'h00 : (i < 'ha7c) ? 8'h80 : (i < 'ha7d) ? 8'h00 : (i < 'ha7f) ? 8'h80 : - (i < 'ha80) ? 8'h87 : (i < 'ha9f) ? 8'h00 : (i < 'haa0) ? 8'h80 : (i < 'haaf) ? 8'h00 : - (i < 'hab0) ? 8'h80 : (i < 'hab7) ? 8'h00 : (i < 'hab8) ? 8'h80 : (i < 'habb) ? 8'h00 : - (i < 'habf) ? 8'h80 : (i < 'hac0) ? 8'h83 : (i < 'hacf) ? 8'h00 : (i < 'had0) ? 8'h80 : - (i < 'had5) ? 8'h00 : (i < 'had8) ? 8'h80 : (i < 'had9) ? 8'h00 : (i < 'hadf) ? 8'h80 : - (i < 'hae0) ? 8'h81 : (i < 'haef) ? 8'h80 : (i < 'haf0) ? 8'h84 : (i < 'haf7) ? 8'h80 : - (i < 'haf8) ? 8'h87 : (i < 'hafb) ? 8'h80 : (i < 'hafc) ? 8'h87 : (i < 'hafd) ? 8'h80 : - (i < 'hafe) ? 8'h8f : (i < 'hb00) ? 8'haf : (i < 'hb0f) ? 8'h00 : (i < 'hb10) ? 8'h80 : - (i < 'hb17) ? 8'h00 : (i < 'hb18) ? 8'h80 : (i < 'hb1b) ? 8'h00 : (i < 'hb20) ? 8'h80 : - (i < 'hb23) ? 8'h00 : (i < 'hb24) ? 8'h80 : (i < 'hb26) ? 8'h00 : (i < 'hb28) ? 8'h80 : - (i < 'hb29) ? 8'h00 : (i < 'hb3f) ? 8'h80 : (i < 'hb40) ? 8'h83 : (i < 'hb5f) ? 8'h80 : - (i < 'hb60) ? 8'h81 : (i < 'hb6f) ? 8'h80 : (i < 'hb70) ? 8'ha0 : (i < 'hb77) ? 8'h80 : - (i < 'hb78) ? 8'ha0 : (i < 'hb7b) ? 8'h80 : (i < 'hb7c) ? 8'ha0 : (i < 'hb7d) ? 8'h80 : - (i < 'hb7e) ? 8'ha3 : (i < 'hb80) ? 8'hb7 : (i < 'hb9f) ? 8'h80 : (i < 'hba0) ? 8'hb1 : - (i < 'hbaf) ? 8'h80 : (i < 'hbb0) ? 8'hb0 : (i < 'hbb7) ? 8'h80 : (i < 'hbb8) ? 8'hb0 : - (i < 'hbb9) ? 8'h80 : (i < 'hbbb) ? 8'ha0 : (i < 'hbbc) ? 8'hb0 : (i < 'hbbd) ? 8'ha0 : - (i < 'hbbe) ? 8'hb8 : (i < 'hbbf) ? 8'hb9 : (i < 'hbc0) ? 8'hbb : (i < 'hbc7) ? 8'h80 : - (i < 'hbc8) ? 8'ha0 : (i < 'hbcb) ? 8'h80 : (i < 'hbcc) ? 8'ha0 : (i < 'hbcd) ? 8'h80 : - (i < 'hbcf) ? 8'ha0 : (i < 'hbd0) ? 8'hb8 : (i < 'hbd1) ? 8'h80 : (i < 'hbd7) ? 8'ha0 : - (i < 'hbd8) ? 8'hb8 : (i < 'hbd9) ? 8'ha0 : (i < 'hbdb) ? 8'hb0 : (i < 'hbdc) ? 8'hb8 : - (i < 'hbdd) ? 8'hb0 : (i < 'hbdf) ? 8'hbc : (i < 'hbe0) ? 8'hbd : (i < 'hbe1) ? 8'ha0 : - (i < 'hbe5) ? 8'hb0 : (i < 'hbe7) ? 8'hb8 : (i < 'hbe8) ? 8'hbc : (i < 'hbe9) ? 8'hb0 : - (i < 'hbeb) ? 8'hb8 : (i < 'hbec) ? 8'hbc : (i < 'hbed) ? 8'hb8 : (i < 'hbee) ? 8'hbc : - (i < 'hbf0) ? 8'hbe : (i < 'hbf1) ? 8'hb8 : (i < 'hbf3) ? 8'hbc : (i < 'hbf4) ? 8'hbe : - (i < 'hbf5) ? 8'hbc : (i < 'hbf7) ? 8'hbe : (i < 'hbf8) ? 8'hbf : (i < 'hbf9) ? 8'hbe : - (i < 'hc00) ? 8'hbf : (i < 'hc03) ? 8'h00 : (i < 'hc04) ? 8'h80 : (i < 'hc07) ? 8'h00 : - (i < 'hc08) ? 8'h80 : (i < 'hc0b) ? 8'h00 : (i < 'hc0c) ? 8'h80 : (i < 'hc0f) ? 8'h00 : - (i < 'hc10) ? 8'h80 : (i < 'hc11) ? 8'h00 : (i < 'hc18) ? 8'h80 : (i < 'hc19) ? 8'h00 : - (i < 'hc3f) ? 8'h80 : (i < 'hc40) ? 8'h81 : (i < 'hc7f) ? 8'h80 : (i < 'hc80) ? 8'hc7 : - (i < 'hcbe) ? 8'h80 : (i < 'hcbf) ? 8'hc0 : (i < 'hcc0) ? 8'hc3 : (i < 'hccf) ? 8'h80 : - (i < 'hcd0) ? 8'hc0 : (i < 'hcd7) ? 8'h80 : (i < 'hcd8) ? 8'hc0 : (i < 'hcdb) ? 8'h80 : - (i < 'hcdc) ? 8'hc0 : (i < 'hcdd) ? 8'h80 : (i < 'hcdf) ? 8'hc0 : (i < 'hce0) ? 8'hc1 : - (i < 'hce7) ? 8'h80 : (i < 'hce8) ? 8'hc0 : (i < 'hceb) ? 8'h80 : (i < 'hcf7) ? 8'hc0 : - (i < 'hcf8) ? 8'hc7 : (i < 'hcfb) ? 8'hc0 : (i < 'hcfc) ? 8'hc7 : (i < 'hcfd) ? 8'hc0 : - (i < 'hd00) ? 8'hcf : (i < 'hd1f) ? 8'h80 : (i < 'hd20) ? 8'hc0 : (i < 'hd2f) ? 8'h80 : - (i < 'hd30) ? 8'hc0 : (i < 'hd36) ? 8'h80 : (i < 'hd38) ? 8'hc0 : (i < 'hd39) ? 8'h80 : - (i < 'hd3f) ? 8'hc0 : (i < 'hd40) ? 8'hc3 : (i < 'hd47) ? 8'h80 : (i < 'hd48) ? 8'hc0 : - (i < 'hd4b) ? 8'h80 : (i < 'hd4c) ? 8'hc0 : (i < 'hd4d) ? 8'h80 : (i < 'hd50) ? 8'hc0 : - (i < 'hd51) ? 8'h80 : (i < 'hd5f) ? 8'hc0 : (i < 'hd60) ? 8'hc1 : (i < 'hd7d) ? 8'hc0 : - (i < 'hd7e) ? 8'hc1 : (i < 'hd7f) ? 8'hc7 : (i < 'hd80) ? 8'hd7 : (i < 'hdaf) ? 8'hc0 : - (i < 'hdb0) ? 8'hd0 : (i < 'hdb7) ? 8'hc0 : (i < 'hdb8) ? 8'hd0 : (i < 'hdbb) ? 8'hc0 : - (i < 'hdbc) ? 8'hd0 : (i < 'hdbd) ? 8'hc0 : (i < 'hdbe) ? 8'hd0 : (i < 'hdbf) ? 8'hd8 : - (i < 'hdc0) ? 8'hdb : (i < 'hdcf) ? 8'hc0 : (i < 'hdd0) ? 8'hd8 : (i < 'hdd7) ? 8'hc0 : - (i < 'hdd8) ? 8'hd8 : (i < 'hddb) ? 8'hc0 : (i < 'hddc) ? 8'hd8 : (i < 'hddd) ? 8'hd0 : - (i < 'hddf) ? 8'hd8 : (i < 'hde0) ? 8'hdd : (i < 'hde3) ? 8'hc0 : (i < 'hde4) ? 8'hd0 : - (i < 'hde5) ? 8'hc0 : (i < 'hde7) ? 8'hd0 : (i < 'hde8) ? 8'hdc : (i < 'hde9) ? 8'hd0 : - (i < 'hdeb) ? 8'hd8 : (i < 'hdec) ? 8'hdc : (i < 'hded) ? 8'hd8 : (i < 'hdef) ? 8'hdc : - (i < 'hdf0) ? 8'hde : (i < 'hdf1) ? 8'hd8 : (i < 'hdf3) ? 8'hdc : (i < 'hdf4) ? 8'hde : - (i < 'hdf5) ? 8'hdc : (i < 'hdf7) ? 8'hde : (i < 'hdf8) ? 8'hdf : (i < 'hdf9) ? 8'hde : - (i < 'he00) ? 8'hdf : (i < 'he3f) ? 8'hc0 : (i < 'he40) ? 8'he3 : (i < 'he57) ? 8'hc0 : - (i < 'he58) ? 8'he0 : (i < 'he5b) ? 8'hc0 : (i < 'he5c) ? 8'he0 : (i < 'he5d) ? 8'hc0 : - (i < 'he5f) ? 8'he0 : (i < 'he60) ? 8'he1 : (i < 'he67) ? 8'hc0 : (i < 'he68) ? 8'he0 : - (i < 'he6b) ? 8'hc0 : (i < 'he70) ? 8'he0 : (i < 'he71) ? 8'hc0 : (i < 'he7d) ? 8'he0 : - (i < 'he7e) ? 8'he1 : (i < 'he7f) ? 8'he3 : (i < 'he80) ? 8'he7 : (i < 'he87) ? 8'hc0 : - (i < 'he88) ? 8'he0 : (i < 'he8b) ? 8'hc0 : (i < 'he8c) ? 8'he0 : (i < 'he8d) ? 8'hc0 : - (i < 'he90) ? 8'he0 : (i < 'he93) ? 8'hc0 : (i < 'he94) ? 8'he0 : (i < 'he95) ? 8'hc0 : - (i < 'hebf) ? 8'he0 : (i < 'hec0) ? 8'heb : (i < 'hedb) ? 8'he0 : (i < 'hedc) ? 8'he8 : - (i < 'hedd) ? 8'he0 : (i < 'hedf) ? 8'he8 : (i < 'hee0) ? 8'hed : (i < 'hee7) ? 8'he0 : - (i < 'hee8) ? 8'hec : (i < 'heeb) ? 8'he0 : (i < 'heec) ? 8'hec : (i < 'heed) ? 8'he8 : - (i < 'heef) ? 8'hec : (i < 'hef0) ? 8'hee : (i < 'hef3) ? 8'he8 : (i < 'hef5) ? 8'hec : - (i < 'hef7) ? 8'hee : (i < 'hef8) ? 8'hef : (i < 'hef9) ? 8'hec : (i < 'hf00) ? 8'hef : - (i < 'hf1f) ? 8'he0 : (i < 'hf20) ? 8'hf0 : (i < 'hf27) ? 8'he0 : (i < 'hf28) ? 8'hf0 : - (i < 'hf2b) ? 8'he0 : (i < 'hf2c) ? 8'hf0 : (i < 'hf2d) ? 8'he0 : (i < 'hf30) ? 8'hf0 : - (i < 'hf33) ? 8'he0 : (i < 'hf3f) ? 8'hf0 : (i < 'hf40) ? 8'hf3 : (i < 'hf43) ? 8'he0 : - (i < 'hf5f) ? 8'hf0 : (i < 'hf60) ? 8'hf5 : (i < 'hf6d) ? 8'hf0 : (i < 'hf6f) ? 8'hf4 : - (i < 'hf70) ? 8'hf6 : (i < 'hf73) ? 8'hf0 : (i < 'hf74) ? 8'hf4 : (i < 'hf75) ? 8'hf0 : - (i < 'hf76) ? 8'hf4 : (i < 'hf77) ? 8'hf6 : (i < 'hf78) ? 8'hf7 : (i < 'hf79) ? 8'hf4 : - (i < 'hf7b) ? 8'hf6 : (i < 'hf80) ? 8'hf7 : (i < 'hf87) ? 8'hf0 : (i < 'hf88) ? 8'hf8 : - (i < 'hf8d) ? 8'hf0 : (i < 'hf90) ? 8'hf8 : (i < 'hf93) ? 8'hf0 : (i < 'hf94) ? 8'hf8 : - (i < 'hf95) ? 8'hf0 : (i < 'hf9f) ? 8'hf8 : (i < 'hfa0) ? 8'hf9 : (i < 'hfaf) ? 8'hf8 : - (i < 'hfb0) ? 8'hfa : (i < 'hfb7) ? 8'hf8 : (i < 'hfb8) ? 8'hfb : (i < 'hfb9) ? 8'hf8 : - (i < 'hfbb) ? 8'hfa : (i < 'hfc0) ? 8'hfb : (i < 'hfc3) ? 8'hf8 : (i < 'hfc4) ? 8'hfc : - (i < 'hfc5) ? 8'hf8 : (i < 'hfd7) ? 8'hfc : (i < 'hfd8) ? 8'hfd : (i < 'hfdb) ? 8'hfc : - (i < 'hfe0) ? 8'hfd : (i < 'hfe2) ? 8'hfc : (i < 'hff0) ? 8'hfe : 8'hff; - - for(i = 0; i<4096; i=i+1) wave_pst[i] = - (i < 'h3ff) ? 8'h00 : (i < 'h400) ? 8'h1f : (i < 'h7ee) ? 8'h00 : (i < 'h7ef) ? 8'h20 : - (i < 'h7f0) ? 8'h70 : (i < 'h7f1) ? 8'h60 : (i < 'h7f2) ? 8'h20 : (i < 'h7f7) ? 8'h70 : - (i < 'h7fa) ? 8'h78 : (i < 'h7fc) ? 8'h7c : (i < 'h7fe) ? 8'h7e : (i < 'h800) ? 8'h7f : - (i < 'hbfd) ? 8'h00 : (i < 'hbfe) ? 8'h08 : (i < 'hbff) ? 8'h1e : (i < 'hc00) ? 8'h3f : - (i < 'hdf7) ? 8'h00 : (i < 'hdfe) ? 8'h80 : (i < 'hdff) ? 8'h8c : (i < 'he00) ? 8'h9f : - (i < 'he3e) ? 8'h00 : (i < 'he40) ? 8'h80 : (i < 'he5e) ? 8'h00 : (i < 'he60) ? 8'h80 : - (i < 'he66) ? 8'h00 : (i < 'he67) ? 8'h80 : (i < 'he6a) ? 8'h00 : (i < 'he80) ? 8'h80 : - (i < 'he82) ? 8'h00 : (i < 'he83) ? 8'h80 : (i < 'he85) ? 8'h00 : (i < 'he89) ? 8'h80 : - (i < 'he8a) ? 8'h00 : (i < 'heee) ? 8'h80 : (i < 'heff) ? 8'hc0 : (i < 'hf00) ? 8'hcf : - (i < 'hf6f) ? 8'hc0 : (i < 'hf70) ? 8'he0 : (i < 'hf74) ? 8'hc0 : (i < 'hf7f) ? 8'he0 : - (i < 'hf80) ? 8'he3 : (i < 'hfb6) ? 8'he0 : (i < 'hfda) ? 8'hf0 : (i < 'hfeb) ? 8'hf8 : - (i < 'hff5) ? 8'hfc : (i < 'hff9) ? 8'hfe : 8'hff; -end - -endmodule diff --git a/cores/c64/rtl/sid8580/sid_voice.v b/cores/c64/rtl/sid8580/sid_voice.v new file mode 100644 index 0000000..1f4cbf0 --- /dev/null +++ b/cores/c64/rtl/sid8580/sid_voice.v @@ -0,0 +1,960 @@ +module sid_voice (clock, reset, freq_lo, freq_hi, pw_lo, pw_hi, + control, att_dec, sus_rel, osc_msb_in, osc_msb_out, + signal_out, osc_out, env_out); + +// Input Signals +input wire [0:0] clock; +input wire [0:0] reset; +input wire [7:0] freq_lo; +input wire [7:0] freq_hi; +input wire [7:0] pw_lo; +input wire [3:0] pw_hi; +input wire [7:0] control; +input wire [7:0] att_dec; +input wire [7:0] sus_rel; +input wire [0:0] osc_msb_in; + +// Output Signals +output wire [ 0:0] osc_msb_out; +output wire [11:0] signal_out; +output wire [ 7:0] osc_out; +output wire [ 7:0] env_out; + +// Internal Signals +reg [23:0] oscillator; +reg [ 0:0] osc_edge; +reg [ 0:0] osc_msb_in_prv; +reg [11:0] triangle; +reg [11:0] sawtooth; +reg [11:0] pulse; +reg [11:0] noise; +reg [22:0] lfsr_noise; +reg [ 7:0] wave__st; +reg [ 7:0] wave_p_t; +reg [ 7:0] wave_ps_; +reg [ 7:0] wave_pst; +wire [ 7:0] envelope; +reg [11:0] wave_out; +reg [19:0] dca_out; + +`define noise_ctrl control[7] +`define pulse_ctrl control[6] +`define saw_ctrl control[5] +`define tri_ctrl control[4] +`define test_ctrl control[3] +`define ringmod_ctrl control[2] +`define sync_ctrl control[1] + +// Signal Assignments +assign osc_msb_out = oscillator[23]; +assign signal_out = dca_out[19:8]; +assign osc_out = wave_out[11:4]; +assign env_out = envelope; + +// Digital Controlled Amplifier +always @(posedge clock) +begin + dca_out <= wave_out * envelope; +end + +// Envelope Instantiation +sid_envelope adsr (.clock(clock), .reset(reset), .gate(control[0]), + .att_dec(att_dec), .sus_rel(sus_rel), .envelope(envelope)); + +// Phase Accumulating Oscillator +always @(posedge clock) +begin + osc_msb_in_prv <= osc_msb_in; + if (reset || `test_ctrl || + ((`sync_ctrl) && (!osc_msb_in) && (osc_msb_in != osc_msb_in_prv))) + oscillator <= 24'h000000; + else + oscillator <= oscillator + {freq_hi, freq_lo}; +end + +// Waveform Generator +always @(posedge clock) +begin + if (reset) + begin + triangle <= 12'h000; + sawtooth <= 12'h000; + pulse <= 12'h000; + noise <= 12'h000; + osc_edge <= 1'b0; + lfsr_noise <= 23'h7fffff; + end + else + begin + triangle <= (`ringmod_ctrl) ? + {({11{osc_msb_in}} ^ + {{11{oscillator[23]}}}) ^ oscillator[22:12], 1'b0} : + {{11{oscillator[23]}} ^ oscillator[22:12], 1'b0}; + sawtooth <= oscillator[23:12]; + pulse <= (`test_ctrl) ? 12'hfff : + (oscillator[23:12] >= {pw_hi, pw_lo}) ? {12{1'b1}} : {12{1'b0}}; + noise <= {lfsr_noise[21], lfsr_noise[19], lfsr_noise[15], + lfsr_noise[12], lfsr_noise[10], lfsr_noise[6], + lfsr_noise[3], lfsr_noise[1], 4'b0000}; + osc_edge <= (oscillator[19] && !osc_edge) ? 1'b1 : + (!oscillator[19] && osc_edge) ? 1'b0 : osc_edge; + lfsr_noise <= (oscillator[19] && !osc_edge) ? + {lfsr_noise[21:0], (lfsr_noise[22] | `test_ctrl) ^ + lfsr_noise[17]} : lfsr_noise; + end +end + +// Waveform Output Selector +always @(posedge clock) +begin + case (control[7:4]) + 4'b0001: + wave_out <= triangle; + 4'b0010: + wave_out <= sawtooth; + 4'b0011: + wave_out <= {wave__st, 4'b0000}; + 4'b0100: + wave_out <= pulse; + 4'b0101: + wave_out <= {wave_p_t, 4'b0000} & pulse; + 4'b0110: + wave_out <= {wave_ps_, 4'b0000} & pulse; + 4'b0111: + wave_out <= {wave_pst, 4'b0000} & pulse; + 4'b1000: + wave_out <= noise; + default: + wave_out <= 12'h000; + endcase +end + +// Combined Waveform Lookup Logic +always @(sawtooth or triangle) +begin + wave__st = (sawtooth < 12'h07e) ? 8'h00 : + (sawtooth < 12'h080) ? 8'h03 : + (sawtooth < 12'h0fc) ? 8'h00 : + (sawtooth < 12'h100) ? 8'h07 : + (sawtooth < 12'h17e) ? 8'h00 : + (sawtooth < 12'h180) ? 8'h03 : + (sawtooth < 12'h1f8) ? 8'h00 : + (sawtooth < 12'h1fc) ? 8'h0e : + (sawtooth < 12'h200) ? 8'h0f : + (sawtooth < 12'h27e) ? 8'h00 : + (sawtooth < 12'h280) ? 8'h03 : + (sawtooth < 12'h2fc) ? 8'h00 : + (sawtooth < 12'h300) ? 8'h07 : + (sawtooth < 12'h37e) ? 8'h00 : + (sawtooth < 12'h380) ? 8'h03 : + (sawtooth < 12'h3bf) ? 8'h00 : + (sawtooth < 12'h3c0) ? 8'h01 : + (sawtooth < 12'h3f0) ? 8'h00 : + (sawtooth < 12'h3f8) ? 8'h1c : + (sawtooth < 12'h3fa) ? 8'h1e : + (sawtooth < 12'h400) ? 8'h1f : + (sawtooth < 12'h47e) ? 8'h00 : + (sawtooth < 12'h480) ? 8'h03 : + (sawtooth < 12'h4fc) ? 8'h00 : + (sawtooth < 12'h500) ? 8'h07 : + (sawtooth < 12'h57e) ? 8'h00 : + (sawtooth < 12'h580) ? 8'h03 : + (sawtooth < 12'h5f8) ? 8'h00 : + (sawtooth < 12'h5fc) ? 8'h0e : + (sawtooth < 12'h5ff) ? 8'h0f : + (sawtooth < 12'h600) ? 8'h1f : + (sawtooth < 12'h67e) ? 8'h00 : + (sawtooth < 12'h680) ? 8'h03 : + (sawtooth < 12'h6fc) ? 8'h00 : + (sawtooth < 12'h700) ? 8'h07 : + (sawtooth < 12'h77e) ? 8'h00 : + (sawtooth < 12'h780) ? 8'h03 : + (sawtooth < 12'h7bf) ? 8'h00 : + (sawtooth < 12'h7c0) ? 8'h01 : + (sawtooth < 12'h7e0) ? 8'h00 : + (sawtooth < 12'h7f0) ? 8'h38 : + (sawtooth < 12'h7f7) ? 8'h3c : + (sawtooth < 12'h7f8) ? 8'h3e : + (sawtooth < 12'h800) ? 8'h7f : + (sawtooth < 12'h87e) ? 8'h00 : + (sawtooth < 12'h880) ? 8'h03 : + (sawtooth < 12'h8fc) ? 8'h00 : + (sawtooth < 12'h900) ? 8'h07 : + (sawtooth < 12'h97e) ? 8'h00 : + (sawtooth < 12'h980) ? 8'h03 : + (sawtooth < 12'h9f8) ? 8'h00 : + (sawtooth < 12'h9fc) ? 8'h0e : + (sawtooth < 12'ha00) ? 8'h0f : + (sawtooth < 12'ha7e) ? 8'h00 : + (sawtooth < 12'ha80) ? 8'h03 : + (sawtooth < 12'hafc) ? 8'h00 : + (sawtooth < 12'hb00) ? 8'h07 : + (sawtooth < 12'hb7e) ? 8'h00 : + (sawtooth < 12'hb80) ? 8'h03 : + (sawtooth < 12'hbbf) ? 8'h00 : + (sawtooth < 12'hbc0) ? 8'h01 : + (sawtooth < 12'hbf0) ? 8'h00 : + (sawtooth < 12'hbf8) ? 8'h1c : + (sawtooth < 12'hbfa) ? 8'h1e : + (sawtooth < 12'hbfe) ? 8'h1f : + (sawtooth < 12'hc00) ? 8'h3f : + (sawtooth < 12'hc7e) ? 8'h00 : + (sawtooth < 12'hc80) ? 8'h03 : + (sawtooth < 12'hcfc) ? 8'h00 : + (sawtooth < 12'hd00) ? 8'h07 : + (sawtooth < 12'hd7e) ? 8'h00 : + (sawtooth < 12'hd80) ? 8'h03 : + (sawtooth < 12'hdbf) ? 8'h00 : + (sawtooth < 12'hdc0) ? 8'h01 : + (sawtooth < 12'hdf8) ? 8'h00 : + (sawtooth < 12'hdfc) ? 8'h0e : + (sawtooth < 12'hdfe) ? 8'h0f : + (sawtooth < 12'he00) ? 8'h1f : + (sawtooth < 12'he7c) ? 8'h00 : + (sawtooth < 12'he7d) ? 8'h80 : + (sawtooth < 12'he7e) ? 8'h00 : + (sawtooth < 12'he80) ? 8'h83 : + (sawtooth < 12'hefc) ? 8'h80 : + (sawtooth < 12'heff) ? 8'h87 : + (sawtooth < 12'hf00) ? 8'h8f : + (sawtooth < 12'hf01) ? 8'hc0 : + (sawtooth < 12'hf03) ? 8'he0 : + (sawtooth < 12'hf05) ? 8'hc0 : + (sawtooth < 12'hf09) ? 8'he0 : + (sawtooth < 12'hf11) ? 8'hc0 : + (sawtooth < 12'hf13) ? 8'he0 : + (sawtooth < 12'hf18) ? 8'hc0 : + (sawtooth < 12'hf19) ? 8'he0 : + (sawtooth < 12'hf21) ? 8'hc0 : + (sawtooth < 12'hf23) ? 8'he0 : + (sawtooth < 12'hf25) ? 8'hc0 : + (sawtooth < 12'hf2b) ? 8'he0 : + (sawtooth < 12'hf2c) ? 8'hc0 : + (sawtooth < 12'hf2d) ? 8'he0 : + (sawtooth < 12'hf2e) ? 8'hc0 : + (sawtooth < 12'hf7e) ? 8'he0 : + (sawtooth < 12'hf80) ? 8'he3 : + (sawtooth < 12'hfbf) ? 8'hf0 : + (sawtooth < 12'hfc0) ? 8'hf1 : + (sawtooth < 12'hfe0) ? 8'hf8 : + (sawtooth < 12'hff0) ? 8'hfc : + (sawtooth < 12'hff8) ? 8'hfe : 8'hff; + wave_p_t = (triangle[11:1] < 11'h0ff) ? 8'h00 : + (triangle[11:1] < 11'h100) ? 8'h07 : + (triangle[11:1] < 11'h1fb) ? 8'h00 : + (triangle[11:1] < 11'h1fc) ? 8'h1c : + (triangle[11:1] < 11'h1fd) ? 8'h00 : + (triangle[11:1] < 11'h1fe) ? 8'h3c : + (triangle[11:1] < 11'h200) ? 8'h3f : + (triangle[11:1] < 11'h2fd) ? 8'h00 : + (triangle[11:1] < 11'h2fe) ? 8'h0c : + (triangle[11:1] < 11'h2ff) ? 8'h5e : + (triangle[11:1] < 11'h300) ? 8'h5f : + (triangle[11:1] < 11'h377) ? 8'h00 : + (triangle[11:1] < 11'h378) ? 8'h40 : + (triangle[11:1] < 11'h37b) ? 8'h00 : + (triangle[11:1] < 11'h37d) ? 8'h40 : + (triangle[11:1] < 11'h37f) ? 8'h60 : + (triangle[11:1] < 11'h380) ? 8'h6f : + (triangle[11:1] < 11'h39f) ? 8'h00 : + (triangle[11:1] < 11'h3a0) ? 8'h40 : + (triangle[11:1] < 11'h3ae) ? 8'h00 : + (triangle[11:1] < 11'h3b0) ? 8'h40 : + (triangle[11:1] < 11'h3b3) ? 8'h00 : + (triangle[11:1] < 11'h3b7) ? 8'h40 : + (triangle[11:1] < 11'h3b8) ? 8'h60 : + (triangle[11:1] < 11'h3ba) ? 8'h40 : + (triangle[11:1] < 11'h3be) ? 8'h60 : + (triangle[11:1] < 11'h3bf) ? 8'h70 : + (triangle[11:1] < 11'h3c0) ? 8'h77 : + (triangle[11:1] < 11'h3c5) ? 8'h00 : + (triangle[11:1] < 11'h3cd) ? 8'h40 : + (triangle[11:1] < 11'h3d0) ? 8'h60 : + (triangle[11:1] < 11'h3d3) ? 8'h40 : + (triangle[11:1] < 11'h3d7) ? 8'h60 : + (triangle[11:1] < 11'h3d8) ? 8'h70 : + (triangle[11:1] < 11'h3db) ? 8'h60 : + (triangle[11:1] < 11'h3de) ? 8'h70 : + (triangle[11:1] < 11'h3df) ? 8'h78 : + (triangle[11:1] < 11'h3e0) ? 8'h7b : + (triangle[11:1] < 11'h3e3) ? 8'h60 : + (triangle[11:1] < 11'h3e4) ? 8'h70 : + (triangle[11:1] < 11'h3e5) ? 8'h60 : + (triangle[11:1] < 11'h3eb) ? 8'h70 : + (triangle[11:1] < 11'h3ef) ? 8'h78 : + (triangle[11:1] < 11'h3f0) ? 8'h7c : + (triangle[11:1] < 11'h3f3) ? 8'h78 : + (triangle[11:1] < 11'h3f4) ? 8'h7c : + (triangle[11:1] < 11'h3f5) ? 8'h78 : + (triangle[11:1] < 11'h3f7) ? 8'h7c : + (triangle[11:1] < 11'h3f8) ? 8'h7e : + (triangle[11:1] < 11'h3f9) ? 8'h7c : + (triangle[11:1] < 11'h3fb) ? 8'h7e : + (triangle[11:1] < 11'h400) ? 8'h7f : + (triangle[11:1] < 11'h47f) ? 8'h00 : + (triangle[11:1] < 11'h480) ? 8'h80 : + (triangle[11:1] < 11'h4bd) ? 8'h00 : + (triangle[11:1] < 11'h4c0) ? 8'h80 : + (triangle[11:1] < 11'h4cf) ? 8'h00 : + (triangle[11:1] < 11'h4d0) ? 8'h80 : + (triangle[11:1] < 11'h4d7) ? 8'h00 : + (triangle[11:1] < 11'h4d8) ? 8'h80 : + (triangle[11:1] < 11'h4da) ? 8'h00 : + (triangle[11:1] < 11'h4e0) ? 8'h80 : + (triangle[11:1] < 11'h4e3) ? 8'h00 : + (triangle[11:1] < 11'h4fe) ? 8'h80 : + (triangle[11:1] < 11'h4ff) ? 8'h8e : + (triangle[11:1] < 11'h500) ? 8'h9f : + (triangle[11:1] < 11'h51f) ? 8'h00 : + (triangle[11:1] < 11'h520) ? 8'h80 : + (triangle[11:1] < 11'h52b) ? 8'h00 : + (triangle[11:1] < 11'h52c) ? 8'h80 : + (triangle[11:1] < 11'h52d) ? 8'h00 : + (triangle[11:1] < 11'h530) ? 8'h80 : + (triangle[11:1] < 11'h532) ? 8'h00 : + (triangle[11:1] < 11'h540) ? 8'h80 : + (triangle[11:1] < 11'h543) ? 8'h00 : + (triangle[11:1] < 11'h544) ? 8'h80 : + (triangle[11:1] < 11'h545) ? 8'h00 : + (triangle[11:1] < 11'h57f) ? 8'h80 : + (triangle[11:1] < 11'h580) ? 8'haf : + (triangle[11:1] < 11'h5bb) ? 8'h80 : + (triangle[11:1] < 11'h5bf) ? 8'ha0 : + (triangle[11:1] < 11'h5c0) ? 8'hb7 : + (triangle[11:1] < 11'h5cf) ? 8'h80 : + (triangle[11:1] < 11'h5d0) ? 8'ha0 : + (triangle[11:1] < 11'h5d6) ? 8'h80 : + (triangle[11:1] < 11'h5db) ? 8'ha0 : + (triangle[11:1] < 11'h5dc) ? 8'hb0 : + (triangle[11:1] < 11'h5dd) ? 8'ha0 : + (triangle[11:1] < 11'h5df) ? 8'hb0 : + (triangle[11:1] < 11'h5e0) ? 8'hbb : + (triangle[11:1] < 11'h5e6) ? 8'ha0 : + (triangle[11:1] < 11'h5e8) ? 8'hb0 : + (triangle[11:1] < 11'h5e9) ? 8'ha0 : + (triangle[11:1] < 11'h5eb) ? 8'hb0 : + (triangle[11:1] < 11'h5ec) ? 8'hb8 : + (triangle[11:1] < 11'h5ed) ? 8'hb0 : + (triangle[11:1] < 11'h5ef) ? 8'hb8 : + (triangle[11:1] < 11'h5f0) ? 8'hbc : + (triangle[11:1] < 11'h5f1) ? 8'hb0 : + (triangle[11:1] < 11'h5f5) ? 8'hb8 : + (triangle[11:1] < 11'h5f7) ? 8'hbc : + (triangle[11:1] < 11'h5f8) ? 8'hbe : + (triangle[11:1] < 11'h5fa) ? 8'hbc : + (triangle[11:1] < 11'h5fb) ? 8'hbe : + (triangle[11:1] < 11'h5fc) ? 8'hbf : + (triangle[11:1] < 11'h5fd) ? 8'hbe : + (triangle[11:1] < 11'h600) ? 8'hbf : + (triangle[11:1] < 11'h63e) ? 8'h80 : + (triangle[11:1] < 11'h640) ? 8'hc0 : + (triangle[11:1] < 11'h657) ? 8'h80 : + (triangle[11:1] < 11'h658) ? 8'hc0 : + (triangle[11:1] < 11'h65a) ? 8'h80 : + (triangle[11:1] < 11'h660) ? 8'hc0 : + (triangle[11:1] < 11'h663) ? 8'h80 : + (triangle[11:1] < 11'h664) ? 8'hc0 : + (triangle[11:1] < 11'h665) ? 8'h80 : + (triangle[11:1] < 11'h67f) ? 8'hc0 : + (triangle[11:1] < 11'h680) ? 8'hcf : + (triangle[11:1] < 11'h686) ? 8'h80 : + (triangle[11:1] < 11'h689) ? 8'hc0 : + (triangle[11:1] < 11'h68a) ? 8'h80 : + (triangle[11:1] < 11'h6bf) ? 8'hc0 : + (triangle[11:1] < 11'h6c0) ? 8'hd7 : + (triangle[11:1] < 11'h6dd) ? 8'hc0 : + (triangle[11:1] < 11'h6df) ? 8'hd0 : + (triangle[11:1] < 11'h6e0) ? 8'hd9 : + (triangle[11:1] < 11'h6e7) ? 8'hc0 : + (triangle[11:1] < 11'h6e8) ? 8'hd0 : + (triangle[11:1] < 11'h6e9) ? 8'hc0 : + (triangle[11:1] < 11'h6ed) ? 8'hd0 : + (triangle[11:1] < 11'h6ef) ? 8'hd8 : + (triangle[11:1] < 11'h6f0) ? 8'hdc : + (triangle[11:1] < 11'h6f2) ? 8'hd0 : + (triangle[11:1] < 11'h6f5) ? 8'hd8 : + (triangle[11:1] < 11'h6f7) ? 8'hdc : + (triangle[11:1] < 11'h6f8) ? 8'hde : + (triangle[11:1] < 11'h6fa) ? 8'hdc : + (triangle[11:1] < 11'h6fb) ? 8'hde : + (triangle[11:1] < 11'h6fc) ? 8'hdf : + (triangle[11:1] < 11'h6fd) ? 8'hde : + (triangle[11:1] < 11'h700) ? 8'hdf : + (triangle[11:1] < 11'h71b) ? 8'hc0 : + (triangle[11:1] < 11'h71c) ? 8'he0 : + (triangle[11:1] < 11'h71d) ? 8'hc0 : + (triangle[11:1] < 11'h720) ? 8'he0 : + (triangle[11:1] < 11'h727) ? 8'hc0 : + (triangle[11:1] < 11'h728) ? 8'he0 : + (triangle[11:1] < 11'h72a) ? 8'hc0 : + (triangle[11:1] < 11'h73f) ? 8'he0 : + (triangle[11:1] < 11'h740) ? 8'he7 : + (triangle[11:1] < 11'h75f) ? 8'he0 : + (triangle[11:1] < 11'h760) ? 8'he8 : + (triangle[11:1] < 11'h76e) ? 8'he0 : + (triangle[11:1] < 11'h76f) ? 8'he8 : + (triangle[11:1] < 11'h770) ? 8'hec : + (triangle[11:1] < 11'h773) ? 8'he0 : + (triangle[11:1] < 11'h776) ? 8'he8 : + (triangle[11:1] < 11'h777) ? 8'hec : + (triangle[11:1] < 11'h778) ? 8'hee : + (triangle[11:1] < 11'h77b) ? 8'hec : + (triangle[11:1] < 11'h77d) ? 8'hee : + (triangle[11:1] < 11'h780) ? 8'hef : + (triangle[11:1] < 11'h78d) ? 8'he0 : + (triangle[11:1] < 11'h790) ? 8'hf0 : + (triangle[11:1] < 11'h792) ? 8'he0 : + (triangle[11:1] < 11'h7af) ? 8'hf0 : + (triangle[11:1] < 11'h7b0) ? 8'hf4 : + (triangle[11:1] < 11'h7b7) ? 8'hf0 : + (triangle[11:1] < 11'h7b8) ? 8'hf4 : + (triangle[11:1] < 11'h7b9) ? 8'hf0 : + (triangle[11:1] < 11'h7bb) ? 8'hf4 : + (triangle[11:1] < 11'h7bd) ? 8'hf6 : + (triangle[11:1] < 11'h7c0) ? 8'hf7 : + (triangle[11:1] < 11'h7c3) ? 8'hf0 : + (triangle[11:1] < 11'h7c4) ? 8'hf8 : + (triangle[11:1] < 11'h7c5) ? 8'hf0 : + (triangle[11:1] < 11'h7db) ? 8'hf8 : + (triangle[11:1] < 11'h7dd) ? 8'hfa : + (triangle[11:1] < 11'h7e0) ? 8'hfb : + (triangle[11:1] < 11'h7e1) ? 8'hf8 : + (triangle[11:1] < 11'h7ed) ? 8'hfc : + (triangle[11:1] < 11'h7f0) ? 8'hfd : + (triangle[11:1] < 11'h7f8) ? 8'hfe : 8'hff; + wave_ps_ = (sawtooth < 12'h07f) ? 8'h00 : + (sawtooth < 12'h080) ? 8'h03 : + (sawtooth < 12'h0bf) ? 8'h00 : + (sawtooth < 12'h0c0) ? 8'h01 : + (sawtooth < 12'h0ff) ? 8'h00 : + (sawtooth < 12'h100) ? 8'h0f : + (sawtooth < 12'h17f) ? 8'h00 : + (sawtooth < 12'h180) ? 8'h07 : + (sawtooth < 12'h1bf) ? 8'h00 : + (sawtooth < 12'h1c0) ? 8'h03 : + (sawtooth < 12'h1df) ? 8'h00 : + (sawtooth < 12'h1e0) ? 8'h01 : + (sawtooth < 12'h1fd) ? 8'h00 : + (sawtooth < 12'h1ff) ? 8'h07 : + (sawtooth < 12'h200) ? 8'h1f : + (sawtooth < 12'h27f) ? 8'h00 : + (sawtooth < 12'h280) ? 8'h03 : + (sawtooth < 12'h2bf) ? 8'h00 : + (sawtooth < 12'h2c0) ? 8'h03 : + (sawtooth < 12'h2df) ? 8'h00 : + (sawtooth < 12'h2e0) ? 8'h01 : + (sawtooth < 12'h2fe) ? 8'h00 : + (sawtooth < 12'h2ff) ? 8'h01 : + (sawtooth < 12'h300) ? 8'h0f : + (sawtooth < 12'h33f) ? 8'h00 : + (sawtooth < 12'h340) ? 8'h01 : + (sawtooth < 12'h37f) ? 8'h00 : + (sawtooth < 12'h380) ? 8'h17 : + (sawtooth < 12'h3bf) ? 8'h00 : + (sawtooth < 12'h3c0) ? 8'h3b : + (sawtooth < 12'h3df) ? 8'h00 : + (sawtooth < 12'h3e0) ? 8'h3d : + (sawtooth < 12'h3ef) ? 8'h00 : + (sawtooth < 12'h3f0) ? 8'h3e : + (sawtooth < 12'h3f7) ? 8'h00 : + (sawtooth < 12'h3f8) ? 8'h3f : + (sawtooth < 12'h3f9) ? 8'h00 : + (sawtooth < 12'h3fa) ? 8'h0c : + (sawtooth < 12'h3fb) ? 8'h1c : + (sawtooth < 12'h3fc) ? 8'h3f : + (sawtooth < 12'h3fd) ? 8'h1e : + (sawtooth < 12'h400) ? 8'h3f : + (sawtooth < 12'h47f) ? 8'h00 : + (sawtooth < 12'h480) ? 8'h03 : + (sawtooth < 12'h4bf) ? 8'h00 : + (sawtooth < 12'h4c0) ? 8'h01 : + (sawtooth < 12'h4ff) ? 8'h00 : + (sawtooth < 12'h500) ? 8'h0f : + (sawtooth < 12'h53f) ? 8'h00 : + (sawtooth < 12'h540) ? 8'h01 : + (sawtooth < 12'h57f) ? 8'h00 : + (sawtooth < 12'h580) ? 8'h07 : + (sawtooth < 12'h5bf) ? 8'h00 : + (sawtooth < 12'h5c0) ? 8'h0b : + (sawtooth < 12'h5df) ? 8'h00 : + (sawtooth < 12'h5e0) ? 8'h0a : + (sawtooth < 12'h5ef) ? 8'h00 : + (sawtooth < 12'h5f0) ? 8'h5e : + (sawtooth < 12'h5f7) ? 8'h00 : + (sawtooth < 12'h5f8) ? 8'h5f : + (sawtooth < 12'h5fb) ? 8'h00 : + (sawtooth < 12'h5fc) ? 8'h5f : + (sawtooth < 12'h5fd) ? 8'h0c : + (sawtooth < 12'h600) ? 8'h5f : + (sawtooth < 12'h63f) ? 8'h00 : + (sawtooth < 12'h640) ? 8'h01 : + (sawtooth < 12'h67f) ? 8'h00 : + (sawtooth < 12'h680) ? 8'h47 : + (sawtooth < 12'h6bf) ? 8'h00 : + (sawtooth < 12'h6c0) ? 8'h43 : + (sawtooth < 12'h6df) ? 8'h00 : + (sawtooth < 12'h6e0) ? 8'h65 : + (sawtooth < 12'h6ef) ? 8'h00 : + (sawtooth < 12'h6f0) ? 8'h6e : + (sawtooth < 12'h6f7) ? 8'h00 : + (sawtooth < 12'h6f8) ? 8'h6f : + (sawtooth < 12'h6f9) ? 8'h00 : + (sawtooth < 12'h6fb) ? 8'h40 : + (sawtooth < 12'h6fc) ? 8'h6f : + (sawtooth < 12'h6fd) ? 8'h40 : + (sawtooth < 12'h700) ? 8'h6f : + (sawtooth < 12'h73f) ? 8'h00 : + (sawtooth < 12'h740) ? 8'h63 : + (sawtooth < 12'h75e) ? 8'h00 : + (sawtooth < 12'h75f) ? 8'h40 : + (sawtooth < 12'h760) ? 8'h61 : + (sawtooth < 12'h767) ? 8'h00 : + (sawtooth < 12'h768) ? 8'h40 : + (sawtooth < 12'h76b) ? 8'h00 : + (sawtooth < 12'h76c) ? 8'h40 : + (sawtooth < 12'h76d) ? 8'h00 : + (sawtooth < 12'h76f) ? 8'h40 : + (sawtooth < 12'h770) ? 8'h70 : + (sawtooth < 12'h772) ? 8'h00 : + (sawtooth < 12'h777) ? 8'h40 : + (sawtooth < 12'h778) ? 8'h70 : + (sawtooth < 12'h779) ? 8'h40 : + (sawtooth < 12'h77b) ? 8'h60 : + (sawtooth < 12'h77c) ? 8'h77 : + (sawtooth < 12'h77d) ? 8'h60 : + (sawtooth < 12'h780) ? 8'h77 : + (sawtooth < 12'h78f) ? 8'h00 : + (sawtooth < 12'h790) ? 8'h40 : + (sawtooth < 12'h796) ? 8'h00 : + (sawtooth < 12'h797) ? 8'h40 : + (sawtooth < 12'h798) ? 8'h60 : + (sawtooth < 12'h799) ? 8'h00 : + (sawtooth < 12'h79b) ? 8'h40 : + (sawtooth < 12'h79c) ? 8'h60 : + (sawtooth < 12'h79d) ? 8'h40 : + (sawtooth < 12'h79f) ? 8'h60 : + (sawtooth < 12'h7a0) ? 8'h79 : + (sawtooth < 12'h7a1) ? 8'h00 : + (sawtooth < 12'h7a7) ? 8'h40 : + (sawtooth < 12'h7a8) ? 8'h60 : + (sawtooth < 12'h7ab) ? 8'h40 : + (sawtooth < 12'h7af) ? 8'h60 : + (sawtooth < 12'h7b0) ? 8'h78 : + (sawtooth < 12'h7b1) ? 8'h40 : + (sawtooth < 12'h7b7) ? 8'h60 : + (sawtooth < 12'h7b8) ? 8'h78 : + (sawtooth < 12'h7b9) ? 8'h60 : + (sawtooth < 12'h7bb) ? 8'h70 : + (sawtooth < 12'h7bc) ? 8'h78 : + (sawtooth < 12'h7bd) ? 8'h70 : + (sawtooth < 12'h7be) ? 8'h79 : + (sawtooth < 12'h7c0) ? 8'h7b : + (sawtooth < 12'h7c7) ? 8'h60 : + (sawtooth < 12'h7c8) ? 8'h70 : + (sawtooth < 12'h7cb) ? 8'h60 : + (sawtooth < 12'h7cc) ? 8'h70 : + (sawtooth < 12'h7cd) ? 8'h60 : + (sawtooth < 12'h7cf) ? 8'h70 : + (sawtooth < 12'h7d0) ? 8'h7c : + (sawtooth < 12'h7d1) ? 8'h60 : + (sawtooth < 12'h7d7) ? 8'h70 : + (sawtooth < 12'h7d8) ? 8'h7c : + (sawtooth < 12'h7d9) ? 8'h70 : + (sawtooth < 12'h7db) ? 8'h78 : + (sawtooth < 12'h7dc) ? 8'h7c : + (sawtooth < 12'h7dd) ? 8'h78 : + (sawtooth < 12'h7df) ? 8'h7c : + (sawtooth < 12'h7e0) ? 8'h7d : + (sawtooth < 12'h7e1) ? 8'h70 : + (sawtooth < 12'h7e7) ? 8'h78 : + (sawtooth < 12'h7e8) ? 8'h7c : + (sawtooth < 12'h7e9) ? 8'h78 : + (sawtooth < 12'h7eb) ? 8'h7c : + (sawtooth < 12'h7ec) ? 8'h7e : + (sawtooth < 12'h7ed) ? 8'h7c : + (sawtooth < 12'h7f0) ? 8'h7e : + (sawtooth < 12'h7f3) ? 8'h7c : + (sawtooth < 12'h7f5) ? 8'h7e : + (sawtooth < 12'h7f8) ? 8'h7f : + (sawtooth < 12'h7f9) ? 8'h7e : + (sawtooth < 12'h7ff) ? 8'h7f : + (sawtooth < 12'h800) ? 8'hff : + (sawtooth < 12'h87f) ? 8'h00 : + (sawtooth < 12'h880) ? 8'h03 : + (sawtooth < 12'h8bf) ? 8'h00 : + (sawtooth < 12'h8c0) ? 8'h01 : + (sawtooth < 12'h8ff) ? 8'h00 : + (sawtooth < 12'h900) ? 8'h8f : + (sawtooth < 12'h93f) ? 8'h00 : + (sawtooth < 12'h940) ? 8'h01 : + (sawtooth < 12'h97f) ? 8'h00 : + (sawtooth < 12'h980) ? 8'h87 : + (sawtooth < 12'h9bf) ? 8'h00 : + (sawtooth < 12'h9c0) ? 8'h83 : + (sawtooth < 12'h9de) ? 8'h00 : + (sawtooth < 12'h9df) ? 8'h80 : + (sawtooth < 12'h9e0) ? 8'h8d : + (sawtooth < 12'h9e7) ? 8'h00 : + (sawtooth < 12'h9e8) ? 8'h80 : + (sawtooth < 12'h9eb) ? 8'h00 : + (sawtooth < 12'h9ec) ? 8'h80 : + (sawtooth < 12'h9ed) ? 8'h00 : + (sawtooth < 12'h9ef) ? 8'h80 : + (sawtooth < 12'h9f0) ? 8'h8e : + (sawtooth < 12'h9f3) ? 8'h00 : + (sawtooth < 12'h9f7) ? 8'h80 : + (sawtooth < 12'h9f8) ? 8'h8f : + (sawtooth < 12'h9fb) ? 8'h80 : + (sawtooth < 12'h9fc) ? 8'h9f : + (sawtooth < 12'h9fd) ? 8'h80 : + (sawtooth < 12'ha00) ? 8'h9f : + (sawtooth < 12'ha3f) ? 8'h00 : + (sawtooth < 12'ha40) ? 8'h01 : + (sawtooth < 12'ha6f) ? 8'h00 : + (sawtooth < 12'ha70) ? 8'h80 : + (sawtooth < 12'ha77) ? 8'h00 : + (sawtooth < 12'ha78) ? 8'h80 : + (sawtooth < 12'ha7b) ? 8'h00 : + (sawtooth < 12'ha7c) ? 8'h80 : + (sawtooth < 12'ha7d) ? 8'h00 : + (sawtooth < 12'ha7f) ? 8'h80 : + (sawtooth < 12'ha80) ? 8'h87 : + (sawtooth < 12'ha9f) ? 8'h00 : + (sawtooth < 12'haa0) ? 8'h80 : + (sawtooth < 12'haaf) ? 8'h00 : + (sawtooth < 12'hab0) ? 8'h80 : + (sawtooth < 12'hab7) ? 8'h00 : + (sawtooth < 12'hab8) ? 8'h80 : + (sawtooth < 12'habb) ? 8'h00 : + (sawtooth < 12'habf) ? 8'h80 : + (sawtooth < 12'hac0) ? 8'h83 : + (sawtooth < 12'hacf) ? 8'h00 : + (sawtooth < 12'had0) ? 8'h80 : + (sawtooth < 12'had5) ? 8'h00 : + (sawtooth < 12'had8) ? 8'h80 : + (sawtooth < 12'had9) ? 8'h00 : + (sawtooth < 12'hadf) ? 8'h80 : + (sawtooth < 12'hae0) ? 8'h81 : + (sawtooth < 12'haef) ? 8'h80 : + (sawtooth < 12'haf0) ? 8'h84 : + (sawtooth < 12'haf7) ? 8'h80 : + (sawtooth < 12'haf8) ? 8'h87 : + (sawtooth < 12'hafb) ? 8'h80 : + (sawtooth < 12'hafc) ? 8'h87 : + (sawtooth < 12'hafd) ? 8'h80 : + (sawtooth < 12'hafe) ? 8'h8f : + (sawtooth < 12'hb00) ? 8'haf : + (sawtooth < 12'hb0f) ? 8'h00 : + (sawtooth < 12'hb10) ? 8'h80 : + (sawtooth < 12'hb17) ? 8'h00 : + (sawtooth < 12'hb18) ? 8'h80 : + (sawtooth < 12'hb1b) ? 8'h00 : + (sawtooth < 12'hb20) ? 8'h80 : + (sawtooth < 12'hb23) ? 8'h00 : + (sawtooth < 12'hb24) ? 8'h80 : + (sawtooth < 12'hb26) ? 8'h00 : + (sawtooth < 12'hb28) ? 8'h80 : + (sawtooth < 12'hb29) ? 8'h00 : + (sawtooth < 12'hb3f) ? 8'h80 : + (sawtooth < 12'hb40) ? 8'h83 : + (sawtooth < 12'hb5f) ? 8'h80 : + (sawtooth < 12'hb60) ? 8'h81 : + (sawtooth < 12'hb6f) ? 8'h80 : + (sawtooth < 12'hb70) ? 8'ha0 : + (sawtooth < 12'hb77) ? 8'h80 : + (sawtooth < 12'hb78) ? 8'ha0 : + (sawtooth < 12'hb7b) ? 8'h80 : + (sawtooth < 12'hb7c) ? 8'ha0 : + (sawtooth < 12'hb7d) ? 8'h80 : + (sawtooth < 12'hb7e) ? 8'ha3 : + (sawtooth < 12'hb80) ? 8'hb7 : + (sawtooth < 12'hb9f) ? 8'h80 : + (sawtooth < 12'hba0) ? 8'hb1 : + (sawtooth < 12'hbaf) ? 8'h80 : + (sawtooth < 12'hbb0) ? 8'hb0 : + (sawtooth < 12'hbb7) ? 8'h80 : + (sawtooth < 12'hbb8) ? 8'hb0 : + (sawtooth < 12'hbb9) ? 8'h80 : + (sawtooth < 12'hbbb) ? 8'ha0 : + (sawtooth < 12'hbbc) ? 8'hb0 : + (sawtooth < 12'hbbd) ? 8'ha0 : + (sawtooth < 12'hbbe) ? 8'hb8 : + (sawtooth < 12'hbbf) ? 8'hb9 : + (sawtooth < 12'hbc0) ? 8'hbb : + (sawtooth < 12'hbc7) ? 8'h80 : + (sawtooth < 12'hbc8) ? 8'ha0 : + (sawtooth < 12'hbcb) ? 8'h80 : + (sawtooth < 12'hbcc) ? 8'ha0 : + (sawtooth < 12'hbcd) ? 8'h80 : + (sawtooth < 12'hbcf) ? 8'ha0 : + (sawtooth < 12'hbd0) ? 8'hb8 : + (sawtooth < 12'hbd1) ? 8'h80 : + (sawtooth < 12'hbd7) ? 8'ha0 : + (sawtooth < 12'hbd8) ? 8'hb8 : + (sawtooth < 12'hbd9) ? 8'ha0 : + (sawtooth < 12'hbdb) ? 8'hb0 : + (sawtooth < 12'hbdc) ? 8'hb8 : + (sawtooth < 12'hbdd) ? 8'hb0 : + (sawtooth < 12'hbdf) ? 8'hbc : + (sawtooth < 12'hbe0) ? 8'hbd : + (sawtooth < 12'hbe1) ? 8'ha0 : + (sawtooth < 12'hbe5) ? 8'hb0 : + (sawtooth < 12'hbe7) ? 8'hb8 : + (sawtooth < 12'hbe8) ? 8'hbc : + (sawtooth < 12'hbe9) ? 8'hb0 : + (sawtooth < 12'hbeb) ? 8'hb8 : + (sawtooth < 12'hbec) ? 8'hbc : + (sawtooth < 12'hbed) ? 8'hb8 : + (sawtooth < 12'hbee) ? 8'hbc : + (sawtooth < 12'hbf0) ? 8'hbe : + (sawtooth < 12'hbf1) ? 8'hb8 : + (sawtooth < 12'hbf3) ? 8'hbc : + (sawtooth < 12'hbf4) ? 8'hbe : + (sawtooth < 12'hbf5) ? 8'hbc : + (sawtooth < 12'hbf7) ? 8'hbe : + (sawtooth < 12'hbf8) ? 8'hbf : + (sawtooth < 12'hbf9) ? 8'hbe : + (sawtooth < 12'hc00) ? 8'hbf : + (sawtooth < 12'hc03) ? 8'h00 : + (sawtooth < 12'hc04) ? 8'h80 : + (sawtooth < 12'hc07) ? 8'h00 : + (sawtooth < 12'hc08) ? 8'h80 : + (sawtooth < 12'hc0b) ? 8'h00 : + (sawtooth < 12'hc0c) ? 8'h80 : + (sawtooth < 12'hc0f) ? 8'h00 : + (sawtooth < 12'hc10) ? 8'h80 : + (sawtooth < 12'hc11) ? 8'h00 : + (sawtooth < 12'hc18) ? 8'h80 : + (sawtooth < 12'hc19) ? 8'h00 : + (sawtooth < 12'hc3f) ? 8'h80 : + (sawtooth < 12'hc40) ? 8'h81 : + (sawtooth < 12'hc7f) ? 8'h80 : + (sawtooth < 12'hc80) ? 8'hc7 : + (sawtooth < 12'hcbe) ? 8'h80 : + (sawtooth < 12'hcbf) ? 8'hc0 : + (sawtooth < 12'hcc0) ? 8'hc3 : + (sawtooth < 12'hccf) ? 8'h80 : + (sawtooth < 12'hcd0) ? 8'hc0 : + (sawtooth < 12'hcd7) ? 8'h80 : + (sawtooth < 12'hcd8) ? 8'hc0 : + (sawtooth < 12'hcdb) ? 8'h80 : + (sawtooth < 12'hcdc) ? 8'hc0 : + (sawtooth < 12'hcdd) ? 8'h80 : + (sawtooth < 12'hcdf) ? 8'hc0 : + (sawtooth < 12'hce0) ? 8'hc1 : + (sawtooth < 12'hce7) ? 8'h80 : + (sawtooth < 12'hce8) ? 8'hc0 : + (sawtooth < 12'hceb) ? 8'h80 : + (sawtooth < 12'hcf7) ? 8'hc0 : + (sawtooth < 12'hcf8) ? 8'hc7 : + (sawtooth < 12'hcfb) ? 8'hc0 : + (sawtooth < 12'hcfc) ? 8'hc7 : + (sawtooth < 12'hcfd) ? 8'hc0 : + (sawtooth < 12'hd00) ? 8'hcf : + (sawtooth < 12'hd1f) ? 8'h80 : + (sawtooth < 12'hd20) ? 8'hc0 : + (sawtooth < 12'hd2f) ? 8'h80 : + (sawtooth < 12'hd30) ? 8'hc0 : + (sawtooth < 12'hd36) ? 8'h80 : + (sawtooth < 12'hd38) ? 8'hc0 : + (sawtooth < 12'hd39) ? 8'h80 : + (sawtooth < 12'hd3f) ? 8'hc0 : + (sawtooth < 12'hd40) ? 8'hc3 : + (sawtooth < 12'hd47) ? 8'h80 : + (sawtooth < 12'hd48) ? 8'hc0 : + (sawtooth < 12'hd4b) ? 8'h80 : + (sawtooth < 12'hd4c) ? 8'hc0 : + (sawtooth < 12'hd4d) ? 8'h80 : + (sawtooth < 12'hd50) ? 8'hc0 : + (sawtooth < 12'hd51) ? 8'h80 : + (sawtooth < 12'hd5f) ? 8'hc0 : + (sawtooth < 12'hd60) ? 8'hc1 : + (sawtooth < 12'hd7d) ? 8'hc0 : + (sawtooth < 12'hd7e) ? 8'hc1 : + (sawtooth < 12'hd7f) ? 8'hc7 : + (sawtooth < 12'hd80) ? 8'hd7 : + (sawtooth < 12'hdaf) ? 8'hc0 : + (sawtooth < 12'hdb0) ? 8'hd0 : + (sawtooth < 12'hdb7) ? 8'hc0 : + (sawtooth < 12'hdb8) ? 8'hd0 : + (sawtooth < 12'hdbb) ? 8'hc0 : + (sawtooth < 12'hdbc) ? 8'hd0 : + (sawtooth < 12'hdbd) ? 8'hc0 : + (sawtooth < 12'hdbe) ? 8'hd0 : + (sawtooth < 12'hdbf) ? 8'hd8 : + (sawtooth < 12'hdc0) ? 8'hdb : + (sawtooth < 12'hdcf) ? 8'hc0 : + (sawtooth < 12'hdd0) ? 8'hd8 : + (sawtooth < 12'hdd7) ? 8'hc0 : + (sawtooth < 12'hdd8) ? 8'hd8 : + (sawtooth < 12'hddb) ? 8'hc0 : + (sawtooth < 12'hddc) ? 8'hd8 : + (sawtooth < 12'hddd) ? 8'hd0 : + (sawtooth < 12'hddf) ? 8'hd8 : + (sawtooth < 12'hde0) ? 8'hdd : + (sawtooth < 12'hde3) ? 8'hc0 : + (sawtooth < 12'hde4) ? 8'hd0 : + (sawtooth < 12'hde5) ? 8'hc0 : + (sawtooth < 12'hde7) ? 8'hd0 : + (sawtooth < 12'hde8) ? 8'hdc : + (sawtooth < 12'hde9) ? 8'hd0 : + (sawtooth < 12'hdeb) ? 8'hd8 : + (sawtooth < 12'hdec) ? 8'hdc : + (sawtooth < 12'hded) ? 8'hd8 : + (sawtooth < 12'hdef) ? 8'hdc : + (sawtooth < 12'hdf0) ? 8'hde : + (sawtooth < 12'hdf1) ? 8'hd8 : + (sawtooth < 12'hdf3) ? 8'hdc : + (sawtooth < 12'hdf4) ? 8'hde : + (sawtooth < 12'hdf5) ? 8'hdc : + (sawtooth < 12'hdf7) ? 8'hde : + (sawtooth < 12'hdf8) ? 8'hdf : + (sawtooth < 12'hdf9) ? 8'hde : + (sawtooth < 12'he00) ? 8'hdf : + (sawtooth < 12'he3f) ? 8'hc0 : + (sawtooth < 12'he40) ? 8'he3 : + (sawtooth < 12'he57) ? 8'hc0 : + (sawtooth < 12'he58) ? 8'he0 : + (sawtooth < 12'he5b) ? 8'hc0 : + (sawtooth < 12'he5c) ? 8'he0 : + (sawtooth < 12'he5d) ? 8'hc0 : + (sawtooth < 12'he5f) ? 8'he0 : + (sawtooth < 12'he60) ? 8'he1 : + (sawtooth < 12'he67) ? 8'hc0 : + (sawtooth < 12'he68) ? 8'he0 : + (sawtooth < 12'he6b) ? 8'hc0 : + (sawtooth < 12'he70) ? 8'he0 : + (sawtooth < 12'he71) ? 8'hc0 : + (sawtooth < 12'he7d) ? 8'he0 : + (sawtooth < 12'he7e) ? 8'he1 : + (sawtooth < 12'he7f) ? 8'he3 : + (sawtooth < 12'he80) ? 8'he7 : + (sawtooth < 12'he87) ? 8'hc0 : + (sawtooth < 12'he88) ? 8'he0 : + (sawtooth < 12'he8b) ? 8'hc0 : + (sawtooth < 12'he8c) ? 8'he0 : + (sawtooth < 12'he8d) ? 8'hc0 : + (sawtooth < 12'he90) ? 8'he0 : + (sawtooth < 12'he93) ? 8'hc0 : + (sawtooth < 12'he94) ? 8'he0 : + (sawtooth < 12'he95) ? 8'hc0 : + (sawtooth < 12'hebf) ? 8'he0 : + (sawtooth < 12'hec0) ? 8'heb : + (sawtooth < 12'hedb) ? 8'he0 : + (sawtooth < 12'hedc) ? 8'he8 : + (sawtooth < 12'hedd) ? 8'he0 : + (sawtooth < 12'hedf) ? 8'he8 : + (sawtooth < 12'hee0) ? 8'hed : + (sawtooth < 12'hee7) ? 8'he0 : + (sawtooth < 12'hee8) ? 8'hec : + (sawtooth < 12'heeb) ? 8'he0 : + (sawtooth < 12'heec) ? 8'hec : + (sawtooth < 12'heed) ? 8'he8 : + (sawtooth < 12'heef) ? 8'hec : + (sawtooth < 12'hef0) ? 8'hee : + (sawtooth < 12'hef3) ? 8'he8 : + (sawtooth < 12'hef5) ? 8'hec : + (sawtooth < 12'hef7) ? 8'hee : + (sawtooth < 12'hef8) ? 8'hef : + (sawtooth < 12'hef9) ? 8'hec : + (sawtooth < 12'hf00) ? 8'hef : + (sawtooth < 12'hf1f) ? 8'he0 : + (sawtooth < 12'hf20) ? 8'hf0 : + (sawtooth < 12'hf27) ? 8'he0 : + (sawtooth < 12'hf28) ? 8'hf0 : + (sawtooth < 12'hf2b) ? 8'he0 : + (sawtooth < 12'hf2c) ? 8'hf0 : + (sawtooth < 12'hf2d) ? 8'he0 : + (sawtooth < 12'hf30) ? 8'hf0 : + (sawtooth < 12'hf33) ? 8'he0 : + (sawtooth < 12'hf3f) ? 8'hf0 : + (sawtooth < 12'hf40) ? 8'hf3 : + (sawtooth < 12'hf43) ? 8'he0 : + (sawtooth < 12'hf5f) ? 8'hf0 : + (sawtooth < 12'hf60) ? 8'hf5 : + (sawtooth < 12'hf6d) ? 8'hf0 : + (sawtooth < 12'hf6f) ? 8'hf4 : + (sawtooth < 12'hf70) ? 8'hf6 : + (sawtooth < 12'hf73) ? 8'hf0 : + (sawtooth < 12'hf74) ? 8'hf4 : + (sawtooth < 12'hf75) ? 8'hf0 : + (sawtooth < 12'hf76) ? 8'hf4 : + (sawtooth < 12'hf77) ? 8'hf6 : + (sawtooth < 12'hf78) ? 8'hf7 : + (sawtooth < 12'hf79) ? 8'hf4 : + (sawtooth < 12'hf7b) ? 8'hf6 : + (sawtooth < 12'hf80) ? 8'hf7 : + (sawtooth < 12'hf87) ? 8'hf0 : + (sawtooth < 12'hf88) ? 8'hf8 : + (sawtooth < 12'hf8d) ? 8'hf0 : + (sawtooth < 12'hf90) ? 8'hf8 : + (sawtooth < 12'hf93) ? 8'hf0 : + (sawtooth < 12'hf94) ? 8'hf8 : + (sawtooth < 12'hf95) ? 8'hf0 : + (sawtooth < 12'hf9f) ? 8'hf8 : + (sawtooth < 12'hfa0) ? 8'hf9 : + (sawtooth < 12'hfaf) ? 8'hf8 : + (sawtooth < 12'hfb0) ? 8'hfa : + (sawtooth < 12'hfb7) ? 8'hf8 : + (sawtooth < 12'hfb8) ? 8'hfb : + (sawtooth < 12'hfb9) ? 8'hf8 : + (sawtooth < 12'hfbb) ? 8'hfa : + (sawtooth < 12'hfc0) ? 8'hfb : + (sawtooth < 12'hfc3) ? 8'hf8 : + (sawtooth < 12'hfc4) ? 8'hfc : + (sawtooth < 12'hfc5) ? 8'hf8 : + (sawtooth < 12'hfd7) ? 8'hfc : + (sawtooth < 12'hfd8) ? 8'hfd : + (sawtooth < 12'hfdb) ? 8'hfc : + (sawtooth < 12'hfe0) ? 8'hfd : + (sawtooth < 12'hfe2) ? 8'hfc : + (sawtooth < 12'hff0) ? 8'hfe : 8'hff; + wave_pst = (sawtooth < 12'h3ff) ? 8'h00 : + (sawtooth < 12'h400) ? 8'h1f : + (sawtooth < 12'h7ee) ? 8'h00 : + (sawtooth < 12'h7ef) ? 8'h20 : + (sawtooth < 12'h7f0) ? 8'h70 : + (sawtooth < 12'h7f1) ? 8'h60 : + (sawtooth < 12'h7f2) ? 8'h20 : + (sawtooth < 12'h7f7) ? 8'h70 : + (sawtooth < 12'h7fa) ? 8'h78 : + (sawtooth < 12'h7fc) ? 8'h7c : + (sawtooth < 12'h7fe) ? 8'h7e : + (sawtooth < 12'h800) ? 8'h7f : + (sawtooth < 12'hbfd) ? 8'h00 : + (sawtooth < 12'hbfe) ? 8'h08 : + (sawtooth < 12'hbff) ? 8'h1e : + (sawtooth < 12'hc00) ? 8'h3f : + (sawtooth < 12'hdf7) ? 8'h00 : + (sawtooth < 12'hdfe) ? 8'h80 : + (sawtooth < 12'hdff) ? 8'h8c : + (sawtooth < 12'he00) ? 8'h9f : + (sawtooth < 12'he3e) ? 8'h00 : + (sawtooth < 12'he40) ? 8'h80 : + (sawtooth < 12'he5e) ? 8'h00 : + (sawtooth < 12'he60) ? 8'h80 : + (sawtooth < 12'he66) ? 8'h00 : + (sawtooth < 12'he67) ? 8'h80 : + (sawtooth < 12'he6a) ? 8'h00 : + (sawtooth < 12'he80) ? 8'h80 : + (sawtooth < 12'he82) ? 8'h00 : + (sawtooth < 12'he83) ? 8'h80 : + (sawtooth < 12'he85) ? 8'h00 : + (sawtooth < 12'he89) ? 8'h80 : + (sawtooth < 12'he8a) ? 8'h00 : + (sawtooth < 12'heee) ? 8'h80 : + (sawtooth < 12'heff) ? 8'hc0 : + (sawtooth < 12'hf00) ? 8'hcf : + (sawtooth < 12'hf6f) ? 8'hc0 : + (sawtooth < 12'hf70) ? 8'he0 : + (sawtooth < 12'hf74) ? 8'hc0 : + (sawtooth < 12'hf7f) ? 8'he0 : + (sawtooth < 12'hf80) ? 8'he3 : + (sawtooth < 12'hfb6) ? 8'he0 : + (sawtooth < 12'hfda) ? 8'hf0 : + (sawtooth < 12'hfeb) ? 8'hf8 : + (sawtooth < 12'hff5) ? 8'hfc : + (sawtooth < 12'hff9) ? 8'hfe : 8'hff; +end + +endmodule