diff --git a/cores/zxgate/zx/zx01/data_io.v b/cores/zxgate/zx/zx01/data_io.v index 541b933..55b9395 100644 --- a/cores/zxgate/zx/zx01/data_io.v +++ b/cores/zxgate/zx/zx01/data_io.v @@ -28,11 +28,11 @@ module data_io ( output downloading, // signal indicating an active download output [15:0] size, // number of bytes in input buffer - + // cpu ram interface input clk, input we, - input [10:0] a, + input [13:0] a, input [8:0] din, output [8:0] dout ); @@ -113,7 +113,7 @@ data_io_ram data_io_ram ( .q_a ( dout ), // io controller port - .address_b ( addr[10:0] ), + .address_b ( addr[13:0] ), .clock_b ( rclk ), .data_b ( {sbuf, sdi} ), .wren_b ( (cmd == UIO_FILE_TX_DAT) && !ss ) diff --git a/cores/zxgate/zx/zx01/data_io_ram.v b/cores/zxgate/zx/zx01/data_io_ram.v index 44bf5a5..96f5a36 100644 --- a/cores/zxgate/zx/zx01/data_io_ram.v +++ b/cores/zxgate/zx/zx01/data_io_ram.v @@ -48,8 +48,8 @@ module data_io_ram ( q_a, q_b); - input [10:0] address_a; - input [10:0] address_b; + input [13:0] address_a; + input [13:0] address_b; input clock_a; input clock_b; input [7:0] data_a; @@ -106,8 +106,8 @@ module data_io_ram ( altsyncram_component.indata_reg_b = "CLOCK1", altsyncram_component.intended_device_family = "Cyclone III", altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = 2048, - altsyncram_component.numwords_b = 2048, + altsyncram_component.numwords_a = 16384, + altsyncram_component.numwords_b = 16384, altsyncram_component.operation_mode = "BIDIR_DUAL_PORT", altsyncram_component.outdata_aclr_a = "NONE", altsyncram_component.outdata_aclr_b = "NONE", @@ -116,8 +116,8 @@ module data_io_ram ( altsyncram_component.power_up_uninitialized = "FALSE", altsyncram_component.read_during_write_mode_port_a = "NEW_DATA_NO_NBE_READ", altsyncram_component.read_during_write_mode_port_b = "NEW_DATA_NO_NBE_READ", - altsyncram_component.widthad_a = 11, - altsyncram_component.widthad_b = 11, + altsyncram_component.widthad_a = 14, + altsyncram_component.widthad_b = 14, altsyncram_component.width_a = 8, altsyncram_component.width_b = 8, altsyncram_component.width_byteena_a = 1, @@ -160,7 +160,7 @@ endmodule // Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" // Retrieval info: PRIVATE: JTAG_ID STRING "NONE" // Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -// Retrieval info: PRIVATE: MEMSIZE NUMERIC "16384" +// Retrieval info: PRIVATE: MEMSIZE NUMERIC "131072" // Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" // Retrieval info: PRIVATE: MIFfilename STRING "" // Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" @@ -198,8 +198,8 @@ endmodule // Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1" // Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" // Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048" -// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048" +// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16384" +// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16384" // Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" // Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" // Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" @@ -208,15 +208,15 @@ endmodule // Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_NO_NBE_READ" // Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_NO_NBE_READ" -// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11" -// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11" +// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "14" +// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "14" // Retrieval info: CONSTANT: WIDTH_A NUMERIC "8" // Retrieval info: CONSTANT: WIDTH_B NUMERIC "8" // Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1" // Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" // Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1" -// Retrieval info: USED_PORT: address_a 0 0 11 0 INPUT NODEFVAL "address_a[10..0]" -// Retrieval info: USED_PORT: address_b 0 0 11 0 INPUT NODEFVAL "address_b[10..0]" +// Retrieval info: USED_PORT: address_a 0 0 14 0 INPUT NODEFVAL "address_a[13..0]" +// Retrieval info: USED_PORT: address_b 0 0 14 0 INPUT NODEFVAL "address_b[13..0]" // Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC "clock_a" // Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL "clock_b" // Retrieval info: USED_PORT: data_a 0 0 8 0 INPUT NODEFVAL "data_a[7..0]" @@ -225,8 +225,8 @@ endmodule // Retrieval info: USED_PORT: q_b 0 0 8 0 OUTPUT NODEFVAL "q_b[7..0]" // Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND "wren_a" // Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND "wren_b" -// Retrieval info: CONNECT: @address_a 0 0 11 0 address_a 0 0 11 0 -// Retrieval info: CONNECT: @address_b 0 0 11 0 address_b 0 0 11 0 +// Retrieval info: CONNECT: @address_a 0 0 14 0 address_a 0 0 14 0 +// Retrieval info: CONNECT: @address_b 0 0 14 0 address_b 0 0 14 0 // Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0 // Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0 // Retrieval info: CONNECT: @data_a 0 0 8 0 data_a 0 0 8 0 diff --git a/cores/zxgate/zx/zx01/tape.v b/cores/zxgate/zx/zx01/tape.v index 833bbe2..ae8b920 100644 --- a/cores/zxgate/zx/zx01/tape.v +++ b/cores/zxgate/zx/zx01/tape.v @@ -204,7 +204,7 @@ data_io data_io ( // ram interface .clk ( clk ), .we ( 1'b0 ), - .a ( byte_count[10:0] ), + .a ( byte_count[13:0] ), .din ( 8'h00 ), .dout ( ram_data_out ) ); diff --git a/cores/zxgate/zx/zx01/zx01.vhd b/cores/zxgate/zx/zx01/zx01.vhd index 8d4cd40..a9c11c9 100644 --- a/cores/zxgate/zx/zx01/zx01.vhd +++ b/cores/zxgate/zx/zx01/zx01.vhd @@ -217,11 +217,11 @@ begin DO => d_cpu_i); c_SSRAM: SSRAM - generic map (AddrWidth => 11) + generic map (AddrWidth => 14) -- 11 port map (Clk => i_phi, CE_n => n_ramcs, WE_n => n_wr, - A => a_mem(10 downto 0), + A => a_mem(13 downto 0), -- 10..0 DIn => d_cpu_i, DOut => d_ram); diff --git a/cores/zxgate/zx/zx01/zx01_mist.v b/cores/zxgate/zx/zx01/zx01_mist.v index e0d53c7..fe6069b 100644 --- a/cores/zxgate/zx/zx01/zx01_mist.v +++ b/cores/zxgate/zx/zx01/zx01_mist.v @@ -191,10 +191,10 @@ reg [7:0] sync_len; reg vs, csD; // horizontal display goes from 40 to 168. We add 16 border pixels left and right -wire h_de = (sd_col >= 2*32) && (sd_col < 2*176); +wire h_de = (sd_col >= 2*32) && (sd_col < 2*182); // 176 // vertical display goes from line 32 to 224.We add 16 border pixels top and bottom -wire v_de = (line_cnt >= 16) && (line_cnt < 240); +wire v_de = (line_cnt >= 16) && (line_cnt < 272); // 240 wire hs = sd_col >= 2*192; @@ -243,13 +243,13 @@ always @(posedge clk13) begin // there are short/long lines if(sd_col != 413) trigger <= 1'b1; - + sd_col <= 9'd0; end else sd_col <= sd_col + 9'd1; // change toggle bit at the end of each zx line - if(!csync && csD) begin + if(csync && !csD) begin sd_toggle <= !sd_toggle; line_cnt <= line_cnt + 10'd1; end