From da29f15118826bfa7901a1407bd0d1adf89adfbd Mon Sep 17 00:00:00 2001 From: Gyorgy Szombathelyi Date: Tue, 12 Feb 2019 23:40:08 +0100 Subject: [PATCH] [Gameboy] Add MBC2-3-5 (MBC 2 is relevant for now) --- cores/gameboy/gb_mist.v | 158 ++++++++++++++++++++++++++++------------ 1 file changed, 113 insertions(+), 45 deletions(-) diff --git a/cores/gameboy/gb_mist.v b/cores/gameboy/gb_mist.v index 87e266c..96503fb 100644 --- a/cores/gameboy/gb_mist.v +++ b/cores/gameboy/gb_mist.v @@ -137,7 +137,7 @@ sdram sdram ( wire [1:0] sdram_ds = dio_download?2'b11:{!cart_addr[0], cart_addr[0]}; wire [15:0] sdram_do; wire [15:0] sdram_di = dio_download?dio_data:{cart_di, cart_di}; -wire [23:0] sdram_addr = dio_download?dio_addr:{3'b000, mbc_bank, cart_addr[12:1]}; +wire [23:0] sdram_addr = dio_download?dio_addr:{1'b0, mbc_bank, cart_addr[12:1]}; wire sdram_oe = !dio_download && cart_rd; wire sdram_we = (dio_download && dio_write) || (!dio_download && cart_ram_wr); @@ -153,55 +153,108 @@ wire dio_write; // 2 2 2 2 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 D // 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 S // ------------------------------------------------- -// 0 0 0 0 X X X X X X X X X X X X X X X X X X X X X up to 2MB used as ROM -// 0 0 0 1 X X X X X X X X X X X X X X X X X X X X X up to 2MB used as RAM +// 0 0 X X X X X X X X X X X X X X X X X X X X X X X up to 8MB used as ROM +// 0 1 X X X X X X X X X X X X X X X X X X X X X X X up to 8MB used as RAM // 0 0 0 0 R R B B B B B C C C C C C C C C C C C C C MBC1 ROM (R=RAM bank in mode 0) -// 0 0 0 1 0 0 0 0 0 0 R R C C C C C C C C C C C C C MBC1 RAM (R=RAM bank in mode 1) +// 0 1 0 0 0 0 0 0 0 0 R R C C C C C C C C C C C C C MBC1 RAM (R=RAM bank in mode 1) +// 0 0 0 0 B B B B B B B C C C C C C C C C C C C C C MBC2 ROM +// 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 C C C C C C C C C MBC2 RAM +// 0 0 0 0 B B B B B B B C C C C C C C C C C C C C C MBC3 ROM +// 0 1 0 0 0 0 0 0 0 R R C C C C C C C C C C C C C C MBC3 RAM +// 0 0 B B B B B B B B B C C C C C C C C C C C C C C MBC5 ROM +// 0 1 0 0 0 0 0 0 R R R R C C C C C C C C C C C C C MBC5 RAM -// --------------------------------------------------------------- -// ----------------------------- MBC1 ---------------------------- // --------------------------------------------------------------- -wire [8:0] mbc1_addr = - (cart_addr[15:14] == 2'b00)?{8'b000000000, cart_addr[13]}: // 16k ROM Bank 0 - (cart_addr[15:14] == 2'b01)?{1'b0, mbc1_rom_bank, cart_addr[13]}: // 16k ROM Bank 1-127 - (cart_addr[15:13] == 3'b101)?{7'b1000000, mbc1_ram_bank}: // 8k RAM Bank 0-3 - 9'd0; +wire [10:0] mbc1_addr = + (cart_addr[15:14] == 2'b00)?{10'd0, cart_addr[13]}: // 16k ROM Bank 0 + (cart_addr[15:14] == 2'b01)?{3'b000, mbc1_rom_bank, cart_addr[13]}: // 16k ROM Bank 1-127 + (cart_addr[15:13] == 3'b101)?{9'b100000000, mbc1_ram_bank}: // 8k RAM Bank 0-3 + 11'd0; + +wire [10:0] mbc2_addr = + (cart_addr[15:14] == 2'b00)?{10'd0, cart_addr[13]}: // 16k ROM Bank 0 + (cart_addr[15:14] == 2'b01)?{6'd0, mbc2_rom_bank, cart_addr[13]}: // 16k ROM Bank 1-15 + (cart_addr[15:9] == 7'b1010000)?(11'b10000000000): // 512x4 bit RAM + 11'd0; + +wire [10:0] mbc3_addr = + (cart_addr[15:14] == 2'b00)?{10'd0, cart_addr[13]}: // 16k ROM Bank 0 + (cart_addr[15:14] == 2'b01)?{3'b000, mbc3_rom_bank, cart_addr[13]}: // 16k ROM Bank 1-127 + (cart_addr[15:13] == 3'b101)?{9'b100000000, mbc3_ram_bank}: // 8k RAM Bank 0-3 + 11'd0; + +wire [10:0] mbc5_addr = + (cart_addr[15:14] == 2'b00)?{10'd0, cart_addr[13]}: // 16k ROM Bank 0 + (cart_addr[15:14] == 2'b01)?{1'b0, mbc5_rom_bank, cart_addr[13]}: // 16k ROM Bank 0-480 (0h-1E0h) + (cart_addr[15:13] == 3'b101)?{7'b1000000, mbc5_ram_bank}: // 8k RAM Bank 0-15 + 11'd0; // -------------------------- RAM banking ------------------------ // in mode 0 (16/8 mode) the ram is not banked // in mode 1 (4/32 mode) four ram banks are used -wire [1:0] mbc1_ram_bank = (mbc1_mode?mbc1_ram_bank_reg:2'b00) & ram_mask; +wire [1:0] mbc1_ram_bank = (mbc1_mode?mbc_ram_bank_reg[1:0]:2'b00) & ram_mask[1:0]; +wire [1:0] mbc3_ram_bank = mbc_ram_bank_reg[1:0] & ram_mask[1:0]; +wire [3:0] mbc5_ram_bank = mbc_ram_bank_reg & ram_mask; // -------------------------- ROM banking ------------------------ - + // in mode 0 (16/8 mode) the ram bank select signals are the upper rom address lines // in mode 1 (4/32 mode) the upper two rom address lines are 2'b00 -wire [6:0] mbc1_rom_bank_mode = { mbc1_mode?2'b00:mbc1_ram_bank_reg, mbc1_rom_bank_reg}; +wire [6:0] mbc1_rom_bank_mode = { mbc1_mode?2'b00:mbc_ram_bank_reg, mbc_rom_bank_reg}; // mask address lines to enable proper mirroring -wire [6:0] mbc1_rom_bank = mbc1_rom_bank_mode & rom_mask; +wire [6:0] mbc1_rom_bank = mbc1_rom_bank_mode & rom_mask[6:0]; +wire [3:0] mbc2_rom_bank = mbc_rom_bank_reg[3:0] & rom_mask[3:0]; //16 +wire [6:0] mbc3_rom_bank = mbc_rom_bank_reg[6:0] & rom_mask[6:0]; //128 +wire [8:0] mbc5_rom_bank = mbc_rom_bank_reg & rom_mask; //480 // --------------------- CPU register interface ------------------ -reg mbc1_ram_enable; +reg mbc_ram_enable; reg mbc1_mode; -reg [4:0] mbc1_rom_bank_reg; -reg [1:0] mbc1_ram_bank_reg; +reg mbc3_mode; +reg [8:0] mbc_rom_bank_reg; +reg [3:0] mbc_ram_bank_reg; + always @(posedge clk64) begin if(reset) begin - mbc1_rom_bank_reg <= 5'd1; - mbc1_ram_bank_reg <= 2'd0; - mbc1_ram_enable <= 1'b0; - mbc1_mode <= 1'b0; + mbc_rom_bank_reg <= 5'd1; + mbc_ram_bank_reg <= 2'd0; + mbc_ram_enable <= 1'b0; + mbc1_mode <= 1'b0; end else begin - if(cart_wr && (cart_addr[15:13] == 3'b000)) - mbc1_ram_enable <= (cart_di[3:0] == 4'ha); + //write to ROM bank register if(cart_wr && (cart_addr[15:13] == 3'b001)) begin - if(cart_di[4:0]==0) mbc1_rom_bank_reg <= 5'd1; - else mbc1_rom_bank_reg <= cart_di[4:0]; + if(~mbc5 && cart_di[6:0]==0) //special case mbc1-3 rombank 0=1 + mbc_rom_bank_reg <= 5'd1; + else if (mbc5) begin + if (cart_addr[13:12] == 2'b11) //3000-3FFF High bit + mbc_rom_bank_reg[8] <= cart_di[0]; + else //2000-2FFF low 8 bits + mbc_rom_bank_reg[7:0] <= cart_di[7:0]; + end else + mbc_rom_bank_reg <= {2'b00,cart_di[6:0]}; //mbc1-3 + end + + //write to RAM bank register + if(cart_wr && (cart_addr[15:13] == 3'b010)) begin + if (mbc3) begin + if (cart_di[3]==1) + mbc3_mode <= 1'b1; //enable RTC + else begin + mbc3_mode <= 1'b0; //enable RAM + mbc_ram_bank_reg <= {2'b00,cart_di[1:0]}; + end + end else + if (mbc5)//can probably be simplified + mbc_ram_bank_reg <= cart_di[3:0]; + else + mbc_ram_bank_reg <= {2'b00,cart_di[1:0]}; end - if(cart_wr && (cart_addr[15:13] == 3'b010)) - mbc1_ram_bank_reg <= cart_di[1:0]; + + if(cart_wr && (cart_addr[15:13] == 3'b000)) + mbc_ram_enable <= (cart_di[3:0] == 4'ha); + if(cart_wr && (cart_addr[15:13] == 3'b011)) mbc1_mode <= cart_di[0]; end @@ -214,22 +267,29 @@ reg [7:0] cart_rom_size; reg [7:0] cart_ram_size; // only write sdram if the write attept comes from the cart ram area -wire cart_ram_wr = cart_wr && mbc1_ram_enable && (cart_addr[15:13] == 3'b101); - +wire cart_ram_wr = cart_wr && mbc_ram_enable && ((cart_addr[15:13] == 3'b101 && ~mbc2) || (cart_addr[15:9] == 7'b1010000 && mbc2)); + // RAM size -wire [1:0] ram_mask = // 0 - no ram - (cart_ram_size == 1)?2'b00: // 1 - 2k, 1 bank - (cart_ram_size == 2)?2'b00: // 2 - 8k, 1 bank - 2'b11; // 3 - 32k, 4 banks +wire [3:0] ram_mask = // 0 - no ram + (cart_ram_size == 1)?4'b0000: // 1 - 2k, 1 bank + (cart_ram_size == 2)?4'b0000: // 2 - 8k, 1 bank + (cart_ram_size == 3)?4'b0011: // 3 - 32k, 4 banks + 4'b1111; // 4 - 128k 16 banks // ROM size -wire [6:0] rom_mask = // 0 - 2 banks, 32k direct mapped - (cart_rom_size == 1)?7'b0000011: // 1 - 4 banks = 64k - (cart_rom_size == 2)?7'b0000111: // 2 - 8 banks = 128k - (cart_rom_size == 3)?7'b0001111: // 3 - 16 banks = 256k - (cart_rom_size == 4)?7'b0011111: // 4 - 32 banks = 512k - (cart_rom_size == 5)?7'b0111111: // 5 - 64 banks = 1M - 7'b1111111; // 6 - 128 banks = 2M +wire [8:0] rom_mask = // 0 - 2 banks, 32k direct mapped + (cart_rom_size == 1)? 9'b000000011: // 1 - 4 banks = 64k + (cart_rom_size == 2)? 9'b000000111: // 2 - 8 banks = 128k + (cart_rom_size == 3)? 9'b000001111: // 3 - 16 banks = 256k + (cart_rom_size == 4)? 9'b000011111: // 4 - 32 banks = 512k + (cart_rom_size == 5)? 9'b000111111: // 5 - 64 banks = 1M + (cart_rom_size == 6)? 9'b001111111: // 6 - 128 banks = 2M + (cart_rom_size == 7)? 9'b011111111: // 7 - 256 banks = 4M + (cart_rom_size == 8)? 9'b111111111: // 8 - 512 banks = 8M + (cart_rom_size == 82)?9'b001111111: //$52 - 72 banks = 1.1M + (cart_rom_size == 83)?9'b001111111: //$53 - 80 banks = 1.2M + (cart_rom_size == 84)?9'b001111111: + 9'b001111111; //$54 - 96 banks = 1.5M// RAM size // MBC types // 0 - none @@ -239,10 +299,18 @@ wire [6:0] rom_mask = // 0 - 2 banks, 32k direct mapped // MBC1, MBC1+RAM, MBC1+RAM+BAT wire mbc1 = (cart_mbc_type == 1) || (cart_mbc_type == 2) || (cart_mbc_type == 3); +wire mbc2 = (cart_mbc_type == 5) || (cart_mbc_type == 6); +//wire mmm01 = (cart_mbc_type == 11) || (cart_mbc_type == 12) || (cart_mbc_type == 13) || (cart_mbc_type == 14); +wire mbc3 = (cart_mbc_type == 15) || (cart_mbc_type == 16) || (cart_mbc_type == 17) || (cart_mbc_type == 18) || (cart_mbc_type == 19); +//wire mbc4 = (cart_mbc_type == 21) || (cart_mbc_type == 22) || (cart_mbc_type == 23); +wire mbc5 = (cart_mbc_type == 25) || (cart_mbc_type == 26) || (cart_mbc_type == 27) || (cart_mbc_type == 28) || (cart_mbc_type == 29) || (cart_mbc_type == 30); -wire [8:0] mbc_bank = +wire [10:0] mbc_bank = mbc1?mbc1_addr: // MBC1, 16k bank 0, 16k bank 1-127 + ram - {7'b0000000, cart_addr[14:13]}; // no MBC, 32k linear address + mbc2?mbc2_addr: // MBC2, 16k bank 0, 16k bank 1-15 + ram + mbc3?mbc3_addr: + mbc5?mbc5_addr: + {9'd0, cart_addr[14:13]}; // no MBC, 32k linear address always @(posedge clk64) begin if(!pll_locked) begin @@ -321,8 +389,8 @@ gb gb ( sigma_delta_dac dac ( .clk ( clk64 ), - .ldatasum ( audio_left[15:1] ), - .rdatasum ( audio_right[15:1] ), + .ldatasum ( {~audio_left[15], audio_left[14:1]} ), + .rdatasum ( {~audio_right[15], audio_right[14:1]} ), .left ( AUDIO_L ), .right ( AUDIO_R ) );