diff --git a/cores/c64/C64_mist.qsf b/cores/c64/C64_mist.qsf index 5e33929..5471243 100644 --- a/cores/c64/C64_mist.qsf +++ b/cores/c64/C64_mist.qsf @@ -41,7 +41,7 @@ # ======================== set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:40:24 MAY 17, 2014" -set_global_assignment -name LAST_QUARTUS_VERSION 13.1 +set_global_assignment -name LAST_QUARTUS_VERSION "13.1 SP4.26" set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name SMART_RECOMPILE ON set_global_assignment -name FLOW_ENABLE_IO_ASSIGNMENT_ANALYSIS ON @@ -166,7 +166,7 @@ set_global_assignment -name USE_CONFIGURATION_DEVICE OFF # SignalTap II Assignments # ======================== set_global_assignment -name ENABLE_SIGNALTAP OFF -set_global_assignment -name USE_SIGNALTAP_FILE output_files/ioctl.stp +set_global_assignment -name USE_SIGNALTAP_FILE output_files/erase.stp # Power Estimation Assignments # ============================ @@ -342,6 +342,7 @@ set_location_assignment PIN_31 -to UART_RX set_location_assignment PLL_1 -to pll|altpll_component|auto_generated|pll1 set_instance_assignment -name CURRENT_STRENGTH_NEW 4MA -to UART_TX +set_instance_assignment -name FAST_INPUT_REGISTER ON -to UART_RX set_global_assignment -name VHDL_FILE rtl/tap_fifo.vhd set_global_assignment -name VHDL_FILE rtl/c1530.vhd set_global_assignment -name VERILOG_FILE rtl/sid8580/sid_voice.v @@ -349,14 +350,8 @@ set_global_assignment -name VERILOG_FILE rtl/sid8580/sid_filters.v set_global_assignment -name VERILOG_FILE rtl/sid8580/sid_envelope.v set_global_assignment -name VERILOG_FILE rtl/sid8580/sid8580.v set_global_assignment -name VERILOG_FILE rtl/mist/sigma_delta_dac.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/mist/video_mixer.sv -set_global_assignment -name VERILOG_FILE rtl/mist/user_io.v set_global_assignment -name VERILOG_FILE rtl/mist/sdram.v -set_global_assignment -name VERILOG_FILE rtl/mist/scandoubler.v set_global_assignment -name VHDL_FILE rtl/mist/pll.vhd -set_global_assignment -name VERILOG_FILE rtl/mist/osd.v -set_global_assignment -name SYSTEMVERILOG_FILE rtl/mist/hq2x.sv -set_global_assignment -name VERILOG_FILE rtl/mist/data_io.v set_global_assignment -name VHDL_FILE rtl/mist/c64_mist.vhd set_global_assignment -name VHDL_FILE rtl/fpga64_sid_iec.vhd set_global_assignment -name VHDL_FILE rtl/video_vicII_656x_e.vhd @@ -400,6 +395,7 @@ set_global_assignment -name VHDL_FILE rtl/t65/T65_MCode.vhd set_global_assignment -name VHDL_FILE rtl/t65/T65_ALU.vhd set_global_assignment -name VHDL_FILE rtl/t65/T65.vhd set_global_assignment -name SIGNALTAP_FILE output_files/sid.stp +set_global_assignment -name QIP_FILE "../../mist-modules/mist.qip" set_global_assignment -name QIP_FILE rtl/mist/pll.qip set_global_assignment -name QIP_FILE rtl/mist/pll_c64.qip set_global_assignment -name QIP_FILE rtl/mist/pll_c64_reconfig.qip @@ -407,5 +403,4 @@ set_global_assignment -name QIP_FILE rtl/mist/rom_reconfig_pal.qip set_global_assignment -name QIP_FILE rtl/mist/rom_reconfig_ntsc.qip set_global_assignment -name SIGNALTAP_FILE output_files/pll.stp set_global_assignment -name SIGNALTAP_FILE output_files/ioctl.stp -set_instance_assignment -name FAST_INPUT_REGISTER ON -to UART_RX set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top \ No newline at end of file diff --git a/cores/c64/C64_mist.sdc b/cores/c64/C64_mist.sdc index 889af13..297c0c8 100644 --- a/cores/c64/C64_mist.sdc +++ b/cores/c64/C64_mist.sdc @@ -39,8 +39,8 @@ set_clock_groups -asynchronous -group [get_clocks {pll_2|altpll_component|auto_g # Some relaxed constrain to the VGA pins. The signals should arrive together, the delay is not really important. -set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0 [get_ports {VGA_*}] -set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -min -5 [get_ports {VGA_*}] +set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -max 0 [get_ports {VGA_*}] +set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[1]}] -min -5 [get_ports {VGA_*}] # SDRAM delays set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports {SDRAM_CLK}] -max 6.4 [get_ports SDRAM_DQ[*]] @@ -49,11 +49,8 @@ set_input_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports {SDRAM_CLK}] -max 1.5 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] set_output_delay -clock [get_clocks {pll|altpll_component|auto_generated|pll1|clk[0]}] -reference_pin [get_ports {SDRAM_CLK}] -min -0.8 [get_ports {SDRAM_D* SDRAM_A* SDRAM_BA* SDRAM_n* SDRAM_CKE}] -set_multicycle_path -from {video_mixer:vmixer|scandoubler:scandoubler|Hq2x:Hq2x|*} -setup 4 -set_multicycle_path -from {video_mixer:vmixer|scandoubler:scandoubler|Hq2x:Hq2x|*} -hold 3 - -set_multicycle_path -to {VGA_*[*]} -setup 4 -set_multicycle_path -to {VGA_*[*]} -hold 3 +set_multicycle_path -to {VGA_*[*]} -setup 2 +set_multicycle_path -to {VGA_*[*]} -hold 1 set_false_path -to [get_ports {SDRAM_CLK}] set_false_path -from [get_ports {UART_RX}] diff --git a/cores/c64/rtl/mist/c64_mist.vhd b/cores/c64/rtl/mist/c64_mist.vhd index 82a9c71..31da337 100644 --- a/cores/c64/rtl/mist/c64_mist.vhd +++ b/cores/c64/rtl/mist/c64_mist.vhd @@ -29,6 +29,7 @@ library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.ALL; use IEEE.numeric_std.all; +use work.mist.ALL; entity c64_mist is port ( @@ -112,7 +113,7 @@ constant CONF_STR : string := "OI,Tape sound,Off,On;"& "OG,Disk Write,Enable,Disable;"& "O2,Video standard,PAL,NTSC;"& - "O8A,Scandoubler Fx,None,HQ2x-320,HQ2x-160,CRT 25%,CRT 50%;"& + "O89,Scandoubler Fx,None,CRT 25%,CRT 50%,CRT 75%;"& "ODF,SID,6581 Mono,6581 Stereo,8580 Mono,8580 Stereo,Pseudo Stereo;"& "O6,Audio filter,On,Off;"& "O3,Joysticks,normal,swapped;"& @@ -136,52 +137,6 @@ begin return rval; end function; -component user_io generic(STRLEN : integer := 0 ); port -( - clk_sys : in std_logic; - clk_sd : in std_logic; - SPI_CLK, SPI_SS_IO, SPI_MOSI :in std_logic; - SPI_MISO : out std_logic; - conf_str : in std_logic_vector(8*STRLEN-1 downto 0); - joystick_0 : out std_logic_vector(31 downto 0); - joystick_1 : out std_logic_vector(31 downto 0); - joystick_2 : out std_logic_vector(31 downto 0); - joystick_3 : out std_logic_vector(31 downto 0); - joystick_4 : out std_logic_vector(31 downto 0); - joystick_analog_0 : out std_logic_vector(15 downto 0); - joystick_analog_1 : out std_logic_vector(15 downto 0); - status: out std_logic_vector(31 downto 0); - switches : out std_logic_vector(1 downto 0); - buttons : out std_logic_vector(1 downto 0); - scandoubler_disable : out std_logic; - ypbpr : out std_logic; - - sd_lba : in std_logic_vector(31 downto 0); - sd_rd : in std_logic; - sd_wr : in std_logic; - sd_ack : out std_logic; - sd_ack_conf : out std_logic; - sd_conf : in std_logic; - sd_sdhc : in std_logic; - img_mounted : out std_logic; - - sd_buff_addr : out std_logic_vector(8 downto 0); - sd_dout : out std_logic_vector(7 downto 0); - sd_din : in std_logic_vector(7 downto 0); - sd_dout_strobe : out std_logic; - - ps2_kbd_clk : out std_logic; - ps2_kbd_data : out std_logic; - - ps2_mouse_clk : out std_logic; - ps2_mouse_data : out std_logic; - mouse_x : out signed(8 downto 0); - mouse_y : out signed(8 downto 0); - mouse_flags : out std_logic_vector(8 downto 0); -- YOvfl, XOvfl, dy8, dx8, 1, mbtn, rbtn, lbtn - mouse_strobe : out std_logic - ); -end component user_io; - -- constants for ioctl_index constant FILE_BOOT : std_logic_vector(7 downto 0) := x"00"; -- ROM files sent at boot time constant FILE_PRG : std_logic_vector(7 downto 0) := x"02"; @@ -201,22 +156,6 @@ component data_io port ); end component data_io; -component video_mixer - generic ( LINE_LENGTH : integer := 512; HALF_DEPTH : integer := 0 ); - port ( - clk_sys, ce_pix, ce_pix_actual : in std_logic; - SPI_SCK, SPI_SS3, SPI_DI : in std_logic; - scanlines : in std_logic_vector(1 downto 0); - scandoubler_disable, hq2x, ypbpr, ypbpr_full : in std_logic; - - R, G, B : in std_logic_vector(5 downto 0); - HSync, VSync, line_start, mono : in std_logic; - - VGA_R,VGA_G, VGA_B : out std_logic_vector(5 downto 0); - VGA_VS, VGA_HS : out std_logic - ); -end component video_mixer; - --------- -- audio -------- @@ -385,7 +324,7 @@ end component cartridge; signal st_disk_readonly : std_logic; -- status(16) signal st_sid_mode : std_logic_vector(2 downto 0); -- status(15 downto 13) signal st_c64gs : std_logic; -- status(11) - signal st_scandoubler_fx : std_logic_vector(2 downto 0); -- status(10 downto 8) + signal st_scandoubler_fx : std_logic_vector(1 downto 0); -- status(9 downto 8) signal st_user_port_uart : std_logic; -- status(7) signal st_audio_filter_off : std_logic; -- status(6) signal st_detach_cartdrige : std_logic; -- status(5) @@ -394,9 +333,6 @@ end component cartridge; signal st_ntsc : std_logic; -- status(2) signal st_reset : std_logic; -- status(0) - signal scanlines : std_logic_vector(1 downto 0); - signal hq2x : std_logic; - signal ce_pix_actual : std_logic; signal sd_lba : std_logic_vector(31 downto 0); signal sd_rd : std_logic; signal sd_wr : std_logic; @@ -421,7 +357,7 @@ end component cartridge; signal mouse_x_pos : signed(10 downto 0); signal mouse_y : signed( 8 downto 0); signal mouse_y_pos : signed(10 downto 0); - signal mouse_flags : std_logic_vector(8 downto 0); + signal mouse_flags : std_logic_vector(7 downto 0); signal mouse_btns : std_logic_vector(1 downto 0); signal mouse_strobe : std_logic; @@ -447,6 +383,7 @@ end component cartridge; signal tv15Khz_mode : std_logic; signal ypbpr : std_logic; + signal no_csync : std_logic; signal ntsc_init_mode : std_logic := '0'; signal ntsc_init_mode_d: std_logic; signal ntsc_init_mode_d2: std_logic; @@ -463,11 +400,6 @@ end component cartridge; signal clk_c64 : std_logic; -- 31.527mhz (PAL), 32.727mhz(NTSC) clock source signal clk_ram : std_logic; -- 2 x clk_c64 signal clk32 : std_logic; -- 32mhz - signal ce_8 : std_logic; - signal ce_4 : std_logic; - signal hq2x160 : std_logic; - signal osdclk : std_logic; - signal clkdiv : std_logic_vector(9 downto 0); signal todclk : std_logic; signal toddiv : std_logic_vector(19 downto 0); signal toddiv3 : std_logic_vector(1 downto 0); @@ -559,6 +491,7 @@ begin buttons => buttons, scandoubler_disable => tv15Khz_mode, ypbpr => ypbpr, + no_csync => no_csync, sd_lba => sd_lba, sd_rd => sd_rd, @@ -585,7 +518,7 @@ begin st_disk_readonly <= status(16); st_sid_mode <= status(15 downto 13); st_c64gs <= status(11); - st_scandoubler_fx <= status(10 downto 8); + st_scandoubler_fx <= status(9 downto 8); st_user_port_uart <= status(7); st_audio_filter_off <= status(6); st_detach_cartdrige <= status(5); @@ -813,23 +746,6 @@ begin c1541rom_wr <= ioctl_wr when (ioctl_index = FILE_BOOT) and (ioctl_addr(14) = '1') and (ioctl_download = '1') else '0'; - process(clk_c64) - begin - if rising_edge(clk_c64) then - clkdiv <= std_logic_vector(unsigned(clkdiv)+1); - if(clkdiv(1 downto 0) = "00") then - ce_8 <= '1'; - else - ce_8 <= '0'; - end if; - if(clkdiv(2 downto 0) = "000") then - ce_4 <= '1'; - else - ce_4 <= '0'; - end if; - end if; - end process; - -- UART_RX synchronizer process(clk_c64) begin @@ -1291,54 +1207,38 @@ begin c64_r <= (others => '0') when blank = '1' else std_logic_vector(r(7 downto 2)); c64_g <= (others => '0') when blank = '1' else std_logic_vector(g(7 downto 2)); c64_b <= (others => '0') when blank = '1' else std_logic_vector(b(7 downto 2)); - - scanlines <= st_scandoubler_fx(2 downto 1); - hq2x <= st_scandoubler_fx(1) xor st_scandoubler_fx(0); - ce_pix_actual <= ce_4 when hq2x160='1' else ce_8; - - process(clk_c64) - begin - if rising_edge(clk_c64) then - if((old_vsync = '0') and (vsync_out = '1')) then - if(st_scandoubler_fx="010") then - hq2x160 <= '1'; - else - hq2x160 <= '0'; - end if; - end if; - old_vsync <= vsync_out; - end if; - end process; - vmixer : video_mixer + mist_video : work.mist.mist_video + generic map ( + SD_HCNT_WIDTH => 10, + COLOR_DEPTH => 6, + OSD_COLOR => "011", + OSD_AUTO_CE => false + ) port map ( - clk_sys => clk_ram, - ce_pix => ce_8, - ce_pix_actual => ce_pix_actual, - - SPI_SCK => SPI_SCK, - SPI_SS3 => SPI_SS3, - SPI_DI => SPI_DI, - - scanlines => scanlines, + clk_sys => clk_c64, + scanlines => st_scandoubler_fx, scandoubler_disable => tv15Khz_mode, - hq2x => hq2x, - ypbpr => ypbpr, - ypbpr_full => '1', + ypbpr => ypbpr, + no_csync => no_csync, + rotate => "00", + blend => '0', - R => c64_r, - G => c64_g, - B => c64_b, - HSync => hsync_out, - VSync => vsync_out, - line_start => '0', - mono => '0', + SPI_SCK => SPI_SCK, + SPI_SS3 => SPI_SS3, + SPI_DI => SPI_DI, - VGA_R => VGA_R, - VGA_G => VGA_G, - VGA_B => VGA_B, - VGA_VS => VGA_VS, - VGA_HS => VGA_HS + HSync => not hsync_out, + VSync => not vsync_out, + R => c64_r, + G => c64_g, + B => c64_b, + + VGA_HS => VGA_HS, + VGA_VS => VGA_VS, + VGA_R => VGA_R, + VGA_G => VGA_G, + VGA_B => VGA_B ); end struct; diff --git a/cores/c64/rtl/mist/data_io.v b/cores/c64/rtl/mist/data_io.v deleted file mode 100644 index 2c29c87..0000000 --- a/cores/c64/rtl/mist/data_io.v +++ /dev/null @@ -1,116 +0,0 @@ -// -// data_io.v -// -// data_io for the MiST board -// http://code.google.com/p/mist-board/ -// -// Copyright (c) 2014 Till Harbaum -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// -/////////////////////////////////////////////////////////////////////// - -module data_io -( - input clk_sys, - - // Global SPI clock from ARM. 24MHz - input SPI_SCK, - input SPI_SS2, - input SPI_DI, - - // ARM -> FPGA download - output reg ioctl_download = 0, // signal indicating an active download - output reg [7:0] ioctl_index, // menu index used to upload the file - output reg ioctl_wr = 0, - output reg [24:0] ioctl_addr, - output reg [7:0] ioctl_dout -); - - -/////////////////////////////// DOWNLOADING /////////////////////////////// - -reg [7:0] data_w; -reg [24:0] addr_w; -reg rclk = 0; - -localparam UIO_FILE_TX = 8'h53; -localparam UIO_FILE_TX_DAT = 8'h54; -localparam UIO_FILE_INDEX = 8'h55; - -// data_io has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS2) begin - reg [6:0] sbuf; - reg [7:0] cmd; - reg [4:0] cnt; - reg [24:0] addr; - - if(SPI_SS2) cnt <= 0; - else begin - rclk <= 0; - - // don't shift in last bit. It is evaluated directly - // when writing to ram - if(cnt != 15) sbuf <= { sbuf[5:0], SPI_DI}; - - // increase target address after write - if(rclk) addr <= addr + 1'd1; - - // count 0-7 8-15 8-15 ... - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - // finished command byte - if(cnt == 7) cmd <= {sbuf, SPI_DI}; - - // prepare/end transmission - if((cmd == UIO_FILE_TX) && (cnt == 15)) begin - // prepare - if(SPI_DI) begin - addr <= 0; - ioctl_download <= 1; - end else begin - addr_w <= addr; - ioctl_download <= 0; - end - end - - // command 0x54: UIO_FILE_TX - if((cmd == UIO_FILE_TX_DAT) && (cnt == 15)) begin - addr_w <= addr; - data_w <= {sbuf, SPI_DI}; - rclk <= 1; - end - - // expose file (menu) index - if((cmd == UIO_FILE_INDEX) && (cnt == 15)) ioctl_index <= {sbuf, SPI_DI}; - end -end - -always@(posedge clk_sys) begin - reg rclkD, rclkD2; - - rclkD <= rclk; - rclkD2 <= rclkD; - ioctl_wr <= 0; - - if(rclkD & ~rclkD2) begin - ioctl_dout <= data_w; - ioctl_addr <= addr_w; - ioctl_wr <= 1; - end - -end - -endmodule \ No newline at end of file diff --git a/cores/c64/rtl/mist/hq2x.sv b/cores/c64/rtl/mist/hq2x.sv deleted file mode 100644 index f17732b..0000000 --- a/cores/c64/rtl/mist/hq2x.sv +++ /dev/null @@ -1,454 +0,0 @@ -// -// -// Copyright (c) 2012-2013 Ludvig Strigeus -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -// synopsys translate_off -`timescale 1 ps / 1 ps -// synopsys translate_on - -`define BITS_TO_FIT(N) ( \ - N <= 2 ? 0 : \ - N <= 4 ? 1 : \ - N <= 8 ? 2 : \ - N <= 16 ? 3 : \ - N <= 32 ? 4 : \ - N <= 64 ? 5 : \ - N <= 128 ? 6 : \ - N <= 256 ? 7 : \ - N <= 512 ? 8 : \ - N <=1024 ? 9 : 10 ) - -module hq2x_in #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH); - wire [DWIDTH:0] out[2]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); -endmodule - - -module hq2x_out #(parameter LENGTH, parameter DWIDTH) -( - input clk, - - input [AWIDTH:0] rdaddr, - input [1:0] rdbuf, - output[DWIDTH:0] q, - - input [AWIDTH:0] wraddr, - input [1:0] wrbuf, - input [DWIDTH:0] data, - input wren -); - - localparam AWIDTH = `BITS_TO_FIT(LENGTH*2); - wire [DWIDTH:0] out[4]; - assign q = out[rdbuf]; - - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf0(clk,data,rdaddr,wraddr,wren && (wrbuf == 0),out[0]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf1(clk,data,rdaddr,wraddr,wren && (wrbuf == 1),out[1]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf2(clk,data,rdaddr,wraddr,wren && (wrbuf == 2),out[2]); - hq2x_buf #(.NUMWORDS(LENGTH*2), .AWIDTH(AWIDTH), .DWIDTH(DWIDTH)) buf3(clk,data,rdaddr,wraddr,wren && (wrbuf == 3),out[3]); -endmodule - - -module hq2x_buf #(parameter NUMWORDS, parameter AWIDTH, parameter DWIDTH) -( - input clock, - input [DWIDTH:0] data, - input [AWIDTH:0] rdaddress, - input [AWIDTH:0] wraddress, - input wren, - output [DWIDTH:0] q -); - - altsyncram altsyncram_component ( - .address_a (wraddress), - .clock0 (clock), - .data_a (data), - .wren_a (wren), - .address_b (rdaddress), - .q_b(q), - .aclr0 (1'b0), - .aclr1 (1'b0), - .addressstall_a (1'b0), - .addressstall_b (1'b0), - .byteena_a (1'b1), - .byteena_b (1'b1), - .clock1 (1'b1), - .clocken0 (1'b1), - .clocken1 (1'b1), - .clocken2 (1'b1), - .clocken3 (1'b1), - .data_b ({(DWIDTH+1){1'b1}}), - .eccstatus (), - .q_a (), - .rden_a (1'b1), - .rden_b (1'b1), - .wren_b (1'b0)); - defparam - altsyncram_component.address_aclr_b = "NONE", - altsyncram_component.address_reg_b = "CLOCK0", - altsyncram_component.clock_enable_input_a = "BYPASS", - altsyncram_component.clock_enable_input_b = "BYPASS", - altsyncram_component.clock_enable_output_b = "BYPASS", - altsyncram_component.intended_device_family = "Cyclone III", - altsyncram_component.lpm_type = "altsyncram", - altsyncram_component.numwords_a = NUMWORDS, - altsyncram_component.numwords_b = NUMWORDS, - altsyncram_component.operation_mode = "DUAL_PORT", - altsyncram_component.outdata_aclr_b = "NONE", - altsyncram_component.outdata_reg_b = "UNREGISTERED", - altsyncram_component.power_up_uninitialized = "FALSE", - altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE", - altsyncram_component.widthad_a = AWIDTH+1, - altsyncram_component.widthad_b = AWIDTH+1, - altsyncram_component.width_a = DWIDTH+1, - altsyncram_component.width_b = DWIDTH+1, - altsyncram_component.width_byteena_a = 1; - -endmodule - -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -module DiffCheck -( - input [17:0] rgb1, - input [17:0] rgb2, - output result -); - - wire [5:0] r = rgb1[5:1] - rgb2[5:1]; - wire [5:0] g = rgb1[11:7] - rgb2[11:7]; - wire [5:0] b = rgb1[17:13] - rgb2[17:13]; - wire [6:0] t = $signed(r) + $signed(b); - wire [6:0] gx = {g[5], g}; - wire [7:0] y = $signed(t) + $signed(gx); - wire [6:0] u = $signed(r) - $signed(b); - wire [7:0] v = $signed({g, 1'b0}) - $signed(t); - - // if y is inside (-24..24) - wire y_inside = (y < 8'h18 || y >= 8'he8); - - // if u is inside (-4, 4) - wire u_inside = (u < 7'h4 || u >= 7'h7c); - - // if v is inside (-6, 6) - wire v_inside = (v < 8'h6 || v >= 8'hfA); - assign result = !(y_inside && u_inside && v_inside); -endmodule - -module InnerBlend -( - input [8:0] Op, - input [5:0] A, - input [5:0] B, - input [5:0] C, - output [5:0] O -); - - function [8:0] mul6x3; - input [5:0] op1; - input [2:0] op2; - begin - mul6x3 = 9'd0; - if(op2[0]) mul6x3 = mul6x3 + op1; - if(op2[1]) mul6x3 = mul6x3 + {op1, 1'b0}; - if(op2[2]) mul6x3 = mul6x3 + {op1, 2'b00}; - end - endfunction - - wire OpOnes = Op[4]; - wire [8:0] Amul = mul6x3(A, Op[7:5]); - wire [8:0] Bmul = mul6x3(B, {Op[3:2], 1'b0}); - wire [8:0] Cmul = mul6x3(C, {Op[1:0], 1'b0}); - wire [8:0] At = Amul; - wire [8:0] Bt = (OpOnes == 0) ? Bmul : {3'b0, B}; - wire [8:0] Ct = (OpOnes == 0) ? Cmul : {3'b0, C}; - wire [9:0] Res = {At, 1'b0} + Bt + Ct; - assign O = Op[8] ? A : Res[9:4]; -endmodule - -module Blend -( - input [5:0] rule, - input disable_hq2x, - input [17:0] E, - input [17:0] A, - input [17:0] B, - input [17:0] D, - input [17:0] F, - input [17:0] H, - output [17:0] Result -); - - reg [1:0] input_ctrl; - reg [8:0] op; - localparam BLEND0 = 9'b1_xxx_x_xx_xx; // 0: A - localparam BLEND1 = 9'b0_110_0_10_00; // 1: (A * 12 + B * 4) >> 4 - localparam BLEND2 = 9'b0_100_0_10_10; // 2: (A * 8 + B * 4 + C * 4) >> 4 - localparam BLEND3 = 9'b0_101_0_10_01; // 3: (A * 10 + B * 4 + C * 2) >> 4 - localparam BLEND4 = 9'b0_110_0_01_01; // 4: (A * 12 + B * 2 + C * 2) >> 4 - localparam BLEND5 = 9'b0_010_0_11_11; // 5: (A * 4 + (B + C) * 6) >> 4 - localparam BLEND6 = 9'b0_111_1_xx_xx; // 6: (A * 14 + B + C) >> 4 - localparam AB = 2'b00; - localparam AD = 2'b01; - localparam DB = 2'b10; - localparam BD = 2'b11; - wire is_diff; - DiffCheck diff_checker(rule[1] ? B : H, rule[0] ? D : F, is_diff); - - always @* begin - case({!is_diff, rule[5:2]}) - 1,17: {op, input_ctrl} = {BLEND1, AB}; - 2,18: {op, input_ctrl} = {BLEND1, DB}; - 3,19: {op, input_ctrl} = {BLEND1, BD}; - 4,20: {op, input_ctrl} = {BLEND2, DB}; - 5,21: {op, input_ctrl} = {BLEND2, AB}; - 6,22: {op, input_ctrl} = {BLEND2, AD}; - - 8: {op, input_ctrl} = {BLEND0, 2'bxx}; - 9: {op, input_ctrl} = {BLEND0, 2'bxx}; - 10: {op, input_ctrl} = {BLEND0, 2'bxx}; - 11: {op, input_ctrl} = {BLEND1, AB}; - 12: {op, input_ctrl} = {BLEND1, AB}; - 13: {op, input_ctrl} = {BLEND1, AB}; - 14: {op, input_ctrl} = {BLEND1, DB}; - 15: {op, input_ctrl} = {BLEND1, BD}; - - 24: {op, input_ctrl} = {BLEND2, DB}; - 25: {op, input_ctrl} = {BLEND5, DB}; - 26: {op, input_ctrl} = {BLEND6, DB}; - 27: {op, input_ctrl} = {BLEND2, DB}; - 28: {op, input_ctrl} = {BLEND4, DB}; - 29: {op, input_ctrl} = {BLEND5, DB}; - 30: {op, input_ctrl} = {BLEND3, BD}; - 31: {op, input_ctrl} = {BLEND3, DB}; - default: {op, input_ctrl} = 11'bx; - endcase - - // Setting op[8] effectively disables HQ2X because blend will always return E. - if (disable_hq2x) op[8] = 1; - end - - // Generate inputs to the inner blender. Valid combinations. - // 00: E A B - // 01: E A D - // 10: E D B - // 11: E B D - wire [17:0] Input1 = E; - wire [17:0] Input2 = !input_ctrl[1] ? A : - !input_ctrl[0] ? D : B; - - wire [17:0] Input3 = !input_ctrl[0] ? B : D; - InnerBlend inner_blend1(op, Input1[5:0], Input2[5:0], Input3[5:0], Result[5:0]); - InnerBlend inner_blend2(op, Input1[11:6], Input2[11:6], Input3[11:6], Result[11:6]); - InnerBlend inner_blend3(op, Input1[17:12], Input2[17:12], Input3[17:12], Result[17:12]); -endmodule - - -//////////////////////////////////////////////////////////////////////////////////////////////////// - -module Hq2x #(parameter LENGTH, parameter HALF_DEPTH) -( - input clk, - input ce_x4, - input [DWIDTH:0] inputpixel, - input mono, - input disable_hq2x, - input reset_frame, - input reset_line, - input [1:0] read_y, - input [AWIDTH+1:0] read_x, - output [DWIDTH:0] outpixel -); - - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -localparam DWIDTH = HALF_DEPTH ? 8 : 17; - -wire [5:0] hqTable[256] = '{ - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 35, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 58, 19, 19, 26, 58, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 35, 35, 23, 61, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 61, 7, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 58, 23, 15, 51, 35, 23, 61, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 47, 35, 23, 15, 55, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 55, 39, 23, 15, 51, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 39, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 51, 39, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 35, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 51, 35, 23, 15, 7, 43, - 19, 19, 26, 11, 19, 19, 26, 11, 23, 15, 7, 35, 23, 15, 7, 43 -}; - -reg [17:0] Prev0, Prev1, Prev2, Curr0, Curr1, Next0, Next1, Next2; -reg [17:0] A, B, D, F, G, H; -reg [7:0] pattern, nextpatt; -reg [1:0] i; -reg [7:0] y; - -wire curbuf = y[0]; -reg prevbuf = 0; -wire iobuf = !curbuf; - -wire diff0, diff1; -DiffCheck diffcheck0(Curr1, (i == 0) ? Prev0 : (i == 1) ? Curr0 : (i == 2) ? Prev2 : Next1, diff0); -DiffCheck diffcheck1(Curr1, (i == 0) ? Prev1 : (i == 1) ? Next0 : (i == 2) ? Curr2 : Next2, diff1); - -wire [7:0] new_pattern = {diff1, diff0, pattern[7:2]}; - -wire [17:0] X = (i == 0) ? A : (i == 1) ? Prev1 : (i == 2) ? Next1 : G; -wire [17:0] blend_result; -Blend blender(hqTable[nextpatt], disable_hq2x, Curr0, X, B, D, F, H, blend_result); - -reg Curr2_addr1; -reg [AWIDTH:0] Curr2_addr2; -wire [17:0] Curr2 = HALF_DEPTH ? h2rgb(Curr2tmp) : Curr2tmp; -wire [DWIDTH:0] Curr2tmp; - -reg [AWIDTH:0] wrin_addr2; -reg [DWIDTH:0] wrpix; -reg wrin_en; - -function [17:0] h2rgb; - input [8:0] v; -begin - h2rgb = mono ? {v[5:3],v[2:0], v[5:3],v[2:0], v[5:3],v[2:0]} : {v[8:6],v[8:6],v[5:3],v[5:3],v[2:0],v[2:0]}; -end -endfunction - -function [8:0] rgb2h; - input [17:0] v; -begin - rgb2h = mono ? {3'b000, v[17:15], v[14:12]} : {v[17:15], v[11:9], v[5:3]}; -end -endfunction - -hq2x_in #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_in -( - .clk(clk), - - .rdaddr(Curr2_addr2), - .rdbuf(Curr2_addr1), - .q(Curr2tmp), - - .wraddr(wrin_addr2), - .wrbuf(iobuf), - .data(wrpix), - .wren(wrin_en) -); - -reg [1:0] wrout_addr1; -reg [AWIDTH+1:0] wrout_addr2; -reg wrout_en; -reg [DWIDTH:0] wrdata; - -hq2x_out #(.LENGTH(LENGTH), .DWIDTH(DWIDTH)) hq2x_out -( - .clk(clk), - - .rdaddr(read_x), - .rdbuf(read_y), - .q(outpixel), - - .wraddr(wrout_addr2), - .wrbuf(wrout_addr1), - .data(wrdata), - .wren(wrout_en) -); - -always @(posedge clk) begin - reg [AWIDTH:0] offs; - reg old_reset_line; - reg old_reset_frame; - - wrout_en <= 0; - wrin_en <= 0; - - if(ce_x4) begin - - pattern <= new_pattern; - - if(~&offs) begin - if (i == 0) begin - Curr2_addr1 <= prevbuf; - Curr2_addr2 <= offs; - end - if (i == 1) begin - Prev2 <= Curr2; - Curr2_addr1 <= curbuf; - Curr2_addr2 <= offs; - end - if (i == 2) begin - Next2 <= HALF_DEPTH ? h2rgb(inputpixel) : inputpixel; - wrpix <= inputpixel; - wrin_addr2 <= offs; - wrin_en <= 1; - end - if (i == 3) begin - offs <= offs + 1'd1; - end - - if(HALF_DEPTH) wrdata <= rgb2h(blend_result); - else wrdata <= blend_result; - - wrout_addr1 <= {curbuf, i[1]}; - wrout_addr2 <= {offs, i[1]^i[0]}; - wrout_en <= 1; - end - - if(i==3) begin - nextpatt <= {new_pattern[7:6], new_pattern[3], new_pattern[5], new_pattern[2], new_pattern[4], new_pattern[1:0]}; - {A, G} <= {Prev0, Next0}; - {B, F, H, D} <= {Prev1, Curr2, Next1, Curr0}; - {Prev0, Prev1} <= {Prev1, Prev2}; - {Curr0, Curr1} <= {Curr1, Curr2}; - {Next0, Next1} <= {Next1, Next2}; - end else begin - nextpatt <= {nextpatt[5], nextpatt[3], nextpatt[0], nextpatt[6], nextpatt[1], nextpatt[7], nextpatt[4], nextpatt[2]}; - {B, F, H, D} <= {F, H, D, B}; - end - - i <= i + 1'b1; - if(old_reset_line && ~reset_line) begin - old_reset_frame <= reset_frame; - offs <= 0; - i <= 0; - y <= y + 1'd1; - prevbuf <= curbuf; - if(old_reset_frame & ~reset_frame) begin - y <= 0; - prevbuf <= 0; - end - end - - old_reset_line <= reset_line; - end -end - -endmodule // Hq2x diff --git a/cores/c64/rtl/mist/osd.v b/cores/c64/rtl/mist/osd.v deleted file mode 100644 index c62c10a..0000000 --- a/cores/c64/rtl/mist/osd.v +++ /dev/null @@ -1,179 +0,0 @@ -// A simple OSD implementation. Can be hooked up between a cores -// VGA output and the physical VGA pins - -module osd ( - // OSDs pixel clock, should be synchronous to cores pixel clock to - // avoid jitter. - input clk_sys, - - // SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // VGA signals coming from core - input [5:0] R_in, - input [5:0] G_in, - input [5:0] B_in, - input HSync, - input VSync, - - // VGA signals going to video connector - output [5:0] R_out, - output [5:0] G_out, - output [5:0] B_out -); - -parameter OSD_X_OFFSET = 10'd0; -parameter OSD_Y_OFFSET = 10'd0; -parameter OSD_COLOR = 3'd0; - -localparam OSD_WIDTH = 10'd256; -localparam OSD_HEIGHT = 10'd128; - -// ********************************************************************************* -// spi client -// ********************************************************************************* - -// this core supports only the display related OSD commands -// of the minimig -reg osd_enable; -(* ramstyle = "no_rw_check" *) reg [7:0] osd_buffer[2047:0]; // the OSD buffer itself - -// the OSD has its own SPI interface to the io controller -always@(posedge SPI_SCK, posedge SPI_SS3) begin - reg [4:0] cnt; - reg [10:0] bcnt; - reg [7:0] sbuf; - reg [7:0] cmd; - - if(SPI_SS3) begin - cnt <= 0; - bcnt <= 0; - end else begin - sbuf <= {sbuf[6:0], SPI_DI}; - - // 0:7 is command, rest payload - if(cnt < 15) cnt <= cnt + 1'd1; - else cnt <= 8; - - if(cnt == 7) begin - cmd <= {sbuf[6:0], SPI_DI}; - - // lower three command bits are line address - bcnt <= {sbuf[1:0], SPI_DI, 8'h00}; - - // command 0x40: OSDCMDENABLE, OSDCMDDISABLE - if(sbuf[6:3] == 4'b0100) osd_enable <= SPI_DI; - end - - // command 0x20: OSDCMDWRITE - if((cmd[7:3] == 5'b00100) && (cnt == 15)) begin - osd_buffer[bcnt] <= {sbuf[6:0], SPI_DI}; - bcnt <= bcnt + 1'd1; - end - end -end - -// ********************************************************************************* -// video timing and sync polarity anaylsis -// ********************************************************************************* - -// horizontal counter -reg [9:0] h_cnt; -reg [9:0] hs_low, hs_high; -wire hs_pol = hs_high < hs_low; -wire [9:0] dsp_width = hs_pol ? hs_low : hs_high; - -// vertical counter -reg [9:0] v_cnt; -reg [9:0] vs_low, vs_high; -wire vs_pol = vs_high < vs_low; -wire [9:0] dsp_height = vs_pol ? vs_low : vs_high; - -wire doublescan = (dsp_height>350); - -reg ce_pix; -always @(negedge clk_sys) begin - integer cnt = 0; - integer pixsz, pixcnt; - reg hs; - - cnt <= cnt + 1; - hs <= HSync; - - pixcnt <= pixcnt + 1; - if(pixcnt == pixsz) pixcnt <= 0; - ce_pix <= !pixcnt; - - if(hs && ~HSync) begin - cnt <= 0; - pixsz <= (cnt >> 9) - 1; - pixcnt <= 0; - ce_pix <= 1; - end -end - -always @(posedge clk_sys) begin - reg hsD, hsD2; - reg vsD, vsD2; - - if(ce_pix) begin - // bring hsync into local clock domain - hsD <= HSync; - hsD2 <= hsD; - - // falling edge of HSync - if(!hsD && hsD2) begin - h_cnt <= 0; - hs_high <= h_cnt; - end - - // rising edge of HSync - else if(hsD && !hsD2) begin - h_cnt <= 0; - hs_low <= h_cnt; - v_cnt <= v_cnt + 1'd1; - end else begin - h_cnt <= h_cnt + 1'd1; - end - - vsD <= VSync; - vsD2 <= vsD; - - // falling edge of VSync - if(!vsD && vsD2) begin - v_cnt <= 0; - vs_high <= v_cnt; - end - - // rising edge of VSync - else if(vsD && !vsD2) begin - v_cnt <= 0; - vs_low <= v_cnt; - end - end -end - -// area in which OSD is being displayed -wire [9:0] h_osd_start = ((dsp_width - OSD_WIDTH)>> 1) + OSD_X_OFFSET; -wire [9:0] h_osd_end = h_osd_start + OSD_WIDTH; -wire [9:0] v_osd_start = ((dsp_height- (OSD_HEIGHT<> 1) + OSD_Y_OFFSET; -wire [9:0] v_osd_end = v_osd_start + (OSD_HEIGHT<= h_osd_start) && (h_cnt < h_osd_end) && - (VSync != vs_pol) && (v_cnt >= v_osd_start) && (v_cnt < v_osd_end); - -reg [7:0] osd_byte; -always @(posedge clk_sys) if(ce_pix) osd_byte <= osd_buffer[{doublescan ? osd_vcnt[7:5] : osd_vcnt[6:4], osd_hcnt[7:0]}]; - -wire osd_pixel = osd_byte[doublescan ? osd_vcnt[4:2] : osd_vcnt[3:1]]; - -assign R_out = !osd_de ? R_in : {osd_pixel, osd_pixel, OSD_COLOR[2], R_in[5:3]}; -assign G_out = !osd_de ? G_in : {osd_pixel, osd_pixel, OSD_COLOR[1], G_in[5:3]}; -assign B_out = !osd_de ? B_in : {osd_pixel, osd_pixel, OSD_COLOR[0], B_in[5:3]}; - -endmodule diff --git a/cores/c64/rtl/mist/scandoubler.v b/cores/c64/rtl/mist/scandoubler.v deleted file mode 100644 index e85cba4..0000000 --- a/cores/c64/rtl/mist/scandoubler.v +++ /dev/null @@ -1,183 +0,0 @@ -// -// scandoubler.v -// -// Copyright (c) 2015 Till Harbaum -// Copyright (c) 2017 Sorgelig -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . - -// TODO: Delay vsync one line - -module scandoubler #(parameter LENGTH, parameter HALF_DEPTH) -( - // system interface - input clk_sys, - input ce_pix, - input ce_pix_actual, - - input hq2x, - - // shifter video interface - input hs_in, - input vs_in, - input line_start, - - input [DWIDTH:0] r_in, - input [DWIDTH:0] g_in, - input [DWIDTH:0] b_in, - input mono, - - // output interface - output reg hs_out, - output vs_out, - output [DWIDTH:0] r_out, - output [DWIDTH:0] g_out, - output [DWIDTH:0] b_out -); - - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -assign vs_out = vs_in; - -reg [2:0] phase; -reg [2:0] ce_div; -reg [7:0] pix_len = 0; -wire [7:0] pl = pix_len + 1'b1; - -reg ce_x1, ce_x4; -reg req_line_reset; -wire ls_in = hs_in | line_start; -always @(negedge clk_sys) begin - reg old_ce; - reg [2:0] ce_cnt; - - reg [7:0] pixsz2, pixsz4 = 0; - - old_ce <= ce_pix; - if(~&pix_len) pix_len <= pix_len + 1'd1; - - ce_x4 <= 0; - ce_x1 <= 0; - - // use such odd comparison to place c_x4 evenly if master clock isn't multiple 4. - if((pl == pixsz4) || (pl == pixsz2) || (pl == (pixsz2+pixsz4))) begin - phase <= phase + 1'd1; - ce_x4 <= 1; - end - - if(~old_ce & ce_pix) begin - pixsz2 <= {1'b0, pl[7:1]}; - pixsz4 <= {2'b00, pl[7:2]}; - ce_x1 <= 1; - ce_x4 <= 1; - pix_len <= 0; - phase <= phase + 1'd1; - - ce_cnt <= ce_cnt + 1'd1; - if(ce_pix_actual) begin - phase <= 0; - ce_div <= ce_cnt + 1'd1; - ce_cnt <= 0; - req_line_reset <= 0; - end - - if(ls_in) req_line_reset <= 1; - end -end - -reg ce_sd; -always @(*) begin - case(ce_div) - 2: ce_sd = !phase[0]; - 4: ce_sd = !phase[1:0]; - default: ce_sd <= 1; - endcase -end - -localparam AWIDTH = `BITS_TO_FIT(LENGTH); -Hq2x #(.LENGTH(LENGTH), .HALF_DEPTH(HALF_DEPTH)) Hq2x -( - .clk(clk_sys), - .ce_x4(ce_x4 & ce_sd), - .inputpixel({b_in,g_in,r_in}), - .mono(mono), - .disable_hq2x(~hq2x), - .reset_frame(vs_in), - .reset_line(req_line_reset), - .read_y(sd_line), - .read_x(sd_h_actual), - .outpixel({b_out,g_out,r_out}) -); - -reg [10:0] sd_h_actual; -always @(*) begin - case(ce_div) - 2: sd_h_actual = sd_h[10:1]; - 4: sd_h_actual = sd_h[10:2]; - default: sd_h_actual = sd_h; - endcase -end - -reg [10:0] sd_h; -reg [1:0] sd_line; -always @(posedge clk_sys) begin - - reg [11:0] hs_max,hs_rise,hs_ls; - reg [10:0] hcnt; - reg [11:0] sd_hcnt; - - reg hs, hs2, vs, ls; - - if(ce_x1) begin - hs <= hs_in; - ls <= ls_in; - - if(ls && !ls_in) hs_ls <= {hcnt,1'b1}; - - // falling edge of hsync indicates start of line - if(hs && !hs_in) begin - hs_max <= {hcnt,1'b1}; - hcnt <= 0; - if(ls && !ls_in) hs_ls <= {10'd0,1'b1}; - end else begin - hcnt <= hcnt + 1'd1; - end - - // save position of rising edge - if(!hs && hs_in) hs_rise <= {hcnt,1'b1}; - - vs <= vs_in; - if(vs && ~vs_in) sd_line <= 0; - end - - if(ce_x4) begin - hs2 <= hs_in; - - // output counter synchronous to input and at twice the rate - sd_hcnt <= sd_hcnt + 1'd1; - sd_h <= sd_h + 1'd1; - if(hs2 && !hs_in) sd_hcnt <= hs_max; - if(sd_hcnt == hs_max) sd_hcnt <= 0; - - // replicate horizontal sync at twice the speed - if(sd_hcnt == hs_max) hs_out <= 0; - if(sd_hcnt == hs_rise) hs_out <= 1; - - if(sd_hcnt == hs_ls) sd_h <= 0; - if(sd_hcnt == hs_ls) sd_line <= sd_line + 1'd1; - end -end - -endmodule diff --git a/cores/c64/rtl/mist/user_io.v b/cores/c64/rtl/mist/user_io.v deleted file mode 100644 index 5b03cd1..0000000 --- a/cores/c64/rtl/mist/user_io.v +++ /dev/null @@ -1,550 +0,0 @@ -// -// user_io.v -// -// user_io for the MiST board -// http://code.google.com/p/mist-board/ -// -// Copyright (c) 2014 Till Harbaum -// -// This source file is free software: you can redistribute it and/or modify -// it under the terms of the GNU General Public License as published -// by the Free Software Foundation, either version 3 of the License, or -// (at your option) any later version. -// -// This source file is distributed in the hope that it will be useful, -// but WITHOUT ANY WARRANTY; without even the implied warranty of -// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -// GNU General Public License for more details. -// -// You should have received a copy of the GNU General Public License -// along with this program. If not, see . -// - -// parameter STRLEN and the actual length of conf_str have to match - -module user_io #(parameter STRLEN=0, parameter PS2DIV=100) ( - input [(8*STRLEN)-1:0] conf_str, - - input clk_sys, // clock for system-related messages (kbd, joy, etc...) - input clk_sd, // clock for SD-card related messages - - input SPI_CLK, - input SPI_SS_IO, - output reg SPI_MISO, - input SPI_MOSI, - - output reg [31:0] joystick_0, - output reg [31:0] joystick_1, - output reg [31:0] joystick_2, - output reg [31:0] joystick_3, - output reg [31:0] joystick_4, - output reg [15:0] joystick_analog_0, - output reg [15:0] joystick_analog_1, - output [1:0] buttons, - output [1:0] switches, - output scandoubler_disable, - output ypbpr, - output reg [31:0] status, - - // connection to sd card emulation - input [31:0] sd_lba, - input sd_rd, - input sd_wr, - output reg sd_ack, - output reg sd_ack_conf, - input sd_conf, - input sd_sdhc, - output reg [7:0] sd_dout, // valid on rising edge of sd_dout_strobe - output reg sd_dout_strobe, - input [7:0] sd_din, - output reg sd_din_strobe, - output reg [8:0] sd_buff_addr, - - output reg img_mounted, //rising edge if a new image is mounted - output reg [31:0] img_size, // size of image in bytes - - // ps2 keyboard/mouse emulation - output ps2_kbd_clk, - output reg ps2_kbd_data, - output ps2_mouse_clk, - output reg ps2_mouse_data, - - // mouse data - output reg [8:0] mouse_x, - output reg [8:0] mouse_y, - output reg [7:0] mouse_flags, // YOvfl, XOvfl, dy8, dx8, 1, mbtn, rbtn, lbtn - output reg mouse_strobe, // mouse data is valid on mouse_strobe - - // serial com port - input [7:0] serial_data, - input serial_strobe -); - -reg [6:0] sbuf; -reg [7:0] cmd; -reg [2:0] bit_cnt; // counts bits 0-7 0-7 ... -reg [9:0] byte_cnt; // counts bytes -reg [7:0] but_sw; -reg [2:0] stick_idx; - -assign buttons = but_sw[1:0]; -assign switches = but_sw[3:2]; -assign scandoubler_disable = but_sw[4]; -assign ypbpr = but_sw[5]; - -// this variant of user_io is for 8 bit cores (type == a4) only -wire [7:0] core_type = 8'ha4; - -// command byte read by the io controller -wire [7:0] sd_cmd = { 4'h5, sd_conf, sd_sdhc, sd_wr, sd_rd }; - -wire spi_sck = SPI_CLK; - -// ---------------- PS2 --------------------- -// 8 byte fifos to store ps2 bytes -localparam PS2_FIFO_BITS = 3; - -reg ps2_clk; -always @(negedge clk_sys) begin - integer cnt; - cnt <= cnt + 1'd1; - if(cnt == PS2DIV) begin - ps2_clk <= ~ps2_clk; - cnt <= 0; - end -end - -// keyboard -reg [7:0] ps2_kbd_fifo [(2**PS2_FIFO_BITS)-1:0]; -reg [PS2_FIFO_BITS-1:0] ps2_kbd_wptr; -reg [PS2_FIFO_BITS-1:0] ps2_kbd_rptr; - -// ps2 transmitter state machine -reg [3:0] ps2_kbd_tx_state; -reg [7:0] ps2_kbd_tx_byte; -reg ps2_kbd_parity; - -assign ps2_kbd_clk = ps2_clk || (ps2_kbd_tx_state == 0); - -// ps2 transmitter -// Takes a byte from the FIFO and sends it in a ps2 compliant serial format. -reg ps2_kbd_r_inc; -always@(posedge clk_sys) begin - reg ps2_clkD; - - ps2_clkD <= ps2_clk; - if (~ps2_clkD & ps2_clk) begin - ps2_kbd_r_inc <= 1'b0; - - if(ps2_kbd_r_inc) - ps2_kbd_rptr <= ps2_kbd_rptr + 1'd1; - - // transmitter is idle? - if(ps2_kbd_tx_state == 0) begin - // data in fifo present? - if(ps2_kbd_wptr != ps2_kbd_rptr) begin - // load tx register from fifo - ps2_kbd_tx_byte <= ps2_kbd_fifo[ps2_kbd_rptr]; - ps2_kbd_r_inc <= 1'b1; - - // reset parity - ps2_kbd_parity <= 1'b1; - - // start transmitter - ps2_kbd_tx_state <= 4'd1; - - // put start bit on data line - ps2_kbd_data <= 1'b0; // start bit is 0 - end - end else begin - - // transmission of 8 data bits - if((ps2_kbd_tx_state >= 1)&&(ps2_kbd_tx_state < 9)) begin - ps2_kbd_data <= ps2_kbd_tx_byte[0]; // data bits - ps2_kbd_tx_byte[6:0] <= ps2_kbd_tx_byte[7:1]; // shift down - if(ps2_kbd_tx_byte[0]) - ps2_kbd_parity <= !ps2_kbd_parity; - end - - // transmission of parity - if(ps2_kbd_tx_state == 9) - ps2_kbd_data <= ps2_kbd_parity; - - // transmission of stop bit - if(ps2_kbd_tx_state == 10) - ps2_kbd_data <= 1'b1; // stop bit is 1 - - // advance state machine - if(ps2_kbd_tx_state < 11) - ps2_kbd_tx_state <= ps2_kbd_tx_state + 4'd1; - else - ps2_kbd_tx_state <= 4'd0; - end - end -end - -// mouse -reg [7:0] ps2_mouse_fifo [(2**PS2_FIFO_BITS)-1:0]; -reg [PS2_FIFO_BITS-1:0] ps2_mouse_wptr; -reg [PS2_FIFO_BITS-1:0] ps2_mouse_rptr; - -// ps2 transmitter state machine -reg [3:0] ps2_mouse_tx_state; -reg [7:0] ps2_mouse_tx_byte; -reg ps2_mouse_parity; - -assign ps2_mouse_clk = ps2_clk || (ps2_mouse_tx_state == 0); - -// ps2 transmitter -// Takes a byte from the FIFO and sends it in a ps2 compliant serial format. -reg ps2_mouse_r_inc; -always@(posedge clk_sys) begin - reg ps2_clkD; - - ps2_clkD <= ps2_clk; - if (~ps2_clkD & ps2_clk) begin - ps2_mouse_r_inc <= 1'b0; - - if(ps2_mouse_r_inc) - ps2_mouse_rptr <= ps2_mouse_rptr + 1'd1; - - // transmitter is idle? - if(ps2_mouse_tx_state == 0) begin - // data in fifo present? - if(ps2_mouse_wptr != ps2_mouse_rptr) begin - // load tx register from fifo - ps2_mouse_tx_byte <= ps2_mouse_fifo[ps2_mouse_rptr]; - ps2_mouse_r_inc <= 1'b1; - - // reset parity - ps2_mouse_parity <= 1'b1; - - // start transmitter - ps2_mouse_tx_state <= 4'd1; - - // put start bit on data line - ps2_mouse_data <= 1'b0; // start bit is 0 - end - end else begin - - // transmission of 8 data bits - if((ps2_mouse_tx_state >= 1)&&(ps2_mouse_tx_state < 9)) begin - ps2_mouse_data <= ps2_mouse_tx_byte[0]; // data bits - ps2_mouse_tx_byte[6:0] <= ps2_mouse_tx_byte[7:1]; // shift down - if(ps2_mouse_tx_byte[0]) - ps2_mouse_parity <= !ps2_mouse_parity; - end - - // transmission of parity - if(ps2_mouse_tx_state == 9) - ps2_mouse_data <= ps2_mouse_parity; - - // transmission of stop bit - if(ps2_mouse_tx_state == 10) - ps2_mouse_data <= 1'b1; // stop bit is 1 - - // advance state machine - if(ps2_mouse_tx_state < 11) - ps2_mouse_tx_state <= ps2_mouse_tx_state + 4'd1; - else - ps2_mouse_tx_state <= 4'd0; - end - end -end - -// fifo to receive serial data from core to be forwarded to io controller - -// 16 byte fifo to store serial bytes -localparam SERIAL_OUT_FIFO_BITS = 6; -reg [7:0] serial_out_fifo [(2**SERIAL_OUT_FIFO_BITS)-1:0]; -reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_wptr; -reg [SERIAL_OUT_FIFO_BITS-1:0] serial_out_rptr; - -wire serial_out_data_available = serial_out_wptr != serial_out_rptr; -wire [7:0] serial_out_byte = serial_out_fifo[serial_out_rptr] /* synthesis keep */; -wire [7:0] serial_out_status = { 7'b1000000, serial_out_data_available}; - -// status[0] is reset signal from io controller and is thus used to flush -// the fifo -always @(posedge serial_strobe or posedge status[0]) begin - if(status[0] == 1) begin - serial_out_wptr <= 0; - end else begin - serial_out_fifo[serial_out_wptr] <= serial_data; - serial_out_wptr <= serial_out_wptr + 1'd1; - end -end - -always@(negedge spi_sck or posedge status[0]) begin - if(status[0] == 1) begin - serial_out_rptr <= 0; - end else begin - if((byte_cnt != 0) && (cmd == 8'h1b)) begin - // read last bit -> advance read pointer - if((bit_cnt == 7) && !byte_cnt[0] && serial_out_data_available) - serial_out_rptr <= serial_out_rptr + 1'd1; - end - end -end - - -// SPI bit and byte counters -always@(posedge spi_sck or posedge SPI_SS_IO) begin - if(SPI_SS_IO == 1) begin - bit_cnt <= 0; - byte_cnt <= 0; - end else begin - if((bit_cnt == 7)&&(~&byte_cnt)) - byte_cnt <= byte_cnt + 8'd1; - - bit_cnt <= bit_cnt + 1'd1; - end -end - -// SPI transmitter FPGA -> IO -reg [7:0] spi_byte_out; - -always@(negedge spi_sck or posedge SPI_SS_IO) begin - if(SPI_SS_IO == 1) begin - SPI_MISO <= 1'bZ; - end else begin - SPI_MISO <= spi_byte_out[~bit_cnt]; - end -end - -always@(posedge spi_sck or posedge SPI_SS_IO) begin - reg [31:0] sd_lba_r; - - if(SPI_SS_IO == 1) begin - spi_byte_out <= core_type; - end else begin - // read the command byte to choose the response - if(bit_cnt == 7) begin - if(!byte_cnt) cmd <= {sbuf, SPI_MOSI}; - - spi_byte_out <= 0; - case({(!byte_cnt) ? {sbuf, SPI_MOSI} : cmd}) - // reading config string - 8'h14: if(byte_cnt < STRLEN) spi_byte_out <= conf_str[(STRLEN - byte_cnt - 1)<<3 +:8]; - - // reading sd card status - 8'h16: if(byte_cnt == 0) begin - spi_byte_out <= sd_cmd; - sd_lba_r <= sd_lba; - end - else if(byte_cnt < 5) spi_byte_out <= sd_lba_r[(4-byte_cnt)<<3 +:8]; - - // reading sd card write data - 8'h18: spi_byte_out <= sd_din; - 8'h1b: - // send alternating flag byte and data - if(byte_cnt[0]) spi_byte_out <= serial_out_status; - else spi_byte_out <= serial_out_byte; - endcase - end - end -end - -// SPI receiver IO -> FPGA - -reg spi_receiver_strobe_r = 0; -reg spi_transfer_end_r = 1; -reg [7:0] spi_byte_in; - -// Read at spi_sck clock domain, assemble bytes for transferring to clk_sys -always@(posedge spi_sck or posedge SPI_SS_IO) begin - - if(SPI_SS_IO == 1) begin - spi_transfer_end_r <= 1; - end else begin - spi_transfer_end_r <= 0; - - if(bit_cnt != 7) - sbuf[6:0] <= { sbuf[5:0], SPI_MOSI }; - - // finished reading a byte, prepare to transfer to clk_sys - if(bit_cnt == 7) begin - spi_byte_in <= { sbuf, SPI_MOSI}; - spi_receiver_strobe_r <= ~spi_receiver_strobe_r; - end - end -end - -// Process bytes from SPI at the clk_sys domain -always @(posedge clk_sys) begin - - reg spi_receiver_strobe; - reg spi_transfer_end; - reg spi_receiver_strobeD; - reg spi_transfer_endD; - reg [7:0] acmd; - reg [7:0] abyte_cnt; // counts bytes - - reg [7:0] mouse_flags_r; - reg [7:0] mouse_x_r; - - //synchronize between SPI and sys clock domains - spi_receiver_strobeD <= spi_receiver_strobe_r; - spi_receiver_strobe <= spi_receiver_strobeD; - spi_transfer_endD <= spi_transfer_end_r; - spi_transfer_end <= spi_transfer_endD; - - mouse_strobe <= 0; - - if (~spi_transfer_endD & spi_transfer_end) begin - abyte_cnt <= 8'd0; - end else if (spi_receiver_strobeD ^ spi_receiver_strobe) begin - - if(~&abyte_cnt) - abyte_cnt <= abyte_cnt + 8'd1; - - if(abyte_cnt == 0) begin - acmd <= spi_byte_in; - end else begin - case(acmd) - // buttons and switches - 8'h01: but_sw <= spi_byte_in; - 8'h60: if (abyte_cnt < 5) joystick_0[(abyte_cnt-1)<<3 +:8] <= spi_byte_in; - 8'h61: if (abyte_cnt < 5) joystick_1[(abyte_cnt-1)<<3 +:8] <= spi_byte_in; - 8'h62: if (abyte_cnt < 5) joystick_2[(abyte_cnt-1)<<3 +:8] <= spi_byte_in; - 8'h63: if (abyte_cnt < 5) joystick_3[(abyte_cnt-1)<<3 +:8] <= spi_byte_in; - 8'h64: if (abyte_cnt < 5) joystick_4[(abyte_cnt-1)<<3 +:8] <= spi_byte_in; - 8'h04: begin - // store incoming ps2 mouse bytes - ps2_mouse_fifo[ps2_mouse_wptr] <= spi_byte_in; - ps2_mouse_wptr <= ps2_mouse_wptr + 1'd1; - if (abyte_cnt == 1) mouse_flags_r <= spi_byte_in; - else if (abyte_cnt == 2) mouse_x_r <= spi_byte_in; - else if (abyte_cnt == 3) begin - // flags: YOvfl, XOvfl, dy8, dx8, 1, mbtn, rbtn, lbtn - mouse_flags <= mouse_flags_r; - mouse_x <= { mouse_flags_r[4], mouse_x_r }; - mouse_y <= { mouse_flags_r[5], spi_byte_in }; - mouse_strobe <= 1; - end - end - 8'h05: begin - // store incoming ps2 keyboard bytes - ps2_kbd_fifo[ps2_kbd_wptr] <= spi_byte_in; - ps2_kbd_wptr <= ps2_kbd_wptr + 1'd1; - end - - // joystick analog - 8'h1a: begin - // first byte is joystick index - if(abyte_cnt == 1) - stick_idx <= spi_byte_in[2:0]; - else if(abyte_cnt == 2) begin - // second byte is x axis - if(stick_idx == 0) - joystick_analog_0[15:8] <= spi_byte_in; - else if(stick_idx == 1) - joystick_analog_1[15:8] <= spi_byte_in; - end else if(abyte_cnt == 3) begin - // third byte is y axis - if(stick_idx == 0) - joystick_analog_0[7:0] <= spi_byte_in; - else if(stick_idx == 1) - joystick_analog_1[7:0] <= spi_byte_in; - end - end - - 8'h15: status <= spi_byte_in; - - // status, 32bit version - 8'h1e: if(abyte_cnt<5) status[(abyte_cnt-1)<<3 +:8] <= spi_byte_in; - - endcase - end - end -end - -// Process SD-card related bytes from SPI at the clk_sd domain -always @(posedge clk_sd) begin - - reg spi_receiver_strobe; - reg spi_transfer_end; - reg spi_receiver_strobeD; - reg spi_transfer_endD; - reg sd_wrD; - reg [7:0] acmd; - reg [7:0] abyte_cnt; // counts bytes - - //synchronize between SPI and sd clock domains - spi_receiver_strobeD <= spi_receiver_strobe_r; - spi_receiver_strobe <= spi_receiver_strobeD; - spi_transfer_endD <= spi_transfer_end_r; - spi_transfer_end <= spi_transfer_endD; - - if(sd_dout_strobe) begin - sd_dout_strobe<= 0; - if(~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; - end - - sd_din_strobe<= 0; - sd_wrD <= sd_wr; - // fetch the first byte immediately after the write command seen - if (~sd_wrD & sd_wr) begin - sd_buff_addr <= 0; - sd_din_strobe <= 1; - end - - img_mounted <= 0; - - if (~spi_transfer_endD & spi_transfer_end) begin - abyte_cnt <= 8'd0; - sd_ack <= 1'b0; - sd_ack_conf <= 1'b0; - sd_dout_strobe <= 1'b0; - sd_din_strobe <= 1'b0; - sd_buff_addr <= 0; - end else if (spi_receiver_strobeD ^ spi_receiver_strobe) begin - - if(~&abyte_cnt) - abyte_cnt <= abyte_cnt + 8'd1; - - if(abyte_cnt == 0) begin - acmd <= spi_byte_in; - - if(spi_byte_in == 8'h18) begin - sd_din_strobe <= 1'b1; - if(~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; - end - - if((spi_byte_in == 8'h17) || (spi_byte_in == 8'h18)) - sd_ack <= 1'b1; - - end else begin - case(acmd) - - // send sector IO -> FPGA - 8'h17: begin - // flag that download begins - sd_dout_strobe <= 1'b1; - sd_dout <= spi_byte_in; - end - - // send sector FPGA -> IO - 8'h18: begin - sd_din_strobe <= 1'b1; - if(~&sd_buff_addr) sd_buff_addr <= sd_buff_addr + 1'b1; - end - - // send SD config IO -> FPGA - 8'h19: begin - // flag that download begins - sd_dout_strobe <= 1'b1; - sd_ack_conf <= 1'b1; - sd_dout <= spi_byte_in; - end - - 8'h1c: img_mounted <= 1; - - // send image info - 8'h1d: if(abyte_cnt<5) img_size[(abyte_cnt-1)<<3 +:8] <= spi_byte_in; - endcase - end - end -end - -endmodule diff --git a/cores/c64/rtl/mist/video_mixer.sv b/cores/c64/rtl/mist/video_mixer.sv deleted file mode 100644 index 04cfd4b..0000000 --- a/cores/c64/rtl/mist/video_mixer.sv +++ /dev/null @@ -1,242 +0,0 @@ -// -// -// Copyright (c) 2017 Sorgelig -// -// This program is GPL Licensed. See COPYING for the full license. -// -// -//////////////////////////////////////////////////////////////////////////////////////////////////////// - -`timescale 1ns / 1ps - -// -// LINE_LENGTH: Length of display line in pixels -// Usually it's length from HSync to HSync. -// May be less if line_start is used. -// -// HALF_DEPTH: If =1 then color dept is 3 bits per component -// For half depth 6 bits monochrome is available with -// mono signal enabled and color = {G, R} - -module video_mixer -#( - parameter LINE_LENGTH = 768, - parameter HALF_DEPTH = 0, - - parameter OSD_COLOR = 3'd4, - parameter OSD_X_OFFSET = 10'd0, - parameter OSD_Y_OFFSET = 10'd0 -) -( - // master clock - // it should be multiple by (ce_pix*4). - input clk_sys, - - // Pixel clock or clock_enable (both are accepted). - input ce_pix, - - // Some systems have multiple resolutions. - // ce_pix_actual should match ce_pix where every second or fourth pulse is enabled, - // thus half or qurter resolutions can be used without brake video sync while switching resolutions. - // For fixed single resolution (or when video sync stability isn't required) ce_pix_actual = ce_pix. - input ce_pix_actual, - - // OSD SPI interface - input SPI_SCK, - input SPI_SS3, - input SPI_DI, - - // scanlines (00-none 01-25% 10-50% 11-75%) - input [1:0] scanlines, - - // 0 = HVSync 31KHz, 1 = CSync 15KHz - input scandoubler_disable, - - // High quality 2x scaling - input hq2x, - - // YPbPr always uses composite sync - input ypbpr, - - // 0 = 16-240 range. 1 = 0-255 range. (only for YPbPr color space) - input ypbpr_full, - - // color - input [DWIDTH:0] R, - input [DWIDTH:0] G, - input [DWIDTH:0] B, - - // Monochrome mode (for HALF_DEPTH only) - input mono, - - // interlace sync. Positive pulses. - input HSync, - input VSync, - - // Falling of this signal means start of informative part of line. - // It can be horizontal blank signal. - // This signal can be used to reduce amount of required FPGA RAM for HQ2x scan doubler - // If FPGA RAM is not an issue, then simply set it to 0 for whole line processing. - // Keep in mind: due to algo first and last pixels of line should be black to avoid side artefacts. - // Thus, if blank signal is used to reduce the line, make sure to feed at least one black (or paper) pixel - // before first informative pixel. - input line_start, - - // MiST video output signals - output [5:0] VGA_R, - output [5:0] VGA_G, - output [5:0] VGA_B, - output VGA_VS, - output VGA_HS -); - -localparam DWIDTH = HALF_DEPTH ? 2 : 5; - -wire [DWIDTH:0] R_sd; -wire [DWIDTH:0] G_sd; -wire [DWIDTH:0] B_sd; -wire hs_sd, vs_sd; - -scandoubler #(.LENGTH(LINE_LENGTH), .HALF_DEPTH(HALF_DEPTH)) scandoubler -( - .*, - .hs_in(HSync), - .vs_in(VSync), - .r_in(R), - .g_in(G), - .b_in(B), - - .hs_out(hs_sd), - .vs_out(vs_sd), - .r_out(R_sd), - .g_out(G_sd), - .b_out(B_sd) -); - -wire [DWIDTH:0] rt = (scandoubler_disable ? R : R_sd); -wire [DWIDTH:0] gt = (scandoubler_disable ? G : G_sd); -wire [DWIDTH:0] bt = (scandoubler_disable ? B : B_sd); - -generate - if(HALF_DEPTH) begin - wire [5:0] r = mono ? {gt,rt} : {rt,rt}; - wire [5:0] g = mono ? {gt,rt} : {gt,gt}; - wire [5:0] b = mono ? {gt,rt} : {bt,bt}; - end else begin - wire [5:0] r = rt; - wire [5:0] g = gt; - wire [5:0] b = bt; - end -endgenerate - -wire hs = (scandoubler_disable ? HSync : hs_sd); -wire vs = (scandoubler_disable ? VSync : vs_sd); - -reg scanline = 0; -always @(posedge clk_sys) begin - reg old_hs, old_vs; - - old_hs <= hs; - old_vs <= vs; - - if(old_hs && ~hs) scanline <= ~scanline; - if(old_vs && ~vs) scanline <= 0; -end - -wire [5:0] r_out, g_out, b_out; -always @(*) begin - case(scanlines & {scanline, scanline}) - 1: begin // reduce 25% = 1/2 + 1/4 - r_out = {1'b0, r[5:1]} + {2'b00, r[5:2]}; - g_out = {1'b0, g[5:1]} + {2'b00, g[5:2]}; - b_out = {1'b0, b[5:1]} + {2'b00, b[5:2]}; - end - - 2: begin // reduce 50% = 1/2 - r_out = {1'b0, r[5:1]}; - g_out = {1'b0, g[5:1]}; - b_out = {1'b0, b[5:1]}; - end - - 3: begin // reduce 75% = 1/4 - r_out = {2'b00, r[5:2]}; - g_out = {2'b00, g[5:2]}; - b_out = {2'b00, b[5:2]}; - end - - default: begin - r_out = r; - g_out = g; - b_out = b; - end - endcase -end - -wire [5:0] red, green, blue; -osd #(OSD_X_OFFSET, OSD_Y_OFFSET, OSD_COLOR) osd -( - .*, - - .R_in(r_out), - .G_in(g_out), - .B_in(b_out), - .HSync(hs), - .VSync(vs), - - .R_out(red), - .G_out(green), - .B_out(blue) -); - -wire [5:0] yuv_full[225] = '{ - 6'd0, 6'd0, 6'd0, 6'd0, 6'd1, 6'd1, 6'd1, 6'd1, - 6'd2, 6'd2, 6'd2, 6'd3, 6'd3, 6'd3, 6'd3, 6'd4, - 6'd4, 6'd4, 6'd5, 6'd5, 6'd5, 6'd5, 6'd6, 6'd6, - 6'd6, 6'd7, 6'd7, 6'd7, 6'd7, 6'd8, 6'd8, 6'd8, - 6'd9, 6'd9, 6'd9, 6'd9, 6'd10, 6'd10, 6'd10, 6'd11, - 6'd11, 6'd11, 6'd11, 6'd12, 6'd12, 6'd12, 6'd13, 6'd13, - 6'd13, 6'd13, 6'd14, 6'd14, 6'd14, 6'd15, 6'd15, 6'd15, - 6'd15, 6'd16, 6'd16, 6'd16, 6'd17, 6'd17, 6'd17, 6'd17, - 6'd18, 6'd18, 6'd18, 6'd19, 6'd19, 6'd19, 6'd19, 6'd20, - 6'd20, 6'd20, 6'd21, 6'd21, 6'd21, 6'd21, 6'd22, 6'd22, - 6'd22, 6'd23, 6'd23, 6'd23, 6'd23, 6'd24, 6'd24, 6'd24, - 6'd25, 6'd25, 6'd25, 6'd25, 6'd26, 6'd26, 6'd26, 6'd27, - 6'd27, 6'd27, 6'd27, 6'd28, 6'd28, 6'd28, 6'd29, 6'd29, - 6'd29, 6'd29, 6'd30, 6'd30, 6'd30, 6'd31, 6'd31, 6'd31, - 6'd31, 6'd32, 6'd32, 6'd32, 6'd33, 6'd33, 6'd33, 6'd33, - 6'd34, 6'd34, 6'd34, 6'd35, 6'd35, 6'd35, 6'd35, 6'd36, - 6'd36, 6'd36, 6'd36, 6'd37, 6'd37, 6'd37, 6'd38, 6'd38, - 6'd38, 6'd38, 6'd39, 6'd39, 6'd39, 6'd40, 6'd40, 6'd40, - 6'd40, 6'd41, 6'd41, 6'd41, 6'd42, 6'd42, 6'd42, 6'd42, - 6'd43, 6'd43, 6'd43, 6'd44, 6'd44, 6'd44, 6'd44, 6'd45, - 6'd45, 6'd45, 6'd46, 6'd46, 6'd46, 6'd46, 6'd47, 6'd47, - 6'd47, 6'd48, 6'd48, 6'd48, 6'd48, 6'd49, 6'd49, 6'd49, - 6'd50, 6'd50, 6'd50, 6'd50, 6'd51, 6'd51, 6'd51, 6'd52, - 6'd52, 6'd52, 6'd52, 6'd53, 6'd53, 6'd53, 6'd54, 6'd54, - 6'd54, 6'd54, 6'd55, 6'd55, 6'd55, 6'd56, 6'd56, 6'd56, - 6'd56, 6'd57, 6'd57, 6'd57, 6'd58, 6'd58, 6'd58, 6'd58, - 6'd59, 6'd59, 6'd59, 6'd60, 6'd60, 6'd60, 6'd60, 6'd61, - 6'd61, 6'd61, 6'd62, 6'd62, 6'd62, 6'd62, 6'd63, 6'd63, - 6'd63 -}; - -// http://marsee101.blog19.fc2.com/blog-entry-2311.html -// Y = 16 + 0.257*R + 0.504*G + 0.098*B (Y = 0.299*R + 0.587*G + 0.114*B) -// Pb = 128 - 0.148*R - 0.291*G + 0.439*B (Pb = -0.169*R - 0.331*G + 0.500*B) -// Pr = 128 + 0.439*R - 0.368*G - 0.071*B (Pr = 0.500*R - 0.419*G - 0.081*B) - -wire [18:0] y_8 = 19'd04096 + ({red, 8'd0} + {red, 3'd0}) + ({green, 9'd0} + {green, 2'd0}) + ({blue, 6'd0} + {blue, 5'd0} + {blue, 2'd0}); -wire [18:0] pb_8 = 19'd32768 - ({red, 7'd0} + {red, 4'd0} + {red, 3'd0}) - ({green, 8'd0} + {green, 5'd0} + {green, 3'd0}) + ({blue, 8'd0} + {blue, 7'd0} + {blue, 6'd0}); -wire [18:0] pr_8 = 19'd32768 + ({red, 8'd0} + {red, 7'd0} + {red, 6'd0}) - ({green, 8'd0} + {green, 6'd0} + {green, 5'd0} + {green, 4'd0} + {green, 3'd0}) - ({blue, 6'd0} + {blue , 3'd0}); - -wire [7:0] y = ( y_8[17:8] < 16) ? 8'd16 : ( y_8[17:8] > 235) ? 8'd235 : y_8[15:8]; -wire [7:0] pb = (pb_8[17:8] < 16) ? 8'd16 : (pb_8[17:8] > 240) ? 8'd240 : pb_8[15:8]; -wire [7:0] pr = (pr_8[17:8] < 16) ? 8'd16 : (pr_8[17:8] > 240) ? 8'd240 : pr_8[15:8]; - -assign VGA_R = ypbpr ? (ypbpr_full ? yuv_full[pr-8'd16] : pr[7:2]) : red; -assign VGA_G = ypbpr ? (ypbpr_full ? yuv_full[y -8'd16] : y[7:2]) : green; -assign VGA_B = ypbpr ? (ypbpr_full ? yuv_full[pb-8'd16] : pb[7:2]) : blue; -assign VGA_VS = (scandoubler_disable | ypbpr) ? 1'b1 : ~vs_sd; -assign VGA_HS = scandoubler_disable ? ~(HSync ^ VSync) : ypbpr ? ~(hs_sd ^ vs_sd) : ~hs_sd; - -endmodule diff --git a/mist-modules b/mist-modules index 232c10f..f4f624e 160000 --- a/mist-modules +++ b/mist-modules @@ -1 +1 @@ -Subproject commit 232c10f768f2af8a7ed0f9b295727b2867cc6084 +Subproject commit f4f624eeb31c6faa0ed556edcd37752140769e73